Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 1 | /* |
Eric Miao | 38f539a | 2009-01-20 12:09:06 +0800 | [diff] [blame] | 2 | * linux/arch/arm/plat-pxa/gpio.c |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 3 | * |
| 4 | * Generic PXA GPIO handling |
| 5 | * |
| 6 | * Author: Nicolas Pitre |
| 7 | * Created: Jun 15, 2001 |
| 8 | * Copyright: MontaVista Software Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 14 | #include <linux/module.h> |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | #include <linux/err.h> |
Russell King | 2f8163b | 2011-07-26 10:53:52 +0100 | [diff] [blame] | 17 | #include <linux/gpio.h> |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 18 | #include <linux/gpio-pxa.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 19 | #include <linux/init.h> |
Rob Herring | ae4f4cf | 2015-01-26 22:46:04 -0600 | [diff] [blame] | 20 | #include <linux/interrupt.h> |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 21 | #include <linux/irq.h> |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 22 | #include <linux/irqdomain.h> |
Catalin Marinas | de88cbb | 2013-01-18 15:31:37 +0000 | [diff] [blame] | 23 | #include <linux/irqchip/chained_irq.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 24 | #include <linux/io.h> |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 25 | #include <linux/of.h> |
| 26 | #include <linux/of_device.h> |
Robert Jarzmik | a770d94 | 2015-12-12 23:55:21 +0100 | [diff] [blame] | 27 | #include <linux/pinctrl/consumer.h> |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 28 | #include <linux/platform_device.h> |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 29 | #include <linux/syscore_ops.h> |
Daniel Mack | 4aa7826 | 2009-06-19 22:56:09 +0200 | [diff] [blame] | 30 | #include <linux/slab.h> |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 31 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 32 | /* |
| 33 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with |
| 34 | * one set of registers. The register offsets are organized below: |
| 35 | * |
| 36 | * GPLR GPDR GPSR GPCR GRER GFER GEDR |
| 37 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 |
| 38 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C |
| 39 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 |
| 40 | * |
| 41 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 |
| 42 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C |
| 43 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 |
| 44 | * |
Rob Herring | 684bba2 | 2015-01-26 22:46:06 -0600 | [diff] [blame] | 45 | * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 |
| 46 | * |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 47 | * NOTE: |
| 48 | * BANK 3 is only available on PXA27x and later processors. |
Rob Herring | 684bba2 | 2015-01-26 22:46:06 -0600 | [diff] [blame] | 49 | * BANK 4 and 5 are only available on PXA935, PXA1928 |
| 50 | * BANK 6 is only available on PXA1928 |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 51 | */ |
| 52 | |
| 53 | #define GPLR_OFFSET 0x00 |
| 54 | #define GPDR_OFFSET 0x0C |
| 55 | #define GPSR_OFFSET 0x18 |
| 56 | #define GPCR_OFFSET 0x24 |
| 57 | #define GRER_OFFSET 0x30 |
| 58 | #define GFER_OFFSET 0x3C |
| 59 | #define GEDR_OFFSET 0x48 |
| 60 | #define GAFR_OFFSET 0x54 |
Haojian Zhuang | be24168 | 2011-10-17 21:07:15 +0800 | [diff] [blame] | 61 | #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 62 | |
Rob Herring | 1e970b7 | 2015-03-02 15:30:58 -0600 | [diff] [blame] | 63 | #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2) |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 64 | |
Eric Miao | 3b8e285 | 2009-01-07 11:30:49 +0800 | [diff] [blame] | 65 | int pxa_last_gpio; |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame] | 66 | static int irq_base; |
Eric Miao | 3b8e285 | 2009-01-07 11:30:49 +0800 | [diff] [blame] | 67 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 68 | struct pxa_gpio_bank { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 69 | void __iomem *regbase; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 70 | unsigned long irq_mask; |
| 71 | unsigned long irq_edge_rise; |
| 72 | unsigned long irq_edge_fall; |
| 73 | |
| 74 | #ifdef CONFIG_PM |
| 75 | unsigned long saved_gplr; |
| 76 | unsigned long saved_gpdr; |
| 77 | unsigned long saved_grer; |
| 78 | unsigned long saved_gfer; |
| 79 | #endif |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 80 | }; |
| 81 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 82 | struct pxa_gpio_chip { |
| 83 | struct device *dev; |
| 84 | struct gpio_chip chip; |
| 85 | struct pxa_gpio_bank *banks; |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 86 | struct irq_domain *irqdomain; |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 87 | |
| 88 | int irq0; |
| 89 | int irq1; |
| 90 | int (*set_wake)(unsigned int gpio, unsigned int on); |
| 91 | }; |
| 92 | |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 93 | enum pxa_gpio_type { |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 94 | PXA25X_GPIO = 0, |
| 95 | PXA26X_GPIO, |
| 96 | PXA27X_GPIO, |
| 97 | PXA3XX_GPIO, |
| 98 | PXA93X_GPIO, |
| 99 | MMP_GPIO = 0x10, |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 100 | MMP2_GPIO, |
Rob Herring | 684bba2 | 2015-01-26 22:46:06 -0600 | [diff] [blame] | 101 | PXA1928_GPIO, |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 102 | }; |
| 103 | |
| 104 | struct pxa_gpio_id { |
| 105 | enum pxa_gpio_type type; |
| 106 | int gpio_nums; |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 107 | }; |
| 108 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 109 | static DEFINE_SPINLOCK(gpio_lock); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 110 | static struct pxa_gpio_chip *pxa_gpio_chip; |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 111 | static enum pxa_gpio_type gpio_type; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 112 | |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 113 | static struct pxa_gpio_id pxa25x_id = { |
| 114 | .type = PXA25X_GPIO, |
| 115 | .gpio_nums = 85, |
| 116 | }; |
| 117 | |
| 118 | static struct pxa_gpio_id pxa26x_id = { |
| 119 | .type = PXA26X_GPIO, |
| 120 | .gpio_nums = 90, |
| 121 | }; |
| 122 | |
| 123 | static struct pxa_gpio_id pxa27x_id = { |
| 124 | .type = PXA27X_GPIO, |
| 125 | .gpio_nums = 121, |
| 126 | }; |
| 127 | |
| 128 | static struct pxa_gpio_id pxa3xx_id = { |
| 129 | .type = PXA3XX_GPIO, |
| 130 | .gpio_nums = 128, |
| 131 | }; |
| 132 | |
| 133 | static struct pxa_gpio_id pxa93x_id = { |
| 134 | .type = PXA93X_GPIO, |
| 135 | .gpio_nums = 192, |
| 136 | }; |
| 137 | |
| 138 | static struct pxa_gpio_id mmp_id = { |
| 139 | .type = MMP_GPIO, |
| 140 | .gpio_nums = 128, |
| 141 | }; |
| 142 | |
| 143 | static struct pxa_gpio_id mmp2_id = { |
| 144 | .type = MMP2_GPIO, |
| 145 | .gpio_nums = 192, |
| 146 | }; |
| 147 | |
Rob Herring | 684bba2 | 2015-01-26 22:46:06 -0600 | [diff] [blame] | 148 | static struct pxa_gpio_id pxa1928_id = { |
| 149 | .type = PXA1928_GPIO, |
| 150 | .gpio_nums = 224, |
| 151 | }; |
| 152 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 153 | #define for_each_gpio_bank(i, b, pc) \ |
| 154 | for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 155 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 156 | static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 157 | { |
Linus Walleij | 81d0c31 | 2015-12-07 11:42:22 +0100 | [diff] [blame] | 158 | struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 159 | |
| 160 | return pxa_chip; |
| 161 | } |
Linus Walleij | 81d0c31 | 2015-12-07 11:42:22 +0100 | [diff] [blame] | 162 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 163 | static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio) |
| 164 | { |
Linus Walleij | 81d0c31 | 2015-12-07 11:42:22 +0100 | [diff] [blame] | 165 | struct pxa_gpio_chip *p = gpiochip_get_data(c); |
| 166 | struct pxa_gpio_bank *bank = p->banks + (gpio / 32); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 167 | |
| 168 | return bank->regbase; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 169 | } |
| 170 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 171 | static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c, |
| 172 | unsigned gpio) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 173 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 174 | return chip_to_pxachip(c)->banks + gpio / 32; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 175 | } |
| 176 | |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 177 | static inline int gpio_is_pxa_type(int type) |
| 178 | { |
| 179 | return (type & MMP_GPIO) == 0; |
| 180 | } |
| 181 | |
| 182 | static inline int gpio_is_mmp_type(int type) |
| 183 | { |
| 184 | return (type & MMP_GPIO) != 0; |
| 185 | } |
| 186 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 187 | /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, |
| 188 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. |
| 189 | */ |
| 190 | static inline int __gpio_is_inverted(int gpio) |
| 191 | { |
| 192 | if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) |
| 193 | return 1; |
| 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | /* |
| 198 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate |
| 199 | * function of a GPIO, and GPDRx cannot be altered once configured. It |
| 200 | * is attributed as "occupied" here (I know this terminology isn't |
| 201 | * accurate, you are welcome to propose a better one :-) |
| 202 | */ |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 203 | static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio) |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 204 | { |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 205 | void __iomem *base; |
| 206 | unsigned long gafr = 0, gpdr = 0; |
| 207 | int ret, af = 0, dir = 0; |
| 208 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 209 | base = gpio_bank_base(&pchip->chip, gpio); |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 210 | gpdr = readl_relaxed(base + GPDR_OFFSET); |
| 211 | |
| 212 | switch (gpio_type) { |
| 213 | case PXA25X_GPIO: |
| 214 | case PXA26X_GPIO: |
| 215 | case PXA27X_GPIO: |
| 216 | gafr = readl_relaxed(base + GAFR_OFFSET); |
| 217 | af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; |
| 218 | dir = gpdr & GPIO_bit(gpio); |
| 219 | |
| 220 | if (__gpio_is_inverted(gpio)) |
| 221 | ret = (af != 1) || (dir == 0); |
| 222 | else |
| 223 | ret = (af != 0) || (dir != 0); |
| 224 | break; |
| 225 | default: |
| 226 | ret = gpdr & GPIO_bit(gpio); |
| 227 | break; |
| 228 | } |
| 229 | return ret; |
| 230 | } |
| 231 | |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 232 | int pxa_irq_to_gpio(int irq) |
| 233 | { |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 234 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
| 235 | int irq_gpio0; |
| 236 | |
| 237 | irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0); |
| 238 | if (irq_gpio0 > 0) |
| 239 | return irq - irq_gpio0; |
| 240 | |
| 241 | return irq_gpio0; |
| 242 | } |
| 243 | |
| 244 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 245 | { |
| 246 | struct pxa_gpio_chip *pchip = chip_to_pxachip(chip); |
| 247 | |
| 248 | return irq_find_mapping(pchip->irqdomain, offset); |
Haojian Zhuang | 4929f5a | 2011-10-10 16:03:51 +0800 | [diff] [blame] | 249 | } |
| 250 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 251 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
| 252 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 253 | void __iomem *base = gpio_bank_base(chip, offset); |
| 254 | uint32_t value, mask = GPIO_bit(offset); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 255 | unsigned long flags; |
Robert Jarzmik | a770d94 | 2015-12-12 23:55:21 +0100 | [diff] [blame] | 256 | int ret; |
| 257 | |
| 258 | ret = pinctrl_gpio_direction_input(chip->base + offset); |
| 259 | if (!ret) |
| 260 | return 0; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 261 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 262 | spin_lock_irqsave(&gpio_lock, flags); |
| 263 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 264 | value = readl_relaxed(base + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 265 | if (__gpio_is_inverted(chip->base + offset)) |
| 266 | value |= mask; |
| 267 | else |
| 268 | value &= ~mask; |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 269 | writel_relaxed(value, base + GPDR_OFFSET); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 270 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 271 | spin_unlock_irqrestore(&gpio_lock, flags); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | static int pxa_gpio_direction_output(struct gpio_chip *chip, |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 276 | unsigned offset, int value) |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 277 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 278 | void __iomem *base = gpio_bank_base(chip, offset); |
| 279 | uint32_t tmp, mask = GPIO_bit(offset); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 280 | unsigned long flags; |
Robert Jarzmik | a770d94 | 2015-12-12 23:55:21 +0100 | [diff] [blame] | 281 | int ret; |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 282 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 283 | writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 284 | |
Robert Jarzmik | a770d94 | 2015-12-12 23:55:21 +0100 | [diff] [blame] | 285 | ret = pinctrl_gpio_direction_output(chip->base + offset); |
Robert Jarzmik | c4e5ffb | 2016-03-29 10:04:00 +0200 | [diff] [blame^] | 286 | if (ret) |
| 287 | return ret; |
Robert Jarzmik | a770d94 | 2015-12-12 23:55:21 +0100 | [diff] [blame] | 288 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 289 | spin_lock_irqsave(&gpio_lock, flags); |
| 290 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 291 | tmp = readl_relaxed(base + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 292 | if (__gpio_is_inverted(chip->base + offset)) |
| 293 | tmp &= ~mask; |
| 294 | else |
| 295 | tmp |= mask; |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 296 | writel_relaxed(tmp, base + GPDR_OFFSET); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 297 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 298 | spin_unlock_irqrestore(&gpio_lock, flags); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 299 | return 0; |
| 300 | } |
| 301 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 302 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 303 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 304 | void __iomem *base = gpio_bank_base(chip, offset); |
| 305 | u32 gplr = readl_relaxed(base + GPLR_OFFSET); |
| 306 | |
| 307 | return !!(gplr & GPIO_bit(offset)); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 308 | } |
| 309 | |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 310 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 311 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 312 | void __iomem *base = gpio_bank_base(chip, offset); |
| 313 | |
| 314 | writel_relaxed(GPIO_bit(offset), |
| 315 | base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
Philipp Zabel | 1c44f5f | 2008-02-04 22:28:22 -0800 | [diff] [blame] | 316 | } |
| 317 | |
Daniel Mack | 7212157 | 2012-07-25 17:35:39 +0200 | [diff] [blame] | 318 | #ifdef CONFIG_OF_GPIO |
| 319 | static int pxa_gpio_of_xlate(struct gpio_chip *gc, |
| 320 | const struct of_phandle_args *gpiospec, |
| 321 | u32 *flags) |
| 322 | { |
| 323 | if (gpiospec->args[0] > pxa_last_gpio) |
| 324 | return -EINVAL; |
| 325 | |
Daniel Mack | 7212157 | 2012-07-25 17:35:39 +0200 | [diff] [blame] | 326 | if (flags) |
| 327 | *flags = gpiospec->args[1]; |
| 328 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 329 | return gpiospec->args[0]; |
Daniel Mack | 7212157 | 2012-07-25 17:35:39 +0200 | [diff] [blame] | 330 | } |
| 331 | #endif |
| 332 | |
Robert Jarzmik | a770d94 | 2015-12-12 23:55:21 +0100 | [diff] [blame] | 333 | static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset) |
| 334 | { |
| 335 | return pinctrl_request_gpio(chip->base + offset); |
| 336 | } |
| 337 | |
| 338 | static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset) |
| 339 | { |
| 340 | pinctrl_free_gpio(chip->base + offset); |
| 341 | } |
| 342 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 343 | static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 344 | struct device_node *np, void __iomem *regbase) |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 345 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 346 | int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32); |
| 347 | struct pxa_gpio_bank *bank; |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 348 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 349 | pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks), |
| 350 | GFP_KERNEL); |
| 351 | if (!pchip->banks) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 352 | return -ENOMEM; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 353 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 354 | pchip->chip.label = "gpio-pxa"; |
| 355 | pchip->chip.direction_input = pxa_gpio_direction_input; |
| 356 | pchip->chip.direction_output = pxa_gpio_direction_output; |
| 357 | pchip->chip.get = pxa_gpio_get; |
| 358 | pchip->chip.set = pxa_gpio_set; |
| 359 | pchip->chip.to_irq = pxa_gpio_to_irq; |
| 360 | pchip->chip.ngpio = ngpio; |
Robert Jarzmik | a770d94 | 2015-12-12 23:55:21 +0100 | [diff] [blame] | 361 | pchip->chip.request = pxa_gpio_request; |
| 362 | pchip->chip.free = pxa_gpio_free; |
Daniel Mack | 7212157 | 2012-07-25 17:35:39 +0200 | [diff] [blame] | 363 | #ifdef CONFIG_OF_GPIO |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 364 | pchip->chip.of_node = np; |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 365 | pchip->chip.of_xlate = pxa_gpio_of_xlate; |
| 366 | pchip->chip.of_gpio_n_cells = 2; |
Daniel Mack | 7212157 | 2012-07-25 17:35:39 +0200 | [diff] [blame] | 367 | #endif |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 368 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 369 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
| 370 | bank = pchip->banks + i; |
| 371 | bank->regbase = regbase + BANK_OFF(i); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 372 | } |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 373 | |
Linus Walleij | 81d0c31 | 2015-12-07 11:42:22 +0100 | [diff] [blame] | 374 | return gpiochip_add_data(&pchip->chip, pchip); |
Eric Miao | a58fbcd | 2009-01-06 17:37:37 +0800 | [diff] [blame] | 375 | } |
| 376 | |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 377 | /* Update only those GRERx and GFERx edge detection register bits if those |
| 378 | * bits are set in c->irq_mask |
| 379 | */ |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 380 | static inline void update_edge_detect(struct pxa_gpio_bank *c) |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 381 | { |
| 382 | uint32_t grer, gfer; |
| 383 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 384 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; |
| 385 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 386 | grer |= c->irq_edge_rise & c->irq_mask; |
| 387 | gfer |= c->irq_edge_fall & c->irq_mask; |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 388 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
| 389 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 390 | } |
| 391 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 392 | static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 393 | { |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 394 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
| 395 | unsigned int gpio = irqd_to_hwirq(d); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 396 | struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 397 | unsigned long gpdr, mask = GPIO_bit(gpio); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 398 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 399 | if (type == IRQ_TYPE_PROBE) { |
| 400 | /* Don't mess with enabled GPIOs using preconfigured edges or |
| 401 | * GPIOs set to alternate function or to output during probe |
| 402 | */ |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 403 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 404 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 405 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 406 | if (__gpio_is_occupied(pchip, gpio)) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 407 | return 0; |
eric miao | 689c04a | 2008-03-04 17:18:38 +0800 | [diff] [blame] | 408 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 409 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 410 | } |
| 411 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 412 | gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 413 | |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 414 | if (__gpio_is_inverted(gpio)) |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 415 | writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); |
Eric Miao | 067455a | 2008-11-26 18:12:04 +0800 | [diff] [blame] | 416 | else |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 417 | writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 418 | |
| 419 | if (type & IRQ_TYPE_EDGE_RISING) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 420 | c->irq_edge_rise |= mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 421 | else |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 422 | c->irq_edge_rise &= ~mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 423 | |
| 424 | if (type & IRQ_TYPE_EDGE_FALLING) |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 425 | c->irq_edge_fall |= mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 426 | else |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 427 | c->irq_edge_fall &= ~mask; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 428 | |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 429 | update_edge_detect(c); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 430 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 431 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 432 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
| 433 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); |
| 434 | return 0; |
| 435 | } |
| 436 | |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 437 | static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 438 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 439 | int loop, gpio, n, handled = 0; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 440 | unsigned long gedr; |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 441 | struct pxa_gpio_chip *pchip = d; |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 442 | struct pxa_gpio_bank *c; |
Chao Xie | 0d2ee5d | 2012-07-31 14:13:09 +0800 | [diff] [blame] | 443 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 444 | do { |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 445 | loop = 0; |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 446 | for_each_gpio_bank(gpio, c, pchip) { |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 447 | gedr = readl_relaxed(c->regbase + GEDR_OFFSET); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 448 | gedr = gedr & c->irq_mask; |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 449 | writel_relaxed(gedr, c->regbase + GEDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 450 | |
Wei Yongjun | d724f1c | 2012-09-14 10:36:59 +0800 | [diff] [blame] | 451 | for_each_set_bit(n, &gedr, BITS_PER_LONG) { |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 452 | loop = 1; |
| 453 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 454 | generic_handle_irq(gpio_to_irq(gpio + n)); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 455 | } |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 456 | } |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 457 | handled += loop; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 458 | } while (loop); |
Chao Xie | 0d2ee5d | 2012-07-31 14:13:09 +0800 | [diff] [blame] | 459 | |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 460 | return handled ? IRQ_HANDLED : IRQ_NONE; |
| 461 | } |
| 462 | |
| 463 | static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d) |
| 464 | { |
| 465 | struct pxa_gpio_chip *pchip = d; |
| 466 | |
| 467 | if (in_irq == pchip->irq0) { |
| 468 | generic_handle_irq(gpio_to_irq(0)); |
| 469 | } else if (in_irq == pchip->irq1) { |
| 470 | generic_handle_irq(gpio_to_irq(1)); |
| 471 | } else { |
| 472 | pr_err("%s() unknown irq %d\n", __func__, in_irq); |
| 473 | return IRQ_NONE; |
| 474 | } |
| 475 | return IRQ_HANDLED; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 476 | } |
| 477 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 478 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 479 | { |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 480 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
| 481 | unsigned int gpio = irqd_to_hwirq(d); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 482 | void __iomem *base = gpio_bank_base(&pchip->chip, gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 483 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 484 | writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 485 | } |
| 486 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 487 | static void pxa_mask_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 488 | { |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 489 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
| 490 | unsigned int gpio = irqd_to_hwirq(d); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 491 | struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio); |
| 492 | void __iomem *base = gpio_bank_base(&pchip->chip, gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 493 | uint32_t grer, gfer; |
| 494 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 495 | b->irq_mask &= ~GPIO_bit(gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 496 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 497 | grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio); |
| 498 | gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio); |
| 499 | writel_relaxed(grer, base + GRER_OFFSET); |
| 500 | writel_relaxed(gfer, base + GFER_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 501 | } |
| 502 | |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 503 | static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) |
| 504 | { |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 505 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
| 506 | unsigned int gpio = irqd_to_hwirq(d); |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 507 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 508 | if (pchip->set_wake) |
| 509 | return pchip->set_wake(gpio, on); |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 510 | else |
| 511 | return 0; |
| 512 | } |
| 513 | |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 514 | static void pxa_unmask_muxed_gpio(struct irq_data *d) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 515 | { |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 516 | struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); |
| 517 | unsigned int gpio = irqd_to_hwirq(d); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 518 | struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 519 | |
| 520 | c->irq_mask |= GPIO_bit(gpio); |
Eric Miao | a8f6fae | 2009-04-21 14:39:07 +0800 | [diff] [blame] | 521 | update_edge_detect(c); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 522 | } |
| 523 | |
| 524 | static struct irq_chip pxa_muxed_gpio_chip = { |
| 525 | .name = "GPIO", |
Lennert Buytenhek | a3f4c92 | 2010-11-29 11:18:26 +0100 | [diff] [blame] | 526 | .irq_ack = pxa_ack_muxed_gpio, |
| 527 | .irq_mask = pxa_mask_muxed_gpio, |
| 528 | .irq_unmask = pxa_unmask_muxed_gpio, |
| 529 | .irq_set_type = pxa_gpio_irq_type, |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 530 | .irq_set_wake = pxa_gpio_set_wake, |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 531 | }; |
| 532 | |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 533 | static int pxa_gpio_nums(struct platform_device *pdev) |
Haojian Zhuang | 478e223 | 2011-10-14 16:44:07 +0800 | [diff] [blame] | 534 | { |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 535 | const struct platform_device_id *id = platform_get_device_id(pdev); |
| 536 | struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; |
Haojian Zhuang | 478e223 | 2011-10-14 16:44:07 +0800 | [diff] [blame] | 537 | int count = 0; |
| 538 | |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 539 | switch (pxa_id->type) { |
| 540 | case PXA25X_GPIO: |
| 541 | case PXA26X_GPIO: |
| 542 | case PXA27X_GPIO: |
| 543 | case PXA3XX_GPIO: |
| 544 | case PXA93X_GPIO: |
| 545 | case MMP_GPIO: |
| 546 | case MMP2_GPIO: |
Rob Herring | 684bba2 | 2015-01-26 22:46:06 -0600 | [diff] [blame] | 547 | case PXA1928_GPIO: |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 548 | gpio_type = pxa_id->type; |
| 549 | count = pxa_id->gpio_nums - 1; |
| 550 | break; |
| 551 | default: |
| 552 | count = -EINVAL; |
| 553 | break; |
Haojian Zhuang | 478e223 | 2011-10-14 16:44:07 +0800 | [diff] [blame] | 554 | } |
Haojian Zhuang | 478e223 | 2011-10-14 16:44:07 +0800 | [diff] [blame] | 555 | return count; |
| 556 | } |
| 557 | |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 558 | static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 559 | irq_hw_number_t hw) |
| 560 | { |
| 561 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
| 562 | handle_edge_irq); |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 563 | irq_set_chip_data(irq, d->host_data); |
Rob Herring | 23393d4 | 2015-07-27 15:55:16 -0500 | [diff] [blame] | 564 | irq_set_noprobe(irq); |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 565 | return 0; |
| 566 | } |
| 567 | |
| 568 | const struct irq_domain_ops pxa_irq_domain_ops = { |
| 569 | .map = pxa_irq_domain_map, |
Daniel Mack | 7212157 | 2012-07-25 17:35:39 +0200 | [diff] [blame] | 570 | .xlate = irq_domain_xlate_twocell, |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 571 | }; |
| 572 | |
Robert Jarzmik | 0440091 | 2015-12-18 21:40:40 +0100 | [diff] [blame] | 573 | #ifdef CONFIG_OF |
| 574 | static const struct of_device_id pxa_gpio_dt_ids[] = { |
| 575 | { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, |
| 576 | { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, |
| 577 | { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, |
| 578 | { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, |
| 579 | { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, |
| 580 | { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, |
| 581 | { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, |
| 582 | { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, }, |
| 583 | {} |
| 584 | }; |
| 585 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 586 | static int pxa_gpio_probe_dt(struct platform_device *pdev, |
| 587 | struct pxa_gpio_chip *pchip) |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 588 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 589 | int nr_gpios; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 590 | const struct of_device_id *of_id = |
| 591 | of_match_device(pxa_gpio_dt_ids, &pdev->dev); |
Haojian Zhuang | f873117 | 2013-04-09 22:27:50 +0800 | [diff] [blame] | 592 | const struct pxa_gpio_id *gpio_id; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 593 | |
Haojian Zhuang | f873117 | 2013-04-09 22:27:50 +0800 | [diff] [blame] | 594 | if (!of_id || !of_id->data) { |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 595 | dev_err(&pdev->dev, "Failed to find gpio controller\n"); |
| 596 | return -EFAULT; |
| 597 | } |
Haojian Zhuang | f873117 | 2013-04-09 22:27:50 +0800 | [diff] [blame] | 598 | gpio_id = of_id->data; |
| 599 | gpio_type = gpio_id->type; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 600 | |
Haojian Zhuang | f873117 | 2013-04-09 22:27:50 +0800 | [diff] [blame] | 601 | nr_gpios = gpio_id->gpio_nums; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 602 | pxa_last_gpio = nr_gpios - 1; |
| 603 | |
| 604 | irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); |
| 605 | if (irq_base < 0) { |
| 606 | dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 607 | return irq_base; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 608 | } |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 609 | return irq_base; |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 610 | } |
| 611 | #else |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 612 | #define pxa_gpio_probe_dt(pdev, pchip) (-1) |
Haojian Zhuang | 7a4d507 | 2012-04-13 15:15:45 +0800 | [diff] [blame] | 613 | #endif |
| 614 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 615 | static int pxa_gpio_probe(struct platform_device *pdev) |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 616 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 617 | struct pxa_gpio_chip *pchip; |
| 618 | struct pxa_gpio_bank *c; |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 619 | struct resource *res; |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 620 | struct clk *clk; |
Robert Jarzmik | b95ace5 | 2012-04-22 13:37:24 +0200 | [diff] [blame] | 621 | struct pxa_gpio_platform_data *info; |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 622 | void __iomem *gpio_reg_base; |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 623 | int gpio, ret; |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 624 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 625 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 626 | pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL); |
| 627 | if (!pchip) |
| 628 | return -ENOMEM; |
| 629 | pchip->dev = &pdev->dev; |
| 630 | |
Haojian Zhuang | b8f649f | 2013-04-09 18:12:04 +0800 | [diff] [blame] | 631 | info = dev_get_platdata(&pdev->dev); |
| 632 | if (info) { |
| 633 | irq_base = info->irq_base; |
| 634 | if (irq_base <= 0) |
| 635 | return -EINVAL; |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 636 | pxa_last_gpio = pxa_gpio_nums(pdev); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 637 | pchip->set_wake = info->gpio_set_wake; |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame] | 638 | } else { |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 639 | irq_base = pxa_gpio_probe_dt(pdev, pchip); |
| 640 | if (irq_base < 0) |
Haojian Zhuang | b8f649f | 2013-04-09 18:12:04 +0800 | [diff] [blame] | 641 | return -EINVAL; |
Daniel Mack | 9450be7 | 2012-07-22 16:55:44 +0200 | [diff] [blame] | 642 | } |
| 643 | |
Haojian Zhuang | 478e223 | 2011-10-14 16:44:07 +0800 | [diff] [blame] | 644 | if (!pxa_last_gpio) |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 645 | return -EINVAL; |
| 646 | |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 647 | pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node, |
| 648 | pxa_last_gpio + 1, irq_base, |
| 649 | 0, &pxa_irq_domain_ops, pchip); |
Dan Carpenter | 41d107a | 2016-01-05 12:56:37 +0300 | [diff] [blame] | 650 | if (!pchip->irqdomain) |
| 651 | return -ENOMEM; |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 652 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 653 | irq0 = platform_get_irq_byname(pdev, "gpio0"); |
| 654 | irq1 = platform_get_irq_byname(pdev, "gpio1"); |
| 655 | irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); |
| 656 | if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) |
| 657 | || (irq_mux <= 0)) |
| 658 | return -EINVAL; |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 659 | |
| 660 | pchip->irq0 = irq0; |
| 661 | pchip->irq1 = irq1; |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 662 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Robert Jarzmik | 8852b2f | 2015-11-28 22:37:43 +0100 | [diff] [blame] | 663 | gpio_reg_base = devm_ioremap(&pdev->dev, res->start, |
| 664 | resource_size(res)); |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 665 | if (!gpio_reg_base) |
| 666 | return -EINVAL; |
| 667 | |
| 668 | if (irq0 > 0) |
| 669 | gpio_offset = 2; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 670 | |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 671 | clk = clk_get(&pdev->dev, NULL); |
| 672 | if (IS_ERR(clk)) { |
| 673 | dev_err(&pdev->dev, "Error %ld to get gpio clock\n", |
| 674 | PTR_ERR(clk)); |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 675 | return PTR_ERR(clk); |
| 676 | } |
Julia Lawall | 6ab49f4 | 2012-08-26 18:00:55 +0200 | [diff] [blame] | 677 | ret = clk_prepare_enable(clk); |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 678 | if (ret) { |
| 679 | clk_put(clk); |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 680 | return ret; |
| 681 | } |
Haojian Zhuang | 389eda1 | 2011-10-17 21:26:55 +0800 | [diff] [blame] | 682 | |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 683 | /* Initialize GPIO chips */ |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 684 | ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node, |
| 685 | gpio_reg_base); |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 686 | if (ret) { |
| 687 | clk_put(clk); |
| 688 | return ret; |
| 689 | } |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 690 | |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 691 | /* clear all GPIO edge detects */ |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 692 | for_each_gpio_bank(gpio, c, pchip) { |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 693 | writel_relaxed(0, c->regbase + GFER_OFFSET); |
| 694 | writel_relaxed(0, c->regbase + GRER_OFFSET); |
Laurent Navet | e37f4af | 2013-03-20 13:15:59 +0100 | [diff] [blame] | 695 | writel_relaxed(~0, c->regbase + GEDR_OFFSET); |
Haojian Zhuang | be24168 | 2011-10-17 21:07:15 +0800 | [diff] [blame] | 696 | /* unmask GPIO edge detect for AP side */ |
| 697 | if (gpio_is_mmp_type(gpio_type)) |
| 698 | writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 699 | } |
| 700 | |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 701 | if (irq0 > 0) { |
| 702 | ret = devm_request_irq(&pdev->dev, |
| 703 | irq0, pxa_gpio_direct_handler, 0, |
| 704 | "gpio-0", pchip); |
| 705 | if (ret) |
| 706 | dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n", |
| 707 | ret); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 708 | } |
Robert Jarzmik | 384ca3c | 2015-11-28 22:37:44 +0100 | [diff] [blame] | 709 | if (irq1 > 0) { |
| 710 | ret = devm_request_irq(&pdev->dev, |
| 711 | irq1, pxa_gpio_direct_handler, 0, |
| 712 | "gpio-1", pchip); |
| 713 | if (ret) |
| 714 | dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n", |
| 715 | ret); |
| 716 | } |
| 717 | ret = devm_request_irq(&pdev->dev, |
| 718 | irq_mux, pxa_gpio_demux_handler, 0, |
| 719 | "gpio-mux", pchip); |
| 720 | if (ret) |
| 721 | dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n", |
| 722 | ret); |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 723 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 724 | pxa_gpio_chip = pchip; |
Rob Herring | ae4f4cf | 2015-01-26 22:46:04 -0600 | [diff] [blame] | 725 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 726 | return 0; |
eric miao | e3630db | 2008-03-04 11:42:26 +0800 | [diff] [blame] | 727 | } |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 728 | |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 729 | static const struct platform_device_id gpio_id_table[] = { |
| 730 | { "pxa25x-gpio", (unsigned long)&pxa25x_id }, |
| 731 | { "pxa26x-gpio", (unsigned long)&pxa26x_id }, |
| 732 | { "pxa27x-gpio", (unsigned long)&pxa27x_id }, |
| 733 | { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, |
| 734 | { "pxa93x-gpio", (unsigned long)&pxa93x_id }, |
| 735 | { "mmp-gpio", (unsigned long)&mmp_id }, |
| 736 | { "mmp2-gpio", (unsigned long)&mmp2_id }, |
Rob Herring | 684bba2 | 2015-01-26 22:46:06 -0600 | [diff] [blame] | 737 | { "pxa1928-gpio", (unsigned long)&pxa1928_id }, |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 738 | { }, |
| 739 | }; |
| 740 | |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 741 | static struct platform_driver pxa_gpio_driver = { |
| 742 | .probe = pxa_gpio_probe, |
| 743 | .driver = { |
| 744 | .name = "pxa-gpio", |
Arnd Bergmann | f43e04e | 2012-08-13 14:36:10 +0000 | [diff] [blame] | 745 | .of_match_table = of_match_ptr(pxa_gpio_dt_ids), |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 746 | }, |
Haojian Zhuang | 2cab029 | 2013-04-07 16:44:33 +0800 | [diff] [blame] | 747 | .id_table = gpio_id_table, |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 748 | }; |
Linus Walleij | cf3fa17 | 2013-04-24 21:41:20 +0200 | [diff] [blame] | 749 | |
Robert Jarzmik | eae122b | 2015-11-13 21:22:38 +0100 | [diff] [blame] | 750 | static int __init pxa_gpio_legacy_init(void) |
Linus Walleij | cf3fa17 | 2013-04-24 21:41:20 +0200 | [diff] [blame] | 751 | { |
Robert Jarzmik | eae122b | 2015-11-13 21:22:38 +0100 | [diff] [blame] | 752 | if (of_have_populated_dt()) |
| 753 | return 0; |
| 754 | |
Linus Walleij | cf3fa17 | 2013-04-24 21:41:20 +0200 | [diff] [blame] | 755 | return platform_driver_register(&pxa_gpio_driver); |
| 756 | } |
Robert Jarzmik | eae122b | 2015-11-13 21:22:38 +0100 | [diff] [blame] | 757 | postcore_initcall(pxa_gpio_legacy_init); |
| 758 | |
| 759 | static int __init pxa_gpio_dt_init(void) |
| 760 | { |
| 761 | if (of_have_populated_dt()) |
| 762 | return platform_driver_register(&pxa_gpio_driver); |
| 763 | |
| 764 | return 0; |
| 765 | } |
| 766 | device_initcall(pxa_gpio_dt_init); |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 767 | |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 768 | #ifdef CONFIG_PM |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 769 | static int pxa_gpio_suspend(void) |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 770 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 771 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
| 772 | struct pxa_gpio_bank *c; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 773 | int gpio; |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 774 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 775 | for_each_gpio_bank(gpio, c, pchip) { |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 776 | c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); |
| 777 | c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
| 778 | c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); |
| 779 | c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 780 | |
| 781 | /* Clear GPIO transition detect bits */ |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 782 | writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 783 | } |
| 784 | return 0; |
| 785 | } |
| 786 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 787 | static void pxa_gpio_resume(void) |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 788 | { |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 789 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
| 790 | struct pxa_gpio_bank *c; |
Eric Miao | 0807da5 | 2009-01-07 18:01:51 +0800 | [diff] [blame] | 791 | int gpio; |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 792 | |
Robert Jarzmik | fc0589c | 2015-11-28 22:37:42 +0100 | [diff] [blame] | 793 | for_each_gpio_bank(gpio, c, pchip) { |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 794 | /* restore level with set/clear */ |
Laurent Navet | e37f4af | 2013-03-20 13:15:59 +0100 | [diff] [blame] | 795 | writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 796 | writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 797 | |
Haojian Zhuang | df664d2 | 2011-10-14 17:24:03 +0800 | [diff] [blame] | 798 | writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); |
| 799 | writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); |
| 800 | writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 801 | } |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 802 | } |
| 803 | #else |
| 804 | #define pxa_gpio_suspend NULL |
| 805 | #define pxa_gpio_resume NULL |
| 806 | #endif |
| 807 | |
Rafael J. Wysocki | 2eaa03b | 2011-04-22 22:03:11 +0200 | [diff] [blame] | 808 | struct syscore_ops pxa_gpio_syscore_ops = { |
eric miao | 663707c | 2008-03-04 16:13:58 +0800 | [diff] [blame] | 809 | .suspend = pxa_gpio_suspend, |
| 810 | .resume = pxa_gpio_resume, |
| 811 | }; |
Haojian Zhuang | 157d264 | 2011-10-17 20:37:52 +0800 | [diff] [blame] | 812 | |
| 813 | static int __init pxa_gpio_sysinit(void) |
| 814 | { |
| 815 | register_syscore_ops(&pxa_gpio_syscore_ops); |
| 816 | return 0; |
| 817 | } |
| 818 | postcore_initcall(pxa_gpio_sysinit); |