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H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H
Thomas Gleixner67c5fc52008-01-30 13:30:15 +01003
Ingo Molnare2780a62009-02-17 13:52:29 +01004#include <linux/cpumask.h>
Thomas Gleixner67c5fc52008-01-30 13:30:15 +01005#include <linux/delay.h>
Ingo Molnare2780a62009-02-17 13:52:29 +01006#include <linux/pm.h>
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +01007
8#include <asm/alternative.h>
Suresh Siddha13c88fb52008-07-10 11:16:52 -07009#include <asm/cpufeature.h>
Ingo Molnare2780a62009-02-17 13:52:29 +010010#include <asm/processor.h>
11#include <asm/apicdef.h>
12#include <asm/atomic.h>
13#include <asm/fixmap.h>
14#include <asm/mpspec.h>
15#include <asm/system.h>
Suresh Siddha13c88fb52008-07-10 11:16:52 -070016#include <asm/msr.h>
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010017
18#define ARCH_APICTIMER_STOPS_ON_C3 1
19
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010020/*
21 * Debugging macros
22 */
23#define APIC_QUIET 0
24#define APIC_VERBOSE 1
25#define APIC_DEBUG 2
26
27/*
28 * Define the default level of output to be very little
29 * This can be turned up by using apic=verbose for more
30 * information and apic=debug for _lots_ of information.
31 * apic_verbosity is defined in apic.c
32 */
33#define apic_printk(v, s, a...) do { \
34 if ((v) <= apic_verbosity) \
35 printk(s, ##a); \
36 } while (0)
37
38
Ingo Molnar160d8da2009-02-11 11:27:39 +010039#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010040extern void generic_apic_probe(void);
Ingo Molnar160d8da2009-02-11 11:27:39 +010041#else
42static inline void generic_apic_probe(void)
43{
44}
45#endif
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010046
47#ifdef CONFIG_X86_LOCAL_APIC
48
Maciej W. Rozyckibaa13182008-07-14 18:44:51 +010049extern unsigned int apic_verbosity;
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010050extern int local_apic_timer_c2_ok;
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010051
Yinghai Lu3c999f12008-06-20 16:11:20 -070052extern int disable_apic;
Ingo Molnar0939e4f2009-01-28 17:16:25 +010053
54#ifdef CONFIG_SMP
55extern void __inquire_remote_apic(int apicid);
56#else /* CONFIG_SMP */
57static inline void __inquire_remote_apic(int apicid)
58{
59}
60#endif /* CONFIG_SMP */
61
62static inline void default_inquire_remote_apic(int apicid)
63{
64 if (apic_verbosity >= APIC_DEBUG)
65 __inquire_remote_apic(apicid);
66}
67
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010068/*
Cyrill Gorcunov83121362009-09-15 11:12:30 +040069 * With 82489DX we can't rely on apic feature bit
70 * retrieved via cpuid but still have to deal with
71 * such an apic chip so we assume that SMP configuration
72 * is found from MP table (64bit case uses ACPI mostly
73 * which set smp presence flag as well so we are safe
74 * to use this helper too).
75 */
76static inline bool apic_from_smp_config(void)
77{
78 return smp_found_config && !disable_apic;
79}
80
81/*
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010082 * Basic functions accessing APICs.
83 */
84#ifdef CONFIG_PARAVIRT
85#include <asm/paravirt.h>
Thomas Gleixner96a388d2007-10-11 11:20:03 +020086#endif
Thomas Gleixner67c5fc52008-01-30 13:30:15 +010087
Ravikiran G Thirumalai70511132009-03-23 23:14:29 -070088#ifdef CONFIG_X86_64
Ravikiran G Thirumalaiaa7d8e25e2008-03-20 00:41:16 -070089extern int is_vsmp_box(void);
Yinghai Lu129d8bc2009-02-25 21:20:50 -080090#else
91static inline int is_vsmp_box(void)
92{
93 return 0;
94}
95#endif
Jaswinder Singh2b97df02008-07-23 17:13:14 +053096extern void xapic_wait_icr_idle(void);
97extern u32 safe_xapic_wait_icr_idle(void);
Jaswinder Singh2b97df02008-07-23 17:13:14 +053098extern void xapic_icr_write(u32, u32);
99extern int setup_profiling_timer(unsigned int);
Ravikiran G Thirumalaiaa7d8e25e2008-03-20 00:41:16 -0700100
Suresh Siddha1b374e42008-07-10 11:16:49 -0700101static inline void native_apic_mem_write(u32 reg, u32 v)
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100102{
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +0100103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100104
Maciej W. Rozycki593f4a72008-07-16 19:15:30 +0100105 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
106 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
107 ASM_OUTPUT2("0" (v), "m" (*addr)));
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100108}
109
Suresh Siddha1b374e42008-07-10 11:16:49 -0700110static inline u32 native_apic_mem_read(u32 reg)
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100111{
112 return *((volatile u32 *)(APIC_BASE + reg));
113}
114
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800115extern void native_apic_wait_icr_idle(void);
116extern u32 native_safe_apic_wait_icr_idle(void);
117extern void native_apic_icr_write(u32 low, u32 id);
118extern u64 native_apic_icr_read(void);
119
Suresh Siddhafc1edaf2009-04-20 13:02:27 -0700120extern int x2apic_mode;
Fenghua Yub24696b2009-03-27 14:22:44 -0700121
Han, Weidongd0b03bd2009-04-03 17:15:50 +0800122#ifdef CONFIG_X86_X2APIC
Suresh Siddhace4e2402009-03-17 10:16:54 -0800123/*
124 * Make previous memory operations globally visible before
125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
126 * mfence for this.
127 */
128static inline void x2apic_wrmsr_fence(void)
129{
130 asm volatile("mfence" : : : "memory");
131}
132
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700133static inline void native_apic_msr_write(u32 reg, u32 v)
134{
135 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
136 reg == APIC_LVR)
137 return;
138
139 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
140}
141
142static inline u32 native_apic_msr_read(u32 reg)
143{
144 u32 low, high;
145
146 if (reg == APIC_DFR)
147 return -1;
148
149 rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
150 return low;
151}
152
Yinghai Luc1eeb2d2009-02-16 23:02:14 -0800153static inline void native_x2apic_wait_icr_idle(void)
154{
155 /* no need to wait for icr idle in x2apic */
156 return;
157}
158
159static inline u32 native_safe_x2apic_wait_icr_idle(void)
160{
161 /* no need to wait for icr idle in x2apic */
162 return 0;
163}
164
165static inline void native_x2apic_icr_write(u32 low, u32 id)
166{
167 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
168}
169
170static inline u64 native_x2apic_icr_read(void)
171{
172 unsigned long val;
173
174 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
175 return val;
176}
177
Suresh Siddhafc1edaf2009-04-20 13:02:27 -0700178extern int x2apic_phys;
Suresh Siddha6e1cb382008-07-10 11:16:58 -0700179extern void check_x2apic(void);
180extern void enable_x2apic(void);
Suresh Siddha6e1cb382008-07-10 11:16:58 -0700181extern void x2apic_icr_write(u32 low, u32 id);
Yinghai Lua11b5ab2008-09-03 16:58:31 -0700182static inline int x2apic_enabled(void)
183{
184 int msr, msr2;
185
186 if (!cpu_has_x2apic)
187 return 0;
188
189 rdmsr(MSR_IA32_APICBASE, msr, msr2);
190 if (msr & X2APIC_ENABLE)
191 return 1;
192 return 0;
193}
Suresh Siddhafc1edaf2009-04-20 13:02:27 -0700194
195#define x2apic_supported() (cpu_has_x2apic)
Gleb Natapovce69a782009-07-20 15:24:17 +0300196static inline void x2apic_force_phys(void)
197{
198 x2apic_phys = 1;
199}
Yinghai Lua11b5ab2008-09-03 16:58:31 -0700200#else
Yinghai Lu06cd9a72009-02-16 17:29:58 -0800201static inline void check_x2apic(void)
202{
203}
204static inline void enable_x2apic(void)
205{
206}
Yinghai Lu06cd9a72009-02-16 17:29:58 -0800207static inline int x2apic_enabled(void)
208{
209 return 0;
210}
Gleb Natapovce69a782009-07-20 15:24:17 +0300211static inline void x2apic_force_phys(void)
212{
213}
Suresh Siddhacf6567f2009-03-16 17:05:00 -0700214
Weidong Han93758232009-04-17 16:42:14 +0800215#define x2apic_preenabled 0
Suresh Siddhafc1edaf2009-04-20 13:02:27 -0700216#define x2apic_supported() 0
Yinghai Luc535b6a2008-07-11 18:41:54 -0700217#endif
Suresh Siddha1b374e42008-07-10 11:16:49 -0700218
Weidong Han93758232009-04-17 16:42:14 +0800219extern void enable_IR_x2apic(void);
220
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100221extern int get_physical_broadcast(void);
222
Cyrill Gorcunov08306ce2009-04-12 20:47:41 +0400223extern void apic_disable(void);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100224extern int lapic_get_maxlvt(void);
225extern void clear_local_APIC(void);
226extern void connect_bsp_APIC(void);
227extern void disconnect_bsp_APIC(int virt_wire_setup);
228extern void disable_local_APIC(void);
229extern void lapic_shutdown(void);
230extern int verify_local_APIC(void);
231extern void cache_APIC_registers(void);
232extern void sync_Arb_IDs(void);
233extern void init_bsp_APIC(void);
234extern void setup_local_APIC(void);
Andi Kleen739f33b2008-01-30 13:30:40 +0100235extern void end_local_APIC_setup(void);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100236extern void init_apic_mappings(void);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100237extern void setup_boot_APIC_clock(void);
238extern void setup_secondary_APIC_clock(void);
239extern int APIC_init_uniprocessor(void);
Jan Beuliche9427102008-01-30 13:31:24 +0100240extern void enable_NMI_through_LVT0(void);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100241
242/*
243 * On 32bit this is mach-xxx local
244 */
245#ifdef CONFIG_X86_64
Yinghai Lu8643f9d2008-02-19 03:21:06 -0800246extern void early_init_lapic_mapping(void);
Alok Kataria8fbbc4b2008-07-01 11:43:34 -0700247extern int apic_is_clustered_box(void);
248#else
249static inline int apic_is_clustered_box(void)
250{
251 return 0;
252}
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100253#endif
254
Robert Richter7b83dae2008-01-30 13:30:40 +0100255extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
256extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100257
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100258
259#else /* !CONFIG_X86_LOCAL_APIC */
260static inline void lapic_shutdown(void) { }
261#define local_apic_timer_c2_ok 1
Yinghai Luf3294a32008-06-27 01:41:56 -0700262static inline void init_apic_mappings(void) { }
Ivan Vecerad3ec5ca2008-11-11 14:33:44 +0100263static inline void disable_local_APIC(void) { }
Cyrill Gorcunov08306ce2009-04-12 20:47:41 +0400264static inline void apic_disable(void) { }
Thomas Gleixner736deca2009-08-19 12:35:53 +0200265# define setup_boot_APIC_clock x86_init_noop
266# define setup_secondary_APIC_clock x86_init_noop
Thomas Gleixner67c5fc52008-01-30 13:30:15 +0100267#endif /* !CONFIG_X86_LOCAL_APIC */
268
Ingo Molnar1f75ed02009-01-28 17:36:56 +0100269#ifdef CONFIG_X86_64
270#define SET_APIC_ID(x) (apic->set_apic_id(x))
271#else
272
Ingo Molnar1f75ed02009-01-28 17:36:56 +0100273#endif
274
Ingo Molnare2780a62009-02-17 13:52:29 +0100275/*
276 * Copyright 2004 James Cleverdon, IBM.
277 * Subject to the GNU Public License, v.2
278 *
279 * Generic APIC sub-arch data struct.
280 *
281 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
282 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
283 * James Cleverdon.
284 */
Ingo Molnarbe163a12009-02-17 16:28:46 +0100285struct apic {
Ingo Molnare2780a62009-02-17 13:52:29 +0100286 char *name;
287
288 int (*probe)(void);
289 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
290 int (*apic_id_registered)(void);
291
292 u32 irq_delivery_mode;
293 u32 irq_dest_mode;
294
295 const struct cpumask *(*target_cpus)(void);
296
297 int disable_esr;
298
299 int dest_logical;
Cyrill Gorcunov7abc0752009-11-10 01:06:59 +0300300 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
Ingo Molnare2780a62009-02-17 13:52:29 +0100301 unsigned long (*check_apicid_present)(int apicid);
302
303 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
304 void (*init_apic_ldr)(void);
305
Cyrill Gorcunov7abc0752009-11-10 01:06:59 +0300306 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
Ingo Molnare2780a62009-02-17 13:52:29 +0100307
308 void (*setup_apic_routing)(void);
309 int (*multi_timer_check)(int apic, int irq);
310 int (*apicid_to_node)(int logical_apicid);
311 int (*cpu_to_logical_apicid)(int cpu);
312 int (*cpu_present_to_apicid)(int mps_cpu);
Cyrill Gorcunov7abc0752009-11-10 01:06:59 +0300313 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
Ingo Molnare2780a62009-02-17 13:52:29 +0100314 void (*setup_portio_remap)(void);
Thomas Gleixnere11dada2009-08-31 15:18:40 +0200315 int (*check_phys_apicid_present)(int phys_apicid);
Ingo Molnare2780a62009-02-17 13:52:29 +0100316 void (*enable_apic_mode)(void);
317 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
318
319 /*
Ingo Molnarbe163a12009-02-17 16:28:46 +0100320 * When one of the next two hooks returns 1 the apic
Ingo Molnare2780a62009-02-17 13:52:29 +0100321 * is switched to this. Essentially they are additional
322 * probe functions:
323 */
324 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
325
326 unsigned int (*get_apic_id)(unsigned long x);
327 unsigned long (*set_apic_id)(unsigned int id);
328 unsigned long apic_id_mask;
329
330 unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
331 unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
332 const struct cpumask *andmask);
333
334 /* ipi */
335 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
336 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
337 int vector);
338 void (*send_IPI_allbutself)(int vector);
339 void (*send_IPI_all)(int vector);
340 void (*send_IPI_self)(int vector);
341
342 /* wakeup_secondary_cpu */
Ingo Molnar1f5bcab2009-02-26 13:51:40 +0100343 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
Ingo Molnare2780a62009-02-17 13:52:29 +0100344
345 int trampoline_phys_low;
346 int trampoline_phys_high;
347
348 void (*wait_for_init_deassert)(atomic_t *deassert);
349 void (*smp_callin_clear_local_apic)(void);
Ingo Molnare2780a62009-02-17 13:52:29 +0100350 void (*inquire_remote_apic)(int apicid);
351
352 /* apic ops */
353 u32 (*read)(u32 reg);
354 void (*write)(u32 reg, u32 v);
355 u64 (*icr_read)(void);
356 void (*icr_write)(u32 low, u32 high);
357 void (*wait_icr_idle)(void);
358 u32 (*safe_wait_icr_idle)(void);
359};
360
Ingo Molnar0917c012009-02-26 12:47:40 +0100361/*
362 * Pointer to the local APIC driver in use on this system (there's
363 * always just one such driver in use - the kernel decides via an
364 * early probing process which one it picks - and then sticks to it):
365 */
Ingo Molnarbe163a12009-02-17 16:28:46 +0100366extern struct apic *apic;
Ingo Molnar0917c012009-02-26 12:47:40 +0100367
368/*
369 * APIC functionality to boot other CPUs - only used on SMP:
370 */
371#ifdef CONFIG_SMP
Yinghai Lu2b6163b2009-02-25 20:50:49 -0800372extern atomic_t init_deasserted;
373extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
Ingo Molnar0917c012009-02-26 12:47:40 +0100374#endif
Ingo Molnare2780a62009-02-17 13:52:29 +0100375
Cyrill Gorcunovd674cd12010-03-17 13:37:00 +0300376#ifdef CONFIG_X86_LOCAL_APIC
Ingo Molnare2780a62009-02-17 13:52:29 +0100377static inline u32 apic_read(u32 reg)
378{
379 return apic->read(reg);
380}
381
382static inline void apic_write(u32 reg, u32 val)
383{
384 apic->write(reg, val);
385}
386
387static inline u64 apic_icr_read(void)
388{
389 return apic->icr_read();
390}
391
392static inline void apic_icr_write(u32 low, u32 high)
393{
394 apic->icr_write(low, high);
395}
396
397static inline void apic_wait_icr_idle(void)
398{
399 apic->wait_icr_idle();
400}
401
402static inline u32 safe_apic_wait_icr_idle(void)
403{
404 return apic->safe_wait_icr_idle();
405}
406
Cyrill Gorcunovd674cd12010-03-17 13:37:00 +0300407#else /* CONFIG_X86_LOCAL_APIC */
408
409static inline u32 apic_read(u32 reg) { return 0; }
410static inline void apic_write(u32 reg, u32 val) { }
411static inline u64 apic_icr_read(void) { return 0; }
412static inline void apic_icr_write(u32 low, u32 high) { }
413static inline void apic_wait_icr_idle(void) { }
414static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
415
416#endif /* CONFIG_X86_LOCAL_APIC */
Ingo Molnare2780a62009-02-17 13:52:29 +0100417
418static inline void ack_APIC_irq(void)
419{
420 /*
421 * ack_APIC_irq() actually gets compiled as a single instruction
422 * ... yummie.
423 */
424
425 /* Docs say use 0 for future compatibility */
426 apic_write(APIC_EOI, 0);
427}
428
429static inline unsigned default_get_apic_id(unsigned long x)
430{
431 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
432
Andreas Herrmann42937e82009-06-08 15:55:09 +0200433 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
Ingo Molnare2780a62009-02-17 13:52:29 +0100434 return (x >> 24) & 0xFF;
435 else
436 return (x >> 24) & 0x0F;
437}
438
439/*
440 * Warm reset vector default position:
441 */
442#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
443#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
444
Yinghai Lu2b6163b2009-02-25 20:50:49 -0800445#ifdef CONFIG_X86_64
Ingo Molnarbe163a12009-02-17 16:28:46 +0100446extern struct apic apic_flat;
447extern struct apic apic_physflat;
448extern struct apic apic_x2apic_cluster;
449extern struct apic apic_x2apic_phys;
Ingo Molnare2780a62009-02-17 13:52:29 +0100450extern int default_acpi_madt_oem_check(char *, char *);
451
452extern void apic_send_IPI_self(int vector);
453
Ingo Molnarbe163a12009-02-17 16:28:46 +0100454extern struct apic apic_x2apic_uv_x;
Ingo Molnare2780a62009-02-17 13:52:29 +0100455DECLARE_PER_CPU(int, x2apic_extra_bits);
456
457extern int default_cpu_present_to_apicid(int mps_cpu);
Thomas Gleixnere11dada2009-08-31 15:18:40 +0200458extern int default_check_phys_apicid_present(int phys_apicid);
Ingo Molnare2780a62009-02-17 13:52:29 +0100459#endif
460
461static inline void default_wait_for_init_deassert(atomic_t *deassert)
462{
463 while (!atomic_read(deassert))
464 cpu_relax();
465 return;
466}
467
468extern void generic_bigsmp_probe(void);
469
470
471#ifdef CONFIG_X86_LOCAL_APIC
472
473#include <asm/smp.h>
474
475#define APIC_DFR_VALUE (APIC_DFR_FLAT)
476
477static inline const struct cpumask *default_target_cpus(void)
478{
479#ifdef CONFIG_SMP
480 return cpu_online_mask;
481#else
482 return cpumask_of(0);
483#endif
484}
485
486DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
487
488
489static inline unsigned int read_apic_id(void)
490{
491 unsigned int reg;
492
493 reg = apic_read(APIC_ID);
494
495 return apic->get_apic_id(reg);
496}
497
498extern void default_setup_apic_routing(void);
499
Cyrill Gorcunov9844ab12009-10-14 00:07:03 +0400500extern struct apic apic_noop;
501
Ingo Molnare2780a62009-02-17 13:52:29 +0100502#ifdef CONFIG_X86_32
Jaswinder Singh Rajput2c1b2842009-04-11 00:03:10 +0530503
504extern struct apic apic_default;
505
Ingo Molnare2780a62009-02-17 13:52:29 +0100506/*
507 * Set up the logical destination ID.
508 *
509 * Intel recommends to set DFR, LDR and TPR before enabling
510 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
511 * document number 292116). So here it goes...
512 */
513extern void default_init_apic_ldr(void);
514
515static inline int default_apic_id_registered(void)
516{
517 return physid_isset(read_apic_id(), phys_cpu_present_map);
518}
519
Yinghai Luf56e5032009-03-24 14:16:30 -0700520static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
521{
522 return cpuid_apic >> index_msb;
523}
524
525extern int default_apicid_to_node(int logical_apicid);
526
527#endif
528
Ingo Molnare2780a62009-02-17 13:52:29 +0100529static inline unsigned int
530default_cpu_mask_to_apicid(const struct cpumask *cpumask)
531{
Yinghai Luf56e5032009-03-24 14:16:30 -0700532 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
Ingo Molnare2780a62009-02-17 13:52:29 +0100533}
534
535static inline unsigned int
536default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
537 const struct cpumask *andmask)
538{
539 unsigned long mask1 = cpumask_bits(cpumask)[0];
540 unsigned long mask2 = cpumask_bits(andmask)[0];
541 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
542
543 return (unsigned int)(mask1 & mask2 & mask3);
544}
545
Cyrill Gorcunov7abc0752009-11-10 01:06:59 +0300546static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
Ingo Molnare2780a62009-02-17 13:52:29 +0100547{
Cyrill Gorcunov7abc0752009-11-10 01:06:59 +0300548 return physid_isset(apicid, *map);
Ingo Molnare2780a62009-02-17 13:52:29 +0100549}
550
551static inline unsigned long default_check_apicid_present(int bit)
552{
553 return physid_isset(bit, phys_cpu_present_map);
554}
555
Cyrill Gorcunov7abc0752009-11-10 01:06:59 +0300556static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
Ingo Molnare2780a62009-02-17 13:52:29 +0100557{
Cyrill Gorcunov7abc0752009-11-10 01:06:59 +0300558 *retmap = *phys_map;
Ingo Molnare2780a62009-02-17 13:52:29 +0100559}
560
561/* Mapping from cpu number to logical apicid */
562static inline int default_cpu_to_logical_apicid(int cpu)
563{
564 return 1 << cpu;
565}
566
567static inline int __default_cpu_present_to_apicid(int mps_cpu)
568{
569 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
570 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
571 else
572 return BAD_APICID;
573}
574
575static inline int
Thomas Gleixnere11dada2009-08-31 15:18:40 +0200576__default_check_phys_apicid_present(int phys_apicid)
Ingo Molnare2780a62009-02-17 13:52:29 +0100577{
Thomas Gleixnere11dada2009-08-31 15:18:40 +0200578 return physid_isset(phys_apicid, phys_cpu_present_map);
Ingo Molnare2780a62009-02-17 13:52:29 +0100579}
580
581#ifdef CONFIG_X86_32
582static inline int default_cpu_present_to_apicid(int mps_cpu)
583{
584 return __default_cpu_present_to_apicid(mps_cpu);
585}
586
587static inline int
Thomas Gleixnere11dada2009-08-31 15:18:40 +0200588default_check_phys_apicid_present(int phys_apicid)
Ingo Molnare2780a62009-02-17 13:52:29 +0100589{
Thomas Gleixnere11dada2009-08-31 15:18:40 +0200590 return __default_check_phys_apicid_present(phys_apicid);
Ingo Molnare2780a62009-02-17 13:52:29 +0100591}
592#else
593extern int default_cpu_present_to_apicid(int mps_cpu);
Thomas Gleixnere11dada2009-08-31 15:18:40 +0200594extern int default_check_phys_apicid_present(int phys_apicid);
Ingo Molnare2780a62009-02-17 13:52:29 +0100595#endif
596
Ingo Molnare2780a62009-02-17 13:52:29 +0100597#endif /* CONFIG_X86_LOCAL_APIC */
598
Ingo Molnar2f205bc2009-02-17 14:45:30 +0100599#ifdef CONFIG_X86_32
600extern u8 cpu_2_logical_apicid[NR_CPUS];
601#endif
602
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700603#endif /* _ASM_X86_APIC_H */