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Feng Tange24c7452009-12-14 14:20:22 -08001/*
Grant Likelyca632f52011-06-06 01:16:30 -06002 * Designware SPI core controller driver (refer pxa2xx_spi.c)
Feng Tange24c7452009-12-14 14:20:22 -08003 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
Feng Tange24c7452009-12-14 14:20:22 -080014 */
15
16#include <linux/dma-mapping.h>
17#include <linux/interrupt.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040018#include <linux/module.h>
Feng Tange24c7452009-12-14 14:20:22 -080019#include <linux/highmem.h>
20#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Feng Tange24c7452009-12-14 14:20:22 -080022#include <linux/spi/spi.h>
Baruch Siachd9c73bb2014-01-31 12:07:47 +020023#include <linux/gpio.h>
Feng Tange24c7452009-12-14 14:20:22 -080024
Grant Likelyca632f52011-06-06 01:16:30 -060025#include "spi-dw.h"
Grant Likely568a60e2011-02-28 12:47:12 -070026
Feng Tange24c7452009-12-14 14:20:22 -080027#ifdef CONFIG_DEBUG_FS
28#include <linux/debugfs.h>
29#endif
30
Feng Tange24c7452009-12-14 14:20:22 -080031/* Slave spi_dev related */
32struct chip_data {
33 u16 cr0;
34 u8 cs; /* chip select pin */
35 u8 n_bytes; /* current is a 1/2/4 byte op */
36 u8 tmode; /* TR/TO/RO/EEPROM */
37 u8 type; /* SPI/SSP/MicroWire */
38
39 u8 poll_mode; /* 1 means use poll mode */
40
41 u32 dma_width;
42 u32 rx_threshold;
43 u32 tx_threshold;
44 u8 enable_dma;
45 u8 bits_per_word;
46 u16 clk_div; /* baud rate divider */
47 u32 speed_hz; /* baud rate */
Feng Tange24c7452009-12-14 14:20:22 -080048 void (*cs_control)(u32 command);
49};
50
51#ifdef CONFIG_DEBUG_FS
Feng Tange24c7452009-12-14 14:20:22 -080052#define SPI_REGS_BUFSIZE 1024
Andy Shevchenko53288fe2014-09-12 15:11:56 +030053static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
54 size_t count, loff_t *ppos)
Feng Tange24c7452009-12-14 14:20:22 -080055{
Andy Shevchenko53288fe2014-09-12 15:11:56 +030056 struct dw_spi *dws = file->private_data;
Feng Tange24c7452009-12-14 14:20:22 -080057 char *buf;
58 u32 len = 0;
59 ssize_t ret;
60
Feng Tange24c7452009-12-14 14:20:22 -080061 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
62 if (!buf)
63 return 0;
64
65 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
Andy Shevchenko53288fe2014-09-12 15:11:56 +030066 "%s registers:\n", dev_name(&dws->master->dev));
Feng Tange24c7452009-12-14 14:20:22 -080067 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
68 "=================================\n");
69 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070070 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
Feng Tange24c7452009-12-14 14:20:22 -080071 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070072 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
Feng Tange24c7452009-12-14 14:20:22 -080073 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070074 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
Feng Tange24c7452009-12-14 14:20:22 -080075 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070076 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
Feng Tange24c7452009-12-14 14:20:22 -080077 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070078 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
Feng Tange24c7452009-12-14 14:20:22 -080079 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070080 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080081 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070082 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
Feng Tange24c7452009-12-14 14:20:22 -080083 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070084 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080085 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070086 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
Feng Tange24c7452009-12-14 14:20:22 -080087 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070088 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
Feng Tange24c7452009-12-14 14:20:22 -080089 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070090 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
Feng Tange24c7452009-12-14 14:20:22 -080091 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070092 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
Feng Tange24c7452009-12-14 14:20:22 -080093 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070094 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
Feng Tange24c7452009-12-14 14:20:22 -080095 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070096 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
Feng Tange24c7452009-12-14 14:20:22 -080097 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070098 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
Feng Tange24c7452009-12-14 14:20:22 -080099 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "=================================\n");
101
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300102 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
Feng Tange24c7452009-12-14 14:20:22 -0800103 kfree(buf);
104 return ret;
105}
106
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300107static const struct file_operations dw_spi_regs_ops = {
Feng Tange24c7452009-12-14 14:20:22 -0800108 .owner = THIS_MODULE,
Stephen Boyd234e3402012-04-05 14:25:11 -0700109 .open = simple_open,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300110 .read = dw_spi_show_regs,
Arnd Bergmann6038f372010-08-15 18:52:59 +0200111 .llseek = default_llseek,
Feng Tange24c7452009-12-14 14:20:22 -0800112};
113
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300114static int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800115{
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300116 dws->debugfs = debugfs_create_dir("dw_spi", NULL);
Feng Tange24c7452009-12-14 14:20:22 -0800117 if (!dws->debugfs)
118 return -ENOMEM;
119
120 debugfs_create_file("registers", S_IFREG | S_IRUGO,
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300121 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
Feng Tange24c7452009-12-14 14:20:22 -0800122 return 0;
123}
124
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300125static void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800126{
Jingoo Hanfadcace2014-09-02 11:49:24 +0900127 debugfs_remove_recursive(dws->debugfs);
Feng Tange24c7452009-12-14 14:20:22 -0800128}
129
130#else
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300131static inline int dw_spi_debugfs_init(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800132{
George Shore20a588f2010-01-21 11:40:49 +0000133 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800134}
135
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300136static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800137{
138}
139#endif /* CONFIG_DEBUG_FS */
140
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200141static void dw_spi_set_cs(struct spi_device *spi, bool enable)
142{
143 struct dw_spi *dws = spi_master_get_devdata(spi->master);
144 struct chip_data *chip = spi_get_ctldata(spi);
145
146 /* Chip select logic is inverted from spi_set_cs() */
Andy Shevchenko207cda92015-03-25 20:26:26 +0200147 if (chip && chip->cs_control)
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200148 chip->cs_control(!enable);
149
150 if (!enable)
151 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
152}
153
Alek Du2ff271b2011-03-30 23:09:54 +0800154/* Return the max entries we can fill into tx fifo */
155static inline u32 tx_max(struct dw_spi *dws)
156{
157 u32 tx_left, tx_room, rxtx_gap;
158
159 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
Thor Thayerdd114442015-03-12 14:19:31 -0500160 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
Alek Du2ff271b2011-03-30 23:09:54 +0800161
162 /*
163 * Another concern is about the tx/rx mismatch, we
164 * though to use (dws->fifo_len - rxflr - txflr) as
165 * one maximum value for tx, but it doesn't cover the
166 * data which is out of tx/rx fifo and inside the
167 * shift registers. So a control from sw point of
168 * view is taken.
169 */
170 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
171 / dws->n_bytes;
172
173 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
174}
175
176/* Return the max entries we should read out of rx fifo */
177static inline u32 rx_max(struct dw_spi *dws)
178{
179 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
180
Thor Thayerdd114442015-03-12 14:19:31 -0500181 return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
Alek Du2ff271b2011-03-30 23:09:54 +0800182}
183
Alek Du3b8a4dd2011-03-30 23:09:55 +0800184static void dw_writer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800185{
Alek Du2ff271b2011-03-30 23:09:54 +0800186 u32 max = tx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800187 u16 txw = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800188
Alek Du2ff271b2011-03-30 23:09:54 +0800189 while (max--) {
190 /* Set the tx word if the transfer's original "tx" is not null */
191 if (dws->tx_end - dws->len) {
192 if (dws->n_bytes == 1)
193 txw = *(u8 *)(dws->tx);
194 else
195 txw = *(u16 *)(dws->tx);
196 }
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200197 dw_write_io_reg(dws, DW_SPI_DR, txw);
Alek Du2ff271b2011-03-30 23:09:54 +0800198 dws->tx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800199 }
Feng Tange24c7452009-12-14 14:20:22 -0800200}
201
Alek Du3b8a4dd2011-03-30 23:09:55 +0800202static void dw_reader(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800203{
Alek Du2ff271b2011-03-30 23:09:54 +0800204 u32 max = rx_max(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800205 u16 rxw;
Feng Tange24c7452009-12-14 14:20:22 -0800206
Alek Du2ff271b2011-03-30 23:09:54 +0800207 while (max--) {
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200208 rxw = dw_read_io_reg(dws, DW_SPI_DR);
Feng Tangde6efe02011-03-30 23:09:52 +0800209 /* Care rx only if the transfer's original "rx" is not null */
210 if (dws->rx_end - dws->len) {
211 if (dws->n_bytes == 1)
212 *(u8 *)(dws->rx) = rxw;
213 else
214 *(u16 *)(dws->rx) = rxw;
215 }
216 dws->rx += dws->n_bytes;
Feng Tange24c7452009-12-14 14:20:22 -0800217 }
Feng Tange24c7452009-12-14 14:20:22 -0800218}
219
Feng Tange24c7452009-12-14 14:20:22 -0800220static void int_error_stop(struct dw_spi *dws, const char *msg)
221{
Andy Shevchenko45746e82015-03-02 14:58:55 +0200222 spi_reset_chip(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800223
224 dev_err(&dws->master->dev, "%s\n", msg);
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200225 dws->master->cur_msg->status = -EIO;
226 spi_finalize_current_transfer(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800227}
228
Feng Tange24c7452009-12-14 14:20:22 -0800229static irqreturn_t interrupt_transfer(struct dw_spi *dws)
230{
Thor Thayerdd114442015-03-12 14:19:31 -0500231 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
Feng Tange24c7452009-12-14 14:20:22 -0800232
Feng Tange24c7452009-12-14 14:20:22 -0800233 /* Error handling */
234 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
Thor Thayerdd114442015-03-12 14:19:31 -0500235 dw_readl(dws, DW_SPI_ICR);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800236 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
Feng Tange24c7452009-12-14 14:20:22 -0800237 return IRQ_HANDLED;
238 }
239
Alek Du3b8a4dd2011-03-30 23:09:55 +0800240 dw_reader(dws);
241 if (dws->rx_end == dws->rx) {
242 spi_mask_intr(dws, SPI_INT_TXEI);
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200243 spi_finalize_current_transfer(dws->master);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800244 return IRQ_HANDLED;
245 }
Feng Tang552e4502010-01-20 13:49:45 -0700246 if (irq_status & SPI_INT_TXEI) {
247 spi_mask_intr(dws, SPI_INT_TXEI);
Alek Du3b8a4dd2011-03-30 23:09:55 +0800248 dw_writer(dws);
249 /* Enable TX irq always, it will be disabled when RX finished */
250 spi_umask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800251 }
Feng Tang552e4502010-01-20 13:49:45 -0700252
Feng Tange24c7452009-12-14 14:20:22 -0800253 return IRQ_HANDLED;
254}
255
256static irqreturn_t dw_spi_irq(int irq, void *dev_id)
257{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200258 struct spi_master *master = dev_id;
259 struct dw_spi *dws = spi_master_get_devdata(master);
Thor Thayerdd114442015-03-12 14:19:31 -0500260 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
Yong Wangcbcc0622010-09-07 15:27:27 +0800261
Yong Wangcbcc0622010-09-07 15:27:27 +0800262 if (!irq_status)
263 return IRQ_NONE;
Feng Tange24c7452009-12-14 14:20:22 -0800264
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200265 if (!master->cur_msg) {
Feng Tange24c7452009-12-14 14:20:22 -0800266 spi_mask_intr(dws, SPI_INT_TXEI);
Feng Tange24c7452009-12-14 14:20:22 -0800267 return IRQ_HANDLED;
268 }
269
270 return dws->transfer_handler(dws);
271}
272
273/* Must be called inside pump_transfers() */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200274static int poll_transfer(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800275{
Alek Du2ff271b2011-03-30 23:09:54 +0800276 do {
277 dw_writer(dws);
Feng Tangde6efe02011-03-30 23:09:52 +0800278 dw_reader(dws);
Alek Du2ff271b2011-03-30 23:09:54 +0800279 cpu_relax();
280 } while (dws->rx_end > dws->rx);
Feng Tange24c7452009-12-14 14:20:22 -0800281
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200282 return 0;
Feng Tange24c7452009-12-14 14:20:22 -0800283}
284
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200285static int dw_spi_transfer_one(struct spi_master *master,
286 struct spi_device *spi, struct spi_transfer *transfer)
Feng Tange24c7452009-12-14 14:20:22 -0800287{
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200288 struct dw_spi *dws = spi_master_get_devdata(master);
289 struct chip_data *chip = spi_get_ctldata(spi);
Feng Tange24c7452009-12-14 14:20:22 -0800290 u8 imask = 0;
Andy Shevchenkoea113702015-02-24 13:32:11 +0200291 u16 txlevel = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800292 u16 clk_div = 0;
293 u32 speed = 0;
294 u32 cr0 = 0;
Andy Shevchenko9f145382015-03-09 16:48:46 +0200295 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800296
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200297 dws->dma_mapped = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800298 dws->n_bytes = chip->n_bytes;
299 dws->dma_width = chip->dma_width;
Feng Tange24c7452009-12-14 14:20:22 -0800300
Feng Tange24c7452009-12-14 14:20:22 -0800301 dws->tx = (void *)transfer->tx_buf;
302 dws->tx_end = dws->tx + transfer->len;
303 dws->rx = transfer->rx_buf;
304 dws->rx_end = dws->rx + transfer->len;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200305 dws->len = transfer->len;
Feng Tange24c7452009-12-14 14:20:22 -0800306
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200307 spi_enable_chip(dws, 0);
308
Feng Tange24c7452009-12-14 14:20:22 -0800309 cr0 = chip->cr0;
310
311 /* Handle per transfer options for bpw and speed */
312 if (transfer->speed_hz) {
313 speed = chip->speed_hz;
314
Andy Shevchenko341c7dc2015-02-24 13:32:12 +0200315 if ((transfer->speed_hz != speed) || !chip->clk_div) {
Feng Tange24c7452009-12-14 14:20:22 -0800316 speed = transfer->speed_hz;
Feng Tange24c7452009-12-14 14:20:22 -0800317
318 /* clk_div doesn't support odd number */
Andy Shevchenko341c7dc2015-02-24 13:32:12 +0200319 clk_div = (dws->max_freq / speed + 1) & 0xfffe;
Feng Tange24c7452009-12-14 14:20:22 -0800320
321 chip->speed_hz = speed;
322 chip->clk_div = clk_div;
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200323
324 spi_set_clk(dws, chip->clk_div);
Feng Tange24c7452009-12-14 14:20:22 -0800325 }
326 }
327 if (transfer->bits_per_word) {
Andy Shevchenkoe31abce2015-03-09 16:48:45 +0200328 if (transfer->bits_per_word == 8) {
329 dws->n_bytes = 1;
330 dws->dma_width = 1;
331 } else if (transfer->bits_per_word == 16) {
332 dws->n_bytes = 2;
333 dws->dma_width = 2;
334 }
335 cr0 = (transfer->bits_per_word - 1)
Feng Tange24c7452009-12-14 14:20:22 -0800336 | (chip->type << SPI_FRF_OFFSET)
337 | (spi->mode << SPI_MODE_OFFSET)
338 | (chip->tmode << SPI_TMOD_OFFSET);
339 }
Feng Tange24c7452009-12-14 14:20:22 -0800340
George Shore052dc7c2010-01-21 11:40:52 +0000341 /*
342 * Adjust transfer mode if necessary. Requires platform dependent
343 * chipselect mechanism.
344 */
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200345 if (chip->cs_control) {
George Shore052dc7c2010-01-21 11:40:52 +0000346 if (dws->rx && dws->tx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800347 chip->tmode = SPI_TMOD_TR;
George Shore052dc7c2010-01-21 11:40:52 +0000348 else if (dws->rx)
Feng Tange3e55ff2010-09-07 15:52:06 +0800349 chip->tmode = SPI_TMOD_RO;
George Shore052dc7c2010-01-21 11:40:52 +0000350 else
Feng Tange3e55ff2010-09-07 15:52:06 +0800351 chip->tmode = SPI_TMOD_TO;
George Shore052dc7c2010-01-21 11:40:52 +0000352
Feng Tange3e55ff2010-09-07 15:52:06 +0800353 cr0 &= ~SPI_TMOD_MASK;
George Shore052dc7c2010-01-21 11:40:52 +0000354 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
355 }
356
Thor Thayerdd114442015-03-12 14:19:31 -0500357 dw_writel(dws, DW_SPI_CTRL0, cr0);
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200358
Feng Tange24c7452009-12-14 14:20:22 -0800359 /* Check if current transfer is a DMA transaction */
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200360 if (master->can_dma && master->can_dma(master, spi, transfer))
361 dws->dma_mapped = master->cur_msg_mapped;
Feng Tange24c7452009-12-14 14:20:22 -0800362
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200363 /* For poll mode just disable all interrupts */
364 spi_mask_intr(dws, 0xff);
365
Feng Tang552e4502010-01-20 13:49:45 -0700366 /*
367 * Interrupt mode
368 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
369 */
Andy Shevchenko9f145382015-03-09 16:48:46 +0200370 if (dws->dma_mapped) {
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200371 ret = dws->dma_ops->dma_setup(dws, transfer);
Andy Shevchenko9f145382015-03-09 16:48:46 +0200372 if (ret < 0) {
373 spi_enable_chip(dws, 1);
374 return ret;
375 }
376 } else if (!chip->poll_mode) {
Andy Shevchenkoea113702015-02-24 13:32:11 +0200377 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
Thor Thayerdd114442015-03-12 14:19:31 -0500378 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
Feng Tang552e4502010-01-20 13:49:45 -0700379
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200380 /* Set the interrupt mask */
Jingoo Hanfadcace2014-09-02 11:49:24 +0900381 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
382 SPI_INT_RXUI | SPI_INT_RXOI;
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200383 spi_umask_intr(dws, imask);
384
Feng Tange24c7452009-12-14 14:20:22 -0800385 dws->transfer_handler = interrupt_transfer;
386 }
387
Andy Shevchenko0b2e8912015-03-02 14:58:56 +0200388 spi_enable_chip(dws, 1);
Feng Tange24c7452009-12-14 14:20:22 -0800389
Andy Shevchenko9f145382015-03-09 16:48:46 +0200390 if (dws->dma_mapped) {
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200391 ret = dws->dma_ops->dma_transfer(dws, transfer);
Andy Shevchenko9f145382015-03-09 16:48:46 +0200392 if (ret < 0)
393 return ret;
394 }
Feng Tange24c7452009-12-14 14:20:22 -0800395
396 if (chip->poll_mode)
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200397 return poll_transfer(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800398
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200399 return 1;
Feng Tange24c7452009-12-14 14:20:22 -0800400}
401
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200402static void dw_spi_handle_err(struct spi_master *master,
Baruch Siachec37e8e2014-01-31 12:07:44 +0200403 struct spi_message *msg)
Feng Tange24c7452009-12-14 14:20:22 -0800404{
Baruch Siachec37e8e2014-01-31 12:07:44 +0200405 struct dw_spi *dws = spi_master_get_devdata(master);
Feng Tange24c7452009-12-14 14:20:22 -0800406
Andy Shevchenko4d5ac1e2015-03-09 16:48:48 +0200407 if (dws->dma_mapped)
408 dws->dma_ops->dma_stop(dws);
409
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200410 spi_reset_chip(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800411}
412
413/* This may be called twice for each spi dev */
414static int dw_spi_setup(struct spi_device *spi)
415{
416 struct dw_spi_chip *chip_info = NULL;
417 struct chip_data *chip;
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200418 int ret;
Feng Tange24c7452009-12-14 14:20:22 -0800419
Feng Tange24c7452009-12-14 14:20:22 -0800420 /* Only alloc on first setup */
421 chip = spi_get_ctldata(spi);
422 if (!chip) {
Axel Lina97c8832014-08-31 12:47:06 +0800423 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
Feng Tange24c7452009-12-14 14:20:22 -0800424 if (!chip)
425 return -ENOMEM;
Baruch Siach43f627a2013-12-30 20:30:46 +0200426 spi_set_ctldata(spi, chip);
Feng Tange24c7452009-12-14 14:20:22 -0800427 }
428
429 /*
430 * Protocol drivers may change the chip settings, so...
431 * if chip_info exists, use it
432 */
433 chip_info = spi->controller_data;
434
435 /* chip_info doesn't always exist */
436 if (chip_info) {
437 if (chip_info->cs_control)
438 chip->cs_control = chip_info->cs_control;
439
440 chip->poll_mode = chip_info->poll_mode;
441 chip->type = chip_info->type;
442
443 chip->rx_threshold = 0;
444 chip->tx_threshold = 0;
Feng Tange24c7452009-12-14 14:20:22 -0800445 }
446
Stephen Warren24778be2013-05-21 20:36:35 -0600447 if (spi->bits_per_word == 8) {
Feng Tange24c7452009-12-14 14:20:22 -0800448 chip->n_bytes = 1;
449 chip->dma_width = 1;
Stephen Warren24778be2013-05-21 20:36:35 -0600450 } else if (spi->bits_per_word == 16) {
Feng Tange24c7452009-12-14 14:20:22 -0800451 chip->n_bytes = 2;
452 chip->dma_width = 2;
Feng Tange24c7452009-12-14 14:20:22 -0800453 }
454 chip->bits_per_word = spi->bits_per_word;
455
Feng Tang552e4502010-01-20 13:49:45 -0700456 if (!spi->max_speed_hz) {
457 dev_err(&spi->dev, "No max speed HZ parameter\n");
458 return -EINVAL;
459 }
Feng Tange24c7452009-12-14 14:20:22 -0800460
461 chip->tmode = 0; /* Tx & Rx */
462 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
463 chip->cr0 = (chip->bits_per_word - 1)
464 | (chip->type << SPI_FRF_OFFSET)
465 | (spi->mode << SPI_MODE_OFFSET)
466 | (chip->tmode << SPI_TMOD_OFFSET);
467
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300468 if (spi->mode & SPI_LOOP)
469 chip->cr0 |= 1 << SPI_SRL_OFFSET;
470
Baruch Siachd9c73bb2014-01-31 12:07:47 +0200471 if (gpio_is_valid(spi->cs_gpio)) {
472 ret = gpio_direction_output(spi->cs_gpio,
473 !(spi->mode & SPI_CS_HIGH));
474 if (ret)
475 return ret;
476 }
477
Feng Tange24c7452009-12-14 14:20:22 -0800478 return 0;
479}
480
Axel Lina97c8832014-08-31 12:47:06 +0800481static void dw_spi_cleanup(struct spi_device *spi)
482{
483 struct chip_data *chip = spi_get_ctldata(spi);
484
485 kfree(chip);
486 spi_set_ctldata(spi, NULL);
487}
488
Feng Tange24c7452009-12-14 14:20:22 -0800489/* Restart the controller, disable all interrupts, clean rx fifo */
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200490static void spi_hw_init(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800491{
Andy Shevchenko45746e82015-03-02 14:58:55 +0200492 spi_reset_chip(dws);
Feng Tangc587b6f2010-01-21 10:41:10 +0800493
494 /*
495 * Try to detect the FIFO depth if not set by interface driver,
496 * the depth could be from 2 to 256 from HW spec
497 */
498 if (!dws->fifo_len) {
499 u32 fifo;
Jingoo Hanfadcace2014-09-02 11:49:24 +0900500
Andy Shevchenko9d239d32015-02-25 11:39:36 +0200501 for (fifo = 1; fifo < 256; fifo++) {
Thor Thayerdd114442015-03-12 14:19:31 -0500502 dw_writel(dws, DW_SPI_TXFLTR, fifo);
503 if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
Feng Tangc587b6f2010-01-21 10:41:10 +0800504 break;
505 }
Thor Thayerdd114442015-03-12 14:19:31 -0500506 dw_writel(dws, DW_SPI_TXFLTR, 0);
Feng Tangc587b6f2010-01-21 10:41:10 +0800507
Andy Shevchenko9d239d32015-02-25 11:39:36 +0200508 dws->fifo_len = (fifo == 1) ? 0 : fifo;
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200509 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
Feng Tangc587b6f2010-01-21 10:41:10 +0800510 }
Feng Tange24c7452009-12-14 14:20:22 -0800511}
512
Baruch Siach04f421e2013-12-30 20:30:44 +0200513int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800514{
515 struct spi_master *master;
516 int ret;
517
518 BUG_ON(dws == NULL);
519
Baruch Siach04f421e2013-12-30 20:30:44 +0200520 master = spi_alloc_master(dev, 0);
521 if (!master)
522 return -ENOMEM;
Feng Tange24c7452009-12-14 14:20:22 -0800523
524 dws->master = master;
525 dws->type = SSI_MOTO_SPI;
Feng Tange24c7452009-12-14 14:20:22 -0800526 dws->dma_inited = 0;
527 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
Andy Shevchenkoc3c6e232014-09-18 20:08:57 +0300528 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
Feng Tange24c7452009-12-14 14:20:22 -0800529
Baruch Siach04f421e2013-12-30 20:30:44 +0200530 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200531 dws->name, master);
Feng Tange24c7452009-12-14 14:20:22 -0800532 if (ret < 0) {
533 dev_err(&master->dev, "can not get IRQ\n");
534 goto err_free_master;
535 }
536
Andy Shevchenkoc3ce15b2014-09-18 20:08:56 +0300537 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
Stephen Warren24778be2013-05-21 20:36:35 -0600538 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Feng Tange24c7452009-12-14 14:20:22 -0800539 master->bus_num = dws->bus_num;
540 master->num_chipselect = dws->num_cs;
Feng Tange24c7452009-12-14 14:20:22 -0800541 master->setup = dw_spi_setup;
Axel Lina97c8832014-08-31 12:47:06 +0800542 master->cleanup = dw_spi_cleanup;
Andy Shevchenkoc22c62d2015-03-02 14:58:57 +0200543 master->set_cs = dw_spi_set_cs;
544 master->transfer_one = dw_spi_transfer_one;
545 master->handle_err = dw_spi_handle_err;
Axel Lin765ee702014-02-20 21:37:56 +0800546 master->max_speed_hz = dws->max_freq;
Thor Thayer9c6de472014-10-08 13:51:34 -0500547 master->dev.of_node = dev->of_node;
Feng Tange24c7452009-12-14 14:20:22 -0800548
Feng Tange24c7452009-12-14 14:20:22 -0800549 /* Basic HW init */
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200550 spi_hw_init(dev, dws);
Feng Tange24c7452009-12-14 14:20:22 -0800551
Feng Tang7063c0d2010-12-24 13:59:11 +0800552 if (dws->dma_ops && dws->dma_ops->dma_init) {
553 ret = dws->dma_ops->dma_init(dws);
554 if (ret) {
Andy Shevchenko3dbb3b92015-01-07 16:56:54 +0200555 dev_warn(dev, "DMA init failed\n");
Feng Tang7063c0d2010-12-24 13:59:11 +0800556 dws->dma_inited = 0;
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200557 } else {
558 master->can_dma = dws->dma_ops->can_dma;
Feng Tang7063c0d2010-12-24 13:59:11 +0800559 }
560 }
561
Feng Tange24c7452009-12-14 14:20:22 -0800562 spi_master_set_devdata(master, dws);
Baruch Siach04f421e2013-12-30 20:30:44 +0200563 ret = devm_spi_register_master(dev, master);
Feng Tange24c7452009-12-14 14:20:22 -0800564 if (ret) {
565 dev_err(&master->dev, "problem registering spi master\n");
Baruch Siachec37e8e2014-01-31 12:07:44 +0200566 goto err_dma_exit;
Feng Tange24c7452009-12-14 14:20:22 -0800567 }
568
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300569 dw_spi_debugfs_init(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800570 return 0;
571
Baruch Siachec37e8e2014-01-31 12:07:44 +0200572err_dma_exit:
Feng Tang7063c0d2010-12-24 13:59:11 +0800573 if (dws->dma_ops && dws->dma_ops->dma_exit)
574 dws->dma_ops->dma_exit(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800575 spi_enable_chip(dws, 0);
Feng Tange24c7452009-12-14 14:20:22 -0800576err_free_master:
577 spi_master_put(master);
Feng Tange24c7452009-12-14 14:20:22 -0800578 return ret;
579}
Feng Tang79290a22010-12-24 13:59:10 +0800580EXPORT_SYMBOL_GPL(dw_spi_add_host);
Feng Tange24c7452009-12-14 14:20:22 -0800581
Grant Likelyfd4a3192012-12-07 16:57:14 +0000582void dw_spi_remove_host(struct dw_spi *dws)
Feng Tange24c7452009-12-14 14:20:22 -0800583{
Feng Tange24c7452009-12-14 14:20:22 -0800584 if (!dws)
585 return;
Andy Shevchenko53288fe2014-09-12 15:11:56 +0300586 dw_spi_debugfs_remove(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800587
Feng Tang7063c0d2010-12-24 13:59:11 +0800588 if (dws->dma_ops && dws->dma_ops->dma_exit)
589 dws->dma_ops->dma_exit(dws);
Feng Tange24c7452009-12-14 14:20:22 -0800590 spi_enable_chip(dws, 0);
591 /* Disable clk */
592 spi_set_clk(dws, 0);
Feng Tange24c7452009-12-14 14:20:22 -0800593}
Feng Tang79290a22010-12-24 13:59:10 +0800594EXPORT_SYMBOL_GPL(dw_spi_remove_host);
Feng Tange24c7452009-12-14 14:20:22 -0800595
596int dw_spi_suspend_host(struct dw_spi *dws)
597{
598 int ret = 0;
599
Baruch Siachec37e8e2014-01-31 12:07:44 +0200600 ret = spi_master_suspend(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800601 if (ret)
602 return ret;
603 spi_enable_chip(dws, 0);
604 spi_set_clk(dws, 0);
605 return ret;
606}
Feng Tang79290a22010-12-24 13:59:10 +0800607EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
Feng Tange24c7452009-12-14 14:20:22 -0800608
609int dw_spi_resume_host(struct dw_spi *dws)
610{
611 int ret;
612
Andy Shevchenko30b4b702015-01-07 16:56:55 +0200613 spi_hw_init(&dws->master->dev, dws);
Baruch Siachec37e8e2014-01-31 12:07:44 +0200614 ret = spi_master_resume(dws->master);
Feng Tange24c7452009-12-14 14:20:22 -0800615 if (ret)
616 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
617 return ret;
618}
Feng Tang79290a22010-12-24 13:59:10 +0800619EXPORT_SYMBOL_GPL(dw_spi_resume_host);
Feng Tange24c7452009-12-14 14:20:22 -0800620
621MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
622MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
623MODULE_LICENSE("GPL v2");