Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | #include <linux/mm.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/io.h> |
| 17 | |
| 18 | #include <asm/clkdev.h> |
| 19 | |
| 20 | #include <mach/hardware.h> |
| 21 | #include <mach/common.h> |
| 22 | #include <mach/clock.h> |
| 23 | |
| 24 | #include "crm_regs.h" |
| 25 | |
| 26 | /* External clock values passed-in by the board code */ |
| 27 | static unsigned long external_high_reference, external_low_reference; |
| 28 | static unsigned long oscillator_reference, ckih2_reference; |
| 29 | |
| 30 | static struct clk osc_clk; |
| 31 | static struct clk pll1_main_clk; |
| 32 | static struct clk pll1_sw_clk; |
| 33 | static struct clk pll2_sw_clk; |
| 34 | static struct clk pll3_sw_clk; |
| 35 | static struct clk lp_apm_clk; |
| 36 | static struct clk periph_apm_clk; |
| 37 | static struct clk ahb_clk; |
| 38 | static struct clk ipg_clk; |
| 39 | |
| 40 | #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ |
| 41 | |
| 42 | static int _clk_ccgr_enable(struct clk *clk) |
| 43 | { |
| 44 | u32 reg; |
| 45 | |
| 46 | reg = __raw_readl(clk->enable_reg); |
| 47 | reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; |
| 48 | __raw_writel(reg, clk->enable_reg); |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | static void _clk_ccgr_disable(struct clk *clk) |
| 54 | { |
| 55 | u32 reg; |
| 56 | reg = __raw_readl(clk->enable_reg); |
| 57 | reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift); |
| 58 | __raw_writel(reg, clk->enable_reg); |
| 59 | |
| 60 | } |
| 61 | |
| 62 | static void _clk_ccgr_disable_inwait(struct clk *clk) |
| 63 | { |
| 64 | u32 reg; |
| 65 | |
| 66 | reg = __raw_readl(clk->enable_reg); |
| 67 | reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); |
| 68 | reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; |
| 69 | __raw_writel(reg, clk->enable_reg); |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * For the 4-to-1 muxed input clock |
| 74 | */ |
| 75 | static inline u32 _get_mux(struct clk *parent, struct clk *m0, |
| 76 | struct clk *m1, struct clk *m2, struct clk *m3) |
| 77 | { |
| 78 | if (parent == m0) |
| 79 | return 0; |
| 80 | else if (parent == m1) |
| 81 | return 1; |
| 82 | else if (parent == m2) |
| 83 | return 2; |
| 84 | else if (parent == m3) |
| 85 | return 3; |
| 86 | else |
| 87 | BUG(); |
| 88 | |
| 89 | return -EINVAL; |
| 90 | } |
| 91 | |
| 92 | static inline void __iomem *_get_pll_base(struct clk *pll) |
| 93 | { |
| 94 | if (pll == &pll1_main_clk) |
| 95 | return MX51_DPLL1_BASE; |
| 96 | else if (pll == &pll2_sw_clk) |
| 97 | return MX51_DPLL2_BASE; |
| 98 | else if (pll == &pll3_sw_clk) |
| 99 | return MX51_DPLL3_BASE; |
| 100 | else |
| 101 | BUG(); |
| 102 | |
| 103 | return NULL; |
| 104 | } |
| 105 | |
| 106 | static unsigned long clk_pll_get_rate(struct clk *clk) |
| 107 | { |
| 108 | long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; |
| 109 | unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; |
| 110 | void __iomem *pllbase; |
| 111 | s64 temp; |
| 112 | unsigned long parent_rate; |
| 113 | |
| 114 | parent_rate = clk_get_rate(clk->parent); |
| 115 | |
| 116 | pllbase = _get_pll_base(clk); |
| 117 | |
| 118 | dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 119 | pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; |
| 120 | dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; |
| 121 | |
| 122 | if (pll_hfsm == 0) { |
| 123 | dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); |
| 124 | dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); |
| 125 | dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); |
| 126 | } else { |
| 127 | dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); |
| 128 | dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); |
| 129 | dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); |
| 130 | } |
| 131 | pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; |
| 132 | mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; |
| 133 | mfi = (mfi <= 5) ? 5 : mfi; |
| 134 | mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; |
| 135 | mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; |
| 136 | /* Sign extend to 32-bits */ |
| 137 | if (mfn >= 0x04000000) { |
| 138 | mfn |= 0xFC000000; |
| 139 | mfn_abs = -mfn; |
| 140 | } |
| 141 | |
| 142 | ref_clk = 2 * parent_rate; |
| 143 | if (dbl != 0) |
| 144 | ref_clk *= 2; |
| 145 | |
| 146 | ref_clk /= (pdf + 1); |
| 147 | temp = (u64) ref_clk * mfn_abs; |
| 148 | do_div(temp, mfd + 1); |
| 149 | if (mfn < 0) |
| 150 | temp = -temp; |
| 151 | temp = (ref_clk * mfi) + temp; |
| 152 | |
| 153 | return temp; |
| 154 | } |
| 155 | |
| 156 | static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) |
| 157 | { |
| 158 | u32 reg; |
| 159 | void __iomem *pllbase; |
| 160 | |
| 161 | long mfi, pdf, mfn, mfd = 999999; |
| 162 | s64 temp64; |
| 163 | unsigned long quad_parent_rate; |
| 164 | unsigned long pll_hfsm, dp_ctl; |
| 165 | unsigned long parent_rate; |
| 166 | |
| 167 | parent_rate = clk_get_rate(clk->parent); |
| 168 | |
| 169 | pllbase = _get_pll_base(clk); |
| 170 | |
| 171 | quad_parent_rate = 4 * parent_rate; |
| 172 | pdf = mfi = -1; |
| 173 | while (++pdf < 16 && mfi < 5) |
| 174 | mfi = rate * (pdf+1) / quad_parent_rate; |
| 175 | if (mfi > 15) |
| 176 | return -EINVAL; |
| 177 | pdf--; |
| 178 | |
| 179 | temp64 = rate * (pdf+1) - quad_parent_rate * mfi; |
| 180 | do_div(temp64, quad_parent_rate/1000000); |
| 181 | mfn = (long)temp64; |
| 182 | |
| 183 | dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 184 | /* use dpdck0_2 */ |
| 185 | __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); |
| 186 | pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; |
| 187 | if (pll_hfsm == 0) { |
| 188 | reg = mfi << 4 | pdf; |
| 189 | __raw_writel(reg, pllbase + MXC_PLL_DP_OP); |
| 190 | __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); |
| 191 | __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); |
| 192 | } else { |
| 193 | reg = mfi << 4 | pdf; |
| 194 | __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); |
| 195 | __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); |
| 196 | __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); |
| 197 | } |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static int _clk_pll_enable(struct clk *clk) |
| 203 | { |
| 204 | u32 reg; |
| 205 | void __iomem *pllbase; |
| 206 | int i = 0; |
| 207 | |
| 208 | pllbase = _get_pll_base(clk); |
| 209 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; |
| 210 | __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); |
| 211 | |
| 212 | /* Wait for lock */ |
| 213 | do { |
| 214 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 215 | if (reg & MXC_PLL_DP_CTL_LRF) |
| 216 | break; |
| 217 | |
| 218 | udelay(1); |
| 219 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 220 | |
| 221 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 222 | pr_err("MX5: pll locking failed\n"); |
| 223 | return -EINVAL; |
| 224 | } |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | static void _clk_pll_disable(struct clk *clk) |
| 230 | { |
| 231 | u32 reg; |
| 232 | void __iomem *pllbase; |
| 233 | |
| 234 | pllbase = _get_pll_base(clk); |
| 235 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; |
| 236 | __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); |
| 237 | } |
| 238 | |
| 239 | static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) |
| 240 | { |
| 241 | u32 reg, step; |
| 242 | |
| 243 | reg = __raw_readl(MXC_CCM_CCSR); |
| 244 | |
| 245 | /* When switching from pll_main_clk to a bypass clock, first select a |
| 246 | * multiplexed clock in 'step_sel', then shift the glitchless mux |
| 247 | * 'pll1_sw_clk_sel'. |
| 248 | * |
| 249 | * When switching back, do it in reverse order |
| 250 | */ |
| 251 | if (parent == &pll1_main_clk) { |
| 252 | /* Switch to pll1_main_clk */ |
| 253 | reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; |
| 254 | __raw_writel(reg, MXC_CCM_CCSR); |
| 255 | /* step_clk mux switched to lp_apm, to save power. */ |
| 256 | reg = __raw_readl(MXC_CCM_CCSR); |
| 257 | reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; |
| 258 | reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM << |
| 259 | MXC_CCM_CCSR_STEP_SEL_OFFSET); |
| 260 | } else { |
| 261 | if (parent == &lp_apm_clk) { |
| 262 | step = MXC_CCM_CCSR_STEP_SEL_LP_APM; |
| 263 | } else if (parent == &pll2_sw_clk) { |
| 264 | step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED; |
| 265 | } else if (parent == &pll3_sw_clk) { |
| 266 | step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED; |
| 267 | } else |
| 268 | return -EINVAL; |
| 269 | |
| 270 | reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; |
| 271 | reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET); |
| 272 | |
| 273 | __raw_writel(reg, MXC_CCM_CCSR); |
| 274 | /* Switch to step_clk */ |
| 275 | reg = __raw_readl(MXC_CCM_CCSR); |
| 276 | reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; |
| 277 | } |
| 278 | __raw_writel(reg, MXC_CCM_CCSR); |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static unsigned long clk_pll1_sw_get_rate(struct clk *clk) |
| 283 | { |
| 284 | u32 reg, div; |
| 285 | unsigned long parent_rate; |
| 286 | |
| 287 | parent_rate = clk_get_rate(clk->parent); |
| 288 | |
| 289 | reg = __raw_readl(MXC_CCM_CCSR); |
| 290 | |
| 291 | if (clk->parent == &pll2_sw_clk) { |
| 292 | div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> |
| 293 | MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; |
| 294 | } else if (clk->parent == &pll3_sw_clk) { |
| 295 | div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> |
| 296 | MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; |
| 297 | } else |
| 298 | div = 1; |
| 299 | return parent_rate / div; |
| 300 | } |
| 301 | |
| 302 | static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) |
| 303 | { |
| 304 | u32 reg; |
| 305 | |
| 306 | reg = __raw_readl(MXC_CCM_CCSR); |
| 307 | |
| 308 | if (parent == &pll2_sw_clk) |
| 309 | reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; |
| 310 | else |
| 311 | reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; |
| 312 | |
| 313 | __raw_writel(reg, MXC_CCM_CCSR); |
| 314 | return 0; |
| 315 | } |
| 316 | |
| 317 | static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) |
| 318 | { |
| 319 | u32 reg; |
| 320 | |
| 321 | if (parent == &osc_clk) |
| 322 | reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; |
| 323 | else |
| 324 | return -EINVAL; |
| 325 | |
| 326 | __raw_writel(reg, MXC_CCM_CCSR); |
| 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
| 331 | static unsigned long clk_arm_get_rate(struct clk *clk) |
| 332 | { |
| 333 | u32 cacrr, div; |
| 334 | unsigned long parent_rate; |
| 335 | |
| 336 | parent_rate = clk_get_rate(clk->parent); |
| 337 | cacrr = __raw_readl(MXC_CCM_CACRR); |
| 338 | div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; |
| 339 | |
| 340 | return parent_rate / div; |
| 341 | } |
| 342 | |
| 343 | static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) |
| 344 | { |
| 345 | u32 reg, mux; |
| 346 | int i = 0; |
| 347 | |
| 348 | mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); |
| 349 | |
| 350 | reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; |
| 351 | reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; |
| 352 | __raw_writel(reg, MXC_CCM_CBCMR); |
| 353 | |
| 354 | /* Wait for lock */ |
| 355 | do { |
| 356 | reg = __raw_readl(MXC_CCM_CDHIPR); |
| 357 | if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)) |
| 358 | break; |
| 359 | |
| 360 | udelay(1); |
| 361 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 362 | |
| 363 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 364 | pr_err("MX5: Set parent for periph_apm clock failed\n"); |
| 365 | return -EINVAL; |
| 366 | } |
| 367 | |
| 368 | return 0; |
| 369 | } |
| 370 | |
| 371 | static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) |
| 372 | { |
| 373 | u32 reg; |
| 374 | |
| 375 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 376 | |
| 377 | if (parent == &pll2_sw_clk) |
| 378 | reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; |
| 379 | else if (parent == &periph_apm_clk) |
| 380 | reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; |
| 381 | else |
| 382 | return -EINVAL; |
| 383 | |
| 384 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | static struct clk main_bus_clk = { |
| 390 | .parent = &pll2_sw_clk, |
| 391 | .set_parent = _clk_main_bus_set_parent, |
| 392 | }; |
| 393 | |
| 394 | static unsigned long clk_ahb_get_rate(struct clk *clk) |
| 395 | { |
| 396 | u32 reg, div; |
| 397 | unsigned long parent_rate; |
| 398 | |
| 399 | parent_rate = clk_get_rate(clk->parent); |
| 400 | |
| 401 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 402 | div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> |
| 403 | MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; |
| 404 | return parent_rate / div; |
| 405 | } |
| 406 | |
| 407 | |
| 408 | static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) |
| 409 | { |
| 410 | u32 reg, div; |
| 411 | unsigned long parent_rate; |
| 412 | int i = 0; |
| 413 | |
| 414 | parent_rate = clk_get_rate(clk->parent); |
| 415 | |
| 416 | div = parent_rate / rate; |
| 417 | if (div > 8 || div < 1 || ((parent_rate / div) != rate)) |
| 418 | return -EINVAL; |
| 419 | |
| 420 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 421 | reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; |
| 422 | reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; |
| 423 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 424 | |
| 425 | /* Wait for lock */ |
| 426 | do { |
| 427 | reg = __raw_readl(MXC_CCM_CDHIPR); |
| 428 | if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY)) |
| 429 | break; |
| 430 | |
| 431 | udelay(1); |
| 432 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 433 | |
| 434 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 435 | pr_err("MX5: clk_ahb_set_rate failed\n"); |
| 436 | return -EINVAL; |
| 437 | } |
| 438 | |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | static unsigned long _clk_ahb_round_rate(struct clk *clk, |
| 443 | unsigned long rate) |
| 444 | { |
| 445 | u32 div; |
| 446 | unsigned long parent_rate; |
| 447 | |
| 448 | parent_rate = clk_get_rate(clk->parent); |
| 449 | |
| 450 | div = parent_rate / rate; |
| 451 | if (div > 8) |
| 452 | div = 8; |
| 453 | else if (div == 0) |
| 454 | div++; |
| 455 | return parent_rate / div; |
| 456 | } |
| 457 | |
| 458 | |
| 459 | static int _clk_max_enable(struct clk *clk) |
| 460 | { |
| 461 | u32 reg; |
| 462 | |
| 463 | _clk_ccgr_enable(clk); |
| 464 | |
| 465 | /* Handshake with MAX when LPM is entered. */ |
| 466 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 467 | reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; |
| 468 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 469 | |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | static void _clk_max_disable(struct clk *clk) |
| 474 | { |
| 475 | u32 reg; |
| 476 | |
| 477 | _clk_ccgr_disable_inwait(clk); |
| 478 | |
| 479 | /* No Handshake with MAX when LPM is entered as its disabled. */ |
| 480 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 481 | reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; |
| 482 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 483 | } |
| 484 | |
| 485 | static unsigned long clk_ipg_get_rate(struct clk *clk) |
| 486 | { |
| 487 | u32 reg, div; |
| 488 | unsigned long parent_rate; |
| 489 | |
| 490 | parent_rate = clk_get_rate(clk->parent); |
| 491 | |
| 492 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 493 | div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> |
| 494 | MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; |
| 495 | |
| 496 | return parent_rate / div; |
| 497 | } |
| 498 | |
| 499 | static unsigned long clk_ipg_per_get_rate(struct clk *clk) |
| 500 | { |
| 501 | u32 reg, prediv1, prediv2, podf; |
| 502 | unsigned long parent_rate; |
| 503 | |
| 504 | parent_rate = clk_get_rate(clk->parent); |
| 505 | |
| 506 | if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { |
| 507 | /* the main_bus_clk is the one before the DVFS engine */ |
| 508 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 509 | prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> |
| 510 | MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; |
| 511 | prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> |
| 512 | MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; |
| 513 | podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> |
| 514 | MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; |
| 515 | return parent_rate / (prediv1 * prediv2 * podf); |
| 516 | } else if (clk->parent == &ipg_clk) |
| 517 | return parent_rate; |
| 518 | else |
| 519 | BUG(); |
| 520 | } |
| 521 | |
| 522 | static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) |
| 523 | { |
| 524 | u32 reg; |
| 525 | |
| 526 | reg = __raw_readl(MXC_CCM_CBCMR); |
| 527 | |
| 528 | reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; |
| 529 | reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; |
| 530 | |
| 531 | if (parent == &ipg_clk) |
| 532 | reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; |
| 533 | else if (parent == &lp_apm_clk) |
| 534 | reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; |
| 535 | else if (parent != &main_bus_clk) |
| 536 | return -EINVAL; |
| 537 | |
| 538 | __raw_writel(reg, MXC_CCM_CBCMR); |
| 539 | |
| 540 | return 0; |
| 541 | } |
| 542 | |
| 543 | static unsigned long clk_uart_get_rate(struct clk *clk) |
| 544 | { |
| 545 | u32 reg, prediv, podf; |
| 546 | unsigned long parent_rate; |
| 547 | |
| 548 | parent_rate = clk_get_rate(clk->parent); |
| 549 | |
| 550 | reg = __raw_readl(MXC_CCM_CSCDR1); |
| 551 | prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> |
| 552 | MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; |
| 553 | podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> |
| 554 | MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; |
| 555 | |
| 556 | return parent_rate / (prediv * podf); |
| 557 | } |
| 558 | |
| 559 | static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) |
| 560 | { |
| 561 | u32 reg, mux; |
| 562 | |
| 563 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, |
| 564 | &lp_apm_clk); |
| 565 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; |
| 566 | reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; |
| 567 | __raw_writel(reg, MXC_CCM_CSCMR1); |
| 568 | |
| 569 | return 0; |
| 570 | } |
| 571 | |
| 572 | static unsigned long get_high_reference_clock_rate(struct clk *clk) |
| 573 | { |
| 574 | return external_high_reference; |
| 575 | } |
| 576 | |
| 577 | static unsigned long get_low_reference_clock_rate(struct clk *clk) |
| 578 | { |
| 579 | return external_low_reference; |
| 580 | } |
| 581 | |
| 582 | static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) |
| 583 | { |
| 584 | return oscillator_reference; |
| 585 | } |
| 586 | |
| 587 | static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) |
| 588 | { |
| 589 | return ckih2_reference; |
| 590 | } |
| 591 | |
| 592 | /* External high frequency clock */ |
| 593 | static struct clk ckih_clk = { |
| 594 | .get_rate = get_high_reference_clock_rate, |
| 595 | }; |
| 596 | |
| 597 | static struct clk ckih2_clk = { |
| 598 | .get_rate = get_ckih2_reference_clock_rate, |
| 599 | }; |
| 600 | |
| 601 | static struct clk osc_clk = { |
| 602 | .get_rate = get_oscillator_reference_clock_rate, |
| 603 | }; |
| 604 | |
| 605 | /* External low frequency (32kHz) clock */ |
| 606 | static struct clk ckil_clk = { |
| 607 | .get_rate = get_low_reference_clock_rate, |
| 608 | }; |
| 609 | |
| 610 | static struct clk pll1_main_clk = { |
| 611 | .parent = &osc_clk, |
| 612 | .get_rate = clk_pll_get_rate, |
| 613 | .enable = _clk_pll_enable, |
| 614 | .disable = _clk_pll_disable, |
| 615 | }; |
| 616 | |
| 617 | /* Clock tree block diagram (WIP): |
| 618 | * CCM: Clock Controller Module |
| 619 | * |
| 620 | * PLL output -> | |
| 621 | * | CCM Switcher -> CCM_CLK_ROOT_GEN -> |
| 622 | * PLL bypass -> | |
| 623 | * |
| 624 | */ |
| 625 | |
| 626 | /* PLL1 SW supplies to ARM core */ |
| 627 | static struct clk pll1_sw_clk = { |
| 628 | .parent = &pll1_main_clk, |
| 629 | .set_parent = _clk_pll1_sw_set_parent, |
| 630 | .get_rate = clk_pll1_sw_get_rate, |
| 631 | }; |
| 632 | |
| 633 | /* PLL2 SW supplies to AXI/AHB/IP buses */ |
| 634 | static struct clk pll2_sw_clk = { |
| 635 | .parent = &osc_clk, |
| 636 | .get_rate = clk_pll_get_rate, |
| 637 | .set_rate = _clk_pll_set_rate, |
| 638 | .set_parent = _clk_pll2_sw_set_parent, |
| 639 | .enable = _clk_pll_enable, |
| 640 | .disable = _clk_pll_disable, |
| 641 | }; |
| 642 | |
| 643 | /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ |
| 644 | static struct clk pll3_sw_clk = { |
| 645 | .parent = &osc_clk, |
| 646 | .set_rate = _clk_pll_set_rate, |
| 647 | .get_rate = clk_pll_get_rate, |
| 648 | .enable = _clk_pll_enable, |
| 649 | .disable = _clk_pll_disable, |
| 650 | }; |
| 651 | |
| 652 | /* Low-power Audio Playback Mode clock */ |
| 653 | static struct clk lp_apm_clk = { |
| 654 | .parent = &osc_clk, |
| 655 | .set_parent = _clk_lp_apm_set_parent, |
| 656 | }; |
| 657 | |
| 658 | static struct clk periph_apm_clk = { |
| 659 | .parent = &pll1_sw_clk, |
| 660 | .set_parent = _clk_periph_apm_set_parent, |
| 661 | }; |
| 662 | |
| 663 | static struct clk cpu_clk = { |
| 664 | .parent = &pll1_sw_clk, |
| 665 | .get_rate = clk_arm_get_rate, |
| 666 | }; |
| 667 | |
| 668 | static struct clk ahb_clk = { |
| 669 | .parent = &main_bus_clk, |
| 670 | .get_rate = clk_ahb_get_rate, |
| 671 | .set_rate = _clk_ahb_set_rate, |
| 672 | .round_rate = _clk_ahb_round_rate, |
| 673 | }; |
| 674 | |
| 675 | /* Main IP interface clock for access to registers */ |
| 676 | static struct clk ipg_clk = { |
| 677 | .parent = &ahb_clk, |
| 678 | .get_rate = clk_ipg_get_rate, |
| 679 | }; |
| 680 | |
| 681 | static struct clk ipg_perclk = { |
| 682 | .parent = &lp_apm_clk, |
| 683 | .get_rate = clk_ipg_per_get_rate, |
| 684 | .set_parent = _clk_ipg_per_set_parent, |
| 685 | }; |
| 686 | |
| 687 | static struct clk uart_root_clk = { |
| 688 | .parent = &pll2_sw_clk, |
| 689 | .get_rate = clk_uart_get_rate, |
| 690 | .set_parent = _clk_uart_set_parent, |
| 691 | }; |
| 692 | |
| 693 | static struct clk ahb_max_clk = { |
| 694 | .parent = &ahb_clk, |
| 695 | .enable_reg = MXC_CCM_CCGR0, |
| 696 | .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, |
| 697 | .enable = _clk_max_enable, |
| 698 | .disable = _clk_max_disable, |
| 699 | }; |
| 700 | |
| 701 | static struct clk aips_tz1_clk = { |
| 702 | .parent = &ahb_clk, |
| 703 | .secondary = &ahb_max_clk, |
| 704 | .enable_reg = MXC_CCM_CCGR0, |
| 705 | .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, |
| 706 | .enable = _clk_ccgr_enable, |
| 707 | .disable = _clk_ccgr_disable_inwait, |
| 708 | }; |
| 709 | |
| 710 | static struct clk aips_tz2_clk = { |
| 711 | .parent = &ahb_clk, |
| 712 | .secondary = &ahb_max_clk, |
| 713 | .enable_reg = MXC_CCM_CCGR0, |
| 714 | .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, |
| 715 | .enable = _clk_ccgr_enable, |
| 716 | .disable = _clk_ccgr_disable_inwait, |
| 717 | }; |
| 718 | |
| 719 | static struct clk gpt_32k_clk = { |
| 720 | .id = 0, |
| 721 | .parent = &ckil_clk, |
| 722 | }; |
| 723 | |
| 724 | #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ |
| 725 | static struct clk name = { \ |
| 726 | .id = i, \ |
| 727 | .enable_reg = er, \ |
| 728 | .enable_shift = es, \ |
| 729 | .get_rate = gr, \ |
| 730 | .set_rate = sr, \ |
| 731 | .enable = _clk_ccgr_enable, \ |
| 732 | .disable = _clk_ccgr_disable, \ |
| 733 | .parent = p, \ |
| 734 | .secondary = s, \ |
| 735 | } |
| 736 | |
| 737 | /* DEFINE_CLOCK(name, id, enable_reg, enable_shift, |
| 738 | get_rate, set_rate, parent, secondary); */ |
| 739 | |
| 740 | /* Shared peripheral bus arbiter */ |
| 741 | DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, |
| 742 | NULL, NULL, &ipg_clk, NULL); |
| 743 | |
| 744 | /* UART */ |
| 745 | DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, |
| 746 | NULL, NULL, &uart_root_clk, NULL); |
| 747 | DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, |
| 748 | NULL, NULL, &uart_root_clk, NULL); |
| 749 | DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, |
| 750 | NULL, NULL, &uart_root_clk, NULL); |
| 751 | DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, |
| 752 | NULL, NULL, &ipg_clk, &aips_tz1_clk); |
| 753 | DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, |
| 754 | NULL, NULL, &ipg_clk, &aips_tz1_clk); |
| 755 | DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, |
| 756 | NULL, NULL, &ipg_clk, &spba_clk); |
| 757 | |
| 758 | /* GPT */ |
| 759 | DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, |
Sascha Hauer | 1b6a2b2 | 2010-03-18 16:56:11 +0100 | [diff] [blame] | 760 | NULL, NULL, &ipg_clk, NULL); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 761 | DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, |
| 762 | NULL, NULL, &ipg_clk, NULL); |
| 763 | |
Dinh Nguyen | c53bdf1 | 2010-04-30 15:48:24 -0500 | [diff] [blame^] | 764 | /* USB */ |
| 765 | DEFINE_CLOCK(usboh3_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG14_OFFSET, |
| 766 | NULL, NULL, &pll3_sw_clk, NULL); |
| 767 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 768 | /* FEC */ |
| 769 | DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, |
| 770 | NULL, NULL, &ipg_clk, NULL); |
| 771 | |
| 772 | #define _REGISTER_CLOCK(d, n, c) \ |
| 773 | { \ |
| 774 | .dev_id = d, \ |
| 775 | .con_id = n, \ |
| 776 | .clk = &c, \ |
| 777 | }, |
| 778 | |
| 779 | static struct clk_lookup lookups[] = { |
| 780 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
| 781 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
| 782 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| 783 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) |
| 784 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
Dinh Nguyen | c53bdf1 | 2010-04-30 15:48:24 -0500 | [diff] [blame^] | 785 | _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) |
| 786 | _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) |
| 787 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) |
| 788 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 789 | }; |
| 790 | |
| 791 | static void clk_tree_init(void) |
| 792 | { |
| 793 | u32 reg; |
| 794 | |
| 795 | ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); |
| 796 | |
| 797 | /* |
| 798 | * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at |
| 799 | * 8MHz, its derived from lp_apm. |
| 800 | * |
| 801 | * FIXME: Verify if true for all boards |
| 802 | */ |
| 803 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 804 | reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; |
| 805 | reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; |
| 806 | reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; |
| 807 | reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); |
| 808 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 809 | } |
| 810 | |
| 811 | int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, |
| 812 | unsigned long ckih1, unsigned long ckih2) |
| 813 | { |
| 814 | int i; |
| 815 | |
| 816 | external_low_reference = ckil; |
| 817 | external_high_reference = ckih1; |
| 818 | ckih2_reference = ckih2; |
| 819 | oscillator_reference = osc; |
| 820 | |
| 821 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
| 822 | clkdev_add(&lookups[i]); |
| 823 | |
| 824 | clk_tree_init(); |
| 825 | |
| 826 | clk_enable(&cpu_clk); |
| 827 | clk_enable(&main_bus_clk); |
| 828 | |
| 829 | /* System timer */ |
| 830 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), |
| 831 | MX51_MXC_INT_GPT); |
| 832 | return 0; |
| 833 | } |