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Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
Sujith394cf0a2009-02-09 13:26:54 +053022#include <linux/io.h>
Gabor Juhosab5c4f72012-12-10 15:30:28 +010023#include <linux/firmware.h>
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070024
Sujith394cf0a2009-02-09 13:26:54 +053025#include "mac.h"
26#include "ani.h"
27#include "eeprom.h"
28#include "calib.h"
Sujith394cf0a2009-02-09 13:26:54 +053029#include "reg.h"
30#include "phy.h"
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -070031#include "btcoex.h"
Luis R. Rodrigueza085ff72008-12-23 15:58:51 -080032
Luis R. Rodriguez203c4802009-03-30 22:30:33 -040033#include "../regd.h"
Bob Copeland3a702e42009-03-30 22:30:29 -040034
Sujith394cf0a2009-02-09 13:26:54 +053035#define ATHEROS_VENDOR_ID 0x168c
Luis R. Rodriguez7976b422009-09-23 23:07:02 -040036
Sujith394cf0a2009-02-09 13:26:54 +053037#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
Luis R. Rodriguez5ffaf8a2010-02-02 11:58:33 -050043#define AR2427_DEVID_PCIE 0x002c
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -040044#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030
Vasanthakumar Thiagarajanb99a7be2011-04-19 19:28:59 +053047#define AR9300_DEVID_AR9340 0x0031
Vasanthakumar Thiagarajan3050c912010-12-06 04:27:36 -080048#define AR9300_DEVID_AR9485_PCIE 0x0032
Luis R. Rodriguez5a63ef02011-08-24 15:36:08 -070049#define AR9300_DEVID_AR9580 0x0033
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +053050#define AR9300_DEVID_AR9462 0x0034
Gabor Juhos03689302011-06-21 11:23:22 +020051#define AR9300_DEVID_AR9330 0x0035
Gabor Juhosb1233772012-07-03 19:13:15 +020052#define AR9300_DEVID_QCA955X 0x0038
Mohammed Shafi Shajakhand4e59792012-08-02 11:58:50 +053053#define AR9485_DEVID_AR1111 0x0037
Sujith Manoharan77fac462012-09-11 20:09:18 +053054#define AR9300_DEVID_AR9565 0x0036
Luis R. Rodriguez7976b422009-09-23 23:07:02 -040055
Sujith394cf0a2009-02-09 13:26:54 +053056#define AR5416_AR9100_DEVID 0x000b
Luis R. Rodriguez7976b422009-09-23 23:07:02 -040057
Sujith394cf0a2009-02-09 13:26:54 +053058#define AR_SUBVENDOR_ID_NOG 0x0e11
59#define AR_SUBVENDOR_ID_NEW_A 0x7065
60#define AR5416_MAGIC 0x19641014
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070061
Vasanthakumar Thiagarajanfe129462009-09-09 15:25:50 +053062#define AR9280_COEX2WIRE_SUBSYSID 0x309b
63#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
64#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
65
Luis R. Rodrigueze3d01bf2009-09-13 23:11:13 -070066#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
67
Luis R. Rodriguezcfe8cba2009-09-13 23:39:31 -070068#define ATH_DEFAULT_NOISE_FLOOR -95
69
John W. Linville04658fb2009-11-13 13:12:59 -050070#define ATH9K_RSSI_BAD -128
Luis R. Rodriguez990b70a2009-09-13 23:55:05 -070071
Felix Fietkaucac42202010-10-09 02:39:30 +020072#define ATH9K_NUM_CHANNELS 38
73
Sujith394cf0a2009-02-09 13:26:54 +053074/* Register read/write primitives */
Luis R. Rodriguez9e4bffd2009-09-10 16:11:21 -070075#define REG_WRITE(_ah, _reg, _val) \
Felix Fietkauf9f84e92011-03-23 20:57:24 +010076 (_ah)->reg_ops.write((_ah), (_val), (_reg))
Luis R. Rodriguez9e4bffd2009-09-10 16:11:21 -070077
78#define REG_READ(_ah, _reg) \
Felix Fietkauf9f84e92011-03-23 20:57:24 +010079 (_ah)->reg_ops.read((_ah), (_reg))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070080
Sujith Manoharan09a525d2011-01-04 13:17:18 +053081#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
Felix Fietkauf9f84e92011-03-23 20:57:24 +010082 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
Sujith Manoharan09a525d2011-01-04 13:17:18 +053083
Felix Fietkau845e03c2011-03-23 20:57:25 +010084#define REG_RMW(_ah, _reg, _set, _clr) \
85 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
86
Sujith20b3efd2010-04-16 11:53:55 +053087#define ENABLE_REGWRITE_BUFFER(_ah) \
88 do { \
Felix Fietkauf9f84e92011-03-23 20:57:24 +010089 if ((_ah)->reg_ops.enable_write_buffer) \
90 (_ah)->reg_ops.enable_write_buffer((_ah)); \
Sujith20b3efd2010-04-16 11:53:55 +053091 } while (0)
92
Sujith20b3efd2010-04-16 11:53:55 +053093#define REGWRITE_BUFFER_FLUSH(_ah) \
94 do { \
Felix Fietkauf9f84e92011-03-23 20:57:24 +010095 if ((_ah)->reg_ops.write_flush) \
96 (_ah)->reg_ops.write_flush((_ah)); \
Sujith20b3efd2010-04-16 11:53:55 +053097 } while (0)
98
Rajkumar Manoharan26526202011-07-29 17:38:08 +053099#define PR_EEP(_s, _val) \
100 do { \
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +0200101 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
102 _s, (_val)); \
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530103 } while (0)
104
Sujith394cf0a2009-02-09 13:26:54 +0530105#define SM(_v, _f) (((_v) << _f##_S) & _f)
106#define MS(_v, _f) (((_v) & _f) >> _f##_S)
Sujith394cf0a2009-02-09 13:26:54 +0530107#define REG_RMW_FIELD(_a, _r, _f, _v) \
Felix Fietkau845e03c2011-03-23 20:57:25 +0100108 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
Luis R. Rodriguez1547da32010-04-15 17:39:15 -0400109#define REG_READ_FIELD(_a, _r, _f) \
110 (((REG_READ(_a, _r) & _f) >> _f##_S))
Sujith394cf0a2009-02-09 13:26:54 +0530111#define REG_SET_BIT(_a, _r, _f) \
Felix Fietkau845e03c2011-03-23 20:57:25 +0100112 REG_RMW(_a, _r, (_f), 0)
Sujith394cf0a2009-02-09 13:26:54 +0530113#define REG_CLR_BIT(_a, _r, _f) \
Felix Fietkau845e03c2011-03-23 20:57:25 +0100114 REG_RMW(_a, _r, 0, (_f))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700115
Rajkumar Manoharane7fc6332011-03-15 23:11:35 +0530116#define DO_DELAY(x) do { \
117 if (((++(x) % 64) == 0) && \
118 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
119 != ATH_USB)) \
120 udelay(1); \
Sujith394cf0a2009-02-09 13:26:54 +0530121 } while (0)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700122
Felix Fietkaua9b6b252011-03-23 20:57:27 +0100123#define REG_WRITE_ARRAY(iniarray, column, regWr) \
124 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700125
Sujith394cf0a2009-02-09 13:26:54 +0530126#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
127#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
128#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
129#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
Vasanthakumar Thiagarajan17739122009-08-26 21:08:50 +0530130#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
Sujith394cf0a2009-02-09 13:26:54 +0530131#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
132#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
Mohammed Shafi Shajakhan93d36e92011-11-30 10:41:14 +0530133#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
134#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
135#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
136#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
137#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
138#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
139#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
140#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
141#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
142#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700143
Sujith394cf0a2009-02-09 13:26:54 +0530144#define AR_GPIOD_MASK 0x00001FFF
145#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700146
Sujith394cf0a2009-02-09 13:26:54 +0530147#define BASE_ACTIVATE_DELAY 100
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530148#define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
Sujith394cf0a2009-02-09 13:26:54 +0530149#define COEF_SCALE_S 24
150#define HT40_CHANNEL_CENTER_SHIFT 10
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700151
Sujith394cf0a2009-02-09 13:26:54 +0530152#define ATH9K_ANTENNA0_CHAINMASK 0x1
153#define ATH9K_ANTENNA1_CHAINMASK 0x2
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700154
Sujith394cf0a2009-02-09 13:26:54 +0530155#define ATH9K_NUM_DMA_DEBUG_REGS 8
156#define ATH9K_NUM_QUEUES 10
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700157
Sujith394cf0a2009-02-09 13:26:54 +0530158#define MAX_RATE_POWER 63
Sujith0caa7b12009-02-16 13:23:20 +0530159#define AH_WAIT_TIMEOUT 100000 /* (us) */
Gabor Juhosf9b604f2009-06-21 00:02:15 +0200160#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
Sujith394cf0a2009-02-09 13:26:54 +0530161#define AH_TIME_QUANTUM 10
162#define AR_KEYTABLE_SIZE 128
Sujithd8caa832009-09-17 09:25:45 +0530163#define POWER_UP_TIME 10000
Sujith394cf0a2009-02-09 13:26:54 +0530164#define SPUR_RSSI_THRESH 40
Mohammed Shafi Shajakhan331c5ea2011-07-08 13:01:32 +0530165#define UPPER_5G_SUB_BAND_START 5700
166#define MID_5G_SUB_BAND_START 5400
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700167
Sujith394cf0a2009-02-09 13:26:54 +0530168#define CAB_TIMEOUT_VAL 10
169#define BEACON_TIMEOUT_VAL 10
170#define MIN_BEACON_TIMEOUT_VAL 1
171#define SLEEP_SLOP 3
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700172
Sujith394cf0a2009-02-09 13:26:54 +0530173#define INIT_CONFIG_STATUS 0x00000000
174#define INIT_RSSI_THR 0x00000700
175#define INIT_BCON_CNTRL_REG 0x00000000
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700176
Sujith394cf0a2009-02-09 13:26:54 +0530177#define TU_TO_USEC(_tu) ((_tu) << 10)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700178
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -0400179#define ATH9K_HW_RX_HP_QDEPTH 16
180#define ATH9K_HW_RX_LP_QDEPTH 128
181
Mohammed Shafi Shajakhan0e44d482011-06-17 14:08:42 +0530182#define PAPRD_GAIN_TABLE_ENTRIES 32
183#define PAPRD_TABLE_SZ 24
184#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
Felix Fietkau717f6be2010-06-12 00:34:00 -0400185
Mohammed Shafi Shajakhan01c78532012-07-10 14:54:34 +0530186/*
187 * Wake on Wireless
188 */
189
190/* Keep Alive Frame */
191#define KAL_FRAME_LEN 28
192#define KAL_FRAME_TYPE 0x2 /* data frame */
193#define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
194#define KAL_DURATION_ID 0x3d
195#define KAL_NUM_DATA_WORDS 6
196#define KAL_NUM_DESC_WORDS 12
197#define KAL_ANTENNA_MODE 1
198#define KAL_TO_DS 1
199#define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
200#define KAL_TIMEOUT 900
201
202#define MAX_PATTERN_SIZE 256
203#define MAX_PATTERN_MASK_SIZE 32
204#define MAX_NUM_PATTERN 8
205#define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
206 deauthenticate packets */
207
208/*
209 * WoW trigger mapping to hardware code
210 */
211
212#define AH_WOW_USER_PATTERN_EN BIT(0)
213#define AH_WOW_MAGIC_PATTERN_EN BIT(1)
214#define AH_WOW_LINK_CHANGE BIT(2)
215#define AH_WOW_BEACON_MISS BIT(3)
216
Felix Fietkau066dae92010-11-07 14:59:39 +0100217enum ath_hw_txq_subtype {
218 ATH_TXQ_AC_BE = 0,
219 ATH_TXQ_AC_BK = 1,
220 ATH_TXQ_AC_VI = 2,
221 ATH_TXQ_AC_VO = 3,
222};
223
Luis R. Rodriguez13ce3e92010-04-15 17:38:37 -0400224enum ath_ini_subsys {
225 ATH_INI_PRE = 0,
226 ATH_INI_CORE,
227 ATH_INI_POST,
228 ATH_INI_NUM_SPLIT,
229};
230
Sujith394cf0a2009-02-09 13:26:54 +0530231enum ath9k_hw_caps {
Felix Fietkau364734f2010-09-14 20:22:44 +0200232 ATH9K_HW_CAP_HT = BIT(0),
233 ATH9K_HW_CAP_RFSILENT = BIT(1),
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +0530234 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
235 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
236 ATH9K_HW_CAP_EDMA = BIT(4),
237 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
238 ATH9K_HW_CAP_LDPC = BIT(6),
239 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
240 ATH9K_HW_CAP_SGI_20 = BIT(8),
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +0530241 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
242 ATH9K_HW_CAP_2GHZ = BIT(11),
243 ATH9K_HW_CAP_5GHZ = BIT(12),
244 ATH9K_HW_CAP_APM = BIT(13),
245 ATH9K_HW_CAP_RTT = BIT(14),
246 ATH9K_HW_CAP_MCI = BIT(15),
247 ATH9K_HW_CAP_DFS = BIT(16),
Mohammed Shafi Shajakhan8e981382012-07-10 14:54:53 +0530248 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17),
Sujith Manoharan846e4382013-06-03 09:19:24 +0530249 ATH9K_HW_CAP_PAPRD = BIT(18),
Sujith Manoharan81dc75b2013-07-16 12:03:18 +0530250 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(19),
Sujith Manoharan3f2da952013-08-04 14:21:56 +0530251 ATH9K_HW_CAP_BT_ANT_DIV = BIT(20),
Sujith394cf0a2009-02-09 13:26:54 +0530252};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700253
Mohammed Shafi Shajakhan8e981382012-07-10 14:54:53 +0530254/*
255 * WoW device capabilities
256 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
257 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
258 * an exact user defined pattern or de-authentication/disassoc pattern.
259 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
260 * bytes of the pattern for user defined pattern, de-authentication and
261 * disassociation patterns for all types of possible frames recieved
262 * of those types.
263 */
264
Sujith394cf0a2009-02-09 13:26:54 +0530265struct ath9k_hw_capabilities {
266 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
Sujith394cf0a2009-02-09 13:26:54 +0530267 u16 rts_aggr_limit;
268 u8 tx_chainmask;
269 u8 rx_chainmask;
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -0800270 u8 max_txchains;
271 u8 max_rxchains;
Sujith394cf0a2009-02-09 13:26:54 +0530272 u8 num_gpio_pins;
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -0400273 u8 rx_hp_qdepth;
274 u8 rx_lp_qdepth;
275 u8 rx_status_len;
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -0400276 u8 tx_desc_len;
Vasanthakumar Thiagarajan5088c2f2010-04-15 17:39:34 -0400277 u8 txs_len;
Sujith394cf0a2009-02-09 13:26:54 +0530278};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700279
Sujith394cf0a2009-02-09 13:26:54 +0530280struct ath9k_ops_config {
281 int dma_beacon_response_time;
282 int sw_beacon_response_time;
Sujith394cf0a2009-02-09 13:26:54 +0530283 int ack_6mb;
Felix Fietkau41f3e542010-06-12 00:33:56 -0400284 u32 cwm_ignore_extcca;
Sujith394cf0a2009-02-09 13:26:54 +0530285 u32 pcie_waen;
Sujith394cf0a2009-02-09 13:26:54 +0530286 u8 analog_shiftreg;
Sujith394cf0a2009-02-09 13:26:54 +0530287 u32 ofdm_trig_low;
288 u32 ofdm_trig_high;
289 u32 cck_trig_high;
290 u32 cck_trig_low;
Felix Fietkau74673db2012-09-08 15:24:17 +0200291 u32 enable_paprd;
Sujith394cf0a2009-02-09 13:26:54 +0530292 int serialize_regmode;
Sujith0ce024c2009-12-14 14:57:00 +0530293 bool rx_intr_mitigation;
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400294 bool tx_intr_mitigation;
Sujith394cf0a2009-02-09 13:26:54 +0530295#define AR_NO_SPUR 0x8000
296#define AR_BASE_FREQ_2GHZ 2300
297#define AR_BASE_FREQ_5GHZ 4900
298#define AR_SPUR_FEEQ_BOUND_HT40 19
299#define AR_SPUR_FEEQ_BOUND_HT20 10
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500300 u8 max_txtrig_level;
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -0400301 u16 ani_poll_interval; /* ANI poll interval in ms */
Sujith Manoharan9b60b642013-06-13 22:51:26 +0530302
303 /* Platform specific config */
Sujith Manoharanb380a43b2013-08-25 14:43:09 +0530304 u32 aspm_l1_fix;
Sujith Manoharan9b60b642013-06-13 22:51:26 +0530305 u32 xlna_gpio;
Sujith Manoharan31fd2162013-08-04 14:22:01 +0530306 u32 ant_ctrl_comm2g_switch_enable;
Sujith Manoharan9b60b642013-06-13 22:51:26 +0530307 bool xatten_margin_cfg;
Sujith Manoharane083a422013-08-19 11:04:01 +0530308 bool alt_mingainidx;
Sujith Manoharan2d22c7d2013-11-08 11:45:25 +0530309 bool no_pll_pwrsave;
Sujith Manoharan0f978bf2013-12-06 16:28:45 +0530310 bool tx_gain_buffalo;
Sujith394cf0a2009-02-09 13:26:54 +0530311};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700312
Sujith394cf0a2009-02-09 13:26:54 +0530313enum ath9k_int {
314 ATH9K_INT_RX = 0x00000001,
315 ATH9K_INT_RXDESC = 0x00000002,
Felix Fietkaub5c804752010-04-15 17:38:48 -0400316 ATH9K_INT_RXHP = 0x00000001,
317 ATH9K_INT_RXLP = 0x00000002,
Sujith394cf0a2009-02-09 13:26:54 +0530318 ATH9K_INT_RXNOFRM = 0x00000008,
319 ATH9K_INT_RXEOL = 0x00000010,
320 ATH9K_INT_RXORN = 0x00000020,
321 ATH9K_INT_TX = 0x00000040,
322 ATH9K_INT_TXDESC = 0x00000080,
323 ATH9K_INT_TIM_TIMER = 0x00000100,
Mohammed Shafi Shajakhan2ee4bd12011-11-30 10:41:13 +0530324 ATH9K_INT_MCI = 0x00000200,
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -0400325 ATH9K_INT_BB_WATCHDOG = 0x00000400,
Sujith394cf0a2009-02-09 13:26:54 +0530326 ATH9K_INT_TXURN = 0x00000800,
327 ATH9K_INT_MIB = 0x00001000,
328 ATH9K_INT_RXPHY = 0x00004000,
329 ATH9K_INT_RXKCM = 0x00008000,
330 ATH9K_INT_SWBA = 0x00010000,
331 ATH9K_INT_BMISS = 0x00040000,
332 ATH9K_INT_BNR = 0x00100000,
333 ATH9K_INT_TIM = 0x00200000,
334 ATH9K_INT_DTIM = 0x00400000,
335 ATH9K_INT_DTIMSYNC = 0x00800000,
336 ATH9K_INT_GPIO = 0x01000000,
337 ATH9K_INT_CABEND = 0x02000000,
Sujith4af9cf42009-02-12 10:06:47 +0530338 ATH9K_INT_TSFOOR = 0x04000000,
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +0530339 ATH9K_INT_GENTIMER = 0x08000000,
Sujith394cf0a2009-02-09 13:26:54 +0530340 ATH9K_INT_CST = 0x10000000,
341 ATH9K_INT_GTT = 0x20000000,
342 ATH9K_INT_FATAL = 0x40000000,
343 ATH9K_INT_GLOBAL = 0x80000000,
344 ATH9K_INT_BMISC = ATH9K_INT_TIM |
345 ATH9K_INT_DTIM |
346 ATH9K_INT_DTIMSYNC |
Sujith4af9cf42009-02-12 10:06:47 +0530347 ATH9K_INT_TSFOOR |
Sujith394cf0a2009-02-09 13:26:54 +0530348 ATH9K_INT_CABEND,
349 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
350 ATH9K_INT_RXDESC |
351 ATH9K_INT_RXEOL |
352 ATH9K_INT_RXORN |
353 ATH9K_INT_TXURN |
354 ATH9K_INT_TXDESC |
355 ATH9K_INT_MIB |
356 ATH9K_INT_RXPHY |
357 ATH9K_INT_RXKCM |
358 ATH9K_INT_SWBA |
359 ATH9K_INT_BMISS |
360 ATH9K_INT_GPIO,
361 ATH9K_INT_NOCARD = 0xffffffff
362};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700363
Rajkumar Manoharan324c74a2011-10-13 11:00:41 +0530364#define MAX_RTT_TABLE_ENTRY 6
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +0530365#define MAX_IQCAL_MEASUREMENT 8
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +0530366#define MAX_CL_TAB_ENTRY 16
Sujith Manoharan96da6fd2013-01-07 14:43:33 +0530367#define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +0530368
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +0530369enum ath9k_cal_flags {
370 RTT_DONE,
371 PAPRD_PACKET_SENT,
372 PAPRD_DONE,
373 NFCAL_PENDING,
374 NFCAL_INTF,
375 TXIQCAL_DONE,
376 TXCLCAL_DONE,
Sujith Manoharan3001f0d2013-09-11 16:36:32 +0530377 SW_PKDET_DONE,
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +0530378};
379
Felix Fietkau20bd2a02010-07-31 00:12:00 +0200380struct ath9k_hw_cal_data {
Sujith394cf0a2009-02-09 13:26:54 +0530381 u16 channel;
Felix Fietkau6b21fd22013-10-11 23:30:56 +0200382 u16 channelFlags;
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +0530383 unsigned long cal_flags;
Sujith394cf0a2009-02-09 13:26:54 +0530384 int32_t CalValid;
Sujith394cf0a2009-02-09 13:26:54 +0530385 int8_t iCoff;
386 int8_t qCoff;
Sujith Manoharan3001f0d2013-09-11 16:36:32 +0530387 u8 caldac[2];
Felix Fietkau717f6be2010-06-12 00:34:00 -0400388 u16 small_signal_gain[AR9300_MAX_CHAINS];
389 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +0530390 u32 num_measures[AR9300_MAX_CHAINS];
391 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +0530392 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
Sujith Manoharan8a905552012-05-04 13:23:59 +0530393 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
Felix Fietkau20bd2a02010-07-31 00:12:00 +0200394 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
395};
396
397struct ath9k_channel {
398 struct ieee80211_channel *chan;
399 u16 channel;
Felix Fietkau6b21fd22013-10-11 23:30:56 +0200400 u16 channelFlags;
Felix Fietkaud9891c72010-09-29 17:15:27 +0200401 s16 noisefloor;
Sujith394cf0a2009-02-09 13:26:54 +0530402};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700403
Felix Fietkau6b21fd22013-10-11 23:30:56 +0200404#define CHANNEL_5GHZ BIT(0)
405#define CHANNEL_HALF BIT(1)
406#define CHANNEL_QUARTER BIT(2)
407#define CHANNEL_HT BIT(3)
408#define CHANNEL_HT40PLUS BIT(4)
409#define CHANNEL_HT40MINUS BIT(5)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700410
Felix Fietkau6b21fd22013-10-11 23:30:56 +0200411#define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
412#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
413
414#define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
415#define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
416#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
417 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
418
419#define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
420
421#define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
422
423#define IS_CHAN_HT40(_c) \
424 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
425
426#define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
427#define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700428
Sujith394cf0a2009-02-09 13:26:54 +0530429enum ath9k_power_mode {
430 ATH9K_PM_AWAKE = 0,
431 ATH9K_PM_FULL_SLEEP,
432 ATH9K_PM_NETWORK_SLEEP,
433 ATH9K_PM_UNDEFINED
434};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700435
Sujith394cf0a2009-02-09 13:26:54 +0530436enum ser_reg_mode {
437 SER_REG_MODE_OFF = 0,
438 SER_REG_MODE_ON = 1,
439 SER_REG_MODE_AUTO = 2,
440};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700441
Vasanthakumar Thiagarajanad7b8062010-04-15 17:38:28 -0400442enum ath9k_rx_qtype {
443 ATH9K_RX_QUEUE_HP,
444 ATH9K_RX_QUEUE_LP,
445 ATH9K_RX_QUEUE_MAX,
446};
447
Sujith394cf0a2009-02-09 13:26:54 +0530448struct ath9k_beacon_state {
449 u32 bs_nexttbtt;
450 u32 bs_nextdtim;
451 u32 bs_intval;
Sujith4af9cf42009-02-12 10:06:47 +0530452#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
Sujith394cf0a2009-02-09 13:26:54 +0530453 u32 bs_dtimperiod;
454 u16 bs_cfpperiod;
455 u16 bs_cfpmaxduration;
456 u32 bs_cfpnext;
457 u16 bs_timoffset;
458 u16 bs_bmissthreshold;
459 u32 bs_sleepduration;
Sujith4af9cf42009-02-12 10:06:47 +0530460 u32 bs_tsfoor_threshold;
Sujith394cf0a2009-02-09 13:26:54 +0530461};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700462
Sujith394cf0a2009-02-09 13:26:54 +0530463struct chan_centers {
464 u16 synth_center;
465 u16 ctl_center;
466 u16 ext_center;
467};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700468
Sujith394cf0a2009-02-09 13:26:54 +0530469enum {
470 ATH9K_RESET_POWER_ON,
471 ATH9K_RESET_WARM,
472 ATH9K_RESET_COLD,
473};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700474
Sujithd535a422009-02-09 13:27:06 +0530475struct ath9k_hw_version {
476 u32 magic;
477 u16 devid;
478 u16 subvendorid;
479 u32 macVersion;
480 u16 macRev;
481 u16 phyRev;
482 u16 analog5GhzRev;
483 u16 analog2GhzRev;
Sujith Manoharan0b5ead92010-12-07 16:31:38 +0530484 enum ath_usb_dev usbdev;
Sujithd535a422009-02-09 13:27:06 +0530485};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700486
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +0530487/* Generic TSF timer definitions */
488
489#define ATH_MAX_GEN_TIMER 16
490
491#define AR_GENTMR_BIT(_index) (1 << (_index))
492
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +0530493struct ath_gen_timer_configuration {
494 u32 next_addr;
495 u32 period_addr;
496 u32 mode_addr;
497 u32 mode_mask;
498};
499
500struct ath_gen_timer {
501 void (*trigger)(void *arg);
502 void (*overflow)(void *arg);
503 void *arg;
504 u8 index;
505};
506
507struct ath_gen_timer_table {
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +0530508 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
Felix Fietkauc67ce332013-12-14 18:03:38 +0100509 u16 timer_mask;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +0530510};
511
Vasanthakumar Thiagarajan21cc6302010-09-02 01:34:42 -0700512struct ath_hw_antcomb_conf {
513 u8 main_lna_conf;
514 u8 alt_lna_conf;
515 u8 fast_div_bias;
Mohammed Shafi Shajakhanc6ba9fe2011-05-13 20:29:53 +0530516 u8 main_gaintb;
517 u8 alt_gaintb;
518 int lna1_lna2_delta;
Sujith Manoharanf96bd2a2013-09-02 13:59:03 +0530519 int lna1_lna2_switch_delta;
Mohammed Shafi Shajakhan8afbcc82011-05-13 20:30:56 +0530520 u8 div_group;
Vasanthakumar Thiagarajan21cc6302010-09-02 01:34:42 -0700521};
522
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400523/**
Felix Fietkau4e8c14e2010-11-11 03:18:38 +0100524 * struct ath_hw_radar_conf - radar detection initialization parameters
525 *
526 * @pulse_inband: threshold for checking the ratio of in-band power
527 * to total power for short radar pulses (half dB steps)
528 * @pulse_inband_step: threshold for checking an in-band power to total
529 * power ratio increase for short radar pulses (half dB steps)
530 * @pulse_height: threshold for detecting the beginning of a short
531 * radar pulse (dB step)
532 * @pulse_rssi: threshold for detecting if a short radar pulse is
533 * gone (dB step)
534 * @pulse_maxlen: maximum pulse length (0.8 us steps)
535 *
536 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
537 * @radar_inband: threshold for checking the ratio of in-band power
538 * to total power for long radar pulses (half dB steps)
539 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
540 *
541 * @ext_channel: enable extension channel radar detection
542 */
543struct ath_hw_radar_conf {
544 unsigned int pulse_inband;
545 unsigned int pulse_inband_step;
546 unsigned int pulse_height;
547 unsigned int pulse_rssi;
548 unsigned int pulse_maxlen;
549
550 unsigned int radar_rssi;
551 unsigned int radar_inband;
552 int fir_power;
553
554 bool ext_channel;
555};
556
557/**
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400558 * struct ath_hw_private_ops - callbacks used internally by hardware code
559 *
560 * This structure contains private callbacks designed to only be used internally
561 * by the hardware core.
562 *
Luis R. Rodriguez795f5e22010-04-15 17:39:00 -0400563 * @init_cal_settings: setup types of calibrations supported
564 * @init_cal: starts actual calibration
565 *
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400566 * @init_mode_gain_regs: Initialize TX/RX gain registers
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400567 *
568 * @rf_set_freq: change frequency
569 * @spur_mitigate_freq: spur mitigation
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400570 * @set_rf_regs:
Luis R. Rodriguez64773962010-04-15 17:38:17 -0400571 * @compute_pll_control: compute the PLL control value to use for
572 * AR_RTC_PLL_CONTROL for a given channel
Luis R. Rodriguez795f5e22010-04-15 17:39:00 -0400573 * @setup_calibration: set up calibration
574 * @iscal_supported: used to query if a type of calibration is supported
Luis R. Rodriguezac0bb762010-06-12 00:33:42 -0400575 *
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -0400576 * @ani_cache_ini_regs: cache the values for ANI from the initial
577 * register settings through the register initialization.
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400578 */
579struct ath_hw_private_ops {
Luis R. Rodriguez795f5e22010-04-15 17:39:00 -0400580 /* Calibration ops */
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400581 void (*init_cal_settings)(struct ath_hw *ah);
Luis R. Rodriguez795f5e22010-04-15 17:39:00 -0400582 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
583
Luis R. Rodriguez991312d2010-04-15 17:39:05 -0400584 void (*init_mode_gain_regs)(struct ath_hw *ah);
Luis R. Rodriguez795f5e22010-04-15 17:39:00 -0400585 void (*setup_calibration)(struct ath_hw *ah,
586 struct ath9k_cal_list *currCal);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400587
588 /* PHY ops */
589 int (*rf_set_freq)(struct ath_hw *ah,
590 struct ath9k_channel *chan);
591 void (*spur_mitigate_freq)(struct ath_hw *ah,
592 struct ath9k_channel *chan);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400593 bool (*set_rf_regs)(struct ath_hw *ah,
594 struct ath9k_channel *chan,
595 u16 modesIndex);
596 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
597 void (*init_bb)(struct ath_hw *ah,
598 struct ath9k_channel *chan);
599 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
600 void (*olc_init)(struct ath_hw *ah);
601 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
602 void (*mark_phy_inactive)(struct ath_hw *ah);
603 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
604 bool (*rfbus_req)(struct ath_hw *ah);
605 void (*rfbus_done)(struct ath_hw *ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400606 void (*restore_chainmask)(struct ath_hw *ah);
Luis R. Rodriguez64773962010-04-15 17:38:17 -0400607 u32 (*compute_pll_control)(struct ath_hw *ah,
608 struct ath9k_channel *chan);
Felix Fietkauc16fcb42010-04-15 17:38:39 -0400609 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
610 int param);
Felix Fietkau641d9922010-04-15 17:38:49 -0400611 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
Felix Fietkau4e8c14e2010-11-11 03:18:38 +0100612 void (*set_radar_params)(struct ath_hw *ah,
613 struct ath_hw_radar_conf *conf);
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +0530614 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
615 u8 *ini_reloaded);
Luis R. Rodriguezac0bb762010-06-12 00:33:42 -0400616
617 /* ANI */
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -0400618 void (*ani_cache_ini_regs)(struct ath_hw *ah);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400619};
620
621/**
Simon Wunderliche93d0832013-01-08 14:48:58 +0100622 * struct ath_spec_scan - parameters for Atheros spectral scan
623 *
624 * @enabled: enable/disable spectral scan
625 * @short_repeat: controls whether the chip is in spectral scan mode
626 * for 4 usec (enabled) or 204 usec (disabled)
627 * @count: number of scan results requested. There are special meanings
628 * in some chip revisions:
629 * AR92xx: highest bit set (>=128) for endless mode
630 * (spectral scan won't stopped until explicitly disabled)
631 * AR9300 and newer: 0 for endless mode
632 * @endless: true if endless mode is intended. Otherwise, count value is
633 * corrected to the next possible value.
634 * @period: time duration between successive spectral scan entry points
635 * (period*256*Tclk). Tclk = ath_common->clockrate
636 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
637 *
638 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
639 * Typically it's 44MHz in 2/5GHz on later chips, but there's
640 * a "fast clock" check for this in 5GHz.
641 *
642 */
643struct ath_spec_scan {
644 bool enabled;
645 bool short_repeat;
646 bool endless;
647 u8 count;
648 u8 period;
649 u8 fft_period;
650};
651
652/**
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400653 * struct ath_hw_ops - callbacks used by hardware code and driver code
654 *
655 * This structure contains callbacks designed to to be used internally by
656 * hardware code and also by the lower level driver.
657 *
658 * @config_pci_powersave:
Luis R. Rodriguez795f5e22010-04-15 17:39:00 -0400659 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
Simon Wunderliche93d0832013-01-08 14:48:58 +0100660 *
661 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
662 * @spectral_scan_trigger: trigger a spectral scan run
663 * @spectral_scan_wait: wait for a spectral scan run to finish
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400664 */
665struct ath_hw_ops {
666 void (*config_pci_powersave)(struct ath_hw *ah,
Stanislaw Gruszka84c87dc2011-08-05 13:10:32 +0200667 bool power_off);
Vasanthakumar Thiagarajancee1f622010-04-15 17:38:26 -0400668 void (*rx_enable)(struct ath_hw *ah);
Vasanthakumar Thiagarajan87d5efb2010-04-15 17:38:43 -0400669 void (*set_desc_link)(void *ds, u32 link);
Luis R. Rodriguez795f5e22010-04-15 17:39:00 -0400670 bool (*calibrate)(struct ath_hw *ah,
671 struct ath9k_channel *chan,
672 u8 rxchainmask,
673 bool longcal);
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400674 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
Felix Fietkau2b63a412011-09-14 21:24:21 +0200675 void (*set_txdesc)(struct ath_hw *ah, void *ds,
676 struct ath_tx_info *i);
Vasanthakumar Thiagarajancc610ac02010-04-15 17:39:26 -0400677 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
678 struct ath_tx_status *ts);
Mohammed Shafi Shajakhan69de3722011-05-13 20:29:04 +0530679 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
680 struct ath_hw_antcomb_conf *antconf);
681 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
682 struct ath_hw_antcomb_conf *antconf);
Simon Wunderliche93d0832013-01-08 14:48:58 +0100683 void (*spectral_scan_config)(struct ath_hw *ah,
684 struct ath_spec_scan *param);
685 void (*spectral_scan_trigger)(struct ath_hw *ah);
686 void (*spectral_scan_wait)(struct ath_hw *ah);
Sujith Manoharan36e88252013-08-06 12:44:15 +0530687
Luis R. Rodriguez89f927a2013-10-14 17:42:11 -0700688 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
689 void (*tx99_stop)(struct ath_hw *ah);
690 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
691
Sujith Manoharan36e88252013-08-06 12:44:15 +0530692#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
693 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
694#endif
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400695};
696
Felix Fietkauf2552e22010-07-02 00:09:50 +0200697struct ath_nf_limits {
698 s16 max;
699 s16 min;
700 s16 nominal;
701};
702
Rajkumar Manoharan8ad74c42011-10-13 11:00:38 +0530703enum ath_cal_list {
704 TX_IQ_CAL = BIT(0),
705 TX_IQ_ON_AGC_CAL = BIT(1),
706 TX_CL_CAL = BIT(2),
707};
708
Sujith Manoharan97dcec52010-12-20 08:02:42 +0530709/* ah_flags */
710#define AH_USE_EEPROM 0x1
711#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
Rajkumar Manoharana126ff52011-10-13 11:00:42 +0530712#define AH_FASTCC 0x4
Sujith Manoharan97dcec52010-12-20 08:02:42 +0530713
Sujithcbe61d82009-02-09 13:27:12 +0530714struct ath_hw {
Felix Fietkauf9f84e92011-03-23 20:57:24 +0100715 struct ath_ops reg_ops;
716
Felix Fietkauc1b976d2012-12-12 13:14:23 +0100717 struct device *dev;
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -0700718 struct ieee80211_hw *hw;
Luis R. Rodriguez27c51f12009-09-10 11:08:14 -0700719 struct ath_common common;
Sujithcbe61d82009-02-09 13:27:12 +0530720 struct ath9k_hw_version hw_version;
Sujith2660b812009-02-09 13:27:26 +0530721 struct ath9k_ops_config config;
722 struct ath9k_hw_capabilities caps;
Felix Fietkaucac42202010-10-09 02:39:30 +0200723 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
Sujith2660b812009-02-09 13:27:26 +0530724 struct ath9k_channel *curchan;
Sujith394cf0a2009-02-09 13:26:54 +0530725
Sujithcbe61d82009-02-09 13:27:12 +0530726 union {
727 struct ar5416_eeprom_def def;
728 struct ar5416_eeprom_4k map4k;
Luis R. Rodriguez475f5982009-08-03 17:31:25 -0400729 struct ar9287_eeprom map9287;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400730 struct ar9300_eeprom ar9300_eep;
Sujith2660b812009-02-09 13:27:26 +0530731 } eeprom;
Sujithf74df6f2009-02-09 13:27:24 +0530732 const struct eeprom_ops *eep_ops;
Sujithcbe61d82009-02-09 13:27:12 +0530733
734 bool sw_mgmt_crypto;
Sujith2660b812009-02-09 13:27:26 +0530735 bool is_pciexpress;
Stanislaw Gruszkad4930082011-07-29 15:59:08 +0200736 bool aspm_enabled;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +0530737 bool is_monitoring;
Pavel Roskin2eb46d92010-04-07 01:33:33 -0400738 bool need_an_top2_fixup;
Sujith2660b812009-02-09 13:27:26 +0530739 u16 tx_trig_level;
Felix Fietkauf2552e22010-07-02 00:09:50 +0200740
Felix Fietkaubbacee12010-07-11 15:44:42 +0200741 u32 nf_regs[6];
Felix Fietkauf2552e22010-07-02 00:09:50 +0200742 struct ath_nf_limits nf_2g;
743 struct ath_nf_limits nf_5g;
Sujith2660b812009-02-09 13:27:26 +0530744 u16 rfsilent;
745 u32 rfkill_gpio;
746 u32 rfkill_polarity;
Sujithcbe61d82009-02-09 13:27:12 +0530747 u32 ah_flags;
Sujithcbe61d82009-02-09 13:27:12 +0530748
Felix Fietkauceb26a62012-10-03 21:07:51 +0200749 bool reset_power_on;
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400750 bool htc_reset_init;
751
Sujith2660b812009-02-09 13:27:26 +0530752 enum nl80211_iftype opmode;
753 enum ath9k_power_mode power_mode;
Sujith394cf0a2009-02-09 13:26:54 +0530754
Felix Fietkauf23fba492011-07-28 14:08:56 +0200755 s8 noise;
Felix Fietkau20bd2a02010-07-31 00:12:00 +0200756 struct ath9k_hw_cal_data *caldata;
Sujitha13883b2009-08-26 08:39:40 +0530757 struct ath9k_pacal_info pacal_info;
Sujith2660b812009-02-09 13:27:26 +0530758 struct ar5416Stats stats;
759 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
Sujith6a2b9e82008-08-11 14:04:32 +0530760
Pavel Roskin30691682010-03-31 18:05:31 -0400761 enum ath9k_int imask;
Pavel Roskin74bad5c2010-02-23 18:15:27 -0500762 u32 imrs2_reg;
Sujith2660b812009-02-09 13:27:26 +0530763 u32 txok_interrupt_mask;
764 u32 txerr_interrupt_mask;
765 u32 txdesc_interrupt_mask;
766 u32 txeol_interrupt_mask;
767 u32 txurn_interrupt_mask;
Rajkumar Manoharane8fe7332011-08-05 18:59:41 +0530768 atomic_t intr_ref_cnt;
Sujith2660b812009-02-09 13:27:26 +0530769 bool chip_fullsleep;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +0530770 u32 modes_index;
Sujith6a2b9e82008-08-11 14:04:32 +0530771
772 /* Calibration */
Felix Fietkau64978272010-10-03 19:07:16 +0200773 u32 supp_cals;
Sujithcbfe9462009-04-13 21:56:56 +0530774 struct ath9k_cal_list iq_caldata;
775 struct ath9k_cal_list adcgain_caldata;
Sujithcbfe9462009-04-13 21:56:56 +0530776 struct ath9k_cal_list adcdc_caldata;
777 struct ath9k_cal_list *cal_list;
778 struct ath9k_cal_list *cal_list_last;
779 struct ath9k_cal_list *cal_list_curr;
Sujith2660b812009-02-09 13:27:26 +0530780#define totalPowerMeasI meas0.unsign
781#define totalPowerMeasQ meas1.unsign
782#define totalIqCorrMeas meas2.sign
783#define totalAdcIOddPhase meas0.unsign
784#define totalAdcIEvenPhase meas1.unsign
785#define totalAdcQOddPhase meas2.unsign
786#define totalAdcQEvenPhase meas3.unsign
787#define totalAdcDcOffsetIOddPhase meas0.sign
788#define totalAdcDcOffsetIEvenPhase meas1.sign
789#define totalAdcDcOffsetQOddPhase meas2.sign
790#define totalAdcDcOffsetQEvenPhase meas3.sign
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700791 union {
792 u32 unsign[AR5416_MAX_CHAINS];
793 int32_t sign[AR5416_MAX_CHAINS];
Sujith2660b812009-02-09 13:27:26 +0530794 } meas0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700795 union {
796 u32 unsign[AR5416_MAX_CHAINS];
797 int32_t sign[AR5416_MAX_CHAINS];
Sujith2660b812009-02-09 13:27:26 +0530798 } meas1;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700799 union {
800 u32 unsign[AR5416_MAX_CHAINS];
801 int32_t sign[AR5416_MAX_CHAINS];
Sujith2660b812009-02-09 13:27:26 +0530802 } meas2;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700803 union {
804 u32 unsign[AR5416_MAX_CHAINS];
805 int32_t sign[AR5416_MAX_CHAINS];
Sujith2660b812009-02-09 13:27:26 +0530806 } meas3;
807 u16 cal_samples;
Rajkumar Manoharan8ad74c42011-10-13 11:00:38 +0530808 u8 enabled_cals;
Sujith6a2b9e82008-08-11 14:04:32 +0530809
Sujith2660b812009-02-09 13:27:26 +0530810 u32 sta_id1_defaults;
811 u32 misc_mode;
Sujith6a2b9e82008-08-11 14:04:32 +0530812
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400813 /* Private to hardware code */
814 struct ath_hw_private_ops private_ops;
815 /* Accessed by the lower level driver */
816 struct ath_hw_ops ops;
817
Luis R. Rodrigueze68a0602009-10-19 02:33:41 -0400818 /* Used to program the radio on non single-chip devices */
Sujith2660b812009-02-09 13:27:26 +0530819 u32 *analogBank6Data;
Sujith6a2b9e82008-08-11 14:04:32 +0530820
Felix Fietkaue239d852010-01-15 02:34:58 +0100821 int coverage_class;
Sujith2660b812009-02-09 13:27:26 +0530822 u32 slottime;
Sujith2660b812009-02-09 13:27:26 +0530823 u32 globaltxtimeout;
Sujith6a2b9e82008-08-11 14:04:32 +0530824
825 /* ANI */
Sujith2660b812009-02-09 13:27:26 +0530826 u32 aniperiod;
Sujith2660b812009-02-09 13:27:26 +0530827 enum ath9k_ani_cmd ani_function;
Rajkumar Manoharan424749c2012-10-10 23:03:02 +0530828 u32 ani_skip_count;
Sujith Manoharanc24bd362013-06-03 09:19:29 +0530829 struct ar5416AniState ani;
Sujith6a2b9e82008-08-11 14:04:32 +0530830
Sujith Manoharandbccdd12012-02-22 17:55:47 +0530831#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -0700832 struct ath_btcoex_hw btcoex_hw;
Sujith Manoharandbccdd12012-02-22 17:55:47 +0530833#endif
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -0700834
Sujith2660b812009-02-09 13:27:26 +0530835 u32 intr_txqs;
Sujith2660b812009-02-09 13:27:26 +0530836 u8 txchainmask;
837 u8 rxchainmask;
Sujith6a2b9e82008-08-11 14:04:32 +0530838
Felix Fietkauc5d08552010-11-13 20:22:41 +0100839 struct ath_hw_radar_conf radar_conf;
840
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530841 u32 originalGain[22];
842 int initPDADC;
843 int PDADCdelta;
Felix Fietkau6de66dd2011-03-19 13:55:40 +0100844 int led_pin;
Felix Fietkau691680b2011-03-19 13:55:38 +0100845 u32 gpio_mask;
846 u32 gpio_val;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530847
Sujith Manoharan4a878b92013-12-06 16:28:40 +0530848 struct ar5416IniArray ini_dfs;
Sujith2660b812009-02-09 13:27:26 +0530849 struct ar5416IniArray iniModes;
850 struct ar5416IniArray iniCommon;
Sujith2660b812009-02-09 13:27:26 +0530851 struct ar5416IniArray iniBB_RfGain;
Sujith2660b812009-02-09 13:27:26 +0530852 struct ar5416IniArray iniBank6;
Sujith2660b812009-02-09 13:27:26 +0530853 struct ar5416IniArray iniAddac;
854 struct ar5416IniArray iniPcieSerdes;
Luis R. Rodriguez13ce3e92010-04-15 17:38:37 -0400855 struct ar5416IniArray iniPcieSerdesLowPower;
Felix Fietkauc7d36f92012-03-14 16:40:31 +0100856 struct ar5416IniArray iniModesFastClock;
857 struct ar5416IniArray iniAdditional;
Sujith2660b812009-02-09 13:27:26 +0530858 struct ar5416IniArray iniModesRxGain;
Gabor Juhos8bc45c62012-07-03 19:13:23 +0200859 struct ar5416IniArray ini_modes_rx_gain_bounds;
Sujith2660b812009-02-09 13:27:26 +0530860 struct ar5416IniArray iniModesTxGain;
Sujith193cd452009-09-18 15:04:07 +0530861 struct ar5416IniArray iniCckfirNormal;
862 struct ar5416IniArray iniCckfirJapan2484;
Sujith70807e92010-03-17 14:25:14 +0530863 struct ar5416IniArray iniModes_9271_ANI_reg;
Senthil Balasubramaniance407af2011-09-13 22:38:16 +0530864 struct ar5416IniArray ini_radio_post_sys2ant;
Sujith Manoharan51dbd0a2013-06-18 10:13:42 +0530865 struct ar5416IniArray ini_modes_rxgain_5g_xlna;
Sujith Manoharanc177fab2013-06-18 15:42:38 +0530866 struct ar5416IniArray ini_modes_rxgain_bb_core;
867 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +0530868
Luis R. Rodriguez13ce3e92010-04-15 17:38:37 -0400869 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
870 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
871 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
872 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
873
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +0530874 u32 intr_gen_timer_trigger;
875 u32 intr_gen_timer_thresh;
876 struct ath_gen_timer_table hw_gen_timers;
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -0400877
878 struct ar9003_txs *ts_ring;
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -0400879 u32 ts_paddr_start;
880 u32 ts_paddr_end;
881 u16 ts_tail;
Rajkumar Manoharan016c2172011-12-23 21:27:02 +0530882 u16 ts_size;
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -0400883
884 u32 bb_watchdog_last_status;
885 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +0530886 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
Felix Fietkau717f6be2010-06-12 00:34:00 -0400887
Felix Fietkau1bf38662010-12-13 08:40:54 +0100888 unsigned int paprd_target_power;
889 unsigned int paprd_training_power;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800890 unsigned int paprd_ratemask;
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100891 unsigned int paprd_ratemask_ht40;
Vasanthakumar Thiagarajan45ef6a0b2010-12-15 07:30:53 -0800892 bool paprd_table_write_done;
Felix Fietkau717f6be2010-06-12 00:34:00 -0400893 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
894 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -0400895 /*
896 * Store the permanent value of Reg 0x4004in WARegVal
897 * so we dont have to R/M/W. We should not be reading
898 * this register when in sleep states.
899 */
900 u32 WARegVal;
Senthil Balasubramanian6ee63f52010-11-10 05:03:16 -0800901
902 /* Enterprise mode cap */
903 u32 ent_mode;
Vasanthakumar Thiagarajanf2f5f2a2011-04-19 19:29:01 +0530904
Sujith Manoharane60001e2013-10-28 12:22:04 +0530905#ifdef CONFIG_ATH9K_WOW
Mohammed Shafi Shajakhan01c78532012-07-10 14:54:34 +0530906 u32 wow_event_mask;
907#endif
Vasanthakumar Thiagarajanf2f5f2a2011-04-19 19:29:01 +0530908 bool is_clk_25mhz;
Gabor Juhos37625612011-06-21 11:23:23 +0200909 int (*get_mac_revision)(void);
Gabor Juhos7d95847c2011-06-21 11:23:51 +0200910 int (*external_reset)(void);
Gabor Juhosab5c4f72012-12-10 15:30:28 +0100911
912 const struct firmware *eeprom_blob;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700913};
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700914
Felix Fietkau0cb9e062011-04-13 21:56:43 +0200915struct ath_bus_ops {
916 enum ath_bus_type ath_bus_type;
917 void (*read_cachesize)(struct ath_common *common, int *csz);
918 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
919 void (*bt_coex_prep)(struct ath_common *common);
Stanislaw Gruszkad4930082011-07-29 15:59:08 +0200920 void (*aspm_init)(struct ath_common *common);
Felix Fietkau0cb9e062011-04-13 21:56:43 +0200921};
922
Luis R. Rodriguez9e4bffd2009-09-10 16:11:21 -0700923static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
924{
925 return &ah->common;
926}
927
928static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
929{
930 return &(ath9k_hw_common(ah)->regulatory);
931}
932
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400933static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
934{
935 return &ah->private_ops;
936}
937
938static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
939{
940 return &ah->ops;
941}
942
Vasanthakumar Thiagarajan895ad7e2010-12-15 07:30:49 -0800943static inline u8 get_streams(int mask)
944{
945 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
946}
947
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700948/* Initialization, Detach, Reset */
Sujith285f2dd2010-01-08 10:36:07 +0530949void ath9k_hw_deinit(struct ath_hw *ah);
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700950int ath9k_hw_init(struct ath_hw *ah);
Sujithcbe61d82009-02-09 13:27:12 +0530951int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
Sujith Manoharancaed6572012-03-14 14:40:46 +0530952 struct ath9k_hw_cal_data *caldata, bool fastcc);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +0100953int ath9k_hw_fill_cap_info(struct ath_hw *ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -0400954u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700955
Sujith394cf0a2009-02-09 13:26:54 +0530956/* GPIO / RFKILL / Antennae */
Sujithcbe61d82009-02-09 13:27:12 +0530957void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
958u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
959void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
Sujith394cf0a2009-02-09 13:26:54 +0530960 u32 ah_signal_type);
Sujithcbe61d82009-02-09 13:27:12 +0530961void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
Sujithcbe61d82009-02-09 13:27:12 +0530962void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700963
Sujith394cf0a2009-02-09 13:26:54 +0530964/* General Operation */
Felix Fietkau7c5adc82012-04-19 21:18:26 +0200965void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
966 int hw_delay);
Sujith0caa7b12009-02-16 13:23:20 +0530967bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
Felix Fietkau0166b4b2013-01-20 18:51:55 +0100968void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
Felix Fietkaua9b6b252011-03-23 20:57:27 +0100969 int column, unsigned int *writecnt);
Sujith394cf0a2009-02-09 13:26:54 +0530970u32 ath9k_hw_reverse_bits(u32 val, u32 n);
Luis R. Rodriguez4f0fc7c2009-05-06 02:20:00 -0400971u16 ath9k_hw_computetxtime(struct ath_hw *ah,
Felix Fietkau545750d2009-11-23 22:21:01 +0100972 u8 phy, int kbps,
Sujith394cf0a2009-02-09 13:26:54 +0530973 u32 frameLen, u16 rateix, bool shortPreamble);
Sujithcbe61d82009-02-09 13:27:12 +0530974void ath9k_hw_get_channel_centers(struct ath_hw *ah,
Sujith394cf0a2009-02-09 13:26:54 +0530975 struct ath9k_channel *chan,
976 struct chan_centers *centers);
Sujithcbe61d82009-02-09 13:27:12 +0530977u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
978void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
979bool ath9k_hw_phy_disable(struct ath_hw *ah);
980bool ath9k_hw_disable(struct ath_hw *ah);
Felix Fietkaude40f312010-10-20 03:08:53 +0200981void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
Sujithcbe61d82009-02-09 13:27:12 +0530982void ath9k_hw_setopmode(struct ath_hw *ah);
983void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
Luis R. Rodriguezf2b21432009-09-10 08:50:20 -0700984void ath9k_hw_write_associd(struct ath_hw *ah);
Felix Fietkaudd347f22011-03-22 21:54:17 +0100985u32 ath9k_hw_gettsf32(struct ath_hw *ah);
Sujithcbe61d82009-02-09 13:27:12 +0530986u64 ath9k_hw_gettsf64(struct ath_hw *ah);
987void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
988void ath9k_hw_reset_tsf(struct ath_hw *ah);
Sujith Manoharan60ca9f82012-07-17 17:15:37 +0530989void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
Felix Fietkau0005baf2010-01-15 02:33:40 +0100990void ath9k_hw_init_global_settings(struct ath_hw *ah);
Senthil Balasubramanianb84628e2011-04-22 11:32:12 +0530991u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
Felix Fietkaue4744ec2013-10-11 23:31:01 +0200992void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
Sujithcbe61d82009-02-09 13:27:12 +0530993void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
994void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
Sujith394cf0a2009-02-09 13:26:54 +0530995 const struct ath9k_beacon_state *bs);
Sujith Manoharan1e516ca2013-09-11 21:30:27 +0530996void ath9k_hw_check_nav(struct ath_hw *ah);
Felix Fietkauc9c99e52010-04-19 19:57:29 +0200997bool ath9k_hw_check_alive(struct ath_hw *ah);
Luis R. Rodrigueza91d75a2009-09-09 20:29:18 -0700998
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700999bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
Luis R. Rodrigueza91d75a2009-09-09 20:29:18 -07001000
Ben Greear462e58f2012-04-12 10:04:00 -07001001#ifdef CONFIG_ATH9K_DEBUGFS
1002void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause);
1003#else
Ben Greear990e08a2012-04-17 15:19:03 -07001004static inline void ath9k_debug_sync_cause(struct ath_common *common,
1005 u32 sync_cause) {}
Ben Greear462e58f2012-04-12 10:04:00 -07001006#endif
1007
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05301008/* Generic hw timer primitives */
1009struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1010 void (*trigger)(void *),
1011 void (*overflow)(void *),
1012 void *arg,
1013 u8 timer_index);
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07001014void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1015 struct ath_gen_timer *timer,
1016 u32 timer_next,
1017 u32 timer_period);
1018void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1019
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05301020void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1021void ath_gen_timer_isr(struct ath_hw *hw);
1022
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04001023void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04001024
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001025/* PHY */
1026void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1027 u32 *coef_mantissa, u32 *coef_exponent);
Gabor Juhos64ea57d2012-04-15 20:38:05 +02001028void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1029 bool test);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001030
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -04001031/*
1032 * Code Specific to AR5008, AR9001 or AR9002,
1033 * we stuff these here to avoid callbacks for AR9003.
1034 */
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -04001035int ar9002_hw_rf_claim(struct ath_hw *ah);
Luis R. Rodriguez78ec2672010-04-15 17:39:23 -04001036void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
Luis R. Rodriguezd8f492b2010-04-15 17:39:04 -04001037
Felix Fietkau641d9922010-04-15 17:38:49 -04001038/*
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -04001039 * Code specific to AR9003, we stuff these here to avoid callbacks
Felix Fietkau641d9922010-04-15 17:38:49 -04001040 * for older families
1041 */
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -04001042void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1043void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1044void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05301045void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
Felix Fietkau717f6be2010-06-12 00:34:00 -04001046void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1047void ar9003_paprd_populate_single_table(struct ath_hw *ah,
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001048 struct ath9k_hw_cal_data *caldata,
1049 int chain);
1050int ar9003_paprd_create_curve(struct ath_hw *ah,
1051 struct ath9k_hw_cal_data *caldata, int chain);
Sujith Manoharan36d29432012-12-10 07:22:35 +05301052void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
Felix Fietkau717f6be2010-06-12 00:34:00 -04001053int ar9003_paprd_init_table(struct ath_hw *ah);
1054bool ar9003_paprd_is_done(struct ath_hw *ah);
Sujith Manoharan0f21ee82012-12-10 07:22:37 +05301055bool ar9003_is_paprd_enabled(struct ath_hw *ah);
Felix Fietkau4a8f1992013-01-20 21:55:20 +01001056void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
Felix Fietkau641d9922010-04-15 17:38:49 -04001057
1058/* Hardware family op attach helpers */
Felix Fietkauc1b976d2012-12-12 13:14:23 +01001059int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
Luis R. Rodriguez8525f282010-04-15 17:38:19 -04001060void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1061void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001062
Luis R. Rodriguez795f5e22010-04-15 17:39:00 -04001063void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1064void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1065
Felix Fietkauc1b976d2012-12-12 13:14:23 +01001066int ar9002_hw_attach_ops(struct ath_hw *ah);
Luis R. Rodriguezb3950e62010-04-15 17:39:03 -04001067void ar9003_hw_attach_ops(struct ath_hw *ah);
1068
Rajkumar Manoharanc2ba3342010-09-03 16:00:00 +05301069void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
Felix Fietkau6790ae72012-06-15 15:25:23 +02001070
Felix Fietkau8eb49802010-10-04 20:09:49 +02001071void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
Felix Fietkau95792172010-10-04 20:09:50 +02001072void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
Luis R. Rodriguezac0bb762010-06-12 00:33:42 -04001073
Felix Fietkau8a309302011-12-17 16:47:56 +01001074#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
Sujith Manoharandbccdd12012-02-22 17:55:47 +05301075static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1076{
1077 return ah->btcoex_hw.enabled;
1078}
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301079static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1080{
Rajkumar Manoharane1ecad72012-06-18 19:02:38 +05301081 return ah->common.btcoex_enabled &&
1082 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301083
1084}
Sujith Manoharandbccdd12012-02-22 17:55:47 +05301085void ath9k_hw_btcoex_enable(struct ath_hw *ah);
Felix Fietkau8a309302011-12-17 16:47:56 +01001086static inline enum ath_btcoex_scheme
1087ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1088{
1089 return ah->btcoex_hw.scheme;
1090}
1091#else
Sujith Manoharandbccdd12012-02-22 17:55:47 +05301092static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1093{
1094 return false;
1095}
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301096static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1097{
1098 return false;
1099}
Sujith Manoharandbccdd12012-02-22 17:55:47 +05301100static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1101{
1102}
1103static inline enum ath_btcoex_scheme
1104ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1105{
1106 return ATH_BTCOEX_CFG_NONE;
1107}
Sujith Manoharan64ab38d2012-02-22 12:41:52 +05301108#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
Felix Fietkau8a309302011-12-17 16:47:56 +01001109
Mohammed Shafi Shajakhan64875c62012-07-10 14:56:15 +05301110
Sujith Manoharane60001e2013-10-28 12:22:04 +05301111#ifdef CONFIG_ATH9K_WOW
Mohammed Shafi Shajakhan64875c62012-07-10 14:56:15 +05301112const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1113void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1114 u8 *user_mask, int pattern_count,
1115 int pattern_len);
1116u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1117void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1118#else
1119static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1120{
1121 return NULL;
1122}
1123static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1124 u8 *user_pattern,
1125 u8 *user_mask,
1126 int pattern_count,
1127 int pattern_len)
1128{
1129}
1130static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1131{
1132 return 0;
1133}
1134static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1135{
1136}
1137#endif
1138
Luis R. Rodriguez73377252010-06-12 00:33:39 -04001139#define ATH9K_CLOCK_RATE_CCK 22
1140#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1141#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1142#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1143
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001144#endif