Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xHCI host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2008 Intel Corp. |
| 5 | * |
| 6 | * Author: Sarah Sharp |
| 7 | * Some code borrowed from the Linux EHCI driver. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software Foundation, |
| 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
Andiry Xu | bdfca50 | 2011-01-06 15:43:39 +0800 | [diff] [blame] | 22 | /* Up to 16 ms to halt an HC */ |
| 23 | #define XHCI_MAX_HALT_USEC (16*1000) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 24 | /* HC not running - set to 1 when run/stop bit is cleared. */ |
| 25 | #define XHCI_STS_HALT (1<<0) |
| 26 | |
| 27 | /* HCCPARAMS offset from PCI base address */ |
| 28 | #define XHCI_HCC_PARAMS_OFFSET 0x10 |
| 29 | /* HCCPARAMS contains the first extended capability pointer */ |
| 30 | #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff) |
| 31 | |
| 32 | /* Command and Status registers offset from the Operational Registers address */ |
| 33 | #define XHCI_CMD_OFFSET 0x00 |
| 34 | #define XHCI_STS_OFFSET 0x04 |
| 35 | |
| 36 | #define XHCI_MAX_EXT_CAPS 50 |
| 37 | |
| 38 | /* Capability Register */ |
| 39 | /* bits 7:0 - how long is the Capabilities register */ |
| 40 | #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff) |
| 41 | |
| 42 | /* Extended capability register fields */ |
| 43 | #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff) |
| 44 | #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff) |
| 45 | #define XHCI_EXT_CAPS_VAL(p) ((p)>>16) |
| 46 | /* Extended capability IDs - ID 0 reserved */ |
| 47 | #define XHCI_EXT_CAPS_LEGACY 1 |
| 48 | #define XHCI_EXT_CAPS_PROTOCOL 2 |
| 49 | #define XHCI_EXT_CAPS_PM 3 |
| 50 | #define XHCI_EXT_CAPS_VIRT 4 |
| 51 | #define XHCI_EXT_CAPS_ROUTE 5 |
| 52 | /* IDs 6-9 reserved */ |
| 53 | #define XHCI_EXT_CAPS_DEBUG 10 |
| 54 | /* USB Legacy Support Capability - section 7.1.1 */ |
| 55 | #define XHCI_HC_BIOS_OWNED (1 << 16) |
| 56 | #define XHCI_HC_OS_OWNED (1 << 24) |
| 57 | |
| 58 | /* USB Legacy Support Capability - section 7.1.1 */ |
| 59 | /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ |
| 60 | #define XHCI_LEGACY_SUPPORT_OFFSET (0x00) |
| 61 | |
| 62 | /* USB Legacy Support Control and Status Register - section 7.1.2 */ |
| 63 | /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */ |
| 64 | #define XHCI_LEGACY_CONTROL_OFFSET (0x04) |
Alex He | 95018a5 | 2012-03-30 10:21:38 +0800 | [diff] [blame] | 65 | /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */ |
| 66 | #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17)) |
| 67 | #define XHCI_LEGACY_SMI_EVENTS (0x7 << 29) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 68 | |
Andiry Xu | fc71ff7 | 2011-09-23 14:19:51 -0700 | [diff] [blame] | 69 | /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */ |
| 70 | #define XHCI_L1C (1 << 16) |
| 71 | |
| 72 | /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */ |
| 73 | #define XHCI_HLC (1 << 19) |
Mathias Nyman | dcf06a0 | 2013-08-21 18:50:09 +0300 | [diff] [blame] | 74 | #define XHCI_BLC (1 << 20) |
Andiry Xu | fc71ff7 | 2011-09-23 14:19:51 -0700 | [diff] [blame] | 75 | |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 76 | /* command register values to disable interrupts and halt the HC */ |
| 77 | /* start/stop HC execution - do not write unless HC is halted*/ |
| 78 | #define XHCI_CMD_RUN (1 << 0) |
| 79 | /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */ |
| 80 | #define XHCI_CMD_EIE (1 << 2) |
| 81 | /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */ |
| 82 | #define XHCI_CMD_HSEIE (1 << 3) |
| 83 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ |
| 84 | #define XHCI_CMD_EWE (1 << 10) |
| 85 | |
| 86 | #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE) |
| 87 | |
| 88 | /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ |
| 89 | #define XHCI_STS_CNR (1 << 11) |
| 90 | |
| 91 | #include <linux/io.h> |
| 92 | |
| 93 | /** |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 94 | * Find the offset of the extended capabilities with capability ID id. |
| 95 | * |
Mathias Nyman | d5ddcdf | 2015-11-24 13:09:58 +0200 | [diff] [blame] | 96 | * @base PCI MMIO registers base address. |
| 97 | * @start address at which to start looking, (0 or HCC_PARAMS to start at |
| 98 | * beginning of list) |
| 99 | * @id Extended capability ID to search for. |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 100 | * |
Mathias Nyman | d5ddcdf | 2015-11-24 13:09:58 +0200 | [diff] [blame] | 101 | * Returns the offset of the next matching extended capability structure. |
| 102 | * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL, |
| 103 | * and this provides a way to find them all. |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 104 | */ |
Mathias Nyman | d5ddcdf | 2015-11-24 13:09:58 +0200 | [diff] [blame] | 105 | |
| 106 | static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id) |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 107 | { |
| 108 | u32 val; |
Mathias Nyman | d5ddcdf | 2015-11-24 13:09:58 +0200 | [diff] [blame] | 109 | u32 next; |
| 110 | u32 offset; |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 111 | |
Mathias Nyman | d5ddcdf | 2015-11-24 13:09:58 +0200 | [diff] [blame] | 112 | offset = start; |
| 113 | if (!start || start == XHCI_HCC_PARAMS_OFFSET) { |
| 114 | val = readl(base + XHCI_HCC_PARAMS_OFFSET); |
Joe Lawrence | 89140fd | 2016-02-03 12:51:12 -0500 | [diff] [blame] | 115 | if (val == ~0) |
| 116 | return 0; |
Mathias Nyman | d5ddcdf | 2015-11-24 13:09:58 +0200 | [diff] [blame] | 117 | offset = XHCI_HCC_EXT_CAPS(val) << 2; |
| 118 | if (!offset) |
| 119 | return 0; |
| 120 | }; |
| 121 | do { |
| 122 | val = readl(base + offset); |
Joe Lawrence | 89140fd | 2016-02-03 12:51:12 -0500 | [diff] [blame] | 123 | if (val == ~0) |
| 124 | return 0; |
Mathias Nyman | d5ddcdf | 2015-11-24 13:09:58 +0200 | [diff] [blame] | 125 | if (XHCI_EXT_CAPS_ID(val) == id && offset != start) |
| 126 | return offset; |
| 127 | |
| 128 | next = XHCI_EXT_CAPS_NEXT(val); |
| 129 | offset += next << 2; |
| 130 | } while (next); |
| 131 | |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 132 | return 0; |
| 133 | } |