blob: 702a5362aaac6169b386ac8ded41e5d5099ed192 [file] [log] [blame]
Grant Likelyca632f52011-06-06 01:16:30 -06001/*
Jassi Brar230d42d2009-11-30 07:39:42 +00002 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/workqueue.h>
Mark Brownc2573122011-11-10 10:57:32 +000023#include <linux/interrupt.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000024#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
Arnd Bergmann78843722013-04-11 22:42:03 +020027#include <linux/dmaengine.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000028#include <linux/platform_device.h>
Mark Brownb97b6622011-12-04 00:58:06 +000029#include <linux/pm_runtime.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000030#include <linux/spi/spi.h>
Thomas Abraham1c20c202012-07-13 07:15:14 +090031#include <linux/gpio.h>
Thomas Abraham2b908072012-07-13 07:15:15 +090032#include <linux/of.h>
33#include <linux/of_gpio.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000034
Arnd Bergmann436d42c2012-08-24 15:22:12 +020035#include <linux/platform_data/spi-s3c64xx.h>
Jassi Brar230d42d2009-11-30 07:39:42 +000036
Mark Brown563b4442013-04-18 18:06:05 +010037#ifdef CONFIG_S3C_DMA
Arnd Bergmann78843722013-04-11 22:42:03 +020038#include <mach/dma.h>
39#endif
40
Thomas Abrahama5238e32012-07-13 07:15:14 +090041#define MAX_SPI_PORTS 3
Girish K S7e995552013-05-20 12:21:32 +053042#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
Thomas Abrahama5238e32012-07-13 07:15:14 +090043
Jassi Brar230d42d2009-11-30 07:39:42 +000044/* Registers and bit-fields */
45
46#define S3C64XX_SPI_CH_CFG 0x00
47#define S3C64XX_SPI_CLK_CFG 0x04
48#define S3C64XX_SPI_MODE_CFG 0x08
49#define S3C64XX_SPI_SLAVE_SEL 0x0C
50#define S3C64XX_SPI_INT_EN 0x10
51#define S3C64XX_SPI_STATUS 0x14
52#define S3C64XX_SPI_TX_DATA 0x18
53#define S3C64XX_SPI_RX_DATA 0x1C
54#define S3C64XX_SPI_PACKET_CNT 0x20
55#define S3C64XX_SPI_PENDING_CLR 0x24
56#define S3C64XX_SPI_SWAP_CFG 0x28
57#define S3C64XX_SPI_FB_CLK 0x2C
58
59#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
60#define S3C64XX_SPI_CH_SW_RST (1<<5)
61#define S3C64XX_SPI_CH_SLAVE (1<<4)
62#define S3C64XX_SPI_CPOL_L (1<<3)
63#define S3C64XX_SPI_CPHA_B (1<<2)
64#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
65#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
66
67#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
68#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
69#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
Jingoo Han75bf3362013-01-31 15:25:01 +090070#define S3C64XX_SPI_PSR_MASK 0xff
Jassi Brar230d42d2009-11-30 07:39:42 +000071
72#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
73#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
74#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
75#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
76#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
77#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
78#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
79#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
80#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
81#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
82#define S3C64XX_SPI_MODE_4BURST (1<<0)
83
84#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
85#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
86
Jassi Brar230d42d2009-11-30 07:39:42 +000087#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
88#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
89#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
90#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
91#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
92#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
93#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
94
95#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
96#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
97#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
98#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
99#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
100#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
101
102#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
103
104#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
105#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
106#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
107#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
108#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
109
110#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
111#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
112#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
113#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
114#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
115#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
116#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
117#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
118
119#define S3C64XX_SPI_FBCLK_MSK (3<<0)
120
Thomas Abrahama5238e32012-07-13 07:15:14 +0900121#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
122#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
123 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
124#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
125#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
126 FIFO_LVL_MASK(i))
Jassi Brar230d42d2009-11-30 07:39:42 +0000127
128#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
129#define S3C64XX_SPI_TRAILCNT_OFF 19
130
131#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
132
133#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
Girish K S7e995552013-05-20 12:21:32 +0530134#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
Jassi Brar230d42d2009-11-30 07:39:42 +0000135
Jassi Brar230d42d2009-11-30 07:39:42 +0000136#define RXBUSY (1<<2)
137#define TXBUSY (1<<3)
138
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900139struct s3c64xx_spi_dma_data {
Arnd Bergmann78843722013-04-11 22:42:03 +0200140 struct dma_chan *ch;
Arnd Bergmannc10356b2012-04-30 16:31:27 +0000141 enum dma_transfer_direction direction;
Arnd Bergmann78843722013-04-11 22:42:03 +0200142 unsigned int dmach;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900143};
144
Jassi Brar230d42d2009-11-30 07:39:42 +0000145/**
Thomas Abrahama5238e32012-07-13 07:15:14 +0900146 * struct s3c64xx_spi_info - SPI Controller hardware info
147 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
148 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
149 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
150 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
151 * @clk_from_cmu: True, if the controller does not include a clock mux and
152 * prescaler unit.
153 *
154 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
155 * differ in some aspects such as the size of the fifo and spi bus clock
156 * setup. Such differences are specified to the driver using this structure
157 * which is provided as driver data to the driver.
158 */
159struct s3c64xx_spi_port_config {
160 int fifo_lvl_mask[MAX_SPI_PORTS];
161 int rx_lvl_offset;
162 int tx_st_done;
Girish K S7e995552013-05-20 12:21:32 +0530163 int quirks;
Thomas Abrahama5238e32012-07-13 07:15:14 +0900164 bool high_speed;
165 bool clk_from_cmu;
166};
167
168/**
Jassi Brar230d42d2009-11-30 07:39:42 +0000169 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
170 * @clk: Pointer to the spi clock.
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700171 * @src_clk: Pointer to the clock used to generate SPI signals.
Jassi Brar230d42d2009-11-30 07:39:42 +0000172 * @master: Pointer to the SPI Protocol master.
Jassi Brar230d42d2009-11-30 07:39:42 +0000173 * @cntrlr_info: Platform specific data for the controller this driver manages.
174 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
Jassi Brar230d42d2009-11-30 07:39:42 +0000175 * @lock: Controller specific lock.
176 * @state: Set of FLAGS to indicate status.
177 * @rx_dmach: Controller's DMA channel for Rx.
178 * @tx_dmach: Controller's DMA channel for Tx.
179 * @sfr_start: BUS address of SPI controller regs.
180 * @regs: Pointer to ioremap'ed controller registers.
Mark Brownc2573122011-11-10 10:57:32 +0000181 * @irq: interrupt
Jassi Brar230d42d2009-11-30 07:39:42 +0000182 * @xfer_completion: To indicate completion of xfer task.
183 * @cur_mode: Stores the active configuration of the controller.
184 * @cur_bpw: Stores the active bits per word settings.
185 * @cur_speed: Stores the active xfer clock speed.
186 */
187struct s3c64xx_spi_driver_data {
188 void __iomem *regs;
189 struct clk *clk;
Jassi Brarb0d5d6e2010-01-20 13:49:44 -0700190 struct clk *src_clk;
Jassi Brar230d42d2009-11-30 07:39:42 +0000191 struct platform_device *pdev;
192 struct spi_master *master;
Jassi Brarad7de722010-01-20 13:49:44 -0700193 struct s3c64xx_spi_info *cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +0000194 struct spi_device *tgl_spi;
Jassi Brar230d42d2009-11-30 07:39:42 +0000195 spinlock_t lock;
Jassi Brar230d42d2009-11-30 07:39:42 +0000196 unsigned long sfr_start;
197 struct completion xfer_completion;
198 unsigned state;
199 unsigned cur_mode, cur_bpw;
200 unsigned cur_speed;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900201 struct s3c64xx_spi_dma_data rx_dma;
202 struct s3c64xx_spi_dma_data tx_dma;
Mark Brown563b4442013-04-18 18:06:05 +0100203#ifdef CONFIG_S3C_DMA
Boojin Kim39d3e802011-09-02 09:44:41 +0900204 struct samsung_dma_ops *ops;
Arnd Bergmann78843722013-04-11 22:42:03 +0200205#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +0900206 struct s3c64xx_spi_port_config *port_conf;
207 unsigned int port_id;
Thomas Abraham2b908072012-07-13 07:15:15 +0900208 unsigned long gpios[4];
Girish K S3146bee2013-06-21 11:26:12 +0530209 bool cs_gpio;
Jassi Brar230d42d2009-11-30 07:39:42 +0000210};
211
Jassi Brar230d42d2009-11-30 07:39:42 +0000212static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
213{
Jassi Brar230d42d2009-11-30 07:39:42 +0000214 void __iomem *regs = sdd->regs;
215 unsigned long loops;
216 u32 val;
217
218 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
219
220 val = readl(regs + S3C64XX_SPI_CH_CFG);
Kyoungil Kim7d859ff2012-05-23 21:29:51 +0900221 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
222 writel(val, regs + S3C64XX_SPI_CH_CFG);
223
224 val = readl(regs + S3C64XX_SPI_CH_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000225 val |= S3C64XX_SPI_CH_SW_RST;
226 val &= ~S3C64XX_SPI_CH_HS_EN;
227 writel(val, regs + S3C64XX_SPI_CH_CFG);
228
229 /* Flush TxFIFO*/
230 loops = msecs_to_loops(1);
231 do {
232 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900233 } while (TX_FIFO_LVL(val, sdd) && loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000234
Mark Brownbe7852a2010-08-23 17:40:56 +0100235 if (loops == 0)
236 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
237
Jassi Brar230d42d2009-11-30 07:39:42 +0000238 /* Flush RxFIFO*/
239 loops = msecs_to_loops(1);
240 do {
241 val = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900242 if (RX_FIFO_LVL(val, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000243 readl(regs + S3C64XX_SPI_RX_DATA);
244 else
245 break;
246 } while (loops--);
247
Mark Brownbe7852a2010-08-23 17:40:56 +0100248 if (loops == 0)
249 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
250
Jassi Brar230d42d2009-11-30 07:39:42 +0000251 val = readl(regs + S3C64XX_SPI_CH_CFG);
252 val &= ~S3C64XX_SPI_CH_SW_RST;
253 writel(val, regs + S3C64XX_SPI_CH_CFG);
254
255 val = readl(regs + S3C64XX_SPI_MODE_CFG);
256 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
257 writel(val, regs + S3C64XX_SPI_MODE_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000258}
259
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900260static void s3c64xx_spi_dmacb(void *data)
Boojin Kim39d3e802011-09-02 09:44:41 +0900261{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900262 struct s3c64xx_spi_driver_data *sdd;
263 struct s3c64xx_spi_dma_data *dma = data;
Boojin Kim39d3e802011-09-02 09:44:41 +0900264 unsigned long flags;
265
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900266 if (dma->direction == DMA_DEV_TO_MEM)
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900267 sdd = container_of(data,
268 struct s3c64xx_spi_driver_data, rx_dma);
269 else
270 sdd = container_of(data,
271 struct s3c64xx_spi_driver_data, tx_dma);
272
Boojin Kim39d3e802011-09-02 09:44:41 +0900273 spin_lock_irqsave(&sdd->lock, flags);
274
Kyoungil Kim054ebcc2012-03-10 09:48:46 +0900275 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900276 sdd->state &= ~RXBUSY;
277 if (!(sdd->state & TXBUSY))
278 complete(&sdd->xfer_completion);
279 } else {
280 sdd->state &= ~TXBUSY;
281 if (!(sdd->state & RXBUSY))
282 complete(&sdd->xfer_completion);
283 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900284
285 spin_unlock_irqrestore(&sdd->lock, flags);
286}
287
Mark Brown563b4442013-04-18 18:06:05 +0100288#ifdef CONFIG_S3C_DMA
Arnd Bergmann78843722013-04-11 22:42:03 +0200289/* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
290
291static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
292 .name = "samsung-spi-dma",
293};
294
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900295static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
296 unsigned len, dma_addr_t buf)
Boojin Kim39d3e802011-09-02 09:44:41 +0900297{
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900298 struct s3c64xx_spi_driver_data *sdd;
Boojin Kim4969c322012-06-19 13:27:03 +0900299 struct samsung_dma_prep info;
300 struct samsung_dma_config config;
Boojin Kim39d3e802011-09-02 09:44:41 +0900301
Boojin Kim4969c322012-06-19 13:27:03 +0900302 if (dma->direction == DMA_DEV_TO_MEM) {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900303 sdd = container_of((void *)dma,
304 struct s3c64xx_spi_driver_data, rx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900305 config.direction = sdd->rx_dma.direction;
306 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
307 config.width = sdd->cur_bpw / 8;
Arnd Bergmann78843722013-04-11 22:42:03 +0200308 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
Boojin Kim4969c322012-06-19 13:27:03 +0900309 } else {
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900310 sdd = container_of((void *)dma,
311 struct s3c64xx_spi_driver_data, tx_dma);
Boojin Kim4969c322012-06-19 13:27:03 +0900312 config.direction = sdd->tx_dma.direction;
313 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
314 config.width = sdd->cur_bpw / 8;
Arnd Bergmann78843722013-04-11 22:42:03 +0200315 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
Boojin Kim4969c322012-06-19 13:27:03 +0900316 }
Boojin Kim39d3e802011-09-02 09:44:41 +0900317
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900318 info.cap = DMA_SLAVE;
319 info.len = len;
320 info.fp = s3c64xx_spi_dmacb;
321 info.fp_param = dma;
322 info.direction = dma->direction;
323 info.buf = buf;
Boojin Kim39d3e802011-09-02 09:44:41 +0900324
Arnd Bergmann78843722013-04-11 22:42:03 +0200325 sdd->ops->prepare((enum dma_ch)dma->ch, &info);
326 sdd->ops->trigger((enum dma_ch)dma->ch);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900327}
328
329static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
330{
Boojin Kim4969c322012-06-19 13:27:03 +0900331 struct samsung_dma_req req;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +0530332 struct device *dev = &sdd->pdev->dev;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900333
334 sdd->ops = samsung_dma_get_ops();
335
Boojin Kim4969c322012-06-19 13:27:03 +0900336 req.cap = DMA_SLAVE;
337 req.client = &s3c64xx_spi_dma_client;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900338
Jingoo Handb0606e2013-07-15 15:11:57 +0900339 sdd->rx_dma.ch = (void *)sdd->ops->request(sdd->rx_dma.dmach,
340 &req, dev, "rx");
341 sdd->tx_dma.ch = (void *)sdd->ops->request(sdd->tx_dma.dmach,
342 &req, dev, "tx");
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900343
344 return 1;
Boojin Kim39d3e802011-09-02 09:44:41 +0900345}
346
Arnd Bergmann78843722013-04-11 22:42:03 +0200347static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
348{
349 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
350
Girish K S7e995552013-05-20 12:21:32 +0530351 /*
352 * If DMA resource was not available during
353 * probe, no need to continue with dma requests
354 * else Acquire DMA channels
355 */
356 while (!is_polling(sdd) && !acquire_dma(sdd))
Arnd Bergmann78843722013-04-11 22:42:03 +0200357 usleep_range(10000, 11000);
358
359 pm_runtime_get_sync(&sdd->pdev->dev);
360
361 return 0;
362}
363
364static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
365{
366 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
367
368 /* Free DMA channels */
Girish K S7e995552013-05-20 12:21:32 +0530369 if (!is_polling(sdd)) {
370 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
371 &s3c64xx_spi_dma_client);
372 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
373 &s3c64xx_spi_dma_client);
374 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200375 pm_runtime_put(&sdd->pdev->dev);
376
377 return 0;
378}
379
380static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
381 struct s3c64xx_spi_dma_data *dma)
382{
383 sdd->ops->stop((enum dma_ch)dma->ch);
384}
385#else
386
387static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
388 unsigned len, dma_addr_t buf)
389{
390 struct s3c64xx_spi_driver_data *sdd;
391 struct dma_slave_config config;
392 struct scatterlist sg;
393 struct dma_async_tx_descriptor *desc;
394
395 if (dma->direction == DMA_DEV_TO_MEM) {
396 sdd = container_of((void *)dma,
397 struct s3c64xx_spi_driver_data, rx_dma);
398 config.direction = dma->direction;
399 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
400 config.src_addr_width = sdd->cur_bpw / 8;
401 config.src_maxburst = 1;
402 dmaengine_slave_config(dma->ch, &config);
403 } else {
404 sdd = container_of((void *)dma,
405 struct s3c64xx_spi_driver_data, tx_dma);
406 config.direction = dma->direction;
407 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
408 config.dst_addr_width = sdd->cur_bpw / 8;
409 config.dst_maxburst = 1;
410 dmaengine_slave_config(dma->ch, &config);
411 }
412
413 sg_init_table(&sg, 1);
414 sg_dma_len(&sg) = len;
415 sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf)),
416 len, offset_in_page(buf));
417 sg_dma_address(&sg) = buf;
418
419 desc = dmaengine_prep_slave_sg(dma->ch,
420 &sg, 1, dma->direction, DMA_PREP_INTERRUPT);
421
422 desc->callback = s3c64xx_spi_dmacb;
423 desc->callback_param = dma;
424
425 dmaengine_submit(desc);
426 dma_async_issue_pending(dma->ch);
427}
428
429static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
430{
431 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
432 dma_filter_fn filter = sdd->cntrlr_info->filter;
433 struct device *dev = &sdd->pdev->dev;
434 dma_cap_mask_t mask;
Mark Brownfb9d0442013-04-18 18:12:00 +0100435 int ret;
Arnd Bergmann78843722013-04-11 22:42:03 +0200436
Girish K S9f4b3232013-06-27 12:26:53 +0530437 if (is_polling(sdd))
438 return 0;
439
Arnd Bergmann78843722013-04-11 22:42:03 +0200440 dma_cap_zero(mask);
441 dma_cap_set(DMA_SLAVE, mask);
442
443 /* Acquire DMA channels */
444 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
Jingoo Handb0606e2013-07-15 15:11:57 +0900445 (void *)sdd->rx_dma.dmach, dev, "rx");
Mark Brownfb9d0442013-04-18 18:12:00 +0100446 if (!sdd->rx_dma.ch) {
447 dev_err(dev, "Failed to get RX DMA channel\n");
448 ret = -EBUSY;
449 goto out;
450 }
451
Arnd Bergmann78843722013-04-11 22:42:03 +0200452 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
Jingoo Handb0606e2013-07-15 15:11:57 +0900453 (void *)sdd->tx_dma.dmach, dev, "tx");
Mark Brownfb9d0442013-04-18 18:12:00 +0100454 if (!sdd->tx_dma.ch) {
455 dev_err(dev, "Failed to get TX DMA channel\n");
456 ret = -EBUSY;
457 goto out_rx;
458 }
459
460 ret = pm_runtime_get_sync(&sdd->pdev->dev);
Sylwester Nawrocki6c6cf642013-06-10 18:22:26 +0200461 if (ret < 0) {
Mark Brownfb9d0442013-04-18 18:12:00 +0100462 dev_err(dev, "Failed to enable device: %d\n", ret);
463 goto out_tx;
464 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200465
466 return 0;
Mark Brownfb9d0442013-04-18 18:12:00 +0100467
468out_tx:
469 dma_release_channel(sdd->tx_dma.ch);
470out_rx:
471 dma_release_channel(sdd->rx_dma.ch);
472out:
473 return ret;
Arnd Bergmann78843722013-04-11 22:42:03 +0200474}
475
476static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
477{
478 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
479
480 /* Free DMA channels */
Girish K S7e995552013-05-20 12:21:32 +0530481 if (!is_polling(sdd)) {
482 dma_release_channel(sdd->rx_dma.ch);
483 dma_release_channel(sdd->tx_dma.ch);
484 }
Arnd Bergmann78843722013-04-11 22:42:03 +0200485
486 pm_runtime_put(&sdd->pdev->dev);
487 return 0;
488}
489
490static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
491 struct s3c64xx_spi_dma_data *dma)
492{
493 dmaengine_terminate_all(dma->ch);
494}
495#endif
496
Jassi Brar230d42d2009-11-30 07:39:42 +0000497static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
498 struct spi_device *spi,
499 struct spi_transfer *xfer, int dma_mode)
500{
Jassi Brar230d42d2009-11-30 07:39:42 +0000501 void __iomem *regs = sdd->regs;
502 u32 modecfg, chcfg;
503
504 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
505 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
506
507 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
508 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
509
510 if (dma_mode) {
511 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
512 } else {
513 /* Always shift in data in FIFO, even if xfer is Tx only,
514 * this helps setting PCKT_CNT value for generating clocks
515 * as exactly needed.
516 */
517 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
518 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
519 | S3C64XX_SPI_PACKET_CNT_EN,
520 regs + S3C64XX_SPI_PACKET_CNT);
521 }
522
523 if (xfer->tx_buf != NULL) {
524 sdd->state |= TXBUSY;
525 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
526 if (dma_mode) {
527 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900528 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000529 } else {
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900530 switch (sdd->cur_bpw) {
531 case 32:
532 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
533 xfer->tx_buf, xfer->len / 4);
534 break;
535 case 16:
536 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
537 xfer->tx_buf, xfer->len / 2);
538 break;
539 default:
540 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
541 xfer->tx_buf, xfer->len);
542 break;
543 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000544 }
545 }
546
547 if (xfer->rx_buf != NULL) {
548 sdd->state |= RXBUSY;
549
Thomas Abrahama5238e32012-07-13 07:15:14 +0900550 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
Jassi Brar230d42d2009-11-30 07:39:42 +0000551 && !(sdd->cur_mode & SPI_CPHA))
552 chcfg |= S3C64XX_SPI_CH_HS_EN;
553
554 if (dma_mode) {
555 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
556 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
557 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
558 | S3C64XX_SPI_PACKET_CNT_EN,
559 regs + S3C64XX_SPI_PACKET_CNT);
Boojin Kim82ab8cd2011-09-02 09:44:42 +0900560 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000561 }
562 }
563
564 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
565 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
566}
567
568static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
569 struct spi_device *spi)
570{
571 struct s3c64xx_spi_csinfo *cs;
572
573 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
574 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
575 /* Deselect the last toggled device */
576 cs = sdd->tgl_spi->controller_data;
Girish K S3146bee2013-06-21 11:26:12 +0530577 if (sdd->cs_gpio)
578 gpio_set_value(cs->line,
579 spi->mode & SPI_CS_HIGH ? 0 : 1);
Jassi Brar230d42d2009-11-30 07:39:42 +0000580 }
581 sdd->tgl_spi = NULL;
582 }
583
584 cs = spi->controller_data;
Girish K S3146bee2013-06-21 11:26:12 +0530585 if (sdd->cs_gpio)
586 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
Girish K S7e995552013-05-20 12:21:32 +0530587
588 /* Start the signals */
589 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
590}
591
Mark Brown79617072013-06-19 19:12:39 +0100592static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
Girish K S7e995552013-05-20 12:21:32 +0530593 int timeout_ms)
594{
595 void __iomem *regs = sdd->regs;
596 unsigned long val = 1;
597 u32 status;
598
599 /* max fifo depth available */
600 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
601
602 if (timeout_ms)
603 val = msecs_to_loops(timeout_ms);
604
605 do {
606 status = readl(regs + S3C64XX_SPI_STATUS);
607 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
608
609 /* return the actual received data length */
610 return RX_FIFO_LVL(status, sdd);
Jassi Brar230d42d2009-11-30 07:39:42 +0000611}
612
613static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
614 struct spi_transfer *xfer, int dma_mode)
615{
Jassi Brar230d42d2009-11-30 07:39:42 +0000616 void __iomem *regs = sdd->regs;
617 unsigned long val;
618 int ms;
619
620 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
621 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
Mark Brown9d8f86b2010-09-07 16:37:52 +0100622 ms += 10; /* some tolerance */
Jassi Brar230d42d2009-11-30 07:39:42 +0000623
624 if (dma_mode) {
625 val = msecs_to_jiffies(ms) + 10;
626 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
627 } else {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900628 u32 status;
Jassi Brar230d42d2009-11-30 07:39:42 +0000629 val = msecs_to_loops(ms);
630 do {
Jassi Brarc3f139b2010-09-03 10:36:46 +0900631 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900632 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
Jassi Brar230d42d2009-11-30 07:39:42 +0000633 }
634
Jassi Brar230d42d2009-11-30 07:39:42 +0000635 if (dma_mode) {
636 u32 status;
637
638 /*
Girish K S7e995552013-05-20 12:21:32 +0530639 * If the previous xfer was completed within timeout, then
640 * proceed further else return -EIO.
Jassi Brar230d42d2009-11-30 07:39:42 +0000641 * DmaTx returns after simply writing data in the FIFO,
642 * w/o waiting for real transmission on the bus to finish.
643 * DmaRx returns only after Dma read data from FIFO which
644 * needs bus transmission to finish, so we don't worry if
645 * Xfer involved Rx(with or without Tx).
646 */
Girish K S7e995552013-05-20 12:21:32 +0530647 if (val && !xfer->rx_buf) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000648 val = msecs_to_loops(10);
649 status = readl(regs + S3C64XX_SPI_STATUS);
Thomas Abrahama5238e32012-07-13 07:15:14 +0900650 while ((TX_FIFO_LVL(status, sdd)
651 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
Jassi Brar230d42d2009-11-30 07:39:42 +0000652 && --val) {
653 cpu_relax();
654 status = readl(regs + S3C64XX_SPI_STATUS);
655 }
656
Jassi Brar230d42d2009-11-30 07:39:42 +0000657 }
Girish K S7e995552013-05-20 12:21:32 +0530658
659 /* If timed out while checking rx/tx status return error */
660 if (!val)
661 return -EIO;
Jassi Brar230d42d2009-11-30 07:39:42 +0000662 } else {
Girish K S7e995552013-05-20 12:21:32 +0530663 int loops;
664 u32 cpy_len;
665 u8 *buf;
666
Jassi Brar230d42d2009-11-30 07:39:42 +0000667 /* If it was only Tx */
Girish K S7e995552013-05-20 12:21:32 +0530668 if (!xfer->rx_buf) {
Jassi Brar230d42d2009-11-30 07:39:42 +0000669 sdd->state &= ~TXBUSY;
670 return 0;
671 }
672
Girish K S7e995552013-05-20 12:21:32 +0530673 /*
674 * If the receive length is bigger than the controller fifo
675 * size, calculate the loops and read the fifo as many times.
676 * loops = length / max fifo size (calculated by using the
677 * fifo mask).
678 * For any size less than the fifo size the below code is
679 * executed atleast once.
680 */
681 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
682 buf = xfer->rx_buf;
683 do {
684 /* wait for data to be received in the fifo */
Mark Brown79617072013-06-19 19:12:39 +0100685 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
686 (loops ? ms : 0));
Girish K S7e995552013-05-20 12:21:32 +0530687
688 switch (sdd->cur_bpw) {
689 case 32:
690 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
691 buf, cpy_len / 4);
692 break;
693 case 16:
694 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
695 buf, cpy_len / 2);
696 break;
697 default:
698 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
699 buf, cpy_len);
700 break;
701 }
702
703 buf = buf + cpy_len;
704 } while (loops--);
Jassi Brar230d42d2009-11-30 07:39:42 +0000705 sdd->state &= ~RXBUSY;
706 }
707
708 return 0;
709}
710
711static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
712 struct spi_device *spi)
713{
714 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
715
716 if (sdd->tgl_spi == spi)
717 sdd->tgl_spi = NULL;
718
Girish K S3146bee2013-06-21 11:26:12 +0530719 if (sdd->cs_gpio)
720 gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
Girish K S7e995552013-05-20 12:21:32 +0530721
722 /* Quiese the signals */
723 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +0000724}
725
726static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
727{
Jassi Brar230d42d2009-11-30 07:39:42 +0000728 void __iomem *regs = sdd->regs;
729 u32 val;
730
731 /* Disable Clock */
Thomas Abrahama5238e32012-07-13 07:15:14 +0900732 if (sdd->port_conf->clk_from_cmu) {
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900733 clk_disable_unprepare(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900734 } else {
735 val = readl(regs + S3C64XX_SPI_CLK_CFG);
736 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
737 writel(val, regs + S3C64XX_SPI_CLK_CFG);
738 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000739
740 /* Set Polarity and Phase */
741 val = readl(regs + S3C64XX_SPI_CH_CFG);
742 val &= ~(S3C64XX_SPI_CH_SLAVE |
743 S3C64XX_SPI_CPOL_L |
744 S3C64XX_SPI_CPHA_B);
745
746 if (sdd->cur_mode & SPI_CPOL)
747 val |= S3C64XX_SPI_CPOL_L;
748
749 if (sdd->cur_mode & SPI_CPHA)
750 val |= S3C64XX_SPI_CPHA_B;
751
752 writel(val, regs + S3C64XX_SPI_CH_CFG);
753
754 /* Set Channel & DMA Mode */
755 val = readl(regs + S3C64XX_SPI_MODE_CFG);
756 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
757 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
758
759 switch (sdd->cur_bpw) {
760 case 32:
761 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900762 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000763 break;
764 case 16:
765 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900766 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
Jassi Brar230d42d2009-11-30 07:39:42 +0000767 break;
768 default:
769 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900770 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
Jassi Brar230d42d2009-11-30 07:39:42 +0000771 break;
772 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000773
774 writel(val, regs + S3C64XX_SPI_MODE_CFG);
775
Thomas Abrahama5238e32012-07-13 07:15:14 +0900776 if (sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +0900777 /* Configure Clock */
778 /* There is half-multiplier before the SPI */
779 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
780 /* Enable Clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +0900781 clk_prepare_enable(sdd->src_clk);
Jassi Brarb42a81c2010-09-29 17:31:33 +0900782 } else {
783 /* Configure Clock */
784 val = readl(regs + S3C64XX_SPI_CLK_CFG);
785 val &= ~S3C64XX_SPI_PSR_MASK;
786 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
787 & S3C64XX_SPI_PSR_MASK);
788 writel(val, regs + S3C64XX_SPI_CLK_CFG);
Jassi Brar230d42d2009-11-30 07:39:42 +0000789
Jassi Brarb42a81c2010-09-29 17:31:33 +0900790 /* Enable Clock */
791 val = readl(regs + S3C64XX_SPI_CLK_CFG);
792 val |= S3C64XX_SPI_ENCLK_ENABLE;
793 writel(val, regs + S3C64XX_SPI_CLK_CFG);
794 }
Jassi Brar230d42d2009-11-30 07:39:42 +0000795}
796
Jassi Brar230d42d2009-11-30 07:39:42 +0000797#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
798
799static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
800 struct spi_message *msg)
801{
802 struct device *dev = &sdd->pdev->dev;
803 struct spi_transfer *xfer;
804
Girish K S7e995552013-05-20 12:21:32 +0530805 if (is_polling(sdd) || msg->is_dma_mapped)
Jassi Brar230d42d2009-11-30 07:39:42 +0000806 return 0;
807
808 /* First mark all xfer unmapped */
809 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
810 xfer->rx_dma = XFER_DMAADDR_INVALID;
811 xfer->tx_dma = XFER_DMAADDR_INVALID;
812 }
813
814 /* Map until end or first fail */
815 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
816
Thomas Abrahama5238e32012-07-13 07:15:14 +0900817 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900818 continue;
819
Jassi Brar230d42d2009-11-30 07:39:42 +0000820 if (xfer->tx_buf != NULL) {
Jassi Brar251ee472010-09-03 10:36:26 +0900821 xfer->tx_dma = dma_map_single(dev,
822 (void *)xfer->tx_buf, xfer->len,
823 DMA_TO_DEVICE);
Jassi Brar230d42d2009-11-30 07:39:42 +0000824 if (dma_mapping_error(dev, xfer->tx_dma)) {
825 dev_err(dev, "dma_map_single Tx failed\n");
826 xfer->tx_dma = XFER_DMAADDR_INVALID;
827 return -ENOMEM;
828 }
829 }
830
831 if (xfer->rx_buf != NULL) {
832 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
833 xfer->len, DMA_FROM_DEVICE);
834 if (dma_mapping_error(dev, xfer->rx_dma)) {
835 dev_err(dev, "dma_map_single Rx failed\n");
836 dma_unmap_single(dev, xfer->tx_dma,
837 xfer->len, DMA_TO_DEVICE);
838 xfer->tx_dma = XFER_DMAADDR_INVALID;
839 xfer->rx_dma = XFER_DMAADDR_INVALID;
840 return -ENOMEM;
841 }
842 }
843 }
844
845 return 0;
846}
847
848static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
849 struct spi_message *msg)
850{
851 struct device *dev = &sdd->pdev->dev;
852 struct spi_transfer *xfer;
853
Girish K S7e995552013-05-20 12:21:32 +0530854 if (is_polling(sdd) || msg->is_dma_mapped)
Jassi Brar230d42d2009-11-30 07:39:42 +0000855 return;
856
857 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
858
Thomas Abrahama5238e32012-07-13 07:15:14 +0900859 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
Jassi Brare02ddd42010-09-29 17:31:31 +0900860 continue;
861
Jassi Brar230d42d2009-11-30 07:39:42 +0000862 if (xfer->rx_buf != NULL
863 && xfer->rx_dma != XFER_DMAADDR_INVALID)
864 dma_unmap_single(dev, xfer->rx_dma,
865 xfer->len, DMA_FROM_DEVICE);
866
867 if (xfer->tx_buf != NULL
868 && xfer->tx_dma != XFER_DMAADDR_INVALID)
869 dma_unmap_single(dev, xfer->tx_dma,
870 xfer->len, DMA_TO_DEVICE);
871 }
872}
873
Mark Brownad2a99a2012-02-15 14:48:32 -0800874static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
875 struct spi_message *msg)
Jassi Brar230d42d2009-11-30 07:39:42 +0000876{
Mark Brownad2a99a2012-02-15 14:48:32 -0800877 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +0000878 struct spi_device *spi = msg->spi;
879 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
880 struct spi_transfer *xfer;
881 int status = 0, cs_toggle = 0;
882 u32 speed;
883 u8 bpw;
884
885 /* If Master's(controller) state differs from that needed by Slave */
886 if (sdd->cur_speed != spi->max_speed_hz
887 || sdd->cur_mode != spi->mode
888 || sdd->cur_bpw != spi->bits_per_word) {
889 sdd->cur_bpw = spi->bits_per_word;
890 sdd->cur_speed = spi->max_speed_hz;
891 sdd->cur_mode = spi->mode;
892 s3c64xx_spi_config(sdd);
893 }
894
895 /* Map all the transfers if needed */
896 if (s3c64xx_spi_map_mssg(sdd, msg)) {
897 dev_err(&spi->dev,
898 "Xfer: Unable to map message buffers!\n");
899 status = -ENOMEM;
900 goto out;
901 }
902
903 /* Configure feedback delay */
904 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
905
906 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
907
908 unsigned long flags;
909 int use_dma;
910
911 INIT_COMPLETION(sdd->xfer_completion);
912
913 /* Only BPW and Speed may change across transfers */
Laxman Dewangan766ed702012-12-18 14:25:43 +0530914 bpw = xfer->bits_per_word;
Jassi Brar230d42d2009-11-30 07:39:42 +0000915 speed = xfer->speed_hz ? : spi->max_speed_hz;
916
Jassi Brar0c92ecf2010-09-29 17:31:33 +0900917 if (xfer->len % (bpw / 8)) {
918 dev_err(&spi->dev,
919 "Xfer length(%u) not a multiple of word size(%u)\n",
920 xfer->len, bpw / 8);
921 status = -EIO;
922 goto out;
923 }
924
Jassi Brar230d42d2009-11-30 07:39:42 +0000925 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
926 sdd->cur_bpw = bpw;
927 sdd->cur_speed = speed;
928 s3c64xx_spi_config(sdd);
929 }
930
931 /* Polling method for xfers not bigger than FIFO capacity */
Arnd Bergmann78843722013-04-11 22:42:03 +0200932 use_dma = 0;
Girish K S7e995552013-05-20 12:21:32 +0530933 if (!is_polling(sdd) &&
934 (sdd->rx_dma.ch && sdd->tx_dma.ch &&
935 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
Jassi Brar230d42d2009-11-30 07:39:42 +0000936 use_dma = 1;
937
938 spin_lock_irqsave(&sdd->lock, flags);
939
940 /* Pending only which is to be done */
941 sdd->state &= ~RXBUSY;
942 sdd->state &= ~TXBUSY;
943
944 enable_datapath(sdd, spi, xfer, use_dma);
945
946 /* Slave Select */
947 enable_cs(sdd, spi);
948
Jassi Brar230d42d2009-11-30 07:39:42 +0000949 spin_unlock_irqrestore(&sdd->lock, flags);
950
951 status = wait_for_xfer(sdd, xfer, use_dma);
952
Jassi Brar230d42d2009-11-30 07:39:42 +0000953 if (status) {
Jingoo Han75bf3362013-01-31 15:25:01 +0900954 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
Jassi Brar230d42d2009-11-30 07:39:42 +0000955 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
956 (sdd->state & RXBUSY) ? 'f' : 'p',
957 (sdd->state & TXBUSY) ? 'f' : 'p',
958 xfer->len);
959
960 if (use_dma) {
961 if (xfer->tx_buf != NULL
962 && (sdd->state & TXBUSY))
Arnd Bergmann78843722013-04-11 22:42:03 +0200963 s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000964 if (xfer->rx_buf != NULL
965 && (sdd->state & RXBUSY))
Arnd Bergmann78843722013-04-11 22:42:03 +0200966 s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
Jassi Brar230d42d2009-11-30 07:39:42 +0000967 }
968
969 goto out;
970 }
971
972 if (xfer->delay_usecs)
973 udelay(xfer->delay_usecs);
974
975 if (xfer->cs_change) {
976 /* Hint that the next mssg is gonna be
977 for the same device */
978 if (list_is_last(&xfer->transfer_list,
979 &msg->transfers))
980 cs_toggle = 1;
Jassi Brar230d42d2009-11-30 07:39:42 +0000981 }
982
983 msg->actual_length += xfer->len;
984
985 flush_fifo(sdd);
986 }
987
988out:
989 if (!cs_toggle || status)
990 disable_cs(sdd, spi);
991 else
992 sdd->tgl_spi = spi;
993
994 s3c64xx_spi_unmap_mssg(sdd, msg);
995
996 msg->status = status;
997
Mark Brownad2a99a2012-02-15 14:48:32 -0800998 spi_finalize_current_message(master);
999
1000 return 0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001001}
1002
Thomas Abraham2b908072012-07-13 07:15:15 +09001003static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
Thomas Abraham2b908072012-07-13 07:15:15 +09001004 struct spi_device *spi)
1005{
1006 struct s3c64xx_spi_csinfo *cs;
Arnd Bergmann4732cc62012-08-04 11:18:20 +00001007 struct device_node *slave_np, *data_np = NULL;
Girish K S3146bee2013-06-21 11:26:12 +05301008 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham2b908072012-07-13 07:15:15 +09001009 u32 fb_delay = 0;
1010
Girish K S3146bee2013-06-21 11:26:12 +05301011 sdd = spi_master_get_devdata(spi->master);
Thomas Abraham2b908072012-07-13 07:15:15 +09001012 slave_np = spi->dev.of_node;
1013 if (!slave_np) {
1014 dev_err(&spi->dev, "device node not found\n");
1015 return ERR_PTR(-EINVAL);
1016 }
1017
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001018 data_np = of_get_child_by_name(slave_np, "controller-data");
Thomas Abraham2b908072012-07-13 07:15:15 +09001019 if (!data_np) {
1020 dev_err(&spi->dev, "child node 'controller-data' not found\n");
1021 return ERR_PTR(-EINVAL);
1022 }
1023
1024 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
1025 if (!cs) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001026 dev_err(&spi->dev, "could not allocate memory for controller data\n");
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001027 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001028 return ERR_PTR(-ENOMEM);
1029 }
1030
Girish K S3146bee2013-06-21 11:26:12 +05301031 /* The CS line is asserted/deasserted by the gpio pin */
1032 if (sdd->cs_gpio)
1033 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
1034
Thomas Abraham2b908072012-07-13 07:15:15 +09001035 if (!gpio_is_valid(cs->line)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001036 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001037 kfree(cs);
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001038 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001039 return ERR_PTR(-EINVAL);
1040 }
1041
1042 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
1043 cs->fb_delay = fb_delay;
Srinivas Kandagatla06455bb2012-09-18 08:10:49 +01001044 of_node_put(data_np);
Thomas Abraham2b908072012-07-13 07:15:15 +09001045 return cs;
1046}
1047
Jassi Brar230d42d2009-11-30 07:39:42 +00001048/*
1049 * Here we only check the validity of requested configuration
1050 * and save the configuration in a local data-structure.
1051 * The controller is actually configured only just before we
1052 * get a message to transfer.
1053 */
1054static int s3c64xx_spi_setup(struct spi_device *spi)
1055{
1056 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
1057 struct s3c64xx_spi_driver_data *sdd;
Jassi Brarad7de722010-01-20 13:49:44 -07001058 struct s3c64xx_spi_info *sci;
Thomas Abraham2b908072012-07-13 07:15:15 +09001059 int err;
Jassi Brar230d42d2009-11-30 07:39:42 +00001060
Thomas Abraham2b908072012-07-13 07:15:15 +09001061 sdd = spi_master_get_devdata(spi->master);
1062 if (!cs && spi->dev.of_node) {
Matthias Brugger5c725b32013-03-26 10:27:35 +01001063 cs = s3c64xx_get_slave_ctrldata(spi);
Thomas Abraham2b908072012-07-13 07:15:15 +09001064 spi->controller_data = cs;
1065 }
1066
1067 if (IS_ERR_OR_NULL(cs)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001068 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
1069 return -ENODEV;
1070 }
1071
Girish K S3146bee2013-06-21 11:26:12 +05301072 /* Request gpio only if cs line is asserted by gpio pins */
1073 if (sdd->cs_gpio) {
Mark Brown707214d2012-07-19 14:36:16 +09001074 err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
1075 dev_name(&spi->dev));
Thomas Abraham1c20c202012-07-13 07:15:14 +09001076 if (err) {
Mark Brown49f3eac2012-07-19 14:36:13 +09001077 dev_err(&spi->dev,
1078 "Failed to get /CS gpio [%d]: %d\n",
1079 cs->line, err);
Thomas Abraham2b908072012-07-13 07:15:15 +09001080 goto err_gpio_req;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001081 }
Thomas Abraham1c20c202012-07-13 07:15:14 +09001082 }
1083
Girish K S3146bee2013-06-21 11:26:12 +05301084 if (!spi_get_ctldata(spi))
1085 spi_set_ctldata(spi, cs);
1086
Jassi Brar230d42d2009-11-30 07:39:42 +00001087 sci = sdd->cntrlr_info;
1088
Mark Brownb97b6622011-12-04 00:58:06 +00001089 pm_runtime_get_sync(&sdd->pdev->dev);
1090
Jassi Brar230d42d2009-11-30 07:39:42 +00001091 /* Check if we can provide the requested rate */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001092 if (!sdd->port_conf->clk_from_cmu) {
Jassi Brarb42a81c2010-09-29 17:31:33 +09001093 u32 psr, speed;
Jassi Brar230d42d2009-11-30 07:39:42 +00001094
Jassi Brarb42a81c2010-09-29 17:31:33 +09001095 /* Max possible */
1096 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
Jassi Brar230d42d2009-11-30 07:39:42 +00001097
Jassi Brarb42a81c2010-09-29 17:31:33 +09001098 if (spi->max_speed_hz > speed)
1099 spi->max_speed_hz = speed;
Jassi Brar230d42d2009-11-30 07:39:42 +00001100
Jassi Brarb42a81c2010-09-29 17:31:33 +09001101 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
1102 psr &= S3C64XX_SPI_PSR_MASK;
1103 if (psr == S3C64XX_SPI_PSR_MASK)
1104 psr--;
1105
1106 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1107 if (spi->max_speed_hz < speed) {
1108 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1109 psr++;
1110 } else {
1111 err = -EINVAL;
1112 goto setup_exit;
1113 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001114 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001115
Jassi Brarb42a81c2010-09-29 17:31:33 +09001116 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
Thomas Abraham2b908072012-07-13 07:15:15 +09001117 if (spi->max_speed_hz >= speed) {
Jassi Brarb42a81c2010-09-29 17:31:33 +09001118 spi->max_speed_hz = speed;
Thomas Abraham2b908072012-07-13 07:15:15 +09001119 } else {
Mark Browne1b0f0d2012-12-20 18:27:31 +00001120 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1121 spi->max_speed_hz);
Jassi Brarb42a81c2010-09-29 17:31:33 +09001122 err = -EINVAL;
Thomas Abraham2b908072012-07-13 07:15:15 +09001123 goto setup_exit;
1124 }
Jassi Brarb42a81c2010-09-29 17:31:33 +09001125 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001126
Mark Brownb97b6622011-12-04 00:58:06 +00001127 pm_runtime_put(&sdd->pdev->dev);
Thomas Abraham2b908072012-07-13 07:15:15 +09001128 disable_cs(sdd, spi);
1129 return 0;
Mark Brownb97b6622011-12-04 00:58:06 +00001130
Jassi Brar230d42d2009-11-30 07:39:42 +00001131setup_exit:
Jassi Brar230d42d2009-11-30 07:39:42 +00001132 /* setup() returns with device de-selected */
1133 disable_cs(sdd, spi);
1134
Thomas Abraham2b908072012-07-13 07:15:15 +09001135 gpio_free(cs->line);
1136 spi_set_ctldata(spi, NULL);
1137
1138err_gpio_req:
Sylwester Nawrocki5bee3b92012-09-13 16:31:30 +02001139 if (spi->dev.of_node)
1140 kfree(cs);
Thomas Abraham2b908072012-07-13 07:15:15 +09001141
Jassi Brar230d42d2009-11-30 07:39:42 +00001142 return err;
1143}
1144
Thomas Abraham1c20c202012-07-13 07:15:14 +09001145static void s3c64xx_spi_cleanup(struct spi_device *spi)
1146{
1147 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
Girish K S3146bee2013-06-21 11:26:12 +05301148 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001149
Girish K S3146bee2013-06-21 11:26:12 +05301150 sdd = spi_master_get_devdata(spi->master);
1151 if (cs && sdd->cs_gpio) {
Thomas Abraham1c20c202012-07-13 07:15:14 +09001152 gpio_free(cs->line);
Thomas Abraham2b908072012-07-13 07:15:15 +09001153 if (spi->dev.of_node)
1154 kfree(cs);
1155 }
Thomas Abraham1c20c202012-07-13 07:15:14 +09001156 spi_set_ctldata(spi, NULL);
1157}
1158
Mark Brownc2573122011-11-10 10:57:32 +00001159static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1160{
1161 struct s3c64xx_spi_driver_data *sdd = data;
1162 struct spi_master *spi = sdd->master;
Girish K S375981f2013-03-13 12:13:30 +05301163 unsigned int val, clr = 0;
Mark Brownc2573122011-11-10 10:57:32 +00001164
Girish K S375981f2013-03-13 12:13:30 +05301165 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
Mark Brownc2573122011-11-10 10:57:32 +00001166
Girish K S375981f2013-03-13 12:13:30 +05301167 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1168 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001169 dev_err(&spi->dev, "RX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301170 }
1171 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1172 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001173 dev_err(&spi->dev, "RX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301174 }
1175 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1176 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001177 dev_err(&spi->dev, "TX overrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301178 }
1179 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1180 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
Mark Brownc2573122011-11-10 10:57:32 +00001181 dev_err(&spi->dev, "TX underrun\n");
Girish K S375981f2013-03-13 12:13:30 +05301182 }
1183
1184 /* Clear the pending irq by setting and then clearing it */
1185 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1186 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
Mark Brownc2573122011-11-10 10:57:32 +00001187
1188 return IRQ_HANDLED;
1189}
1190
Jassi Brar230d42d2009-11-30 07:39:42 +00001191static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1192{
Jassi Brarad7de722010-01-20 13:49:44 -07001193 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001194 void __iomem *regs = sdd->regs;
1195 unsigned int val;
1196
1197 sdd->cur_speed = 0;
1198
Mark Brown5fc3e832012-07-19 14:36:23 +09001199 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
Jassi Brar230d42d2009-11-30 07:39:42 +00001200
1201 /* Disable Interrupts - we use Polling if not DMA mode */
1202 writel(0, regs + S3C64XX_SPI_INT_EN);
1203
Thomas Abrahama5238e32012-07-13 07:15:14 +09001204 if (!sdd->port_conf->clk_from_cmu)
Jassi Brarb42a81c2010-09-29 17:31:33 +09001205 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
Jassi Brar230d42d2009-11-30 07:39:42 +00001206 regs + S3C64XX_SPI_CLK_CFG);
1207 writel(0, regs + S3C64XX_SPI_MODE_CFG);
1208 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1209
Girish K S375981f2013-03-13 12:13:30 +05301210 /* Clear any irq pending bits, should set and clear the bits */
1211 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1212 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1213 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1214 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1215 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1216 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
Jassi Brar230d42d2009-11-30 07:39:42 +00001217
1218 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1219
1220 val = readl(regs + S3C64XX_SPI_MODE_CFG);
1221 val &= ~S3C64XX_SPI_MODE_4BURST;
1222 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1223 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1224 writel(val, regs + S3C64XX_SPI_MODE_CFG);
1225
1226 flush_fifo(sdd);
1227}
1228
Thomas Abraham2b908072012-07-13 07:15:15 +09001229#ifdef CONFIG_OF
Jingoo Han75bf3362013-01-31 15:25:01 +09001230static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
Thomas Abraham2b908072012-07-13 07:15:15 +09001231{
1232 struct s3c64xx_spi_info *sci;
1233 u32 temp;
1234
1235 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1236 if (!sci) {
1237 dev_err(dev, "memory allocation for spi_info failed\n");
1238 return ERR_PTR(-ENOMEM);
1239 }
1240
1241 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001242 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001243 sci->src_clk_nr = 0;
1244 } else {
1245 sci->src_clk_nr = temp;
1246 }
1247
1248 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001249 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
Thomas Abraham2b908072012-07-13 07:15:15 +09001250 sci->num_cs = 1;
1251 } else {
1252 sci->num_cs = temp;
1253 }
1254
1255 return sci;
1256}
1257#else
1258static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1259{
1260 return dev->platform_data;
1261}
Thomas Abraham2b908072012-07-13 07:15:15 +09001262#endif
1263
1264static const struct of_device_id s3c64xx_spi_dt_match[];
1265
Thomas Abrahama5238e32012-07-13 07:15:14 +09001266static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1267 struct platform_device *pdev)
1268{
Thomas Abraham2b908072012-07-13 07:15:15 +09001269#ifdef CONFIG_OF
1270 if (pdev->dev.of_node) {
1271 const struct of_device_id *match;
1272 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1273 return (struct s3c64xx_spi_port_config *)match->data;
1274 }
1275#endif
Thomas Abrahama5238e32012-07-13 07:15:14 +09001276 return (struct s3c64xx_spi_port_config *)
1277 platform_get_device_id(pdev)->driver_data;
1278}
1279
Grant Likely2deff8d2013-02-05 13:27:35 +00001280static int s3c64xx_spi_probe(struct platform_device *pdev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001281{
Thomas Abraham2b908072012-07-13 07:15:15 +09001282 struct resource *mem_res;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301283 struct resource *res;
Jassi Brar230d42d2009-11-30 07:39:42 +00001284 struct s3c64xx_spi_driver_data *sdd;
Thomas Abraham2b908072012-07-13 07:15:15 +09001285 struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
Jassi Brar230d42d2009-11-30 07:39:42 +00001286 struct spi_master *master;
Mark Brownc2573122011-11-10 10:57:32 +00001287 int ret, irq;
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001288 char clk_name[16];
Jassi Brar230d42d2009-11-30 07:39:42 +00001289
Thomas Abraham2b908072012-07-13 07:15:15 +09001290 if (!sci && pdev->dev.of_node) {
1291 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1292 if (IS_ERR(sci))
1293 return PTR_ERR(sci);
Jassi Brar230d42d2009-11-30 07:39:42 +00001294 }
1295
Thomas Abraham2b908072012-07-13 07:15:15 +09001296 if (!sci) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001297 dev_err(&pdev->dev, "platform_data missing!\n");
1298 return -ENODEV;
1299 }
1300
Jassi Brar230d42d2009-11-30 07:39:42 +00001301 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1302 if (mem_res == NULL) {
1303 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1304 return -ENXIO;
1305 }
1306
Mark Brownc2573122011-11-10 10:57:32 +00001307 irq = platform_get_irq(pdev, 0);
1308 if (irq < 0) {
1309 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1310 return irq;
1311 }
1312
Jassi Brar230d42d2009-11-30 07:39:42 +00001313 master = spi_alloc_master(&pdev->dev,
1314 sizeof(struct s3c64xx_spi_driver_data));
1315 if (master == NULL) {
1316 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1317 return -ENOMEM;
1318 }
1319
Jassi Brar230d42d2009-11-30 07:39:42 +00001320 platform_set_drvdata(pdev, master);
1321
1322 sdd = spi_master_get_devdata(master);
Thomas Abrahama5238e32012-07-13 07:15:14 +09001323 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001324 sdd->master = master;
1325 sdd->cntrlr_info = sci;
1326 sdd->pdev = pdev;
1327 sdd->sfr_start = mem_res->start;
Girish K S3146bee2013-06-21 11:26:12 +05301328 sdd->cs_gpio = true;
Thomas Abraham2b908072012-07-13 07:15:15 +09001329 if (pdev->dev.of_node) {
Girish K S3146bee2013-06-21 11:26:12 +05301330 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
1331 sdd->cs_gpio = false;
1332
Thomas Abraham2b908072012-07-13 07:15:15 +09001333 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1334 if (ret < 0) {
Jingoo Han75bf3362013-01-31 15:25:01 +09001335 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1336 ret);
Thomas Abraham2b908072012-07-13 07:15:15 +09001337 goto err0;
1338 }
1339 sdd->port_id = ret;
1340 } else {
1341 sdd->port_id = pdev->id;
1342 }
Jassi Brar230d42d2009-11-30 07:39:42 +00001343
1344 sdd->cur_bpw = 8;
1345
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301346 if (!sdd->pdev->dev.of_node) {
1347 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1348 if (!res) {
Jingoo Handb0606e2013-07-15 15:11:57 +09001349 dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n");
Girish K S7e995552013-05-20 12:21:32 +05301350 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1351 } else
1352 sdd->tx_dma.dmach = res->start;
Thomas Abraham2b908072012-07-13 07:15:15 +09001353
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301354 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1355 if (!res) {
Jingoo Handb0606e2013-07-15 15:11:57 +09001356 dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n");
Girish K S7e995552013-05-20 12:21:32 +05301357 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1358 } else
1359 sdd->rx_dma.dmach = res->start;
Padmavathi Vennab5be04d2013-01-18 17:17:03 +05301360 }
1361
1362 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1363 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
Thomas Abraham2b908072012-07-13 07:15:15 +09001364
1365 master->dev.of_node = pdev->dev.of_node;
Thomas Abrahama5238e32012-07-13 07:15:14 +09001366 master->bus_num = sdd->port_id;
Jassi Brar230d42d2009-11-30 07:39:42 +00001367 master->setup = s3c64xx_spi_setup;
Thomas Abraham1c20c202012-07-13 07:15:14 +09001368 master->cleanup = s3c64xx_spi_cleanup;
Mark Brownad2a99a2012-02-15 14:48:32 -08001369 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1370 master->transfer_one_message = s3c64xx_spi_transfer_one_message;
1371 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
Jassi Brar230d42d2009-11-30 07:39:42 +00001372 master->num_chipselect = sci->num_cs;
1373 master->dma_alignment = 8;
Stephen Warren24778be2013-05-21 20:36:35 -06001374 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1375 SPI_BPW_MASK(8);
Jassi Brar230d42d2009-11-30 07:39:42 +00001376 /* the spi->mode bits understood by this driver: */
1377 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1378
Thierry Redingb0ee5602013-01-21 11:09:18 +01001379 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1380 if (IS_ERR(sdd->regs)) {
1381 ret = PTR_ERR(sdd->regs);
Jingoo Han4eb77002013-01-10 11:04:21 +09001382 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001383 }
1384
Thomas Abraham00ab5392013-04-15 20:42:57 -07001385 if (sci->cfg_gpio && sci->cfg_gpio()) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001386 dev_err(&pdev->dev, "Unable to config gpio\n");
1387 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001388 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001389 }
1390
1391 /* Setup clocks */
Jingoo Han4eb77002013-01-10 11:04:21 +09001392 sdd->clk = devm_clk_get(&pdev->dev, "spi");
Jassi Brar230d42d2009-11-30 07:39:42 +00001393 if (IS_ERR(sdd->clk)) {
1394 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1395 ret = PTR_ERR(sdd->clk);
Thomas Abraham00ab5392013-04-15 20:42:57 -07001396 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001397 }
1398
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001399 if (clk_prepare_enable(sdd->clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001400 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1401 ret = -EBUSY;
Thomas Abraham00ab5392013-04-15 20:42:57 -07001402 goto err0;
Jassi Brar230d42d2009-11-30 07:39:42 +00001403 }
1404
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001405 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
Jingoo Han4eb77002013-01-10 11:04:21 +09001406 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001407 if (IS_ERR(sdd->src_clk)) {
Jassi Brar230d42d2009-11-30 07:39:42 +00001408 dev_err(&pdev->dev,
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001409 "Unable to acquire clock '%s'\n", clk_name);
Jassi Brarb0d5d6e2010-01-20 13:49:44 -07001410 ret = PTR_ERR(sdd->src_clk);
Jingoo Han4eb77002013-01-10 11:04:21 +09001411 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001412 }
1413
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001414 if (clk_prepare_enable(sdd->src_clk)) {
Padmavathi Vennaa24d8502011-11-02 20:04:19 +09001415 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
Jassi Brar230d42d2009-11-30 07:39:42 +00001416 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001417 goto err2;
Jassi Brar230d42d2009-11-30 07:39:42 +00001418 }
1419
Jassi Brar230d42d2009-11-30 07:39:42 +00001420 /* Setup Deufult Mode */
Thomas Abrahama5238e32012-07-13 07:15:14 +09001421 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001422
1423 spin_lock_init(&sdd->lock);
1424 init_completion(&sdd->xfer_completion);
Jassi Brar230d42d2009-11-30 07:39:42 +00001425
Jingoo Han4eb77002013-01-10 11:04:21 +09001426 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1427 "spi-s3c64xx", sdd);
Mark Brownc2573122011-11-10 10:57:32 +00001428 if (ret != 0) {
1429 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1430 irq, ret);
Jingoo Han4eb77002013-01-10 11:04:21 +09001431 goto err3;
Mark Brownc2573122011-11-10 10:57:32 +00001432 }
1433
1434 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1435 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1436 sdd->regs + S3C64XX_SPI_INT_EN);
1437
Jassi Brar230d42d2009-11-30 07:39:42 +00001438 if (spi_register_master(master)) {
1439 dev_err(&pdev->dev, "cannot register SPI master\n");
1440 ret = -EBUSY;
Jingoo Han4eb77002013-01-10 11:04:21 +09001441 goto err3;
Jassi Brar230d42d2009-11-30 07:39:42 +00001442 }
1443
Jingoo Han75bf3362013-01-31 15:25:01 +09001444 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
Thomas Abrahama5238e32012-07-13 07:15:14 +09001445 sdd->port_id, master->num_chipselect);
Jingoo Hanc65bc4a2013-07-16 08:53:33 +09001446 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n",
1447 mem_res,
Boojin Kim82ab8cd2011-09-02 09:44:42 +09001448 sdd->rx_dma.dmach, sdd->tx_dma.dmach);
Jassi Brar230d42d2009-11-30 07:39:42 +00001449
Mark Brownb97b6622011-12-04 00:58:06 +00001450 pm_runtime_enable(&pdev->dev);
1451
Jassi Brar230d42d2009-11-30 07:39:42 +00001452 return 0;
1453
Jassi Brar230d42d2009-11-30 07:39:42 +00001454err3:
Jingoo Han4eb77002013-01-10 11:04:21 +09001455 clk_disable_unprepare(sdd->src_clk);
1456err2:
1457 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001458err0:
Jassi Brar230d42d2009-11-30 07:39:42 +00001459 spi_master_put(master);
1460
1461 return ret;
1462}
1463
1464static int s3c64xx_spi_remove(struct platform_device *pdev)
1465{
1466 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1467 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001468
Mark Brownb97b6622011-12-04 00:58:06 +00001469 pm_runtime_disable(&pdev->dev);
1470
Jassi Brar230d42d2009-11-30 07:39:42 +00001471 spi_unregister_master(master);
1472
Mark Brownc2573122011-11-10 10:57:32 +00001473 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1474
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001475 clk_disable_unprepare(sdd->src_clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001476
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001477 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001478
Jassi Brar230d42d2009-11-30 07:39:42 +00001479 spi_master_put(master);
1480
1481 return 0;
1482}
1483
Jingoo Han997230d2013-03-22 02:09:08 +00001484#ifdef CONFIG_PM_SLEEP
Mark Browne25d0bf2011-12-04 00:36:18 +00001485static int s3c64xx_spi_suspend(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001486{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001487 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001488 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001489
Mark Brownad2a99a2012-02-15 14:48:32 -08001490 spi_master_suspend(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001491
1492 /* Disable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001493 clk_disable_unprepare(sdd->src_clk);
1494 clk_disable_unprepare(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001495
1496 sdd->cur_speed = 0; /* Output Clock is stopped */
1497
1498 return 0;
1499}
1500
Mark Browne25d0bf2011-12-04 00:36:18 +00001501static int s3c64xx_spi_resume(struct device *dev)
Jassi Brar230d42d2009-11-30 07:39:42 +00001502{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001503 struct spi_master *master = dev_get_drvdata(dev);
Jassi Brar230d42d2009-11-30 07:39:42 +00001504 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
Jassi Brarad7de722010-01-20 13:49:44 -07001505 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
Jassi Brar230d42d2009-11-30 07:39:42 +00001506
Thomas Abraham00ab5392013-04-15 20:42:57 -07001507 if (sci->cfg_gpio)
Thomas Abraham2b908072012-07-13 07:15:15 +09001508 sci->cfg_gpio();
Jassi Brar230d42d2009-11-30 07:39:42 +00001509
1510 /* Enable the clock */
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001511 clk_prepare_enable(sdd->src_clk);
1512 clk_prepare_enable(sdd->clk);
Jassi Brar230d42d2009-11-30 07:39:42 +00001513
Thomas Abrahama5238e32012-07-13 07:15:14 +09001514 s3c64xx_spi_hwinit(sdd, sdd->port_id);
Jassi Brar230d42d2009-11-30 07:39:42 +00001515
Mark Brownad2a99a2012-02-15 14:48:32 -08001516 spi_master_resume(master);
Jassi Brar230d42d2009-11-30 07:39:42 +00001517
1518 return 0;
1519}
Jingoo Han997230d2013-03-22 02:09:08 +00001520#endif /* CONFIG_PM_SLEEP */
Jassi Brar230d42d2009-11-30 07:39:42 +00001521
Mark Brownb97b6622011-12-04 00:58:06 +00001522#ifdef CONFIG_PM_RUNTIME
1523static int s3c64xx_spi_runtime_suspend(struct device *dev)
1524{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001525 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001526 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1527
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001528 clk_disable_unprepare(sdd->clk);
1529 clk_disable_unprepare(sdd->src_clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001530
1531 return 0;
1532}
1533
1534static int s3c64xx_spi_runtime_resume(struct device *dev)
1535{
Guenter Roeck9a2a5242012-08-16 20:14:25 -07001536 struct spi_master *master = dev_get_drvdata(dev);
Mark Brownb97b6622011-12-04 00:58:06 +00001537 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1538
Thomas Abraham9f667bf2012-10-03 08:30:12 +09001539 clk_prepare_enable(sdd->src_clk);
1540 clk_prepare_enable(sdd->clk);
Mark Brownb97b6622011-12-04 00:58:06 +00001541
1542 return 0;
1543}
1544#endif /* CONFIG_PM_RUNTIME */
1545
Mark Browne25d0bf2011-12-04 00:36:18 +00001546static const struct dev_pm_ops s3c64xx_spi_pm = {
1547 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
Mark Brownb97b6622011-12-04 00:58:06 +00001548 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1549 s3c64xx_spi_runtime_resume, NULL)
Mark Browne25d0bf2011-12-04 00:36:18 +00001550};
1551
Sachin Kamat10ce0472012-08-03 10:08:12 +05301552static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001553 .fifo_lvl_mask = { 0x7f },
1554 .rx_lvl_offset = 13,
1555 .tx_st_done = 21,
1556 .high_speed = true,
1557};
1558
Sachin Kamat10ce0472012-08-03 10:08:12 +05301559static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001560 .fifo_lvl_mask = { 0x7f, 0x7F },
1561 .rx_lvl_offset = 13,
1562 .tx_st_done = 21,
1563};
1564
Sachin Kamat10ce0472012-08-03 10:08:12 +05301565static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001566 .fifo_lvl_mask = { 0x1ff, 0x7F },
1567 .rx_lvl_offset = 15,
1568 .tx_st_done = 25,
1569};
1570
Sachin Kamat10ce0472012-08-03 10:08:12 +05301571static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001572 .fifo_lvl_mask = { 0x7f, 0x7F },
1573 .rx_lvl_offset = 13,
1574 .tx_st_done = 21,
1575 .high_speed = true,
1576};
1577
Sachin Kamat10ce0472012-08-03 10:08:12 +05301578static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001579 .fifo_lvl_mask = { 0x1ff, 0x7F },
1580 .rx_lvl_offset = 15,
1581 .tx_st_done = 25,
1582 .high_speed = true,
1583};
1584
Sachin Kamat10ce0472012-08-03 10:08:12 +05301585static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
Thomas Abrahama5238e32012-07-13 07:15:14 +09001586 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1587 .rx_lvl_offset = 15,
1588 .tx_st_done = 25,
1589 .high_speed = true,
1590 .clk_from_cmu = true,
1591};
1592
Girish K Sbff82032013-06-21 11:26:13 +05301593static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1594 .fifo_lvl_mask = { 0x1ff },
1595 .rx_lvl_offset = 15,
1596 .tx_st_done = 25,
1597 .high_speed = true,
1598 .clk_from_cmu = true,
1599 .quirks = S3C64XX_SPI_QUIRK_POLL,
1600};
1601
Thomas Abrahama5238e32012-07-13 07:15:14 +09001602static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1603 {
1604 .name = "s3c2443-spi",
1605 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1606 }, {
1607 .name = "s3c6410-spi",
1608 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1609 }, {
1610 .name = "s5p64x0-spi",
1611 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
1612 }, {
1613 .name = "s5pc100-spi",
1614 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
1615 }, {
1616 .name = "s5pv210-spi",
1617 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1618 }, {
1619 .name = "exynos4210-spi",
1620 .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
1621 },
1622 { },
1623};
1624
Thomas Abraham2b908072012-07-13 07:15:15 +09001625static const struct of_device_id s3c64xx_spi_dt_match[] = {
1626 { .compatible = "samsung,exynos4210-spi",
1627 .data = (void *)&exynos4_spi_port_config,
1628 },
Girish K Sbff82032013-06-21 11:26:13 +05301629 { .compatible = "samsung,exynos5440-spi",
1630 .data = (void *)&exynos5440_spi_port_config,
1631 },
Thomas Abraham2b908072012-07-13 07:15:15 +09001632 { },
1633};
1634MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
Thomas Abraham2b908072012-07-13 07:15:15 +09001635
Jassi Brar230d42d2009-11-30 07:39:42 +00001636static struct platform_driver s3c64xx_spi_driver = {
1637 .driver = {
1638 .name = "s3c64xx-spi",
1639 .owner = THIS_MODULE,
Mark Browne25d0bf2011-12-04 00:36:18 +00001640 .pm = &s3c64xx_spi_pm,
Thomas Abraham2b908072012-07-13 07:15:15 +09001641 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
Jassi Brar230d42d2009-11-30 07:39:42 +00001642 },
1643 .remove = s3c64xx_spi_remove,
Thomas Abrahama5238e32012-07-13 07:15:14 +09001644 .id_table = s3c64xx_spi_driver_ids,
Jassi Brar230d42d2009-11-30 07:39:42 +00001645};
1646MODULE_ALIAS("platform:s3c64xx-spi");
1647
1648static int __init s3c64xx_spi_init(void)
1649{
1650 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1651}
Mark Brownd2a787f2010-09-07 11:29:17 +01001652subsys_initcall(s3c64xx_spi_init);
Jassi Brar230d42d2009-11-30 07:39:42 +00001653
1654static void __exit s3c64xx_spi_exit(void)
1655{
1656 platform_driver_unregister(&s3c64xx_spi_driver);
1657}
1658module_exit(s3c64xx_spi_exit);
1659
1660MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1661MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1662MODULE_LICENSE("GPL");