R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 10 | #include <dt-bindings/gpio/gpio.h> |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 12 | #include <dt-bindings/pinctrl/omap.h> |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 13 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 14 | #include "skeleton.dtsi" |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 15 | |
| 16 | / { |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 17 | #address-cells = <1>; |
| 18 | #size-cells = <1>; |
| 19 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 20 | compatible = "ti,omap5"; |
| 21 | interrupt-parent = <&gic>; |
| 22 | |
| 23 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 24 | i2c0 = &i2c1; |
| 25 | i2c1 = &i2c2; |
| 26 | i2c2 = &i2c3; |
| 27 | i2c3 = &i2c4; |
| 28 | i2c4 = &i2c5; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 29 | serial0 = &uart1; |
| 30 | serial1 = &uart2; |
| 31 | serial2 = &uart3; |
| 32 | serial3 = &uart4; |
| 33 | serial4 = &uart5; |
| 34 | serial5 = &uart6; |
| 35 | }; |
| 36 | |
| 37 | cpus { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 38 | #address-cells = <1>; |
| 39 | #size-cells = <0>; |
| 40 | |
Nishanth Menon | b8981d7 | 2013-10-16 10:39:04 -0500 | [diff] [blame] | 41 | cpu0: cpu@0 { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 42 | device_type = "cpu"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 43 | compatible = "arm,cortex-a15"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 44 | reg = <0x0>; |
J Keerthy | 6c24894 | 2013-10-16 10:39:06 -0500 | [diff] [blame] | 45 | |
| 46 | operating-points = < |
| 47 | /* kHz uV */ |
| 48 | 500000 880000 |
| 49 | 1000000 1060000 |
| 50 | 1500000 1250000 |
| 51 | >; |
Nishanth Menon | 8d766fa | 2014-01-29 12:19:17 -0600 | [diff] [blame] | 52 | |
| 53 | clocks = <&dpll_mpu_ck>; |
| 54 | clock-names = "cpu"; |
| 55 | |
| 56 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
| 57 | |
Eduardo Valentin | 2cd29f6 | 2013-08-16 11:30:47 -0400 | [diff] [blame] | 58 | /* cooling options */ |
| 59 | cooling-min-level = <0>; |
| 60 | cooling-max-level = <2>; |
| 61 | #cooling-cells = <2>; /* min followed by max */ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 62 | }; |
| 63 | cpu@1 { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 64 | device_type = "cpu"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 65 | compatible = "arm,cortex-a15"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 66 | reg = <0x1>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 67 | }; |
| 68 | }; |
| 69 | |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 70 | thermal-zones { |
| 71 | #include "omap4-cpu-thermal.dtsi" |
| 72 | #include "omap5-gpu-thermal.dtsi" |
| 73 | #include "omap5-core-thermal.dtsi" |
| 74 | }; |
| 75 | |
Santosh Shilimkar | b45ccc4 | 2013-02-10 21:40:19 +0530 | [diff] [blame] | 76 | timer { |
| 77 | compatible = "arm,armv7-timer"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 78 | /* PPI secure/nonsecure IRQ */ |
| 79 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 80 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 81 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 82 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; |
Santosh Shilimkar | b45ccc4 | 2013-02-10 21:40:19 +0530 | [diff] [blame] | 83 | }; |
| 84 | |
Nathan Lynch | 69a126c | 2014-03-19 10:45:53 -0500 | [diff] [blame] | 85 | pmu { |
| 86 | compatible = "arm,cortex-a15-pmu"; |
| 87 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 88 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; |
| 89 | }; |
| 90 | |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 91 | gic: interrupt-controller@48211000 { |
| 92 | compatible = "arm,cortex-a15-gic"; |
| 93 | interrupt-controller; |
| 94 | #interrupt-cells = <3>; |
| 95 | reg = <0x48211000 0x1000>, |
Santosh Shilimkar | 0129c16 | 2013-02-19 17:29:24 +0530 | [diff] [blame] | 96 | <0x48212000 0x1000>, |
| 97 | <0x48214000 0x2000>, |
| 98 | <0x48216000 0x2000>; |
Santosh Shilimkar | ba1829b | 2013-02-12 15:57:55 +0530 | [diff] [blame] | 99 | }; |
| 100 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 101 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 102 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 103 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 104 | */ |
| 105 | soc { |
| 106 | compatible = "ti,omap-infra"; |
| 107 | mpu { |
| 108 | compatible = "ti,omap5-mpu"; |
| 109 | ti,hwmods = "mpu"; |
| 110 | }; |
| 111 | }; |
| 112 | |
| 113 | /* |
| 114 | * XXX: Use a flat representation of the OMAP3 interconnect. |
| 115 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 116 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 117 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 118 | * hierarchy. |
| 119 | */ |
| 120 | ocp { |
| 121 | compatible = "ti,omap4-l3-noc", "simple-bus"; |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <1>; |
| 124 | ranges; |
| 125 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
Santosh Shilimkar | 20a60ea | 2013-02-26 17:36:14 +0530 | [diff] [blame] | 126 | reg = <0x44000000 0x2000>, |
| 127 | <0x44800000 0x3000>, |
| 128 | <0x45000000 0x4000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 129 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 130 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 131 | |
Tero Kristo | 85dc74e | 2013-07-18 17:09:29 +0300 | [diff] [blame] | 132 | prm: prm@4ae06000 { |
| 133 | compatible = "ti,omap5-prm"; |
| 134 | reg = <0x4ae06000 0x3000>; |
| 135 | |
| 136 | prm_clocks: clocks { |
| 137 | #address-cells = <1>; |
| 138 | #size-cells = <0>; |
| 139 | }; |
| 140 | |
| 141 | prm_clockdomains: clockdomains { |
| 142 | }; |
| 143 | }; |
| 144 | |
| 145 | cm_core_aon: cm_core_aon@4a004000 { |
| 146 | compatible = "ti,omap5-cm-core-aon"; |
| 147 | reg = <0x4a004000 0x2000>; |
| 148 | |
| 149 | cm_core_aon_clocks: clocks { |
| 150 | #address-cells = <1>; |
| 151 | #size-cells = <0>; |
| 152 | }; |
| 153 | |
| 154 | cm_core_aon_clockdomains: clockdomains { |
| 155 | }; |
| 156 | }; |
| 157 | |
| 158 | scrm: scrm@4ae0a000 { |
| 159 | compatible = "ti,omap5-scrm"; |
| 160 | reg = <0x4ae0a000 0x2000>; |
| 161 | |
| 162 | scrm_clocks: clocks { |
| 163 | #address-cells = <1>; |
| 164 | #size-cells = <0>; |
| 165 | }; |
| 166 | |
| 167 | scrm_clockdomains: clockdomains { |
| 168 | }; |
| 169 | }; |
| 170 | |
| 171 | cm_core: cm_core@4a008000 { |
| 172 | compatible = "ti,omap5-cm-core"; |
| 173 | reg = <0x4a008000 0x3000>; |
| 174 | |
| 175 | cm_core_clocks: clocks { |
| 176 | #address-cells = <1>; |
| 177 | #size-cells = <0>; |
| 178 | }; |
| 179 | |
| 180 | cm_core_clockdomains: clockdomains { |
| 181 | }; |
| 182 | }; |
| 183 | |
Jon Hunter | 3b3132f | 2012-11-01 09:12:23 -0500 | [diff] [blame] | 184 | counter32k: counter@4ae04000 { |
| 185 | compatible = "ti,omap-counter32k"; |
| 186 | reg = <0x4ae04000 0x40>; |
| 187 | ti,hwmods = "counter_32k"; |
| 188 | }; |
| 189 | |
Peter Ujfalusi | 5da6a2d | 2012-10-04 14:57:27 +0300 | [diff] [blame] | 190 | omap5_pmx_core: pinmux@4a002840 { |
| 191 | compatible = "ti,omap4-padconf", "pinctrl-single"; |
| 192 | reg = <0x4a002840 0x01b6>; |
| 193 | #address-cells = <1>; |
| 194 | #size-cells = <0>; |
| 195 | pinctrl-single,register-width = <16>; |
| 196 | pinctrl-single,function-mask = <0x7fff>; |
| 197 | }; |
| 198 | omap5_pmx_wkup: pinmux@4ae0c840 { |
| 199 | compatible = "ti,omap4-padconf", "pinctrl-single"; |
| 200 | reg = <0x4ae0c840 0x0038>; |
| 201 | #address-cells = <1>; |
| 202 | #size-cells = <0>; |
| 203 | pinctrl-single,register-width = <16>; |
| 204 | pinctrl-single,function-mask = <0x7fff>; |
| 205 | }; |
| 206 | |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 207 | omap5_padconf_global: tisyscon@4a002da0 { |
| 208 | compatible = "syscon"; |
| 209 | reg = <0x4A002da0 0xec>; |
| 210 | }; |
| 211 | |
| 212 | pbias_regulator: pbias_regulator { |
| 213 | compatible = "ti,pbias-omap"; |
| 214 | reg = <0x60 0x4>; |
| 215 | syscon = <&omap5_padconf_global>; |
| 216 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 217 | regulator-name = "pbias_mmc_omap5"; |
| 218 | regulator-min-microvolt = <1800000>; |
| 219 | regulator-max-microvolt = <3000000>; |
| 220 | }; |
| 221 | }; |
| 222 | |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 223 | sdma: dma-controller@4a056000 { |
| 224 | compatible = "ti,omap4430-sdma"; |
| 225 | reg = <0x4a056000 0x1000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 226 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 227 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 228 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 229 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 230 | #dma-cells = <1>; |
| 231 | #dma-channels = <32>; |
| 232 | #dma-requests = <127>; |
| 233 | }; |
| 234 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 235 | gpio1: gpio@4ae10000 { |
| 236 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 237 | reg = <0x4ae10000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 238 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 239 | ti,hwmods = "gpio1"; |
Jon Hunter | e4b9b9f | 2013-04-04 15:16:16 -0500 | [diff] [blame] | 240 | ti,gpio-always-on; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 241 | gpio-controller; |
| 242 | #gpio-cells = <2>; |
| 243 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 244 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | gpio2: gpio@48055000 { |
| 248 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 249 | reg = <0x48055000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 250 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 251 | ti,hwmods = "gpio2"; |
| 252 | gpio-controller; |
| 253 | #gpio-cells = <2>; |
| 254 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 255 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 256 | }; |
| 257 | |
| 258 | gpio3: gpio@48057000 { |
| 259 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 260 | reg = <0x48057000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 261 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 262 | ti,hwmods = "gpio3"; |
| 263 | gpio-controller; |
| 264 | #gpio-cells = <2>; |
| 265 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 266 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | gpio4: gpio@48059000 { |
| 270 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 271 | reg = <0x48059000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 272 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 273 | ti,hwmods = "gpio4"; |
| 274 | gpio-controller; |
| 275 | #gpio-cells = <2>; |
| 276 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 277 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 278 | }; |
| 279 | |
| 280 | gpio5: gpio@4805b000 { |
| 281 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 282 | reg = <0x4805b000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 283 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 284 | ti,hwmods = "gpio5"; |
| 285 | gpio-controller; |
| 286 | #gpio-cells = <2>; |
| 287 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 288 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | gpio6: gpio@4805d000 { |
| 292 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 293 | reg = <0x4805d000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 294 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 295 | ti,hwmods = "gpio6"; |
| 296 | gpio-controller; |
| 297 | #gpio-cells = <2>; |
| 298 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 299 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 300 | }; |
| 301 | |
| 302 | gpio7: gpio@48051000 { |
| 303 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 304 | reg = <0x48051000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 305 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 306 | ti,hwmods = "gpio7"; |
| 307 | gpio-controller; |
| 308 | #gpio-cells = <2>; |
| 309 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 310 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 311 | }; |
| 312 | |
| 313 | gpio8: gpio@48053000 { |
| 314 | compatible = "ti,omap4-gpio"; |
Sebastien Guiriec | f4b224f | 2012-10-23 10:37:09 +0200 | [diff] [blame] | 315 | reg = <0x48053000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 316 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 317 | ti,hwmods = "gpio8"; |
| 318 | gpio-controller; |
| 319 | #gpio-cells = <2>; |
| 320 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 321 | #interrupt-cells = <2>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 322 | }; |
| 323 | |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 324 | gpmc: gpmc@50000000 { |
| 325 | compatible = "ti,omap4430-gpmc"; |
| 326 | reg = <0x50000000 0x1000>; |
| 327 | #address-cells = <2>; |
| 328 | #size-cells = <1>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 329 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 330 | gpmc,num-cs = <8>; |
| 331 | gpmc,num-waitpins = <4>; |
| 332 | ti,hwmods = "gpmc"; |
Florian Vaussard | 7b8b6af | 2014-02-26 11:38:09 +0100 | [diff] [blame] | 333 | clocks = <&l3_iclk_div>; |
| 334 | clock-names = "fck"; |
Jon Hunter | 1c7dbb5 | 2013-02-22 15:33:31 -0600 | [diff] [blame] | 335 | }; |
| 336 | |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 337 | i2c1: i2c@48070000 { |
| 338 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 339 | reg = <0x48070000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 340 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 341 | #address-cells = <1>; |
| 342 | #size-cells = <0>; |
| 343 | ti,hwmods = "i2c1"; |
| 344 | }; |
| 345 | |
| 346 | i2c2: i2c@48072000 { |
| 347 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 348 | reg = <0x48072000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 349 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 350 | #address-cells = <1>; |
| 351 | #size-cells = <0>; |
| 352 | ti,hwmods = "i2c2"; |
| 353 | }; |
| 354 | |
| 355 | i2c3: i2c@48060000 { |
| 356 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 357 | reg = <0x48060000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 358 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 359 | #address-cells = <1>; |
| 360 | #size-cells = <0>; |
| 361 | ti,hwmods = "i2c3"; |
| 362 | }; |
| 363 | |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 364 | i2c4: i2c@4807a000 { |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 365 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 366 | reg = <0x4807a000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 367 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 368 | #address-cells = <1>; |
| 369 | #size-cells = <0>; |
| 370 | ti,hwmods = "i2c4"; |
| 371 | }; |
| 372 | |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 373 | i2c5: i2c@4807c000 { |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 374 | compatible = "ti,omap4-i2c"; |
Sebastien Guiriec | d7118bb | 2012-10-23 10:37:10 +0200 | [diff] [blame] | 375 | reg = <0x4807c000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 376 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | 6e6a9a5 | 2012-07-25 10:57:58 +0530 | [diff] [blame] | 377 | #address-cells = <1>; |
| 378 | #size-cells = <0>; |
| 379 | ti,hwmods = "i2c5"; |
| 380 | }; |
| 381 | |
Suman Anna | fe0e09e | 2013-10-10 16:15:34 -0500 | [diff] [blame] | 382 | hwspinlock: spinlock@4a0f6000 { |
| 383 | compatible = "ti,omap4-hwspinlock"; |
| 384 | reg = <0x4a0f6000 0x1000>; |
| 385 | ti,hwmods = "spinlock"; |
Suman Anna | 3405421 | 2014-01-13 18:26:45 -0600 | [diff] [blame] | 386 | #hwlock-cells = <1>; |
Suman Anna | fe0e09e | 2013-10-10 16:15:34 -0500 | [diff] [blame] | 387 | }; |
| 388 | |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 389 | mcspi1: spi@48098000 { |
| 390 | compatible = "ti,omap4-mcspi"; |
| 391 | reg = <0x48098000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 392 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 393 | #address-cells = <1>; |
| 394 | #size-cells = <0>; |
| 395 | ti,hwmods = "mcspi1"; |
| 396 | ti,spi-num-cs = <4>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 397 | dmas = <&sdma 35>, |
| 398 | <&sdma 36>, |
| 399 | <&sdma 37>, |
| 400 | <&sdma 38>, |
| 401 | <&sdma 39>, |
| 402 | <&sdma 40>, |
| 403 | <&sdma 41>, |
| 404 | <&sdma 42>; |
| 405 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 406 | "tx2", "rx2", "tx3", "rx3"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 407 | }; |
| 408 | |
| 409 | mcspi2: spi@4809a000 { |
| 410 | compatible = "ti,omap4-mcspi"; |
| 411 | reg = <0x4809a000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 412 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 413 | #address-cells = <1>; |
| 414 | #size-cells = <0>; |
| 415 | ti,hwmods = "mcspi2"; |
| 416 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 417 | dmas = <&sdma 43>, |
| 418 | <&sdma 44>, |
| 419 | <&sdma 45>, |
| 420 | <&sdma 46>; |
| 421 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 422 | }; |
| 423 | |
| 424 | mcspi3: spi@480b8000 { |
| 425 | compatible = "ti,omap4-mcspi"; |
| 426 | reg = <0x480b8000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 427 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 428 | #address-cells = <1>; |
| 429 | #size-cells = <0>; |
| 430 | ti,hwmods = "mcspi3"; |
| 431 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 432 | dmas = <&sdma 15>, <&sdma 16>; |
| 433 | dma-names = "tx0", "rx0"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 434 | }; |
| 435 | |
| 436 | mcspi4: spi@480ba000 { |
| 437 | compatible = "ti,omap4-mcspi"; |
| 438 | reg = <0x480ba000 0x200>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 439 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 440 | #address-cells = <1>; |
| 441 | #size-cells = <0>; |
| 442 | ti,hwmods = "mcspi4"; |
| 443 | ti,spi-num-cs = <1>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 444 | dmas = <&sdma 70>, <&sdma 71>; |
| 445 | dma-names = "tx0", "rx0"; |
Felipe Balbi | 43286b1 | 2013-02-13 14:58:36 +0530 | [diff] [blame] | 446 | }; |
| 447 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 448 | uart1: serial@4806a000 { |
| 449 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 450 | reg = <0x4806a000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 451 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 452 | ti,hwmods = "uart1"; |
| 453 | clock-frequency = <48000000>; |
| 454 | }; |
| 455 | |
| 456 | uart2: serial@4806c000 { |
| 457 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 458 | reg = <0x4806c000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 459 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 460 | ti,hwmods = "uart2"; |
| 461 | clock-frequency = <48000000>; |
| 462 | }; |
| 463 | |
| 464 | uart3: serial@48020000 { |
| 465 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 466 | reg = <0x48020000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 467 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 468 | ti,hwmods = "uart3"; |
| 469 | clock-frequency = <48000000>; |
| 470 | }; |
| 471 | |
| 472 | uart4: serial@4806e000 { |
| 473 | compatible = "ti,omap4-uart"; |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 474 | reg = <0x4806e000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 475 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 476 | ti,hwmods = "uart4"; |
| 477 | clock-frequency = <48000000>; |
| 478 | }; |
| 479 | |
| 480 | uart5: serial@48066000 { |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 481 | compatible = "ti,omap4-uart"; |
| 482 | reg = <0x48066000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 483 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 484 | ti,hwmods = "uart5"; |
| 485 | clock-frequency = <48000000>; |
| 486 | }; |
| 487 | |
| 488 | uart6: serial@48068000 { |
Sebastien Guiriec | 8e80f66 | 2012-10-23 10:37:11 +0200 | [diff] [blame] | 489 | compatible = "ti,omap4-uart"; |
| 490 | reg = <0x48068000 0x100>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 491 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 492 | ti,hwmods = "uart6"; |
| 493 | clock-frequency = <48000000>; |
| 494 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 495 | |
| 496 | mmc1: mmc@4809c000 { |
| 497 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 498 | reg = <0x4809c000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 499 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 500 | ti,hwmods = "mmc1"; |
| 501 | ti,dual-volt; |
| 502 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 503 | dmas = <&sdma 61>, <&sdma 62>; |
| 504 | dma-names = "tx", "rx"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 505 | pbias-supply = <&pbias_mmc_reg>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 506 | }; |
| 507 | |
| 508 | mmc2: mmc@480b4000 { |
| 509 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 510 | reg = <0x480b4000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 511 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 512 | ti,hwmods = "mmc2"; |
| 513 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 514 | dmas = <&sdma 47>, <&sdma 48>; |
| 515 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 516 | }; |
| 517 | |
| 518 | mmc3: mmc@480ad000 { |
| 519 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 520 | reg = <0x480ad000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 521 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 522 | ti,hwmods = "mmc3"; |
| 523 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 524 | dmas = <&sdma 77>, <&sdma 78>; |
| 525 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 526 | }; |
| 527 | |
| 528 | mmc4: mmc@480d1000 { |
| 529 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 530 | reg = <0x480d1000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 531 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 532 | ti,hwmods = "mmc4"; |
| 533 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 534 | dmas = <&sdma 57>, <&sdma 58>; |
| 535 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 536 | }; |
| 537 | |
| 538 | mmc5: mmc@480d5000 { |
| 539 | compatible = "ti,omap4-hsmmc"; |
Sebastien Guiriec | 9a64236 | 2012-10-23 10:37:12 +0200 | [diff] [blame] | 540 | reg = <0x480d5000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 541 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 542 | ti,hwmods = "mmc5"; |
| 543 | ti,needs-special-reset; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 544 | dmas = <&sdma 59>, <&sdma 60>; |
| 545 | dma-names = "tx", "rx"; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 546 | }; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 547 | |
Suman Anna | 2dcfa56 | 2014-03-05 18:24:19 -0600 | [diff] [blame] | 548 | mmu_dsp: mmu@4a066000 { |
| 549 | compatible = "ti,omap4-iommu"; |
| 550 | reg = <0x4a066000 0x100>; |
| 551 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 552 | ti,hwmods = "mmu_dsp"; |
| 553 | }; |
| 554 | |
| 555 | mmu_ipu: mmu@55082000 { |
| 556 | compatible = "ti,omap4-iommu"; |
| 557 | reg = <0x55082000 0x100>; |
| 558 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 559 | ti,hwmods = "mmu_ipu"; |
| 560 | ti,iommu-bus-err-back; |
| 561 | }; |
| 562 | |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 563 | keypad: keypad@4ae1c000 { |
| 564 | compatible = "ti,omap4-keypad"; |
Santosh Shilimkar | 8cc8b89 | 2013-01-23 19:53:30 +0530 | [diff] [blame] | 565 | reg = <0x4ae1c000 0x400>; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 566 | ti,hwmods = "kbd"; |
| 567 | }; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 568 | |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 569 | mcpdm: mcpdm@40132000 { |
| 570 | compatible = "ti,omap4-mcpdm"; |
| 571 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 572 | <0x49032000 0x7f>; /* L3 Interconnect */ |
| 573 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 574 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 575 | ti,hwmods = "mcpdm"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 576 | dmas = <&sdma 65>, |
| 577 | <&sdma 66>; |
| 578 | dma-names = "up_link", "dn_link"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 579 | status = "disabled"; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 580 | }; |
| 581 | |
| 582 | dmic: dmic@4012e000 { |
| 583 | compatible = "ti,omap4-dmic"; |
| 584 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 585 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
| 586 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 587 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 588 | ti,hwmods = "dmic"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 589 | dmas = <&sdma 67>; |
| 590 | dma-names = "up_link"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 591 | status = "disabled"; |
Peter Ujfalusi | cbb57f0 | 2012-08-29 16:31:07 +0300 | [diff] [blame] | 592 | }; |
| 593 | |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 594 | mcbsp1: mcbsp@40122000 { |
| 595 | compatible = "ti,omap4-mcbsp"; |
| 596 | reg = <0x40122000 0xff>, /* MPU private access */ |
| 597 | <0x49022000 0xff>; /* L3 Interconnect */ |
| 598 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 599 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 600 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 601 | ti,buffer-size = <128>; |
| 602 | ti,hwmods = "mcbsp1"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 603 | dmas = <&sdma 33>, |
| 604 | <&sdma 34>; |
| 605 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 606 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 607 | }; |
| 608 | |
| 609 | mcbsp2: mcbsp@40124000 { |
| 610 | compatible = "ti,omap4-mcbsp"; |
| 611 | reg = <0x40124000 0xff>, /* MPU private access */ |
| 612 | <0x49024000 0xff>; /* L3 Interconnect */ |
| 613 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 614 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 615 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 616 | ti,buffer-size = <128>; |
| 617 | ti,hwmods = "mcbsp2"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 618 | dmas = <&sdma 17>, |
| 619 | <&sdma 18>; |
| 620 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 621 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 622 | }; |
| 623 | |
| 624 | mcbsp3: mcbsp@40126000 { |
| 625 | compatible = "ti,omap4-mcbsp"; |
| 626 | reg = <0x40126000 0xff>, /* MPU private access */ |
| 627 | <0x49026000 0xff>; /* L3 Interconnect */ |
| 628 | reg-names = "mpu", "dma"; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 629 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 630 | interrupt-names = "common"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 631 | ti,buffer-size = <128>; |
| 632 | ti,hwmods = "mcbsp3"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 633 | dmas = <&sdma 19>, |
| 634 | <&sdma 20>; |
| 635 | dma-names = "tx", "rx"; |
Peter Ujfalusi | f15534e | 2014-01-24 10:19:04 +0200 | [diff] [blame] | 636 | status = "disabled"; |
Peter Ujfalusi | ffd5db2 | 2012-08-29 16:31:04 +0300 | [diff] [blame] | 637 | }; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 638 | |
| 639 | timer1: timer@4ae18000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 640 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 641 | reg = <0x4ae18000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 642 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 643 | ti,hwmods = "timer1"; |
| 644 | ti,timer-alwon; |
| 645 | }; |
| 646 | |
| 647 | timer2: timer@48032000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 648 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 649 | reg = <0x48032000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 650 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 651 | ti,hwmods = "timer2"; |
| 652 | }; |
| 653 | |
| 654 | timer3: timer@48034000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 655 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 656 | reg = <0x48034000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 657 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 658 | ti,hwmods = "timer3"; |
| 659 | }; |
| 660 | |
| 661 | timer4: timer@48036000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 662 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 663 | reg = <0x48036000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 664 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 665 | ti,hwmods = "timer4"; |
| 666 | }; |
| 667 | |
| 668 | timer5: timer@40138000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 669 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 670 | reg = <0x40138000 0x80>, |
| 671 | <0x49038000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 672 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 673 | ti,hwmods = "timer5"; |
| 674 | ti,timer-dsp; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 675 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 676 | }; |
| 677 | |
| 678 | timer6: timer@4013a000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 679 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 680 | reg = <0x4013a000 0x80>, |
| 681 | <0x4903a000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 682 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 683 | ti,hwmods = "timer6"; |
| 684 | ti,timer-dsp; |
| 685 | ti,timer-pwm; |
| 686 | }; |
| 687 | |
| 688 | timer7: timer@4013c000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 689 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 690 | reg = <0x4013c000 0x80>, |
| 691 | <0x4903c000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 692 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 693 | ti,hwmods = "timer7"; |
| 694 | ti,timer-dsp; |
| 695 | }; |
| 696 | |
| 697 | timer8: timer@4013e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 698 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 699 | reg = <0x4013e000 0x80>, |
| 700 | <0x4903e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 701 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 702 | ti,hwmods = "timer8"; |
| 703 | ti,timer-dsp; |
| 704 | ti,timer-pwm; |
| 705 | }; |
| 706 | |
| 707 | timer9: timer@4803e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 708 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 709 | reg = <0x4803e000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 710 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 711 | ti,hwmods = "timer9"; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 712 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 713 | }; |
| 714 | |
| 715 | timer10: timer@48086000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 716 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 717 | reg = <0x48086000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 718 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 719 | ti,hwmods = "timer10"; |
Suman Anna | 8341613 | 2013-04-17 18:23:15 -0500 | [diff] [blame] | 720 | ti,timer-pwm; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 721 | }; |
| 722 | |
| 723 | timer11: timer@48088000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 724 | compatible = "ti,omap5430-timer"; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 725 | reg = <0x48088000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 726 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
Jon Hunter | df692a9 | 2012-11-01 09:09:51 -0500 | [diff] [blame] | 727 | ti,hwmods = "timer11"; |
| 728 | ti,timer-pwm; |
| 729 | }; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 730 | |
Lokesh Vutla | 5545219 | 2013-02-27 11:54:45 +0530 | [diff] [blame] | 731 | wdt2: wdt@4ae14000 { |
| 732 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; |
| 733 | reg = <0x4ae14000 0x80>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 734 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | 5545219 | 2013-02-27 11:54:45 +0530 | [diff] [blame] | 735 | ti,hwmods = "wd_timer2"; |
| 736 | }; |
| 737 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 738 | dmm@4e000000 { |
| 739 | compatible = "ti,omap5-dmm"; |
| 740 | reg = <0x4e000000 0x800>; |
| 741 | interrupts = <0 113 0x4>; |
| 742 | ti,hwmods = "dmm"; |
| 743 | }; |
| 744 | |
Lee Jones | 8906d65 | 2013-07-22 11:52:37 +0100 | [diff] [blame] | 745 | emif1: emif@4c000000 { |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 746 | compatible = "ti,emif-4d5"; |
| 747 | ti,hwmods = "emif1"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 748 | ti,no-idle-on-init; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 749 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 750 | reg = <0x4c000000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 751 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 752 | hw-caps-read-idle-ctrl; |
| 753 | hw-caps-ll-interface; |
| 754 | hw-caps-temp-alert; |
| 755 | }; |
| 756 | |
Lee Jones | 8906d65 | 2013-07-22 11:52:37 +0100 | [diff] [blame] | 757 | emif2: emif@4d000000 { |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 758 | compatible = "ti,emif-4d5"; |
| 759 | ti,hwmods = "emif2"; |
Rajendra Nayak | f12ecbe | 2013-10-15 12:37:50 +0530 | [diff] [blame] | 760 | ti,no-idle-on-init; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 761 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 762 | reg = <0x4d000000 0x400>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 763 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | e6900dd | 2012-11-05 18:22:51 +0530 | [diff] [blame] | 764 | hw-caps-read-idle-ctrl; |
| 765 | hw-caps-ll-interface; |
| 766 | hw-caps-temp-alert; |
| 767 | }; |
Kishon Vijay Abraham I | fedc428 | 2013-03-07 19:05:17 +0530 | [diff] [blame] | 768 | |
Roger Quadros | b297c29 | 2013-10-03 18:12:37 +0300 | [diff] [blame] | 769 | omap_control_usb2phy: control-phy@4a002300 { |
| 770 | compatible = "ti,control-phy-usb2"; |
| 771 | reg = <0x4a002300 0x4>; |
| 772 | reg-names = "power"; |
| 773 | }; |
| 774 | |
| 775 | omap_control_usb3phy: control-phy@4a002370 { |
| 776 | compatible = "ti,control-phy-pipe3"; |
| 777 | reg = <0x4a002370 0x4>; |
| 778 | reg-names = "power"; |
Kishon Vijay Abraham I | fedc428 | 2013-03-07 19:05:17 +0530 | [diff] [blame] | 779 | }; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 780 | |
Felipe Balbi | e3a412c | 2013-08-21 20:01:32 +0530 | [diff] [blame] | 781 | usb3: omap_dwc3@4a020000 { |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 782 | compatible = "ti,dwc3"; |
| 783 | ti,hwmods = "usb_otg_ss"; |
Felipe Balbi | 6f61ee2 | 2013-08-21 20:01:30 +0530 | [diff] [blame] | 784 | reg = <0x4a020000 0x10000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 785 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 786 | #address-cells = <1>; |
| 787 | #size-cells = <1>; |
| 788 | utmi-mode = <2>; |
| 789 | ranges; |
| 790 | dwc3@4a030000 { |
Felipe Balbi | 22a5aa1 | 2013-07-02 21:20:24 +0300 | [diff] [blame] | 791 | compatible = "snps,dwc3"; |
Felipe Balbi | 6f61ee2 | 2013-08-21 20:01:30 +0530 | [diff] [blame] | 792 | reg = <0x4a030000 0x10000>; |
Florian Vaussard | 8fea7d5 | 2013-05-31 14:32:57 +0200 | [diff] [blame] | 793 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 794 | phys = <&usb2_phy>, <&usb3_phy>; |
| 795 | phy-names = "usb2-phy", "usb3-phy"; |
George Cherian | c47ee6e | 2013-10-10 16:19:54 +0530 | [diff] [blame] | 796 | dr_mode = "peripheral"; |
Kishon Vijay Abraham I | 72f6f95 | 2013-03-07 19:05:20 +0530 | [diff] [blame] | 797 | tx-fifo-resize; |
| 798 | }; |
| 799 | }; |
| 800 | |
Felipe Balbi | b6731f7 | 2013-08-21 20:01:31 +0530 | [diff] [blame] | 801 | ocp2scp@4a080000 { |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 802 | compatible = "ti,omap-ocp2scp"; |
| 803 | #address-cells = <1>; |
| 804 | #size-cells = <1>; |
Felipe Balbi | b6731f7 | 2013-08-21 20:01:31 +0530 | [diff] [blame] | 805 | reg = <0x4a080000 0x20>; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 806 | ranges; |
| 807 | ti,hwmods = "ocp2scp1"; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 808 | usb2_phy: usb2phy@4a084000 { |
| 809 | compatible = "ti,omap-usb2"; |
| 810 | reg = <0x4a084000 0x7c>; |
Roger Quadros | b297c29 | 2013-10-03 18:12:37 +0300 | [diff] [blame] | 811 | ctrl-module = <&omap_control_usb2phy>; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 812 | #phy-cells = <0>; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 813 | }; |
| 814 | |
| 815 | usb3_phy: usb3phy@4a084400 { |
| 816 | compatible = "ti,omap-usb3"; |
| 817 | reg = <0x4a084400 0x80>, |
| 818 | <0x4a084800 0x64>, |
| 819 | <0x4a084c00 0x40>; |
| 820 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
Roger Quadros | b297c29 | 2013-10-03 18:12:37 +0300 | [diff] [blame] | 821 | ctrl-module = <&omap_control_usb3phy>; |
Roger Quadros | ada7657 | 2014-04-01 13:37:27 +0300 | [diff] [blame] | 822 | clocks = <&usb_phy_cm_clk32k>, |
| 823 | <&sys_clkin>, |
| 824 | <&usb_otg_ss_refclk960m>; |
| 825 | clock-names = "wkupclk", |
| 826 | "sysclk", |
| 827 | "refclk"; |
Kishon Vijay Abraham I | 073addc | 2014-03-03 17:08:15 +0530 | [diff] [blame] | 828 | #phy-cells = <0>; |
Kishon Vijay Abraham I | ae6a32d | 2013-03-07 19:05:19 +0530 | [diff] [blame] | 829 | }; |
Kishon Vijay Abraham I | e983196 | 2013-03-07 19:05:18 +0530 | [diff] [blame] | 830 | }; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 831 | |
| 832 | usbhstll: usbhstll@4a062000 { |
| 833 | compatible = "ti,usbhs-tll"; |
| 834 | reg = <0x4a062000 0x1000>; |
| 835 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| 836 | ti,hwmods = "usb_tll_hs"; |
| 837 | }; |
| 838 | |
| 839 | usbhshost: usbhshost@4a064000 { |
| 840 | compatible = "ti,usbhs-host"; |
| 841 | reg = <0x4a064000 0x800>; |
| 842 | ti,hwmods = "usb_host_hs"; |
| 843 | #address-cells = <1>; |
| 844 | #size-cells = <1>; |
| 845 | ranges; |
Roger Quadros | 051fc06 | 2014-02-27 16:18:26 +0200 | [diff] [blame] | 846 | clocks = <&l3init_60m_fclk>, |
| 847 | <&xclk60mhsp1_ck>, |
| 848 | <&xclk60mhsp2_ck>; |
| 849 | clock-names = "refclk_60m_int", |
| 850 | "refclk_60m_ext_p1", |
| 851 | "refclk_60m_ext_p2"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 852 | |
| 853 | usbhsohci: ohci@4a064800 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 854 | compatible = "ti,ohci-omap3"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 855 | reg = <0x4a064800 0x400>; |
| 856 | interrupt-parent = <&gic>; |
| 857 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 858 | }; |
| 859 | |
| 860 | usbhsehci: ehci@4a064c00 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 861 | compatible = "ti,ehci-omap"; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 862 | reg = <0x4a064c00 0x400>; |
| 863 | interrupt-parent = <&gic>; |
| 864 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 865 | }; |
| 866 | }; |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 867 | |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 868 | bandgap: bandgap@4a0021e0 { |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 869 | reg = <0x4a0021e0 0xc |
| 870 | 0x4a00232c 0xc |
| 871 | 0x4a002380 0x2c |
| 872 | 0x4a0023C0 0x3c>; |
| 873 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| 874 | compatible = "ti,omap5430-bandgap"; |
Eduardo Valentin | 1b761fc | 2013-08-16 12:01:02 -0400 | [diff] [blame] | 875 | |
| 876 | #thermal-sensor-cells = <1>; |
Eduardo Valentin | cbad26d | 2013-06-18 22:36:38 -0400 | [diff] [blame] | 877 | }; |
Balaji T K | 4f82952 | 2014-04-23 20:35:33 +0300 | [diff] [blame] | 878 | |
| 879 | omap_control_sata: control-phy@4a002374 { |
| 880 | compatible = "ti,control-phy-pipe3"; |
| 881 | reg = <0x4a002374 0x4>; |
| 882 | reg-names = "power"; |
| 883 | clocks = <&sys_clkin>; |
| 884 | clock-names = "sysclk"; |
| 885 | }; |
| 886 | |
| 887 | /* OCP2SCP3 */ |
| 888 | ocp2scp@4a090000 { |
| 889 | compatible = "ti,omap-ocp2scp"; |
| 890 | #address-cells = <1>; |
| 891 | #size-cells = <1>; |
| 892 | reg = <0x4a090000 0x20>; |
| 893 | ranges; |
| 894 | ti,hwmods = "ocp2scp3"; |
| 895 | sata_phy: phy@4a096000 { |
| 896 | compatible = "ti,phy-pipe3-sata"; |
| 897 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 898 | <0x4A096400 0x64>, /* phy_tx */ |
| 899 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 900 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 901 | ctrl-module = <&omap_control_sata>; |
| 902 | clocks = <&sys_clkin>; |
| 903 | clock-names = "sysclk"; |
| 904 | #phy-cells = <0>; |
| 905 | }; |
| 906 | }; |
| 907 | |
| 908 | sata: sata@4a141100 { |
| 909 | compatible = "snps,dwc-ahci"; |
| 910 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
| 911 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| 912 | phys = <&sata_phy>; |
| 913 | phy-names = "sata-phy"; |
| 914 | clocks = <&sata_ref_clk>; |
| 915 | ti,hwmods = "sata"; |
| 916 | }; |
| 917 | |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 918 | }; |
| 919 | }; |
Tero Kristo | 85dc74e | 2013-07-18 17:09:29 +0300 | [diff] [blame] | 920 | |
| 921 | /include/ "omap54xx-clocks.dtsi" |