| Kukjin Kim | fc35124 | 2013-01-01 19:40:53 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005 Simtec Electronics |
| 3 | * http://www.simtec.co.uk/products/ |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * ANUBIS - CPLD control constants |
| 7 | * ANUBIS - IRQ Number definitions |
| 8 | * ANUBIS - Memory map definitions |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #ifndef __MACH_S3C24XX_ANUBIS_H |
| 16 | #define __MACH_S3C24XX_ANUBIS_H __FILE__ |
| 17 | |
| 18 | /* CTRL2 - NAND WP control, IDE Reset assert/check */ |
| 19 | |
| 20 | #define ANUBIS_CTRL1_NANDSEL (0x3) |
| 21 | |
| 22 | /* IDREG - revision */ |
| 23 | |
| 24 | #define ANUBIS_IDREG_REVMASK (0x7) |
| 25 | |
| 26 | /* irq */ |
| 27 | |
| 28 | #define ANUBIS_IRQ_IDE0 IRQ_EINT2 |
| 29 | #define ANUBIS_IRQ_IDE1 IRQ_EINT3 |
| 30 | #define ANUBIS_IRQ_ASIX IRQ_EINT1 |
| 31 | |
| 32 | /* map */ |
| 33 | |
| 34 | /* start peripherals off after the S3C2410 */ |
| 35 | |
| 36 | #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) |
| 37 | |
| 38 | #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) |
| 39 | |
| 40 | /* we put the CPLD registers next, to get them out of the way */ |
| 41 | |
| 42 | #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) |
| 43 | #define ANUBIS_PA_CTRL1 ANUBIS_PA_CPLD |
| 44 | |
| 45 | #define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) |
| 46 | #define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3 << 23)) |
| 47 | |
| 48 | #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) |
| 49 | #define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000) |
| 50 | #define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000) |
| 51 | #define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000) |
| 52 | |
| 53 | #endif /* __MACH_S3C24XX_ANUBIS_H */ |