Lokesh Batra | f7f72ff | 2016-10-13 11:51:59 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | &soc { |
| 14 | |
| 15 | msm_bus: qcom,kgsl-busmon{ |
| 16 | label = "kgsl-busmon"; |
| 17 | compatible = "qcom,kgsl-busmon"; |
| 18 | }; |
| 19 | |
| 20 | gpubw: qcom,gpubw { |
| 21 | compatible = "qcom,devbw"; |
| 22 | governor = "bw_vbif"; |
| 23 | qcom,src-dst-ports = <26 512>; |
| 24 | /* |
| 25 | * active-only flag is used while registering the bus |
| 26 | * governor.It helps release the bus vote when the CPU |
| 27 | * subsystem is inactiv3 |
| 28 | */ |
| 29 | qcom,active-only; |
| 30 | qcom,bw-tbl = |
| 31 | < 0 /* off */ >, |
| 32 | < 762 /* 100 MHz */ >, |
| 33 | < 1144 /* 150 MHz */ >, |
| 34 | < 1525 /* 200 MHz */ >, |
| 35 | < 2288 /* 300 MHz */ >, |
| 36 | < 3143 /* 412 MHz */ >, |
| 37 | < 4173 /* 547 MHz */ >, |
| 38 | < 5195 /* 681 MHz */ >, |
| 39 | < 5859 /* 768 MHz */ >, |
| 40 | < 7759 /* 1017 MHz */ >, |
| 41 | < 9887 /* 1296 MHz */ >, |
| 42 | < 11863 /* 1555 MHz */ >, |
| 43 | < 13763 /* 1804 MHz */ >; |
| 44 | }; |
| 45 | |
| 46 | msm_gpu: qcom,kgsl-3d0@5000000 { |
| 47 | label = "kgsl-3d0"; |
| 48 | compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; |
| 49 | status = "ok"; |
| 50 | reg = <0x5000000 0x40000>; |
| 51 | reg-names = "kgsl_3d0_reg_memory"; |
| 52 | interrupts = <0 300 0>; |
| 53 | interrupt-names = "kgsl_3d0_irq"; |
| 54 | qcom,id = <0>; |
| 55 | |
| 56 | qcom,chipid = <0x06030000>; |
| 57 | |
| 58 | qcom,initial-pwrlevel = <2>; |
| 59 | |
| 60 | qcom,gpu-quirk-hfi-use-reg; |
| 61 | qcom,gpu-quirk-two-pass-use-wfi; |
| 62 | |
| 63 | qcom,idle-timeout = <100000000>; //msecs |
| 64 | qcom,no-nap; |
| 65 | |
| 66 | qcom,highest-bank-bit = <15>; |
| 67 | |
| 68 | qcom,min-access-length = <32>; |
| 69 | |
| 70 | qcom,ubwc-mode = <2>; |
| 71 | |
| 72 | qcom,snapshot-size = <1048576>; //bytes |
| 73 | |
| 74 | qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size |
| 75 | |
| 76 | qcom,tsens-name = "tsens_tz_sensor12"; |
Ram Chandrasekar | 36ffe55 | 2017-04-17 16:33:05 -0600 | [diff] [blame] | 77 | #cooling-cells = <2>; |
Lokesh Batra | f7f72ff | 2016-10-13 11:51:59 -0700 | [diff] [blame] | 78 | |
| 79 | clocks = <&clock_gfx GPU_CC_GX_GFX3D_CLK>, |
| 80 | <&clock_gcc GCC_GPU_CFG_AHB_CLK>, |
| 81 | <&clock_gpucc GPU_CC_CXO_CLK>, |
| 82 | <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 83 | <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; |
| 84 | |
| 85 | clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", |
| 86 | "mem_clk", "mem_iface_clk"; |
| 87 | |
| 88 | qcom,isense-clk-on-level = <1>; |
| 89 | |
| 90 | /* Bus Scale Settings */ |
| 91 | qcom,gpubw-dev = <&gpubw>; |
| 92 | qcom,bus-control; |
| 93 | qcom,msm-bus,name = "grp3d"; |
| 94 | qcom,msm-bus,num-cases = <13>; |
| 95 | qcom,msm-bus,num-paths = <1>; |
| 96 | qcom,msm-bus,vectors-KBps = |
| 97 | <26 512 0 0>, |
| 98 | |
| 99 | <26 512 0 800000>, // 1 bus=100 |
| 100 | <26 512 0 1200000>, // 2 bus=150 |
| 101 | <26 512 0 1600000>, // 3 bus=200 |
| 102 | <26 512 0 2400000>, // 4 bus=300 |
| 103 | <26 512 0 3296000>, // 5 bus=412 |
| 104 | <26 512 0 4376000>, // 6 bus=547 |
| 105 | <26 512 0 5448000>, // 7 bus=681 |
| 106 | <26 512 0 6144000>, // 8 bus=768 |
| 107 | <26 512 0 8136000>, // 9 bus=1017 |
| 108 | <26 512 0 10368000>, // 10 bus=1296 |
| 109 | <26 512 0 12440000>, // 11 bus=1555 |
| 110 | <26 512 0 14432000>; // 12 bus=1804 |
| 111 | |
| 112 | /* GDSC regulator names */ |
| 113 | regulator-names = "vddcx", "vdd"; |
| 114 | /* GDSC oxili regulators */ |
| 115 | vddcx-supply = <&gpu_cx_gdsc>; |
| 116 | vdd-supply = <&gpu_gx_gdsc>; |
| 117 | |
| 118 | /* GPU related llc slices */ |
| 119 | cache-slice-names = "gpu", "gpuhtw"; |
| 120 | cache-slices = <&llcc 12>, <&llcc 11>; |
| 121 | |
| 122 | /* GPU Mempools */ |
| 123 | qcom,gpu-mempools { |
| 124 | #address-cells = <1>; |
| 125 | #size-cells = <0>; |
| 126 | compatible = "qcom,gpu-mempools"; |
| 127 | |
| 128 | /* 4K Page Pool configuration */ |
| 129 | qcom,gpu-mempool@0 { |
| 130 | reg = <0>; |
| 131 | qcom,mempool-page-size = <4096>; |
| 132 | qcom,mempool-reserved = <2048>; |
| 133 | qcom,mempool-allocate; |
| 134 | }; |
| 135 | /* 8K Page Pool configuration */ |
| 136 | qcom,gpu-mempool@1 { |
| 137 | reg = <1>; |
| 138 | qcom,mempool-page-size = <8192>; |
| 139 | qcom,mempool-reserved = <1024>; |
| 140 | qcom,mempool-allocate; |
| 141 | }; |
| 142 | /* 64K Page Pool configuration */ |
| 143 | qcom,gpu-mempool@2 { |
| 144 | reg = <2>; |
| 145 | qcom,mempool-page-size = <65536>; |
| 146 | qcom,mempool-reserved = <256>; |
| 147 | }; |
| 148 | /* 1M Page Pool configuration */ |
| 149 | qcom,gpu-mempool@3 { |
| 150 | reg = <3>; |
| 151 | qcom,mempool-page-size = <1048576>; |
| 152 | qcom,mempool-reserved = <32>; |
| 153 | }; |
| 154 | }; |
| 155 | |
| 156 | /* Power levels */ |
| 157 | qcom,gpu-pwrlevels { |
| 158 | #address-cells = <1>; |
| 159 | #size-cells = <0>; |
| 160 | |
| 161 | compatible = "qcom,gpu-pwrlevels"; |
| 162 | |
| 163 | qcom,gpu-pwrlevel@0 { |
| 164 | reg = <0>; |
| 165 | qcom,gpu-freq = <548000000>; |
| 166 | qcom,bus-freq = <12>; |
| 167 | qcom,bus-min = <11>; |
| 168 | qcom,bus-max = <12>; |
| 169 | }; |
| 170 | |
| 171 | |
| 172 | qcom,gpu-pwrlevel@1 { |
| 173 | reg = <1>; |
| 174 | qcom,gpu-freq = <425000000>; |
| 175 | qcom,bus-freq = <7>; |
| 176 | qcom,bus-min = <6>; |
| 177 | qcom,bus-max = <8>; |
| 178 | }; |
| 179 | |
| 180 | qcom,gpu-pwrlevel@2 { |
| 181 | reg = <2>; |
| 182 | qcom,gpu-freq = <280000000>; |
| 183 | qcom,bus-freq = <4>; |
| 184 | qcom,bus-min = <3>; |
| 185 | qcom,bus-max = <5>; |
| 186 | }; |
| 187 | |
| 188 | qcom,gpu-pwrlevel@3 { |
| 189 | reg = <3>; |
| 190 | qcom,gpu-freq = <27000000>; |
| 191 | qcom,bus-freq = <0>; |
| 192 | qcom,bus-min = <0>; |
| 193 | qcom,bus-max = <0>; |
| 194 | }; |
| 195 | }; |
| 196 | |
| 197 | }; |
| 198 | |
| 199 | kgsl_msm_iommu: qcom,kgsl-iommu { |
| 200 | compatible = "qcom,kgsl-smmu-v2"; |
| 201 | |
| 202 | reg = <0x05040000 0x10000>; |
| 203 | qcom,protect = <0x40000 0x10000>; |
| 204 | qcom,micro-mmu-control = <0x6000>; |
| 205 | |
| 206 | clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, |
| 207 | <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 208 | <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; |
| 209 | |
| 210 | clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; |
| 211 | |
| 212 | qcom,secure_align_mask = <0xfff>; |
| 213 | qcom,global_pt; |
| 214 | |
| 215 | gfx3d_user: gfx3d_user { |
| 216 | compatible = "qcom,smmu-kgsl-cb"; |
| 217 | label = "gfx3d_user"; |
| 218 | iommus = <&kgsl_smmu 0>; |
| 219 | qcom,gpu-offset = <0x48000>; |
| 220 | }; |
| 221 | |
| 222 | gfx3d_secure: gfx3d_secure { |
| 223 | compatible = "qcom,smmu-kgsl-cb"; |
| 224 | iommus = <&kgsl_smmu 2>; |
| 225 | }; |
| 226 | }; |
| 227 | |
| 228 | gmu: qcom,gmu { |
| 229 | label = "kgsl-gmu"; |
| 230 | compatible = "qcom,gpu-gmu"; |
| 231 | |
| 232 | reg = <0x506a000 0x26000>, <0xb200000 0x300000>; |
| 233 | reg-names = "kgsl_gmu_reg", "kgsl_gmu_pdc_reg"; |
| 234 | |
| 235 | interrupts = <0 304 0>, <0 305 0>; |
| 236 | interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; |
| 237 | |
| 238 | qcom,msm-bus,name = "cnoc"; |
| 239 | qcom,msm-bus,num-cases = <2>; |
| 240 | qcom,msm-bus,num-paths = <1>; |
| 241 | qcom,msm-bus,vectors-KBps = |
| 242 | <26 10036 0 0>, // CNOC off |
| 243 | <26 10036 0 100>; // CNOC on |
| 244 | |
| 245 | regulator-names = "vddcx", "vdd"; |
| 246 | vddcx-supply = <&gpu_cx_gdsc>; |
| 247 | vdd-supply = <&gpu_gx_gdsc>; |
| 248 | |
| 249 | |
| 250 | clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, |
| 251 | <&clock_gcc GCC_GPU_CFG_AHB_CLK>, |
| 252 | <&clock_gpucc GPU_CC_CXO_CLK>, |
| 253 | <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 254 | <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; |
| 255 | |
| 256 | clock-names = "gmu_clk", "ahb_clk", "cxo_clk", |
| 257 | "axi_clk", "memnoc_clk"; |
| 258 | |
| 259 | qcom,gmu-pwrlevels { |
Kyle Piefer | 3d1d2da | 2017-04-10 14:50:19 -0700 | [diff] [blame] | 260 | #address-cells = <1>; |
| 261 | #size-cells = <0>; |
| 262 | |
Lokesh Batra | f7f72ff | 2016-10-13 11:51:59 -0700 | [diff] [blame] | 263 | compatible = "qcom,gmu-pwrlevels"; |
| 264 | |
| 265 | qcom,gmu-pwrlevel@0 { |
| 266 | reg = <0>; |
| 267 | qcom,gmu-freq = <400000000>; |
| 268 | }; |
| 269 | |
| 270 | qcom,gmu-pwrlevel@1 { |
| 271 | reg = <1>; |
| 272 | qcom,gmu-freq = <19200000>; |
| 273 | }; |
| 274 | |
| 275 | qcom,gmu-pwrlevel@2 { |
| 276 | reg = <2>; |
| 277 | qcom,gmu-freq = <0>; |
| 278 | }; |
| 279 | }; |
| 280 | |
| 281 | gmu_user: gmu_user { |
| 282 | compatible = "qcom,smmu-gmu-user-cb"; |
| 283 | iommus = <&kgsl_smmu 4>; |
| 284 | }; |
| 285 | |
| 286 | gmu_kernel: gmu_kernel { |
| 287 | compatible = "qcom,smmu-gmu-kernel-cb"; |
| 288 | iommus = <&kgsl_smmu 5>; |
| 289 | }; |
| 290 | }; |
| 291 | }; |