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Bryan Wue190d6b2007-07-17 14:43:44 +08001/*
Mike Frysinger2fb9d6f2008-01-30 16:52:24 +08002 * Blackfin On-Chip MAC Driver
Bryan Wue190d6b2007-07-17 14:43:44 +08003 *
Sonic Zhang02460d02010-06-11 10:44:22 +00004 * Copyright 2004-2010 Analog Devices Inc.
Bryan Wue190d6b2007-07-17 14:43:44 +08005 *
Mike Frysinger2fb9d6f2008-01-30 16:52:24 +08006 * Enter bugs at http://blackfin.uclinux.org/
Bryan Wue190d6b2007-07-17 14:43:44 +08007 *
Mike Frysinger2fb9d6f2008-01-30 16:52:24 +08008 * Licensed under the GPL-2 or later.
Bryan Wue190d6b2007-07-17 14:43:44 +08009 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/crc32.h>
23#include <linux/device.h>
24#include <linux/spinlock.h>
Bryan Wue190d6b2007-07-17 14:43:44 +080025#include <linux/mii.h>
Bryan Wue190d6b2007-07-17 14:43:44 +080026#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
Bryan Wu679dce32008-04-25 11:53:11 +080028#include <linux/ethtool.h>
Bryan Wue190d6b2007-07-17 14:43:44 +080029#include <linux/skbuff.h>
Bryan Wue190d6b2007-07-17 14:43:44 +080030#include <linux/platform_device.h>
Bryan Wue190d6b2007-07-17 14:43:44 +080031
32#include <asm/dma.h>
33#include <linux/dma-mapping.h>
34
Barry Songfe92afe2010-05-17 17:19:40 -070035#include <asm/div64.h>
Mike Frysinger98f672c2010-01-18 21:14:12 +000036#include <asm/dpmc.h>
Bryan Wue190d6b2007-07-17 14:43:44 +080037#include <asm/blackfin.h>
38#include <asm/cacheflush.h>
39#include <asm/portmux.h>
David Howells3dcc1e72010-10-07 14:08:49 +010040#include <mach/pll.h>
Bryan Wue190d6b2007-07-17 14:43:44 +080041
42#include "bfin_mac.h"
43
44#define DRV_NAME "bfin_mac"
45#define DRV_VERSION "1.1"
46#define DRV_AUTHOR "Bryan Wu, Luke Yang"
Bryan Wu7ef0a7e2008-04-25 11:53:10 +080047#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
Bryan Wue190d6b2007-07-17 14:43:44 +080048
49MODULE_AUTHOR(DRV_AUTHOR);
50MODULE_LICENSE("GPL");
51MODULE_DESCRIPTION(DRV_DESC);
Kay Sievers72abb462008-04-18 13:50:44 -070052MODULE_ALIAS("platform:bfin_mac");
Bryan Wue190d6b2007-07-17 14:43:44 +080053
54#if defined(CONFIG_BFIN_MAC_USE_L1)
55# define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size)
56# define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr)
57#else
58# define bfin_mac_alloc(dma_handle, size) \
59 dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL)
60# define bfin_mac_free(dma_handle, ptr) \
61 dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle)
62#endif
63
64#define PKT_BUF_SZ 1580
65
66#define MAX_TIMEOUT_CNT 500
67
68/* pointers to maintain transmit list */
69static struct net_dma_desc_tx *tx_list_head;
70static struct net_dma_desc_tx *tx_list_tail;
71static struct net_dma_desc_rx *rx_list_head;
72static struct net_dma_desc_rx *rx_list_tail;
73static struct net_dma_desc_rx *current_rx_ptr;
74static struct net_dma_desc_tx *current_tx_ptr;
75static struct net_dma_desc_tx *tx_desc;
76static struct net_dma_desc_rx *rx_desc;
77
78static void desc_list_free(void)
79{
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
82 int i;
83#if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
85#endif
86
87 if (tx_desc) {
88 t = tx_list_head;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
90 if (t) {
91 if (t->skb) {
92 dev_kfree_skb(t->skb);
93 t->skb = NULL;
94 }
95 t = t->next;
96 }
97 }
98 bfin_mac_free(dma_handle, tx_desc);
99 }
100
101 if (rx_desc) {
102 r = rx_list_head;
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
104 if (r) {
105 if (r->skb) {
106 dev_kfree_skb(r->skb);
107 r->skb = NULL;
108 }
109 r = r->next;
110 }
111 }
112 bfin_mac_free(dma_handle, rx_desc);
113 }
114}
115
116static int desc_list_init(void)
117{
118 int i;
119 struct sk_buff *new_skb;
120#if !defined(CONFIG_BFIN_MAC_USE_L1)
121 /*
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
124 */
125 dma_addr_t dma_handle;
126#endif
127
128 tx_desc = bfin_mac_alloc(&dma_handle,
129 sizeof(struct net_dma_desc_tx) *
130 CONFIG_BFIN_TX_DESC_NUM);
131 if (tx_desc == NULL)
132 goto init_error;
133
134 rx_desc = bfin_mac_alloc(&dma_handle,
135 sizeof(struct net_dma_desc_rx) *
136 CONFIG_BFIN_RX_DESC_NUM);
137 if (rx_desc == NULL)
138 goto init_error;
139
140 /* init tx_list */
141 tx_list_head = tx_list_tail = tx_desc;
142
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
147
148 /*
149 * disable DMA
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
153 * large desc flow
154 */
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
157 a->x_count = 0;
158 a->next_dma_desc = b;
159
160 /*
161 * enabled DMA
162 * write to memory WNR = 1
163 * wordsize is 32 bits
164 * disable interrupt
165 * 6 half words is desc size
166 * large desc flow
167 */
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
170 b->x_count = 0;
171
172 t->skb = NULL;
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
175 tx_list_tail = t;
176 }
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
180
181 /* init rx_list */
182 rx_list_head = rx_list_tail = rx_desc;
183
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
188
189 /* allocate a new skb for next time receive */
Michael Hennerich015dac82009-05-29 03:41:15 +0000190 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
Bryan Wue190d6b2007-07-17 14:43:44 +0800191 if (!new_skb) {
192 printk(KERN_NOTICE DRV_NAME
193 ": init: low on mem - packet dropped\n");
194 goto init_error;
195 }
Michael Hennerich015dac82009-05-29 03:41:15 +0000196 skb_reserve(new_skb, NET_IP_ALIGN);
Sonic Zhangf6e1e4f2010-05-10 05:39:08 +0000197 /* Invidate the data cache of skb->data range when it is write back
198 * cache. It will prevent overwritting the new data from DMA
199 */
200 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
201 (unsigned long)new_skb->end);
Bryan Wue190d6b2007-07-17 14:43:44 +0800202 r->skb = new_skb;
203
204 /*
205 * enabled DMA
206 * write to memory WNR = 1
207 * wordsize is 32 bits
208 * disable interrupt
209 * 6 half words is desc size
210 * large desc flow
211 */
212 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
213 /* since RXDWA is enabled */
214 a->start_addr = (unsigned long)new_skb->data - 2;
215 a->x_count = 0;
216 a->next_dma_desc = b;
217
218 /*
219 * enabled DMA
220 * write to memory WNR = 1
221 * wordsize is 32 bits
222 * enable interrupt
223 * 6 half words is desc size
224 * large desc flow
225 */
226 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
227 NDSIZE_6 | DMAFLOW_LARGE;
228 b->start_addr = (unsigned long)(&(r->status));
229 b->x_count = 0;
230
231 rx_list_tail->desc_b.next_dma_desc = a;
232 rx_list_tail->next = r;
233 rx_list_tail = r;
234 }
235 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
236 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
237 current_rx_ptr = rx_list_head;
238
239 return 0;
240
241init_error:
242 desc_list_free();
243 printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
244 return -ENOMEM;
245}
246
247
248/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
249
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800250/*
251 * MII operations
252 */
Bryan Wue190d6b2007-07-17 14:43:44 +0800253/* Wait until the previous MDC/MDIO transaction has completed */
Mike Frysinger2bfa0f02010-05-10 05:39:13 +0000254static int bfin_mdio_poll(void)
Bryan Wue190d6b2007-07-17 14:43:44 +0800255{
256 int timeout_cnt = MAX_TIMEOUT_CNT;
257
258 /* poll the STABUSY bit */
259 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
Bryan Wu6db9e462008-01-30 16:52:21 +0800260 udelay(1);
Bryan Wue190d6b2007-07-17 14:43:44 +0800261 if (timeout_cnt-- < 0) {
262 printk(KERN_ERR DRV_NAME
263 ": wait MDC/MDIO transaction to complete timeout\n");
Mike Frysinger2bfa0f02010-05-10 05:39:13 +0000264 return -ETIMEDOUT;
Bryan Wue190d6b2007-07-17 14:43:44 +0800265 }
266 }
Mike Frysinger2bfa0f02010-05-10 05:39:13 +0000267
268 return 0;
Bryan Wue190d6b2007-07-17 14:43:44 +0800269}
270
271/* Read an off-chip register in a PHY through the MDC/MDIO port */
Adrian Bunk0ed0563e2008-10-12 21:15:17 -0700272static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
Bryan Wue190d6b2007-07-17 14:43:44 +0800273{
Mike Frysinger2bfa0f02010-05-10 05:39:13 +0000274 int ret;
275
276 ret = bfin_mdio_poll();
277 if (ret)
278 return ret;
Bryan Wue190d6b2007-07-17 14:43:44 +0800279
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800280 /* read mode */
281 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
282 SET_REGAD((u16) regnum) |
283 STABUSY);
284
Mike Frysinger2bfa0f02010-05-10 05:39:13 +0000285 ret = bfin_mdio_poll();
286 if (ret)
287 return ret;
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800288
289 return (int) bfin_read_EMAC_STADAT();
Bryan Wue190d6b2007-07-17 14:43:44 +0800290}
291
292/* Write an off-chip register in a PHY through the MDC/MDIO port */
Adrian Bunk0ed0563e2008-10-12 21:15:17 -0700293static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
294 u16 value)
Bryan Wue190d6b2007-07-17 14:43:44 +0800295{
Mike Frysinger2bfa0f02010-05-10 05:39:13 +0000296 int ret;
297
298 ret = bfin_mdio_poll();
299 if (ret)
300 return ret;
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800301
302 bfin_write_EMAC_STADAT((u32) value);
Bryan Wue190d6b2007-07-17 14:43:44 +0800303
304 /* write mode */
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800305 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
306 SET_REGAD((u16) regnum) |
Bryan Wue190d6b2007-07-17 14:43:44 +0800307 STAOP |
308 STABUSY);
309
Mike Frysinger2bfa0f02010-05-10 05:39:13 +0000310 return bfin_mdio_poll();
Bryan Wue190d6b2007-07-17 14:43:44 +0800311}
312
Adrian Bunk0ed0563e2008-10-12 21:15:17 -0700313static int bfin_mdiobus_reset(struct mii_bus *bus)
Bryan Wue190d6b2007-07-17 14:43:44 +0800314{
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800315 return 0;
Bryan Wue190d6b2007-07-17 14:43:44 +0800316}
317
Bryan Wu7ef0a7e2008-04-25 11:53:10 +0800318static void bfin_mac_adjust_link(struct net_device *dev)
Bryan Wue190d6b2007-07-17 14:43:44 +0800319{
Bryan Wu7ef0a7e2008-04-25 11:53:10 +0800320 struct bfin_mac_local *lp = netdev_priv(dev);
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800321 struct phy_device *phydev = lp->phydev;
322 unsigned long flags;
323 int new_state = 0;
Bryan Wue190d6b2007-07-17 14:43:44 +0800324
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800325 spin_lock_irqsave(&lp->lock, flags);
326 if (phydev->link) {
327 /* Now we make sure that we can be in full duplex mode.
328 * If not, we operate in half-duplex mode. */
329 if (phydev->duplex != lp->old_duplex) {
330 u32 opmode = bfin_read_EMAC_OPMODE();
331 new_state = 1;
Bryan Wue190d6b2007-07-17 14:43:44 +0800332
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800333 if (phydev->duplex)
334 opmode |= FDMODE;
335 else
336 opmode &= ~(FDMODE);
Bryan Wue190d6b2007-07-17 14:43:44 +0800337
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800338 bfin_write_EMAC_OPMODE(opmode);
339 lp->old_duplex = phydev->duplex;
340 }
Bryan Wue190d6b2007-07-17 14:43:44 +0800341
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800342 if (phydev->speed != lp->old_speed) {
Sonic Zhang02460d02010-06-11 10:44:22 +0000343 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
344 u32 opmode = bfin_read_EMAC_OPMODE();
345 switch (phydev->speed) {
346 case 10:
347 opmode |= RMII_10;
348 break;
349 case 100:
350 opmode &= ~RMII_10;
351 break;
352 default:
353 printk(KERN_WARNING
354 "%s: Ack! Speed (%d) is not 10/100!\n",
355 DRV_NAME, phydev->speed);
356 break;
357 }
358 bfin_write_EMAC_OPMODE(opmode);
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800359 }
Bryan Wue190d6b2007-07-17 14:43:44 +0800360
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800361 new_state = 1;
362 lp->old_speed = phydev->speed;
363 }
Bryan Wue190d6b2007-07-17 14:43:44 +0800364
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800365 if (!lp->old_link) {
366 new_state = 1;
367 lp->old_link = 1;
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800368 }
369 } else if (lp->old_link) {
370 new_state = 1;
371 lp->old_link = 0;
372 lp->old_speed = 0;
373 lp->old_duplex = -1;
Bryan Wue190d6b2007-07-17 14:43:44 +0800374 }
375
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800376 if (new_state) {
377 u32 opmode = bfin_read_EMAC_OPMODE();
378 phy_print_status(phydev);
379 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
Bryan Wue190d6b2007-07-17 14:43:44 +0800380 }
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800381
382 spin_unlock_irqrestore(&lp->lock, flags);
383}
384
Bryan Wu7cc8f382008-01-30 16:52:22 +0800385/* MDC = 2.5 MHz */
386#define MDC_CLK 2500000
387
Sonic Zhang02460d02010-06-11 10:44:22 +0000388static int mii_probe(struct net_device *dev, int phy_mode)
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800389{
Bryan Wu7ef0a7e2008-04-25 11:53:10 +0800390 struct bfin_mac_local *lp = netdev_priv(dev);
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800391 struct phy_device *phydev = NULL;
392 unsigned short sysctl;
393 int i;
Bryan Wu7cc8f382008-01-30 16:52:22 +0800394 u32 sclk, mdc_div;
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800395
396 /* Enable PHY output early */
Mike Frysinger98f672c2010-01-18 21:14:12 +0000397 if (!(bfin_read_VR_CTL() & CLKBUFOE))
398 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800399
Bryan Wu7cc8f382008-01-30 16:52:22 +0800400 sclk = get_sclk();
401 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
402
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800403 sysctl = bfin_read_EMAC_SYSCTL();
Bryan Wu9dc7f302008-01-30 16:52:28 +0800404 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800405 bfin_write_EMAC_SYSCTL(sysctl);
406
Sonic Zhang02460d02010-06-11 10:44:22 +0000407 /* search for connected PHY device */
408 for (i = 0; i < PHY_MAX_ADDR; ++i) {
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -0700409 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800410
411 if (!tmp_phydev)
412 continue; /* no PHY here... */
413
414 phydev = tmp_phydev;
415 break; /* found it */
416 }
417
418 /* now we are supposed to have a proper phydev, to attach to... */
419 if (!phydev) {
420 printk(KERN_INFO "%s: Don't found any phy device at all\n",
421 dev->name);
422 return -ENODEV;
423 }
424
Sonic Zhang02460d02010-06-11 10:44:22 +0000425 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
426 phy_mode != PHY_INTERFACE_MODE_MII) {
427 printk(KERN_INFO "%s: Invalid phy interface mode\n", dev->name);
428 return -EINVAL;
429 }
430
Kay Sieversc2313552009-03-24 16:38:22 -0700431 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
Sonic Zhang02460d02010-06-11 10:44:22 +0000432 0, phy_mode);
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800433
434 if (IS_ERR(phydev)) {
435 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
436 return PTR_ERR(phydev);
437 }
438
439 /* mask with MAC supported features */
440 phydev->supported &= (SUPPORTED_10baseT_Half
441 | SUPPORTED_10baseT_Full
442 | SUPPORTED_100baseT_Half
443 | SUPPORTED_100baseT_Full
444 | SUPPORTED_Autoneg
445 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
446 | SUPPORTED_MII
447 | SUPPORTED_TP);
448
449 phydev->advertising = phydev->supported;
450
451 lp->old_link = 0;
452 lp->old_speed = 0;
453 lp->old_duplex = -1;
454 lp->phydev = phydev;
455
456 printk(KERN_INFO "%s: attached PHY driver [%s] "
Bryan Wu7cc8f382008-01-30 16:52:22 +0800457 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
458 "@sclk=%dMHz)\n",
Kay Sieversc2313552009-03-24 16:38:22 -0700459 DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
Bryan Wu7cc8f382008-01-30 16:52:22 +0800460 MDC_CLK, mdc_div, sclk/1000000);
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800461
462 return 0;
Bryan Wue190d6b2007-07-17 14:43:44 +0800463}
464
Bryan Wu679dce32008-04-25 11:53:11 +0800465/*
466 * Ethtool support
467 */
468
Michael Hennerich53fd3f22010-05-10 05:39:11 +0000469/*
470 * interrupt routine for magic packet wakeup
471 */
472static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
473{
474 return IRQ_HANDLED;
475}
476
Bryan Wu679dce32008-04-25 11:53:11 +0800477static int
478bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
479{
480 struct bfin_mac_local *lp = netdev_priv(dev);
481
482 if (lp->phydev)
483 return phy_ethtool_gset(lp->phydev, cmd);
484
485 return -EINVAL;
486}
487
488static int
489bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
490{
491 struct bfin_mac_local *lp = netdev_priv(dev);
492
493 if (!capable(CAP_NET_ADMIN))
494 return -EPERM;
495
496 if (lp->phydev)
497 return phy_ethtool_sset(lp->phydev, cmd);
498
499 return -EINVAL;
500}
501
502static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
503 struct ethtool_drvinfo *info)
504{
505 strcpy(info->driver, DRV_NAME);
506 strcpy(info->version, DRV_VERSION);
507 strcpy(info->fw_version, "N/A");
Kay Sieversc2313552009-03-24 16:38:22 -0700508 strcpy(info->bus_info, dev_name(&dev->dev));
Bryan Wu679dce32008-04-25 11:53:11 +0800509}
510
Michael Hennerich53fd3f22010-05-10 05:39:11 +0000511static void bfin_mac_ethtool_getwol(struct net_device *dev,
512 struct ethtool_wolinfo *wolinfo)
513{
514 struct bfin_mac_local *lp = netdev_priv(dev);
515
516 wolinfo->supported = WAKE_MAGIC;
517 wolinfo->wolopts = lp->wol;
518}
519
520static int bfin_mac_ethtool_setwol(struct net_device *dev,
521 struct ethtool_wolinfo *wolinfo)
522{
523 struct bfin_mac_local *lp = netdev_priv(dev);
524 int rc;
525
526 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
527 WAKE_UCAST |
528 WAKE_MCAST |
529 WAKE_BCAST |
530 WAKE_ARP))
531 return -EOPNOTSUPP;
532
533 lp->wol = wolinfo->wolopts;
534
535 if (lp->wol && !lp->irq_wake_requested) {
536 /* register wake irq handler */
537 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
538 IRQF_DISABLED, "EMAC_WAKE", dev);
539 if (rc)
540 return rc;
541 lp->irq_wake_requested = true;
542 }
543
544 if (!lp->wol && lp->irq_wake_requested) {
545 free_irq(IRQ_MAC_WAKEDET, dev);
546 lp->irq_wake_requested = false;
547 }
548
549 /* Make sure the PHY driver doesn't suspend */
550 device_init_wakeup(&dev->dev, lp->wol);
551
552 return 0;
553}
554
Stephen Hemminger0fc0b732009-09-02 01:03:33 -0700555static const struct ethtool_ops bfin_mac_ethtool_ops = {
Bryan Wu679dce32008-04-25 11:53:11 +0800556 .get_settings = bfin_mac_ethtool_getsettings,
557 .set_settings = bfin_mac_ethtool_setsettings,
558 .get_link = ethtool_op_get_link,
559 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
Michael Hennerich53fd3f22010-05-10 05:39:11 +0000560 .get_wol = bfin_mac_ethtool_getwol,
561 .set_wol = bfin_mac_ethtool_setwol,
Bryan Wu679dce32008-04-25 11:53:11 +0800562};
563
Bryan Wue190d6b2007-07-17 14:43:44 +0800564/**************************************************************************/
565void setup_system_regs(struct net_device *dev)
566{
Sonic Zhang02460d02010-06-11 10:44:22 +0000567 struct bfin_mac_local *lp = netdev_priv(dev);
568 int i;
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800569 unsigned short sysctl;
Bryan Wue190d6b2007-07-17 14:43:44 +0800570
Bryan Wu4ae5a3a2007-09-19 23:37:36 +0800571 /*
572 * Odd word alignment for Receive Frame DMA word
573 * Configure checksum support and rcve frame word alignment
574 */
575 sysctl = bfin_read_EMAC_SYSCTL();
Sonic Zhang02460d02010-06-11 10:44:22 +0000576 /*
577 * check if interrupt is requested for any PHY,
578 * enable PHY interrupt only if needed
579 */
580 for (i = 0; i < PHY_MAX_ADDR; ++i)
581 if (lp->mii_bus->irq[i] != PHY_POLL)
582 break;
583 if (i < PHY_MAX_ADDR)
584 sysctl |= PHYIE;
Bryan Wue190d6b2007-07-17 14:43:44 +0800585 sysctl |= RXDWA;
Sonic Zhang812a9de2010-05-10 05:39:10 +0000586#if defined(BFIN_MAC_CSUM_OFFLOAD)
587 sysctl |= RXCKS;
588#else
589 sysctl &= ~RXCKS;
Bryan Wue190d6b2007-07-17 14:43:44 +0800590#endif
591 bfin_write_EMAC_SYSCTL(sysctl);
Bryan Wue190d6b2007-07-17 14:43:44 +0800592
593 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
594
595 /* Initialize the TX DMA channel registers */
596 bfin_write_DMA2_X_COUNT(0);
597 bfin_write_DMA2_X_MODIFY(4);
598 bfin_write_DMA2_Y_COUNT(0);
599 bfin_write_DMA2_Y_MODIFY(0);
600
601 /* Initialize the RX DMA channel registers */
602 bfin_write_DMA1_X_COUNT(0);
603 bfin_write_DMA1_X_MODIFY(4);
604 bfin_write_DMA1_Y_COUNT(0);
605 bfin_write_DMA1_Y_MODIFY(0);
606}
607
Alex Landau73f83182007-09-19 23:14:18 +0800608static void setup_mac_addr(u8 *mac_addr)
Bryan Wue190d6b2007-07-17 14:43:44 +0800609{
610 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
611 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
612
613 /* this depends on a little-endian machine */
614 bfin_write_EMAC_ADDRLO(addr_low);
615 bfin_write_EMAC_ADDRHI(addr_hi);
616}
617
Bryan Wu7ef0a7e2008-04-25 11:53:10 +0800618static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
Alex Landau73f83182007-09-19 23:14:18 +0800619{
620 struct sockaddr *addr = p;
621 if (netif_running(dev))
622 return -EBUSY;
623 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
624 setup_mac_addr(dev->dev_addr);
625 return 0;
626}
627
Barry Songfe92afe2010-05-17 17:19:40 -0700628#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
629#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
630
631static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
632 struct ifreq *ifr, int cmd)
633{
634 struct hwtstamp_config config;
635 struct bfin_mac_local *lp = netdev_priv(netdev);
636 u16 ptpctl;
637 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
638
639 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
640 return -EFAULT;
641
642 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
643 __func__, config.flags, config.tx_type, config.rx_filter);
644
645 /* reserved for future extensions */
646 if (config.flags)
647 return -EINVAL;
648
649 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
650 (config.tx_type != HWTSTAMP_TX_ON))
651 return -ERANGE;
652
653 ptpctl = bfin_read_EMAC_PTP_CTL();
654
655 switch (config.rx_filter) {
656 case HWTSTAMP_FILTER_NONE:
657 /*
658 * Dont allow any timestamping
659 */
660 ptpfv3 = 0xFFFFFFFF;
661 bfin_write_EMAC_PTP_FV3(ptpfv3);
662 break;
663 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
664 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
665 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
666 /*
667 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
668 * to enable all the field matches.
669 */
670 ptpctl &= ~0x1F00;
671 bfin_write_EMAC_PTP_CTL(ptpctl);
672 /*
673 * Keep the default values of the EMAC_PTP_FOFF register.
674 */
675 ptpfoff = 0x4A24170C;
676 bfin_write_EMAC_PTP_FOFF(ptpfoff);
677 /*
678 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
679 * registers.
680 */
681 ptpfv1 = 0x11040800;
682 bfin_write_EMAC_PTP_FV1(ptpfv1);
683 ptpfv2 = 0x0140013F;
684 bfin_write_EMAC_PTP_FV2(ptpfv2);
685 /*
686 * The default value (0xFFFC) allows the timestamping of both
687 * received Sync messages and Delay_Req messages.
688 */
689 ptpfv3 = 0xFFFFFFFC;
690 bfin_write_EMAC_PTP_FV3(ptpfv3);
691
692 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
693 break;
694 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
695 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
696 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
697 /* Clear all five comparison mask bits (bits[12:8]) in the
698 * EMAC_PTP_CTL register to enable all the field matches.
699 */
700 ptpctl &= ~0x1F00;
701 bfin_write_EMAC_PTP_CTL(ptpctl);
702 /*
703 * Keep the default values of the EMAC_PTP_FOFF register, except set
704 * the PTPCOF field to 0x2A.
705 */
706 ptpfoff = 0x2A24170C;
707 bfin_write_EMAC_PTP_FOFF(ptpfoff);
708 /*
709 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
710 * registers.
711 */
712 ptpfv1 = 0x11040800;
713 bfin_write_EMAC_PTP_FV1(ptpfv1);
714 ptpfv2 = 0x0140013F;
715 bfin_write_EMAC_PTP_FV2(ptpfv2);
716 /*
717 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
718 * the value to 0xFFF0.
719 */
720 ptpfv3 = 0xFFFFFFF0;
721 bfin_write_EMAC_PTP_FV3(ptpfv3);
722
723 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
724 break;
725 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
726 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
727 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
728 /*
729 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
730 * EFTM and PTPCM field comparison.
731 */
732 ptpctl &= ~0x1100;
733 bfin_write_EMAC_PTP_CTL(ptpctl);
734 /*
735 * Keep the default values of all the fields of the EMAC_PTP_FOFF
736 * register, except set the PTPCOF field to 0x0E.
737 */
738 ptpfoff = 0x0E24170C;
739 bfin_write_EMAC_PTP_FOFF(ptpfoff);
740 /*
741 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
742 * corresponds to PTP messages on the MAC layer.
743 */
744 ptpfv1 = 0x110488F7;
745 bfin_write_EMAC_PTP_FV1(ptpfv1);
746 ptpfv2 = 0x0140013F;
747 bfin_write_EMAC_PTP_FV2(ptpfv2);
748 /*
749 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
750 * messages, set the value to 0xFFF0.
751 */
752 ptpfv3 = 0xFFFFFFF0;
753 bfin_write_EMAC_PTP_FV3(ptpfv3);
754
755 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
756 break;
757 default:
758 return -ERANGE;
759 }
760
761 if (config.tx_type == HWTSTAMP_TX_OFF &&
762 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
763 ptpctl &= ~PTP_EN;
764 bfin_write_EMAC_PTP_CTL(ptpctl);
765
766 SSYNC();
767 } else {
768 ptpctl |= PTP_EN;
769 bfin_write_EMAC_PTP_CTL(ptpctl);
770
771 /*
772 * clear any existing timestamp
773 */
774 bfin_read_EMAC_PTP_RXSNAPLO();
775 bfin_read_EMAC_PTP_RXSNAPHI();
776
777 bfin_read_EMAC_PTP_TXSNAPLO();
778 bfin_read_EMAC_PTP_TXSNAPHI();
779
780 /*
781 * Set registers so that rollover occurs soon to test this.
782 */
783 bfin_write_EMAC_PTP_TIMELO(0x00000000);
784 bfin_write_EMAC_PTP_TIMEHI(0xFF800000);
785
786 SSYNC();
787
788 lp->compare.last_update = 0;
789 timecounter_init(&lp->clock,
790 &lp->cycles,
791 ktime_to_ns(ktime_get_real()));
792 timecompare_update(&lp->compare, 0);
793 }
794
795 lp->stamp_cfg = config;
796 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
797 -EFAULT : 0;
798}
799
800static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp)
801{
802 ktime_t sys = ktime_get_real();
803
804 pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n",
805 __func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec,
806 sys.tv.nsec, cmp->offset, cmp->skew);
807}
808
809static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
810{
811 struct bfin_mac_local *lp = netdev_priv(netdev);
Barry Songfe92afe2010-05-17 17:19:40 -0700812
Oliver Hartkopp2244d072010-08-17 08:59:14 +0000813 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
Barry Songfe92afe2010-05-17 17:19:40 -0700814 int timeout_cnt = MAX_TIMEOUT_CNT;
815
816 /* When doing time stamping, keep the connection to the socket
817 * a while longer
818 */
Oliver Hartkopp2244d072010-08-17 08:59:14 +0000819 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
Barry Songfe92afe2010-05-17 17:19:40 -0700820
821 /*
822 * The timestamping is done at the EMAC module's MII/RMII interface
823 * when the module sees the Start of Frame of an event message packet. This
824 * interface is the closest possible place to the physical Ethernet transmission
825 * medium, providing the best timing accuracy.
826 */
827 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
828 udelay(1);
829 if (timeout_cnt == 0)
830 printk(KERN_ERR DRV_NAME
831 ": fails to timestamp the TX packet\n");
832 else {
833 struct skb_shared_hwtstamps shhwtstamps;
834 u64 ns;
835 u64 regval;
836
837 regval = bfin_read_EMAC_PTP_TXSNAPLO();
838 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
839 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
840 ns = timecounter_cyc2time(&lp->clock,
841 regval);
842 timecompare_update(&lp->compare, ns);
843 shhwtstamps.hwtstamp = ns_to_ktime(ns);
844 shhwtstamps.syststamp =
845 timecompare_transform(&lp->compare, ns);
846 skb_tstamp_tx(skb, &shhwtstamps);
847
848 bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare);
849 }
850 }
851}
852
853static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
854{
855 struct bfin_mac_local *lp = netdev_priv(netdev);
856 u32 valid;
857 u64 regval, ns;
858 struct skb_shared_hwtstamps *shhwtstamps;
859
860 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
861 return;
862
863 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
864 if (!valid)
865 return;
866
867 shhwtstamps = skb_hwtstamps(skb);
868
869 regval = bfin_read_EMAC_PTP_RXSNAPLO();
870 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
871 ns = timecounter_cyc2time(&lp->clock, regval);
872 timecompare_update(&lp->compare, ns);
873 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
874 shhwtstamps->hwtstamp = ns_to_ktime(ns);
875 shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns);
876
877 bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare);
878}
879
880/*
881 * bfin_read_clock - read raw cycle counter (to be used by time counter)
882 */
883static cycle_t bfin_read_clock(const struct cyclecounter *tc)
884{
885 u64 stamp;
886
887 stamp = bfin_read_EMAC_PTP_TIMELO();
888 stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL;
889
890 return stamp;
891}
892
893#define PTP_CLK 25000000
894
895static void bfin_mac_hwtstamp_init(struct net_device *netdev)
896{
897 struct bfin_mac_local *lp = netdev_priv(netdev);
898 u64 append;
899
900 /* Initialize hardware timer */
901 append = PTP_CLK * (1ULL << 32);
902 do_div(append, get_sclk());
903 bfin_write_EMAC_PTP_ADDEND((u32)append);
904
905 memset(&lp->cycles, 0, sizeof(lp->cycles));
906 lp->cycles.read = bfin_read_clock;
907 lp->cycles.mask = CLOCKSOURCE_MASK(64);
908 lp->cycles.mult = 1000000000 / PTP_CLK;
909 lp->cycles.shift = 0;
910
911 /* Synchronize our NIC clock against system wall clock */
912 memset(&lp->compare, 0, sizeof(lp->compare));
913 lp->compare.source = &lp->clock;
914 lp->compare.target = ktime_get_real;
915 lp->compare.num_samples = 10;
916
917 /* Initialize hwstamp config */
918 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
919 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
920}
921
922#else
923# define bfin_mac_hwtstamp_is_none(cfg) 0
924# define bfin_mac_hwtstamp_init(dev)
925# define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
926# define bfin_rx_hwtstamp(dev, skb)
927# define bfin_tx_hwtstamp(dev, skb)
928#endif
929
Sonic Zhang4fcc3d32010-06-11 17:44:31 +0800930static inline void _tx_reclaim_skb(void)
Bryan Wue190d6b2007-07-17 14:43:44 +0800931{
Bryan Wue190d6b2007-07-17 14:43:44 +0800932 do {
933 tx_list_head->desc_a.config &= ~DMAEN;
934 tx_list_head->status.status_word = 0;
935 if (tx_list_head->skb) {
936 dev_kfree_skb(tx_list_head->skb);
937 tx_list_head->skb = NULL;
Bryan Wue190d6b2007-07-17 14:43:44 +0800938 }
939 tx_list_head = tx_list_head->next;
Bryan Wue190d6b2007-07-17 14:43:44 +0800940
Sonic Zhang4fcc3d32010-06-11 17:44:31 +0800941 } while (tx_list_head->status.status_word != 0);
942}
943
944static void tx_reclaim_skb(struct bfin_mac_local *lp)
945{
946 int timeout_cnt = MAX_TIMEOUT_CNT;
947
948 if (tx_list_head->status.status_word != 0)
949 _tx_reclaim_skb();
950
951 if (current_tx_ptr->next == tx_list_head) {
952 while (tx_list_head->status.status_word == 0) {
953 /* slow down polling to avoid too many queue stop. */
954 udelay(10);
955 /* reclaim skb if DMA is not running. */
956 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
957 break;
958 if (timeout_cnt-- < 0)
959 break;
960 }
961
962 if (timeout_cnt >= 0)
963 _tx_reclaim_skb();
964 else
965 netif_stop_queue(lp->ndev);
966 }
967
968 if (current_tx_ptr->next != tx_list_head &&
969 netif_queue_stopped(lp->ndev))
970 netif_wake_queue(lp->ndev);
971
972 if (tx_list_head != current_tx_ptr) {
973 /* shorten the timer interval if tx queue is stopped */
974 if (netif_queue_stopped(lp->ndev))
975 lp->tx_reclaim_timer.expires =
976 jiffies + (TX_RECLAIM_JIFFIES >> 4);
977 else
978 lp->tx_reclaim_timer.expires =
979 jiffies + TX_RECLAIM_JIFFIES;
980
981 mod_timer(&lp->tx_reclaim_timer,
982 lp->tx_reclaim_timer.expires);
983 }
984
985 return;
986}
987
988static void tx_reclaim_skb_timeout(unsigned long lp)
989{
990 tx_reclaim_skb((struct bfin_mac_local *)lp);
Bryan Wue190d6b2007-07-17 14:43:44 +0800991}
992
Bryan Wu7ef0a7e2008-04-25 11:53:10 +0800993static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
Bryan Wue190d6b2007-07-17 14:43:44 +0800994 struct net_device *dev)
995{
Sonic Zhang4fcc3d32010-06-11 17:44:31 +0800996 struct bfin_mac_local *lp = netdev_priv(dev);
Bryan Wua50c0c02008-07-27 22:45:04 +0800997 u16 *data;
Michael Hennerich015dac82009-05-29 03:41:15 +0000998 u32 data_align = (unsigned long)(skb->data) & 0x3;
Barry Songfe92afe2010-05-17 17:19:40 -0700999
Bryan Wue190d6b2007-07-17 14:43:44 +08001000 current_tx_ptr->skb = skb;
1001
Michael Hennerich015dac82009-05-29 03:41:15 +00001002 if (data_align == 0x2) {
1003 /* move skb->data to current_tx_ptr payload */
1004 data = (u16 *)(skb->data) - 1;
Barry Songfe92afe2010-05-17 17:19:40 -07001005 *data = (u16)(skb->len);
1006 /*
1007 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1008 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1009 * of this field are the length of the packet payload in bytes and the higher
1010 * 4 bits are the timestamping enable field.
1011 */
Oliver Hartkopp2244d072010-08-17 08:59:14 +00001012 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
Barry Songfe92afe2010-05-17 17:19:40 -07001013 *data |= 0x1000;
1014
Michael Hennerich015dac82009-05-29 03:41:15 +00001015 current_tx_ptr->desc_a.start_addr = (u32)data;
1016 /* this is important! */
1017 blackfin_dcache_flush_range((u32)data,
1018 (u32)((u8 *)data + skb->len + 4));
Bryan Wue190d6b2007-07-17 14:43:44 +08001019 } else {
Michael Hennerich015dac82009-05-29 03:41:15 +00001020 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
Barry Songfe92afe2010-05-17 17:19:40 -07001021 /* enable timestamping for the sent packet */
Oliver Hartkopp2244d072010-08-17 08:59:14 +00001022 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
Barry Songfe92afe2010-05-17 17:19:40 -07001023 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
Michael Hennerich015dac82009-05-29 03:41:15 +00001024 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1025 skb->len);
1026 current_tx_ptr->desc_a.start_addr =
1027 (u32)current_tx_ptr->packet;
Michael Hennerich015dac82009-05-29 03:41:15 +00001028 blackfin_dcache_flush_range(
1029 (u32)current_tx_ptr->packet,
1030 (u32)(current_tx_ptr->packet + skb->len + 2));
Bryan Wue190d6b2007-07-17 14:43:44 +08001031 }
1032
Sonic Zhang805a8ab2009-05-29 03:40:43 +00001033 /* make sure the internal data buffers in the core are drained
1034 * so that the DMA descriptors are completely written when the
1035 * DMA engine goes to fetch them below
1036 */
1037 SSYNC();
1038
Sonic Zhang4fcc3d32010-06-11 17:44:31 +08001039 /* always clear status buffer before start tx dma */
1040 current_tx_ptr->status.status_word = 0;
1041
Bryan Wue190d6b2007-07-17 14:43:44 +08001042 /* enable this packet's dma */
1043 current_tx_ptr->desc_a.config |= DMAEN;
1044
1045 /* tx dma is running, just return */
Michael Hennerich015dac82009-05-29 03:41:15 +00001046 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
Bryan Wue190d6b2007-07-17 14:43:44 +08001047 goto out;
1048
1049 /* tx dma is not running */
1050 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1051 /* dma enabled, read from memory, size is 6 */
1052 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1053 /* Turn on the EMAC tx */
1054 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1055
1056out:
Barry Songfe92afe2010-05-17 17:19:40 -07001057 bfin_tx_hwtstamp(dev, skb);
1058
Bryan Wue190d6b2007-07-17 14:43:44 +08001059 current_tx_ptr = current_tx_ptr->next;
Jeff Garzik09f75cd2007-10-03 17:41:50 -07001060 dev->stats.tx_packets++;
1061 dev->stats.tx_bytes += (skb->len);
Sonic Zhang4fcc3d32010-06-11 17:44:31 +08001062
1063 tx_reclaim_skb(lp);
1064
Patrick McHardy6ed10652009-06-23 06:03:08 +00001065 return NETDEV_TX_OK;
Bryan Wue190d6b2007-07-17 14:43:44 +08001066}
1067
Sonic Zhangad2864d2010-05-10 05:39:09 +00001068#define IP_HEADER_OFF 0
Peter Meerwaldec497b32010-05-17 17:20:50 -07001069#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1070 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1071
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001072static void bfin_mac_rx(struct net_device *dev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001073{
1074 struct sk_buff *skb, *new_skb;
Bryan Wue190d6b2007-07-17 14:43:44 +08001075 unsigned short len;
Barry Songfe92afe2010-05-17 17:19:40 -07001076 struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
Sonic Zhangad2864d2010-05-10 05:39:09 +00001077#if defined(BFIN_MAC_CSUM_OFFLOAD)
1078 unsigned int i;
1079 unsigned char fcs[ETH_FCS_LEN + 1];
1080#endif
Bryan Wue190d6b2007-07-17 14:43:44 +08001081
Peter Meerwaldec497b32010-05-17 17:20:50 -07001082 /* check if frame status word reports an error condition
1083 * we which case we simply drop the packet
1084 */
1085 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
1086 printk(KERN_NOTICE DRV_NAME
1087 ": rx: receive error - packet dropped\n");
1088 dev->stats.rx_dropped++;
1089 goto out;
1090 }
1091
Bryan Wue190d6b2007-07-17 14:43:44 +08001092 /* allocate a new skb for next time receive */
1093 skb = current_rx_ptr->skb;
Barry Songfe92afe2010-05-17 17:19:40 -07001094
Michael Hennerich015dac82009-05-29 03:41:15 +00001095 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
Bryan Wue190d6b2007-07-17 14:43:44 +08001096 if (!new_skb) {
1097 printk(KERN_NOTICE DRV_NAME
1098 ": rx: low on mem - packet dropped\n");
Jeff Garzik09f75cd2007-10-03 17:41:50 -07001099 dev->stats.rx_dropped++;
Bryan Wue190d6b2007-07-17 14:43:44 +08001100 goto out;
1101 }
1102 /* reserve 2 bytes for RXDWA padding */
Michael Hennerich015dac82009-05-29 03:41:15 +00001103 skb_reserve(new_skb, NET_IP_ALIGN);
Alexey Demin6e01d1a2008-01-30 16:52:27 +08001104 /* Invidate the data cache of skb->data range when it is write back
1105 * cache. It will prevent overwritting the new data from DMA
1106 */
1107 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1108 (unsigned long)new_skb->end);
1109
Sonic Zhangf6e1e4f2010-05-10 05:39:08 +00001110 current_rx_ptr->skb = new_skb;
1111 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1112
Bryan Wue190d6b2007-07-17 14:43:44 +08001113 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
Sonic Zhangad2864d2010-05-10 05:39:09 +00001114 /* Deduce Ethernet FCS length from Ethernet payload length */
1115 len -= ETH_FCS_LEN;
Bryan Wue190d6b2007-07-17 14:43:44 +08001116 skb_put(skb, len);
Bryan Wue190d6b2007-07-17 14:43:44 +08001117
Bryan Wue190d6b2007-07-17 14:43:44 +08001118 skb->protocol = eth_type_trans(skb, dev);
Barry Songfe92afe2010-05-17 17:19:40 -07001119
1120 bfin_rx_hwtstamp(dev, skb);
1121
Bryan Wue190d6b2007-07-17 14:43:44 +08001122#if defined(BFIN_MAC_CSUM_OFFLOAD)
Sonic Zhangad2864d2010-05-10 05:39:09 +00001123 /* Checksum offloading only works for IPv4 packets with the standard IP header
1124 * length of 20 bytes, because the blackfin MAC checksum calculation is
1125 * based on that assumption. We must NOT use the calculated checksum if our
1126 * IP version or header break that assumption.
1127 */
1128 if (skb->data[IP_HEADER_OFF] == 0x45) {
1129 skb->csum = current_rx_ptr->status.ip_payload_csum;
1130 /*
1131 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1132 * IP checksum is based on 16-bit one's complement algorithm.
1133 * To deduce a value from checksum is equal to add its inversion.
1134 * If the IP payload len is odd, the inversed FCS should also
1135 * begin from odd address and leave first byte zero.
1136 */
1137 if (skb->len % 2) {
1138 fcs[0] = 0;
1139 for (i = 0; i < ETH_FCS_LEN; i++)
1140 fcs[i + 1] = ~skb->data[skb->len + i];
1141 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1142 } else {
1143 for (i = 0; i < ETH_FCS_LEN; i++)
1144 fcs[i] = ~skb->data[skb->len + i];
1145 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1146 }
1147 skb->ip_summed = CHECKSUM_COMPLETE;
1148 }
Bryan Wue190d6b2007-07-17 14:43:44 +08001149#endif
1150
1151 netif_rx(skb);
Jeff Garzik09f75cd2007-10-03 17:41:50 -07001152 dev->stats.rx_packets++;
1153 dev->stats.rx_bytes += len;
Peter Meerwaldec497b32010-05-17 17:20:50 -07001154out:
Bryan Wue190d6b2007-07-17 14:43:44 +08001155 current_rx_ptr->status.status_word = 0x00000000;
1156 current_rx_ptr = current_rx_ptr->next;
Bryan Wue190d6b2007-07-17 14:43:44 +08001157}
1158
1159/* interrupt routine to handle rx and error signal */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001160static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
Bryan Wue190d6b2007-07-17 14:43:44 +08001161{
1162 struct net_device *dev = dev_id;
1163 int number = 0;
1164
1165get_one_packet:
1166 if (current_rx_ptr->status.status_word == 0) {
1167 /* no more new packet received */
1168 if (number == 0) {
1169 if (current_rx_ptr->next->status.status_word != 0) {
1170 current_rx_ptr = current_rx_ptr->next;
1171 goto real_rx;
1172 }
1173 }
1174 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1175 DMA_DONE | DMA_ERR);
1176 return IRQ_HANDLED;
1177 }
1178
1179real_rx:
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001180 bfin_mac_rx(dev);
Bryan Wue190d6b2007-07-17 14:43:44 +08001181 number++;
1182 goto get_one_packet;
1183}
1184
1185#ifdef CONFIG_NET_POLL_CONTROLLER
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001186static void bfin_mac_poll(struct net_device *dev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001187{
Sonic Zhang4fcc3d32010-06-11 17:44:31 +08001188 struct bfin_mac_local *lp = netdev_priv(dev);
1189
Bryan Wue190d6b2007-07-17 14:43:44 +08001190 disable_irq(IRQ_MAC_RX);
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001191 bfin_mac_interrupt(IRQ_MAC_RX, dev);
Sonic Zhang4fcc3d32010-06-11 17:44:31 +08001192 tx_reclaim_skb(lp);
Bryan Wue190d6b2007-07-17 14:43:44 +08001193 enable_irq(IRQ_MAC_RX);
1194}
1195#endif /* CONFIG_NET_POLL_CONTROLLER */
1196
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001197static void bfin_mac_disable(void)
Bryan Wue190d6b2007-07-17 14:43:44 +08001198{
1199 unsigned int opmode;
1200
1201 opmode = bfin_read_EMAC_OPMODE();
1202 opmode &= (~RE);
1203 opmode &= (~TE);
1204 /* Turn off the EMAC */
1205 bfin_write_EMAC_OPMODE(opmode);
1206}
1207
1208/*
1209 * Enable Interrupts, Receive, and Transmit
1210 */
Sonic Zhang02460d02010-06-11 10:44:22 +00001211static int bfin_mac_enable(struct phy_device *phydev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001212{
Mike Frysinger2bfa0f02010-05-10 05:39:13 +00001213 int ret;
Bryan Wue190d6b2007-07-17 14:43:44 +08001214 u32 opmode;
1215
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001216 pr_debug("%s: %s\n", DRV_NAME, __func__);
Bryan Wue190d6b2007-07-17 14:43:44 +08001217
1218 /* Set RX DMA */
1219 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1220 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1221
1222 /* Wait MII done */
Mike Frysinger2bfa0f02010-05-10 05:39:13 +00001223 ret = bfin_mdio_poll();
1224 if (ret)
1225 return ret;
Bryan Wue190d6b2007-07-17 14:43:44 +08001226
1227 /* We enable only RX here */
1228 /* ASTP : Enable Automatic Pad Stripping
1229 PR : Promiscuous Mode for test
1230 PSF : Receive frames with total length less than 64 bytes.
1231 FDMODE : Full Duplex Mode
1232 LB : Internal Loopback for test
1233 RE : Receiver Enable */
1234 opmode = bfin_read_EMAC_OPMODE();
1235 if (opmode & FDMODE)
1236 opmode |= PSF;
1237 else
1238 opmode |= DRO | DC | PSF;
1239 opmode |= RE;
1240
Sonic Zhang02460d02010-06-11 10:44:22 +00001241 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1242 opmode |= RMII; /* For Now only 100MBit are supported */
Michael Hennerich6893ff12008-01-30 16:52:25 +08001243#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2
Sonic Zhang02460d02010-06-11 10:44:22 +00001244 opmode |= TE;
Bryan Wue190d6b2007-07-17 14:43:44 +08001245#endif
Sonic Zhang02460d02010-06-11 10:44:22 +00001246 }
1247
Bryan Wue190d6b2007-07-17 14:43:44 +08001248 /* Turn on the EMAC rx */
1249 bfin_write_EMAC_OPMODE(opmode);
Mike Frysinger2bfa0f02010-05-10 05:39:13 +00001250
1251 return 0;
Bryan Wue190d6b2007-07-17 14:43:44 +08001252}
1253
1254/* Our watchdog timed out. Called by the networking layer */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001255static void bfin_mac_timeout(struct net_device *dev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001256{
Sonic Zhang4fcc3d32010-06-11 17:44:31 +08001257 struct bfin_mac_local *lp = netdev_priv(dev);
1258
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001259 pr_debug("%s: %s\n", dev->name, __func__);
Bryan Wue190d6b2007-07-17 14:43:44 +08001260
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001261 bfin_mac_disable();
Bryan Wue190d6b2007-07-17 14:43:44 +08001262
Sonic Zhang4fcc3d32010-06-11 17:44:31 +08001263 del_timer(&lp->tx_reclaim_timer);
1264
1265 /* reset tx queue and free skb */
1266 while (tx_list_head != current_tx_ptr) {
1267 tx_list_head->desc_a.config &= ~DMAEN;
1268 tx_list_head->status.status_word = 0;
1269 if (tx_list_head->skb) {
1270 dev_kfree_skb(tx_list_head->skb);
1271 tx_list_head->skb = NULL;
1272 }
1273 tx_list_head = tx_list_head->next;
1274 }
1275
1276 if (netif_queue_stopped(lp->ndev))
1277 netif_wake_queue(lp->ndev);
Bryan Wue190d6b2007-07-17 14:43:44 +08001278
Sonic Zhang02460d02010-06-11 10:44:22 +00001279 bfin_mac_enable(lp->phydev);
Bryan Wue190d6b2007-07-17 14:43:44 +08001280
1281 /* We can accept TX packets again */
Eric Dumazet1ae5dc32010-05-10 05:01:31 -07001282 dev->trans_start = jiffies; /* prevent tx timeout */
Bryan Wue190d6b2007-07-17 14:43:44 +08001283 netif_wake_queue(dev);
1284}
1285
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001286static void bfin_mac_multicast_hash(struct net_device *dev)
Aidan Williams775919b2008-01-30 16:52:23 +08001287{
1288 u32 emac_hashhi, emac_hashlo;
Jiri Pirko22bedad32010-04-01 21:22:57 +00001289 struct netdev_hw_addr *ha;
Aidan Williams775919b2008-01-30 16:52:23 +08001290 char *addrs;
Aidan Williams775919b2008-01-30 16:52:23 +08001291 u32 crc;
1292
1293 emac_hashhi = emac_hashlo = 0;
1294
Jiri Pirko22bedad32010-04-01 21:22:57 +00001295 netdev_for_each_mc_addr(ha, dev) {
1296 addrs = ha->addr;
Aidan Williams775919b2008-01-30 16:52:23 +08001297
1298 /* skip non-multicast addresses */
1299 if (!(*addrs & 1))
1300 continue;
1301
1302 crc = ether_crc(ETH_ALEN, addrs);
1303 crc >>= 26;
1304
1305 if (crc & 0x20)
1306 emac_hashhi |= 1 << (crc & 0x1f);
1307 else
1308 emac_hashlo |= 1 << (crc & 0x1f);
1309 }
1310
1311 bfin_write_EMAC_HASHHI(emac_hashhi);
1312 bfin_write_EMAC_HASHLO(emac_hashlo);
Aidan Williams775919b2008-01-30 16:52:23 +08001313}
1314
Bryan Wue190d6b2007-07-17 14:43:44 +08001315/*
Bryan Wue190d6b2007-07-17 14:43:44 +08001316 * This routine will, depending on the values passed to it,
1317 * either make it accept multicast packets, go into
1318 * promiscuous mode (for TCPDUMP and cousins) or accept
1319 * a select set of multicast packets
1320 */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001321static void bfin_mac_set_multicast_list(struct net_device *dev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001322{
1323 u32 sysctl;
1324
1325 if (dev->flags & IFF_PROMISC) {
1326 printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
1327 sysctl = bfin_read_EMAC_OPMODE();
Sonic Zhangc0da7762010-05-10 05:39:12 +00001328 sysctl |= PR;
Bryan Wue190d6b2007-07-17 14:43:44 +08001329 bfin_write_EMAC_OPMODE(sysctl);
Aidan Williams775919b2008-01-30 16:52:23 +08001330 } else if (dev->flags & IFF_ALLMULTI) {
Bryan Wue190d6b2007-07-17 14:43:44 +08001331 /* accept all multicast */
1332 sysctl = bfin_read_EMAC_OPMODE();
1333 sysctl |= PAM;
1334 bfin_write_EMAC_OPMODE(sysctl);
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00001335 } else if (!netdev_mc_empty(dev)) {
Aidan Williams775919b2008-01-30 16:52:23 +08001336 /* set up multicast hash table */
1337 sysctl = bfin_read_EMAC_OPMODE();
1338 sysctl |= HM;
1339 bfin_write_EMAC_OPMODE(sysctl);
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001340 bfin_mac_multicast_hash(dev);
Bryan Wue190d6b2007-07-17 14:43:44 +08001341 } else {
1342 /* clear promisc or multicast mode */
1343 sysctl = bfin_read_EMAC_OPMODE();
1344 sysctl &= ~(RAF | PAM);
1345 bfin_write_EMAC_OPMODE(sysctl);
1346 }
1347}
1348
Barry Songfe92afe2010-05-17 17:19:40 -07001349static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1350{
Sonic Zhang02460d02010-06-11 10:44:22 +00001351 struct bfin_mac_local *lp = netdev_priv(netdev);
1352
1353 if (!netif_running(netdev))
1354 return -EINVAL;
1355
Barry Songfe92afe2010-05-17 17:19:40 -07001356 switch (cmd) {
1357 case SIOCSHWTSTAMP:
1358 return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1359 default:
Sonic Zhang02460d02010-06-11 10:44:22 +00001360 if (lp->phydev)
1361 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1362 else
1363 return -EOPNOTSUPP;
Barry Songfe92afe2010-05-17 17:19:40 -07001364 }
1365}
1366
Bryan Wue190d6b2007-07-17 14:43:44 +08001367/*
1368 * this puts the device in an inactive state
1369 */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001370static void bfin_mac_shutdown(struct net_device *dev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001371{
1372 /* Turn off the EMAC */
1373 bfin_write_EMAC_OPMODE(0x00000000);
1374 /* Turn off the EMAC RX DMA */
1375 bfin_write_DMA1_CONFIG(0x0000);
1376 bfin_write_DMA2_CONFIG(0x0000);
1377}
1378
1379/*
1380 * Open and Initialize the interface
1381 *
1382 * Set up everything, reset the card, etc..
1383 */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001384static int bfin_mac_open(struct net_device *dev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001385{
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001386 struct bfin_mac_local *lp = netdev_priv(dev);
Mike Frysinger2bfa0f02010-05-10 05:39:13 +00001387 int ret;
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001388 pr_debug("%s: %s\n", dev->name, __func__);
Bryan Wue190d6b2007-07-17 14:43:44 +08001389
1390 /*
1391 * Check that the address is valid. If its not, refuse
1392 * to bring the device up. The user must specify an
1393 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1394 */
1395 if (!is_valid_ether_addr(dev->dev_addr)) {
1396 printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
1397 return -EINVAL;
1398 }
1399
1400 /* initial rx and tx list */
Mike Frysinger2bfa0f02010-05-10 05:39:13 +00001401 ret = desc_list_init();
1402 if (ret)
1403 return ret;
Bryan Wue190d6b2007-07-17 14:43:44 +08001404
Bryan Wu4ae5a3a2007-09-19 23:37:36 +08001405 phy_start(lp->phydev);
Vitja Makarov136492b2008-01-30 16:52:26 +08001406 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
Bryan Wue190d6b2007-07-17 14:43:44 +08001407 setup_system_regs(dev);
Michael Hennerichee02fee2008-07-27 22:45:05 +08001408 setup_mac_addr(dev->dev_addr);
Mike Frysinger2bfa0f02010-05-10 05:39:13 +00001409
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001410 bfin_mac_disable();
Sonic Zhang02460d02010-06-11 10:44:22 +00001411 ret = bfin_mac_enable(lp->phydev);
Mike Frysinger2bfa0f02010-05-10 05:39:13 +00001412 if (ret)
1413 return ret;
Bryan Wue190d6b2007-07-17 14:43:44 +08001414 pr_debug("hardware init finished\n");
Mike Frysinger2bfa0f02010-05-10 05:39:13 +00001415
Bryan Wue190d6b2007-07-17 14:43:44 +08001416 netif_start_queue(dev);
1417 netif_carrier_on(dev);
1418
1419 return 0;
1420}
1421
1422/*
Bryan Wue190d6b2007-07-17 14:43:44 +08001423 * this makes the board clean up everything that it can
1424 * and not talk to the outside world. Caused by
1425 * an 'ifconfig ethX down'
1426 */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001427static int bfin_mac_close(struct net_device *dev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001428{
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001429 struct bfin_mac_local *lp = netdev_priv(dev);
Harvey Harrisonb39d66a2008-08-20 16:52:04 -07001430 pr_debug("%s: %s\n", dev->name, __func__);
Bryan Wue190d6b2007-07-17 14:43:44 +08001431
1432 netif_stop_queue(dev);
1433 netif_carrier_off(dev);
1434
Bryan Wu4ae5a3a2007-09-19 23:37:36 +08001435 phy_stop(lp->phydev);
Vitja Makarov136492b2008-01-30 16:52:26 +08001436 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
Bryan Wu4ae5a3a2007-09-19 23:37:36 +08001437
Bryan Wue190d6b2007-07-17 14:43:44 +08001438 /* clear everything */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001439 bfin_mac_shutdown(dev);
Bryan Wue190d6b2007-07-17 14:43:44 +08001440
1441 /* free the rx/tx buffers */
1442 desc_list_free();
1443
1444 return 0;
1445}
1446
Mike Frysingerb63dc8f2009-05-26 20:55:33 -07001447static const struct net_device_ops bfin_mac_netdev_ops = {
1448 .ndo_open = bfin_mac_open,
1449 .ndo_stop = bfin_mac_close,
1450 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1451 .ndo_set_mac_address = bfin_mac_set_mac_address,
1452 .ndo_tx_timeout = bfin_mac_timeout,
1453 .ndo_set_multicast_list = bfin_mac_set_multicast_list,
Barry Songfe92afe2010-05-17 17:19:40 -07001454 .ndo_do_ioctl = bfin_mac_ioctl,
Mike Frysingerb63dc8f2009-05-26 20:55:33 -07001455 .ndo_validate_addr = eth_validate_addr,
1456 .ndo_change_mtu = eth_change_mtu,
1457#ifdef CONFIG_NET_POLL_CONTROLLER
1458 .ndo_poll_controller = bfin_mac_poll,
1459#endif
1460};
1461
Mike Frysingerd7b843d32008-07-27 22:45:03 +08001462static int __devinit bfin_mac_probe(struct platform_device *pdev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001463{
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001464 struct net_device *ndev;
1465 struct bfin_mac_local *lp;
Graf Yang080c8252009-05-29 03:41:48 +00001466 struct platform_device *pd;
Sonic Zhang02460d02010-06-11 10:44:22 +00001467 struct bfin_mii_bus_platform_data *mii_bus_data;
Graf Yang080c8252009-05-29 03:41:48 +00001468 int rc;
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001469
1470 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
1471 if (!ndev) {
1472 dev_err(&pdev->dev, "Cannot allocate net device!\n");
1473 return -ENOMEM;
1474 }
1475
1476 SET_NETDEV_DEV(ndev, &pdev->dev);
1477 platform_set_drvdata(pdev, ndev);
1478 lp = netdev_priv(ndev);
Sonic Zhang4fcc3d32010-06-11 17:44:31 +08001479 lp->ndev = ndev;
Bryan Wue190d6b2007-07-17 14:43:44 +08001480
1481 /* Grab the MAC address in the MAC */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001482 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1483 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
Bryan Wue190d6b2007-07-17 14:43:44 +08001484
1485 /* probe mac */
1486 /*todo: how to proble? which is revision_register */
1487 bfin_write_EMAC_ADDRLO(0x12345678);
1488 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001489 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1490 rc = -ENODEV;
1491 goto out_err_probe_mac;
Bryan Wue190d6b2007-07-17 14:43:44 +08001492 }
1493
Bryan Wue190d6b2007-07-17 14:43:44 +08001494
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001495 /*
1496 * Is it valid? (Did bootloader initialize it?)
1497 * Grab the MAC from the board somehow
1498 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1499 */
1500 if (!is_valid_ether_addr(ndev->dev_addr))
1501 bfin_get_ether_addr(ndev->dev_addr);
1502
Bryan Wue190d6b2007-07-17 14:43:44 +08001503 /* If still not valid, get a random one */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001504 if (!is_valid_ether_addr(ndev->dev_addr))
1505 random_ether_addr(ndev->dev_addr);
Bryan Wue190d6b2007-07-17 14:43:44 +08001506
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001507 setup_mac_addr(ndev->dev_addr);
Bryan Wue190d6b2007-07-17 14:43:44 +08001508
Graf Yang080c8252009-05-29 03:41:48 +00001509 if (!pdev->dev.platform_data) {
1510 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1511 rc = -ENODEV;
1512 goto out_err_probe_mac;
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001513 }
Graf Yang080c8252009-05-29 03:41:48 +00001514 pd = pdev->dev.platform_data;
1515 lp->mii_bus = platform_get_drvdata(pd);
Sonic Zhang0e995cd2010-05-10 05:39:14 +00001516 if (!lp->mii_bus) {
1517 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1518 rc = -ENODEV;
Sonic Zhang02460d02010-06-11 10:44:22 +00001519 goto out_err_probe_mac;
Sonic Zhang0e995cd2010-05-10 05:39:14 +00001520 }
Graf Yang080c8252009-05-29 03:41:48 +00001521 lp->mii_bus->priv = ndev;
Sonic Zhang02460d02010-06-11 10:44:22 +00001522 mii_bus_data = pd->dev.platform_data;
Bryan Wu4ae5a3a2007-09-19 23:37:36 +08001523
Sonic Zhang02460d02010-06-11 10:44:22 +00001524 rc = mii_probe(ndev, mii_bus_data->phy_mode);
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001525 if (rc) {
1526 dev_err(&pdev->dev, "MII Probe failed!\n");
1527 goto out_err_mii_probe;
1528 }
Bryan Wu4ae5a3a2007-09-19 23:37:36 +08001529
Bryan Wue190d6b2007-07-17 14:43:44 +08001530 /* Fill in the fields of the device structure with ethernet values. */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001531 ether_setup(ndev);
Bryan Wue190d6b2007-07-17 14:43:44 +08001532
Alexander Beregalov149da652009-04-14 18:30:24 +00001533 ndev->netdev_ops = &bfin_mac_netdev_ops;
Bryan Wu679dce32008-04-25 11:53:11 +08001534 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
Bryan Wue190d6b2007-07-17 14:43:44 +08001535
Sonic Zhang4fcc3d32010-06-11 17:44:31 +08001536 init_timer(&lp->tx_reclaim_timer);
1537 lp->tx_reclaim_timer.data = (unsigned long)lp;
1538 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1539
Bryan Wue190d6b2007-07-17 14:43:44 +08001540 spin_lock_init(&lp->lock);
1541
1542 /* now, enable interrupts */
1543 /* register irq handler */
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001544 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
Michael Hennerich91a455f2009-05-29 03:39:45 +00001545 IRQF_DISABLED, "EMAC_RX", ndev);
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001546 if (rc) {
1547 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1548 rc = -EBUSY;
1549 goto out_err_request_irq;
Bryan Wue190d6b2007-07-17 14:43:44 +08001550 }
1551
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001552 rc = register_netdev(ndev);
1553 if (rc) {
1554 dev_err(&pdev->dev, "Cannot register net device!\n");
1555 goto out_err_reg_ndev;
Bryan Wue190d6b2007-07-17 14:43:44 +08001556 }
1557
Barry Songfe92afe2010-05-17 17:19:40 -07001558 bfin_mac_hwtstamp_init(ndev);
1559
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001560 /* now, print out the card info, in a short format.. */
1561 dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
Bryan Wue190d6b2007-07-17 14:43:44 +08001562
1563 return 0;
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001564
1565out_err_reg_ndev:
1566 free_irq(IRQ_MAC_RX, ndev);
1567out_err_request_irq:
1568out_err_mii_probe:
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001569 mdiobus_unregister(lp->mii_bus);
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001570 mdiobus_free(lp->mii_bus);
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001571out_err_probe_mac:
1572 platform_set_drvdata(pdev, NULL);
1573 free_netdev(ndev);
1574
1575 return rc;
Bryan Wue190d6b2007-07-17 14:43:44 +08001576}
1577
Mike Frysingerd7b843d32008-07-27 22:45:03 +08001578static int __devexit bfin_mac_remove(struct platform_device *pdev)
Bryan Wue190d6b2007-07-17 14:43:44 +08001579{
1580 struct net_device *ndev = platform_get_drvdata(pdev);
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001581 struct bfin_mac_local *lp = netdev_priv(ndev);
Bryan Wue190d6b2007-07-17 14:43:44 +08001582
1583 platform_set_drvdata(pdev, NULL);
1584
Graf Yang080c8252009-05-29 03:41:48 +00001585 lp->mii_bus->priv = NULL;
Bryan Wu7ef0a7e2008-04-25 11:53:10 +08001586
Bryan Wue190d6b2007-07-17 14:43:44 +08001587 unregister_netdev(ndev);
1588
1589 free_irq(IRQ_MAC_RX, ndev);
1590
1591 free_netdev(ndev);
1592
Bryan Wue190d6b2007-07-17 14:43:44 +08001593 return 0;
1594}
1595
Bryan Wu496a34c2007-09-19 23:37:14 +08001596#ifdef CONFIG_PM
1597static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
Bryan Wue190d6b2007-07-17 14:43:44 +08001598{
Bryan Wu496a34c2007-09-19 23:37:14 +08001599 struct net_device *net_dev = platform_get_drvdata(pdev);
Michael Hennerich53fd3f22010-05-10 05:39:11 +00001600 struct bfin_mac_local *lp = netdev_priv(net_dev);
Bryan Wu496a34c2007-09-19 23:37:14 +08001601
Michael Hennerich53fd3f22010-05-10 05:39:11 +00001602 if (lp->wol) {
1603 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1604 bfin_write_EMAC_WKUP_CTL(MPKE);
1605 enable_irq_wake(IRQ_MAC_WAKEDET);
1606 } else {
1607 if (netif_running(net_dev))
1608 bfin_mac_close(net_dev);
1609 }
Bryan Wu496a34c2007-09-19 23:37:14 +08001610
Bryan Wue190d6b2007-07-17 14:43:44 +08001611 return 0;
1612}
1613
1614static int bfin_mac_resume(struct platform_device *pdev)
1615{
Bryan Wu496a34c2007-09-19 23:37:14 +08001616 struct net_device *net_dev = platform_get_drvdata(pdev);
Michael Hennerich53fd3f22010-05-10 05:39:11 +00001617 struct bfin_mac_local *lp = netdev_priv(net_dev);
Bryan Wu496a34c2007-09-19 23:37:14 +08001618
Michael Hennerich53fd3f22010-05-10 05:39:11 +00001619 if (lp->wol) {
1620 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1621 bfin_write_EMAC_WKUP_CTL(0);
1622 disable_irq_wake(IRQ_MAC_WAKEDET);
1623 } else {
1624 if (netif_running(net_dev))
1625 bfin_mac_open(net_dev);
1626 }
Bryan Wu496a34c2007-09-19 23:37:14 +08001627
Bryan Wue190d6b2007-07-17 14:43:44 +08001628 return 0;
1629}
Bryan Wu496a34c2007-09-19 23:37:14 +08001630#else
1631#define bfin_mac_suspend NULL
1632#define bfin_mac_resume NULL
1633#endif /* CONFIG_PM */
Bryan Wue190d6b2007-07-17 14:43:44 +08001634
Graf Yang080c8252009-05-29 03:41:48 +00001635static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1636{
1637 struct mii_bus *miibus;
Sonic Zhang02460d02010-06-11 10:44:22 +00001638 struct bfin_mii_bus_platform_data *mii_bus_pd;
1639 const unsigned short *pin_req;
Graf Yang080c8252009-05-29 03:41:48 +00001640 int rc, i;
1641
Sonic Zhang02460d02010-06-11 10:44:22 +00001642 mii_bus_pd = dev_get_platdata(&pdev->dev);
1643 if (!mii_bus_pd) {
1644 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1645 return -EINVAL;
1646 }
1647
Graf Yang080c8252009-05-29 03:41:48 +00001648 /*
1649 * We are setting up a network card,
1650 * so set the GPIO pins to Ethernet mode
1651 */
Sonic Zhang02460d02010-06-11 10:44:22 +00001652 pin_req = mii_bus_pd->mac_peripherals;
Graf Yang080c8252009-05-29 03:41:48 +00001653 rc = peripheral_request_list(pin_req, DRV_NAME);
1654 if (rc) {
1655 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1656 return rc;
1657 }
1658
1659 rc = -ENOMEM;
1660 miibus = mdiobus_alloc();
1661 if (miibus == NULL)
1662 goto out_err_alloc;
1663 miibus->read = bfin_mdiobus_read;
1664 miibus->write = bfin_mdiobus_write;
1665 miibus->reset = bfin_mdiobus_reset;
1666
1667 miibus->parent = &pdev->dev;
1668 miibus->name = "bfin_mii_bus";
Sonic Zhang02460d02010-06-11 10:44:22 +00001669 miibus->phy_mask = mii_bus_pd->phy_mask;
1670
Graf Yang080c8252009-05-29 03:41:48 +00001671 snprintf(miibus->id, MII_BUS_ID_SIZE, "0");
1672 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
Sonic Zhang02460d02010-06-11 10:44:22 +00001673 if (!miibus->irq)
1674 goto out_err_irq_alloc;
1675
1676 for (i = rc; i < PHY_MAX_ADDR; ++i)
Graf Yang080c8252009-05-29 03:41:48 +00001677 miibus->irq[i] = PHY_POLL;
1678
Sonic Zhang02460d02010-06-11 10:44:22 +00001679 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1680 if (rc != mii_bus_pd->phydev_number)
1681 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1682 mii_bus_pd->phydev_number);
1683 for (i = 0; i < rc; ++i) {
1684 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1685 if (phyaddr < PHY_MAX_ADDR)
1686 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1687 else
1688 dev_err(&pdev->dev,
1689 "Invalid PHY address %i for phydev %i\n",
1690 phyaddr, i);
1691 }
1692
Graf Yang080c8252009-05-29 03:41:48 +00001693 rc = mdiobus_register(miibus);
1694 if (rc) {
1695 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1696 goto out_err_mdiobus_register;
1697 }
1698
1699 platform_set_drvdata(pdev, miibus);
1700 return 0;
1701
1702out_err_mdiobus_register:
Denis Kirjanov7f267de2010-05-18 01:34:46 +00001703 kfree(miibus->irq);
Sonic Zhang02460d02010-06-11 10:44:22 +00001704out_err_irq_alloc:
Graf Yang080c8252009-05-29 03:41:48 +00001705 mdiobus_free(miibus);
1706out_err_alloc:
1707 peripheral_free_list(pin_req);
1708
1709 return rc;
1710}
1711
1712static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1713{
1714 struct mii_bus *miibus = platform_get_drvdata(pdev);
Sonic Zhang02460d02010-06-11 10:44:22 +00001715 struct bfin_mii_bus_platform_data *mii_bus_pd =
1716 dev_get_platdata(&pdev->dev);
1717
Graf Yang080c8252009-05-29 03:41:48 +00001718 platform_set_drvdata(pdev, NULL);
1719 mdiobus_unregister(miibus);
Denis Kirjanov7f267de2010-05-18 01:34:46 +00001720 kfree(miibus->irq);
Graf Yang080c8252009-05-29 03:41:48 +00001721 mdiobus_free(miibus);
Sonic Zhang02460d02010-06-11 10:44:22 +00001722 peripheral_free_list(mii_bus_pd->mac_peripherals);
1723
Graf Yang080c8252009-05-29 03:41:48 +00001724 return 0;
1725}
1726
1727static struct platform_driver bfin_mii_bus_driver = {
1728 .probe = bfin_mii_bus_probe,
1729 .remove = __devexit_p(bfin_mii_bus_remove),
1730 .driver = {
1731 .name = "bfin_mii_bus",
1732 .owner = THIS_MODULE,
1733 },
1734};
1735
Bryan Wue190d6b2007-07-17 14:43:44 +08001736static struct platform_driver bfin_mac_driver = {
1737 .probe = bfin_mac_probe,
Mike Frysingerd7b843d32008-07-27 22:45:03 +08001738 .remove = __devexit_p(bfin_mac_remove),
Bryan Wue190d6b2007-07-17 14:43:44 +08001739 .resume = bfin_mac_resume,
1740 .suspend = bfin_mac_suspend,
1741 .driver = {
Kay Sievers72abb462008-04-18 13:50:44 -07001742 .name = DRV_NAME,
1743 .owner = THIS_MODULE,
1744 },
Bryan Wue190d6b2007-07-17 14:43:44 +08001745};
1746
1747static int __init bfin_mac_init(void)
1748{
Graf Yang080c8252009-05-29 03:41:48 +00001749 int ret;
1750 ret = platform_driver_register(&bfin_mii_bus_driver);
1751 if (!ret)
1752 return platform_driver_register(&bfin_mac_driver);
1753 return -ENODEV;
Bryan Wue190d6b2007-07-17 14:43:44 +08001754}
1755
1756module_init(bfin_mac_init);
1757
1758static void __exit bfin_mac_cleanup(void)
1759{
1760 platform_driver_unregister(&bfin_mac_driver);
Graf Yang080c8252009-05-29 03:41:48 +00001761 platform_driver_unregister(&bfin_mii_bus_driver);
Bryan Wue190d6b2007-07-17 14:43:44 +08001762}
1763
1764module_exit(bfin_mac_cleanup);
Kay Sievers72abb462008-04-18 13:50:44 -07001765