Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
Carolyn Wyborny | 74cfb2e | 2014-02-25 17:58:57 -0800 | [diff] [blame] | 4 | Copyright(c) 2007-2014 Intel Corporation. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
Carolyn Wyborny | 74cfb2e | 2014-02-25 17:58:57 -0800 | [diff] [blame] | 16 | this program; if not, see <http://www.gnu.org/licenses/>. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 17 | |
| 18 | The full GNU General Public License is included in this distribution in |
| 19 | the file called "COPYING". |
| 20 | |
| 21 | Contact Information: |
| 22 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 23 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 24 | |
| 25 | *******************************************************************************/ |
| 26 | |
| 27 | /* e1000_82575 |
| 28 | * e1000_82576 |
| 29 | */ |
| 30 | |
Joe Perches | 82bbcde | 2011-10-21 20:04:09 +0000 | [diff] [blame] | 31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 32 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 33 | #include <linux/types.h> |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 34 | #include <linux/if_ether.h> |
Carolyn Wyborny | 441fc6f | 2012-12-07 03:00:30 +0000 | [diff] [blame] | 35 | #include <linux/i2c.h> |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 36 | |
| 37 | #include "e1000_mac.h" |
| 38 | #include "e1000_82575.h" |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 39 | #include "e1000_i210.h" |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 40 | |
| 41 | static s32 igb_get_invariants_82575(struct e1000_hw *); |
| 42 | static s32 igb_acquire_phy_82575(struct e1000_hw *); |
| 43 | static void igb_release_phy_82575(struct e1000_hw *); |
| 44 | static s32 igb_acquire_nvm_82575(struct e1000_hw *); |
| 45 | static void igb_release_nvm_82575(struct e1000_hw *); |
| 46 | static s32 igb_check_for_link_82575(struct e1000_hw *); |
| 47 | static s32 igb_get_cfg_done_82575(struct e1000_hw *); |
| 48 | static s32 igb_init_hw_82575(struct e1000_hw *); |
| 49 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); |
| 50 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 51 | static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); |
| 52 | static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 53 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 54 | static s32 igb_reset_hw_82580(struct e1000_hw *); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 55 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
Carolyn Wyborny | da02cde | 2012-03-04 03:26:26 +0000 | [diff] [blame] | 56 | static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); |
| 57 | static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 58 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 59 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 60 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); |
| 61 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *); |
| 62 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 63 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, |
| 64 | u16 *); |
| 65 | static s32 igb_get_phy_id_82575(struct e1000_hw *); |
| 66 | static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); |
| 67 | static bool igb_sgmii_active_82575(struct e1000_hw *); |
| 68 | static s32 igb_reset_init_script_82575(struct e1000_hw *); |
| 69 | static s32 igb_read_mac_addr_82575(struct e1000_hw *); |
Alexander Duyck | 009bc06 | 2009-07-23 18:08:35 +0000 | [diff] [blame] | 70 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); |
Alexander Duyck | 99870a7 | 2010-08-03 11:50:08 +0000 | [diff] [blame] | 71 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 72 | static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); |
| 73 | static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 74 | static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); |
| 75 | static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 76 | static const u16 e1000_82580_rxpbs_table[] = |
| 77 | { 36, 72, 144, 1, 2, 4, 8, 16, |
| 78 | 35, 70, 140 }; |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 79 | |
Nick Nunley | 4085f74 | 2010-07-26 13:15:06 +0000 | [diff] [blame] | 80 | /** |
| 81 | * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO |
| 82 | * @hw: pointer to the HW structure |
| 83 | * |
| 84 | * Called to determine if the I2C pins are being used for I2C or as an |
| 85 | * external MDIO interface since the two options are mutually exclusive. |
| 86 | **/ |
| 87 | static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) |
| 88 | { |
| 89 | u32 reg = 0; |
| 90 | bool ext_mdio = false; |
| 91 | |
| 92 | switch (hw->mac.type) { |
| 93 | case e1000_82575: |
| 94 | case e1000_82576: |
| 95 | reg = rd32(E1000_MDIC); |
| 96 | ext_mdio = !!(reg & E1000_MDIC_DEST); |
| 97 | break; |
| 98 | case e1000_82580: |
| 99 | case e1000_i350: |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 100 | case e1000_i354: |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 101 | case e1000_i210: |
| 102 | case e1000_i211: |
Nick Nunley | 4085f74 | 2010-07-26 13:15:06 +0000 | [diff] [blame] | 103 | reg = rd32(E1000_MDICNFG); |
| 104 | ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); |
| 105 | break; |
| 106 | default: |
| 107 | break; |
| 108 | } |
| 109 | return ext_mdio; |
| 110 | } |
| 111 | |
Akeem G. Abodunrin | 73bfcd9 | 2013-01-29 10:14:55 +0000 | [diff] [blame] | 112 | /** |
Carolyn Wyborny | 2bdfc4e | 2013-10-17 05:23:01 +0000 | [diff] [blame] | 113 | * igb_check_for_link_media_swap - Check which M88E1112 interface linked |
| 114 | * @hw: pointer to the HW structure |
| 115 | * |
| 116 | * Poll the M88E1112 interfaces to see which interface achieved link. |
| 117 | */ |
| 118 | static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) |
| 119 | { |
| 120 | struct e1000_phy_info *phy = &hw->phy; |
| 121 | s32 ret_val; |
| 122 | u16 data; |
| 123 | u8 port = 0; |
| 124 | |
| 125 | /* Check the copper medium. */ |
| 126 | ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); |
| 127 | if (ret_val) |
| 128 | return ret_val; |
| 129 | |
| 130 | ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); |
| 131 | if (ret_val) |
| 132 | return ret_val; |
| 133 | |
| 134 | if (data & E1000_M88E1112_STATUS_LINK) |
| 135 | port = E1000_MEDIA_PORT_COPPER; |
| 136 | |
| 137 | /* Check the other medium. */ |
| 138 | ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); |
| 139 | if (ret_val) |
| 140 | return ret_val; |
| 141 | |
| 142 | ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); |
| 143 | if (ret_val) |
| 144 | return ret_val; |
| 145 | |
| 146 | /* reset page to 0 */ |
| 147 | ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); |
| 148 | if (ret_val) |
| 149 | return ret_val; |
| 150 | |
| 151 | if (data & E1000_M88E1112_STATUS_LINK) |
| 152 | port = E1000_MEDIA_PORT_OTHER; |
| 153 | |
| 154 | /* Determine if a swap needs to happen. */ |
| 155 | if (port && (hw->dev_spec._82575.media_port != port)) { |
| 156 | hw->dev_spec._82575.media_port = port; |
| 157 | hw->dev_spec._82575.media_changed = true; |
| 158 | } else { |
| 159 | ret_val = igb_check_for_link_82575(hw); |
| 160 | } |
| 161 | |
| 162 | return E1000_SUCCESS; |
| 163 | } |
| 164 | |
| 165 | /** |
Akeem G. Abodunrin | 73bfcd9 | 2013-01-29 10:14:55 +0000 | [diff] [blame] | 166 | * igb_init_phy_params_82575 - Init PHY func ptrs. |
| 167 | * @hw: pointer to the HW structure |
| 168 | **/ |
| 169 | static s32 igb_init_phy_params_82575(struct e1000_hw *hw) |
| 170 | { |
| 171 | struct e1000_phy_info *phy = &hw->phy; |
| 172 | s32 ret_val = 0; |
| 173 | u32 ctrl_ext; |
| 174 | |
| 175 | if (hw->phy.media_type != e1000_media_type_copper) { |
| 176 | phy->type = e1000_phy_none; |
| 177 | goto out; |
| 178 | } |
| 179 | |
| 180 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 181 | phy->reset_delay_us = 100; |
| 182 | |
| 183 | ctrl_ext = rd32(E1000_CTRL_EXT); |
| 184 | |
| 185 | if (igb_sgmii_active_82575(hw)) { |
| 186 | phy->ops.reset = igb_phy_hw_reset_sgmii_82575; |
| 187 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
| 188 | } else { |
| 189 | phy->ops.reset = igb_phy_hw_reset; |
| 190 | ctrl_ext &= ~E1000_CTRL_I2C_ENA; |
| 191 | } |
| 192 | |
| 193 | wr32(E1000_CTRL_EXT, ctrl_ext); |
| 194 | igb_reset_mdicnfg_82580(hw); |
| 195 | |
| 196 | if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { |
| 197 | phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; |
| 198 | phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; |
| 199 | } else { |
| 200 | switch (hw->mac.type) { |
| 201 | case e1000_82580: |
| 202 | case e1000_i350: |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 203 | case e1000_i354: |
Akeem G. Abodunrin | 73bfcd9 | 2013-01-29 10:14:55 +0000 | [diff] [blame] | 204 | phy->ops.read_reg = igb_read_phy_reg_82580; |
| 205 | phy->ops.write_reg = igb_write_phy_reg_82580; |
| 206 | break; |
| 207 | case e1000_i210: |
| 208 | case e1000_i211: |
| 209 | phy->ops.read_reg = igb_read_phy_reg_gs40g; |
| 210 | phy->ops.write_reg = igb_write_phy_reg_gs40g; |
| 211 | break; |
| 212 | default: |
| 213 | phy->ops.read_reg = igb_read_phy_reg_igp; |
| 214 | phy->ops.write_reg = igb_write_phy_reg_igp; |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | /* set lan id */ |
| 219 | hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> |
| 220 | E1000_STATUS_FUNC_SHIFT; |
| 221 | |
| 222 | /* Set phy->phy_addr and phy->id. */ |
| 223 | ret_val = igb_get_phy_id_82575(hw); |
| 224 | if (ret_val) |
| 225 | return ret_val; |
| 226 | |
| 227 | /* Verify phy id and set remaining function pointers */ |
| 228 | switch (phy->id) { |
Akeem G Abodunrin | 99af472 | 2013-08-28 02:22:58 +0000 | [diff] [blame] | 229 | case M88E1543_E_PHY_ID: |
Akeem G. Abodunrin | 73bfcd9 | 2013-01-29 10:14:55 +0000 | [diff] [blame] | 230 | case I347AT4_E_PHY_ID: |
| 231 | case M88E1112_E_PHY_ID: |
| 232 | case M88E1111_I_PHY_ID: |
| 233 | phy->type = e1000_phy_m88; |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 234 | phy->ops.check_polarity = igb_check_polarity_m88; |
Akeem G. Abodunrin | 73bfcd9 | 2013-01-29 10:14:55 +0000 | [diff] [blame] | 235 | phy->ops.get_phy_info = igb_get_phy_info_m88; |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 236 | if (phy->id != M88E1111_I_PHY_ID) |
Akeem G. Abodunrin | 73bfcd9 | 2013-01-29 10:14:55 +0000 | [diff] [blame] | 237 | phy->ops.get_cable_length = |
| 238 | igb_get_cable_length_m88_gen2; |
| 239 | else |
| 240 | phy->ops.get_cable_length = igb_get_cable_length_m88; |
| 241 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; |
Carolyn Wyborny | 2bdfc4e | 2013-10-17 05:23:01 +0000 | [diff] [blame] | 242 | /* Check if this PHY is confgured for media swap. */ |
| 243 | if (phy->id == M88E1112_E_PHY_ID) { |
| 244 | u16 data; |
| 245 | |
| 246 | ret_val = phy->ops.write_reg(hw, |
| 247 | E1000_M88E1112_PAGE_ADDR, |
| 248 | 2); |
| 249 | if (ret_val) |
| 250 | goto out; |
| 251 | |
| 252 | ret_val = phy->ops.read_reg(hw, |
| 253 | E1000_M88E1112_MAC_CTRL_1, |
| 254 | &data); |
| 255 | if (ret_val) |
| 256 | goto out; |
| 257 | |
| 258 | data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> |
| 259 | E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; |
| 260 | if (data == E1000_M88E1112_AUTO_COPPER_SGMII || |
| 261 | data == E1000_M88E1112_AUTO_COPPER_BASEX) |
| 262 | hw->mac.ops.check_for_link = |
| 263 | igb_check_for_link_media_swap; |
| 264 | } |
Akeem G. Abodunrin | 73bfcd9 | 2013-01-29 10:14:55 +0000 | [diff] [blame] | 265 | break; |
| 266 | case IGP03E1000_E_PHY_ID: |
| 267 | phy->type = e1000_phy_igp_3; |
| 268 | phy->ops.get_phy_info = igb_get_phy_info_igp; |
| 269 | phy->ops.get_cable_length = igb_get_cable_length_igp_2; |
| 270 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; |
| 271 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; |
| 272 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; |
| 273 | break; |
| 274 | case I82580_I_PHY_ID: |
| 275 | case I350_I_PHY_ID: |
| 276 | phy->type = e1000_phy_82580; |
| 277 | phy->ops.force_speed_duplex = |
| 278 | igb_phy_force_speed_duplex_82580; |
| 279 | phy->ops.get_cable_length = igb_get_cable_length_82580; |
| 280 | phy->ops.get_phy_info = igb_get_phy_info_82580; |
| 281 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; |
| 282 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; |
| 283 | break; |
| 284 | case I210_I_PHY_ID: |
| 285 | phy->type = e1000_phy_i210; |
| 286 | phy->ops.check_polarity = igb_check_polarity_m88; |
| 287 | phy->ops.get_phy_info = igb_get_phy_info_m88; |
| 288 | phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; |
| 289 | phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; |
| 290 | phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; |
| 291 | phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; |
| 292 | break; |
| 293 | default: |
| 294 | ret_val = -E1000_ERR_PHY; |
| 295 | goto out; |
| 296 | } |
| 297 | |
| 298 | out: |
| 299 | return ret_val; |
| 300 | } |
| 301 | |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 302 | /** |
| 303 | * igb_init_nvm_params_82575 - Init NVM func ptrs. |
| 304 | * @hw: pointer to the HW structure |
| 305 | **/ |
Akeem G. Abodunrin | c826892 | 2013-02-16 07:09:06 +0000 | [diff] [blame] | 306 | static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 307 | { |
| 308 | struct e1000_nvm_info *nvm = &hw->nvm; |
| 309 | u32 eecd = rd32(E1000_EECD); |
| 310 | u16 size; |
| 311 | |
| 312 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
| 313 | E1000_EECD_SIZE_EX_SHIFT); |
Carolyn Wyborny | 5a823d8 | 2013-07-16 19:17:32 +0000 | [diff] [blame] | 314 | |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 315 | /* Added to a constant, "size" becomes the left-shift value |
| 316 | * for setting word_size. |
| 317 | */ |
| 318 | size += NVM_WORD_SIZE_BASE_SHIFT; |
| 319 | |
| 320 | /* Just in case size is out of range, cap it to the largest |
| 321 | * EEPROM size supported |
| 322 | */ |
| 323 | if (size > 15) |
| 324 | size = 15; |
| 325 | |
| 326 | nvm->word_size = 1 << size; |
Carolyn Wyborny | 5a823d8 | 2013-07-16 19:17:32 +0000 | [diff] [blame] | 327 | nvm->opcode_bits = 8; |
| 328 | nvm->delay_usec = 1; |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 329 | |
Carolyn Wyborny | 5a823d8 | 2013-07-16 19:17:32 +0000 | [diff] [blame] | 330 | switch (nvm->override) { |
| 331 | case e1000_nvm_override_spi_large: |
| 332 | nvm->page_size = 32; |
| 333 | nvm->address_bits = 16; |
| 334 | break; |
| 335 | case e1000_nvm_override_spi_small: |
| 336 | nvm->page_size = 8; |
| 337 | nvm->address_bits = 8; |
| 338 | break; |
| 339 | default: |
| 340 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; |
| 341 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? |
| 342 | 16 : 8; |
| 343 | break; |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 344 | } |
Carolyn Wyborny | 5a823d8 | 2013-07-16 19:17:32 +0000 | [diff] [blame] | 345 | if (nvm->word_size == (1 << 15)) |
| 346 | nvm->page_size = 128; |
| 347 | |
| 348 | nvm->type = e1000_nvm_eeprom_spi; |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 349 | |
| 350 | /* NVM Function Pointers */ |
Carolyn Wyborny | 5a823d8 | 2013-07-16 19:17:32 +0000 | [diff] [blame] | 351 | nvm->ops.acquire = igb_acquire_nvm_82575; |
| 352 | nvm->ops.release = igb_release_nvm_82575; |
| 353 | nvm->ops.write = igb_write_nvm_spi; |
| 354 | nvm->ops.validate = igb_validate_nvm_checksum; |
| 355 | nvm->ops.update = igb_update_nvm_checksum; |
| 356 | if (nvm->word_size < (1 << 15)) |
| 357 | nvm->ops.read = igb_read_nvm_eerd; |
| 358 | else |
| 359 | nvm->ops.read = igb_read_nvm_spi; |
| 360 | |
| 361 | /* override generic family function pointers for specific descendants */ |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 362 | switch (hw->mac.type) { |
| 363 | case e1000_82580: |
| 364 | nvm->ops.validate = igb_validate_nvm_checksum_82580; |
| 365 | nvm->ops.update = igb_update_nvm_checksum_82580; |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 366 | break; |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 367 | case e1000_i354: |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 368 | case e1000_i350: |
| 369 | nvm->ops.validate = igb_validate_nvm_checksum_i350; |
| 370 | nvm->ops.update = igb_update_nvm_checksum_i350; |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 371 | break; |
| 372 | default: |
Akeem G. Abodunrin | 56d8c27 | 2013-01-29 10:15:00 +0000 | [diff] [blame] | 373 | break; |
| 374 | } |
| 375 | |
| 376 | return 0; |
| 377 | } |
| 378 | |
Akeem G. Abodunrin | a1bf1f4 | 2013-01-29 10:15:05 +0000 | [diff] [blame] | 379 | /** |
| 380 | * igb_init_mac_params_82575 - Init MAC func ptrs. |
| 381 | * @hw: pointer to the HW structure |
| 382 | **/ |
| 383 | static s32 igb_init_mac_params_82575(struct e1000_hw *hw) |
| 384 | { |
| 385 | struct e1000_mac_info *mac = &hw->mac; |
| 386 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
| 387 | |
| 388 | /* Set mta register count */ |
| 389 | mac->mta_reg_count = 128; |
| 390 | /* Set rar entry count */ |
| 391 | switch (mac->type) { |
| 392 | case e1000_82576: |
| 393 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; |
| 394 | break; |
| 395 | case e1000_82580: |
| 396 | mac->rar_entry_count = E1000_RAR_ENTRIES_82580; |
| 397 | break; |
| 398 | case e1000_i350: |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 399 | case e1000_i354: |
Akeem G. Abodunrin | a1bf1f4 | 2013-01-29 10:15:05 +0000 | [diff] [blame] | 400 | mac->rar_entry_count = E1000_RAR_ENTRIES_I350; |
| 401 | break; |
| 402 | default: |
| 403 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; |
| 404 | break; |
| 405 | } |
| 406 | /* reset */ |
| 407 | if (mac->type >= e1000_82580) |
| 408 | mac->ops.reset_hw = igb_reset_hw_82580; |
| 409 | else |
| 410 | mac->ops.reset_hw = igb_reset_hw_82575; |
| 411 | |
| 412 | if (mac->type >= e1000_i210) { |
| 413 | mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; |
| 414 | mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; |
| 415 | |
| 416 | } else { |
| 417 | mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; |
| 418 | mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; |
| 419 | } |
| 420 | |
| 421 | /* Set if part includes ASF firmware */ |
| 422 | mac->asf_firmware_present = true; |
| 423 | /* Set if manageability features are enabled. */ |
| 424 | mac->arc_subsystem_valid = |
| 425 | (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) |
| 426 | ? true : false; |
| 427 | /* enable EEE on i350 parts and later parts */ |
| 428 | if (mac->type >= e1000_i350) |
| 429 | dev_spec->eee_disable = false; |
| 430 | else |
| 431 | dev_spec->eee_disable = true; |
Matthew Vick | d44e7a9 | 2013-03-22 07:34:20 +0000 | [diff] [blame] | 432 | /* Allow a single clear of the SW semaphore on I210 and newer */ |
| 433 | if (mac->type >= e1000_i210) |
| 434 | dev_spec->clear_semaphore_once = true; |
Akeem G. Abodunrin | a1bf1f4 | 2013-01-29 10:15:05 +0000 | [diff] [blame] | 435 | /* physical interface link setup */ |
| 436 | mac->ops.setup_physical_interface = |
| 437 | (hw->phy.media_type == e1000_media_type_copper) |
| 438 | ? igb_setup_copper_link_82575 |
| 439 | : igb_setup_serdes_link_82575; |
| 440 | |
Carolyn Wyborny | 56cec24 | 2013-10-17 05:36:26 +0000 | [diff] [blame] | 441 | if (mac->type == e1000_82580) { |
| 442 | switch (hw->device_id) { |
| 443 | /* feature not supported on these id's */ |
| 444 | case E1000_DEV_ID_DH89XXCC_SGMII: |
| 445 | case E1000_DEV_ID_DH89XXCC_SERDES: |
| 446 | case E1000_DEV_ID_DH89XXCC_BACKPLANE: |
| 447 | case E1000_DEV_ID_DH89XXCC_SFP: |
| 448 | break; |
| 449 | default: |
| 450 | hw->dev_spec._82575.mas_capable = true; |
| 451 | break; |
| 452 | } |
| 453 | } |
Akeem G. Abodunrin | a1bf1f4 | 2013-01-29 10:15:05 +0000 | [diff] [blame] | 454 | return 0; |
| 455 | } |
| 456 | |
Akeem G. Abodunrin | 641ac5c | 2013-04-24 16:54:50 +0000 | [diff] [blame] | 457 | /** |
| 458 | * igb_set_sfp_media_type_82575 - derives SFP module media type. |
| 459 | * @hw: pointer to the HW structure |
| 460 | * |
| 461 | * The media type is chosen based on SFP module. |
| 462 | * compatibility flags retrieved from SFP ID EEPROM. |
| 463 | **/ |
| 464 | static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) |
| 465 | { |
| 466 | s32 ret_val = E1000_ERR_CONFIG; |
| 467 | u32 ctrl_ext = 0; |
| 468 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
| 469 | struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; |
| 470 | u8 tranceiver_type = 0; |
| 471 | s32 timeout = 3; |
| 472 | |
| 473 | /* Turn I2C interface ON and power on sfp cage */ |
| 474 | ctrl_ext = rd32(E1000_CTRL_EXT); |
| 475 | ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; |
| 476 | wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); |
| 477 | |
| 478 | wrfl(); |
| 479 | |
| 480 | /* Read SFP module data */ |
| 481 | while (timeout) { |
| 482 | ret_val = igb_read_sfp_data_byte(hw, |
| 483 | E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), |
| 484 | &tranceiver_type); |
| 485 | if (ret_val == 0) |
| 486 | break; |
| 487 | msleep(100); |
| 488 | timeout--; |
| 489 | } |
| 490 | if (ret_val != 0) |
| 491 | goto out; |
| 492 | |
| 493 | ret_val = igb_read_sfp_data_byte(hw, |
| 494 | E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), |
| 495 | (u8 *)eth_flags); |
| 496 | if (ret_val != 0) |
| 497 | goto out; |
| 498 | |
| 499 | /* Check if there is some SFP module plugged and powered */ |
| 500 | if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || |
| 501 | (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { |
| 502 | dev_spec->module_plugged = true; |
| 503 | if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { |
| 504 | hw->phy.media_type = e1000_media_type_internal_serdes; |
| 505 | } else if (eth_flags->e100_base_fx) { |
| 506 | dev_spec->sgmii_active = true; |
| 507 | hw->phy.media_type = e1000_media_type_internal_serdes; |
| 508 | } else if (eth_flags->e1000_base_t) { |
| 509 | dev_spec->sgmii_active = true; |
| 510 | hw->phy.media_type = e1000_media_type_copper; |
| 511 | } else { |
| 512 | hw->phy.media_type = e1000_media_type_unknown; |
| 513 | hw_dbg("PHY module has not been recognized\n"); |
| 514 | goto out; |
| 515 | } |
| 516 | } else { |
| 517 | hw->phy.media_type = e1000_media_type_unknown; |
| 518 | } |
| 519 | ret_val = 0; |
| 520 | out: |
| 521 | /* Restore I2C interface setting */ |
| 522 | wr32(E1000_CTRL_EXT, ctrl_ext); |
| 523 | return ret_val; |
| 524 | } |
| 525 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 526 | static s32 igb_get_invariants_82575(struct e1000_hw *hw) |
| 527 | { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 528 | struct e1000_mac_info *mac = &hw->mac; |
Alexander Duyck | c1889bf | 2009-02-06 23:16:45 +0000 | [diff] [blame] | 529 | struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 530 | s32 ret_val; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 531 | u32 ctrl_ext = 0; |
Akeem G. Abodunrin | 641ac5c | 2013-04-24 16:54:50 +0000 | [diff] [blame] | 532 | u32 link_mode = 0; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 533 | |
| 534 | switch (hw->device_id) { |
| 535 | case E1000_DEV_ID_82575EB_COPPER: |
| 536 | case E1000_DEV_ID_82575EB_FIBER_SERDES: |
| 537 | case E1000_DEV_ID_82575GB_QUAD_COPPER: |
| 538 | mac->type = e1000_82575; |
| 539 | break; |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 540 | case E1000_DEV_ID_82576: |
Alexander Duyck | 9eb2341 | 2009-03-13 20:42:15 +0000 | [diff] [blame] | 541 | case E1000_DEV_ID_82576_NS: |
Alexander Duyck | 747d49b | 2009-10-05 06:33:27 +0000 | [diff] [blame] | 542 | case E1000_DEV_ID_82576_NS_SERDES: |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 543 | case E1000_DEV_ID_82576_FIBER: |
| 544 | case E1000_DEV_ID_82576_SERDES: |
Alexander Duyck | c8ea5ea | 2009-03-13 20:42:35 +0000 | [diff] [blame] | 545 | case E1000_DEV_ID_82576_QUAD_COPPER: |
Carolyn Wyborny | b894fa2 | 2010-03-19 06:07:48 +0000 | [diff] [blame] | 546 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
Alexander Duyck | 4703bf7 | 2009-07-23 18:09:48 +0000 | [diff] [blame] | 547 | case E1000_DEV_ID_82576_SERDES_QUAD: |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 548 | mac->type = e1000_82576; |
| 549 | break; |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 550 | case E1000_DEV_ID_82580_COPPER: |
| 551 | case E1000_DEV_ID_82580_FIBER: |
Carolyn Wyborny | 6493d24 | 2011-01-14 05:33:46 +0000 | [diff] [blame] | 552 | case E1000_DEV_ID_82580_QUAD_FIBER: |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 553 | case E1000_DEV_ID_82580_SERDES: |
| 554 | case E1000_DEV_ID_82580_SGMII: |
| 555 | case E1000_DEV_ID_82580_COPPER_DUAL: |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 556 | case E1000_DEV_ID_DH89XXCC_SGMII: |
| 557 | case E1000_DEV_ID_DH89XXCC_SERDES: |
Gasparakis, Joseph | 1b5dda3 | 2010-12-09 01:41:01 +0000 | [diff] [blame] | 558 | case E1000_DEV_ID_DH89XXCC_BACKPLANE: |
| 559 | case E1000_DEV_ID_DH89XXCC_SFP: |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 560 | mac->type = e1000_82580; |
| 561 | break; |
Alexander Duyck | d2ba2ed | 2010-03-22 14:08:06 +0000 | [diff] [blame] | 562 | case E1000_DEV_ID_I350_COPPER: |
| 563 | case E1000_DEV_ID_I350_FIBER: |
| 564 | case E1000_DEV_ID_I350_SERDES: |
| 565 | case E1000_DEV_ID_I350_SGMII: |
| 566 | mac->type = e1000_i350; |
| 567 | break; |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 568 | case E1000_DEV_ID_I210_COPPER: |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 569 | case E1000_DEV_ID_I210_FIBER: |
| 570 | case E1000_DEV_ID_I210_SERDES: |
| 571 | case E1000_DEV_ID_I210_SGMII: |
Carolyn Wyborny | 53b87ce | 2013-07-16 19:18:36 +0000 | [diff] [blame] | 572 | case E1000_DEV_ID_I210_COPPER_FLASHLESS: |
| 573 | case E1000_DEV_ID_I210_SERDES_FLASHLESS: |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 574 | mac->type = e1000_i210; |
| 575 | break; |
| 576 | case E1000_DEV_ID_I211_COPPER: |
| 577 | mac->type = e1000_i211; |
| 578 | break; |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 579 | case E1000_DEV_ID_I354_BACKPLANE_1GBPS: |
| 580 | case E1000_DEV_ID_I354_SGMII: |
| 581 | case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: |
| 582 | mac->type = e1000_i354; |
| 583 | break; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 584 | default: |
| 585 | return -E1000_ERR_MAC_INIT; |
| 586 | break; |
| 587 | } |
| 588 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 589 | /* Set media type */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 590 | /* The 82575 uses bits 22:23 for link mode. The mode can be changed |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 591 | * based on the EEPROM. We cannot rely upon device ID. There |
| 592 | * is no distinguishable difference between fiber and internal |
| 593 | * SerDes mode on the 82575. There can be an external PHY attached |
| 594 | * on the SGMII interface. For this, we'll set sgmii_active to true. |
| 595 | */ |
Akeem G. Abodunrin | a6053d7 | 2013-01-29 10:15:10 +0000 | [diff] [blame] | 596 | hw->phy.media_type = e1000_media_type_copper; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 597 | dev_spec->sgmii_active = false; |
Akeem G. Abodunrin | 641ac5c | 2013-04-24 16:54:50 +0000 | [diff] [blame] | 598 | dev_spec->module_plugged = false; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 599 | |
| 600 | ctrl_ext = rd32(E1000_CTRL_EXT); |
Akeem G. Abodunrin | 641ac5c | 2013-04-24 16:54:50 +0000 | [diff] [blame] | 601 | |
| 602 | link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; |
| 603 | switch (link_mode) { |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 604 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 605 | hw->phy.media_type = e1000_media_type_internal_serdes; |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 606 | break; |
Akeem G. Abodunrin | 641ac5c | 2013-04-24 16:54:50 +0000 | [diff] [blame] | 607 | case E1000_CTRL_EXT_LINK_MODE_SGMII: |
| 608 | /* Get phy control interface type set (MDIO vs. I2C)*/ |
| 609 | if (igb_sgmii_uses_mdio_82575(hw)) { |
| 610 | hw->phy.media_type = e1000_media_type_copper; |
| 611 | dev_spec->sgmii_active = true; |
| 612 | break; |
| 613 | } |
| 614 | /* fall through for I2C based SGMII */ |
| 615 | case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: |
| 616 | /* read media type from SFP EEPROM */ |
| 617 | ret_val = igb_set_sfp_media_type_82575(hw); |
| 618 | if ((ret_val != 0) || |
| 619 | (hw->phy.media_type == e1000_media_type_unknown)) { |
| 620 | /* If media type was not identified then return media |
| 621 | * type defined by the CTRL_EXT settings. |
| 622 | */ |
| 623 | hw->phy.media_type = e1000_media_type_internal_serdes; |
| 624 | |
| 625 | if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { |
| 626 | hw->phy.media_type = e1000_media_type_copper; |
| 627 | dev_spec->sgmii_active = true; |
| 628 | } |
| 629 | |
| 630 | break; |
| 631 | } |
| 632 | |
| 633 | /* do not change link mode for 100BaseFX */ |
| 634 | if (dev_spec->eth_flags.e100_base_fx) |
| 635 | break; |
| 636 | |
| 637 | /* change current link mode setting */ |
| 638 | ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; |
| 639 | |
| 640 | if (hw->phy.media_type == e1000_media_type_copper) |
| 641 | ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; |
| 642 | else |
| 643 | ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; |
| 644 | |
| 645 | wr32(E1000_CTRL_EXT, ctrl_ext); |
| 646 | |
| 647 | break; |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 648 | default: |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 649 | break; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 650 | } |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 651 | |
Akeem G. Abodunrin | a6053d7 | 2013-01-29 10:15:10 +0000 | [diff] [blame] | 652 | /* mac initialization and operations */ |
| 653 | ret_val = igb_init_mac_params_82575(hw); |
| 654 | if (ret_val) |
| 655 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 656 | |
| 657 | /* NVM initialization */ |
Akeem G. Abodunrin | a6053d7 | 2013-01-29 10:15:10 +0000 | [diff] [blame] | 658 | ret_val = igb_init_nvm_params_82575(hw); |
Carolyn Wyborny | 5a823d8 | 2013-07-16 19:17:32 +0000 | [diff] [blame] | 659 | switch (hw->mac.type) { |
| 660 | case e1000_i210: |
| 661 | case e1000_i211: |
| 662 | ret_val = igb_init_nvm_params_i210(hw); |
| 663 | break; |
| 664 | default: |
| 665 | break; |
| 666 | } |
| 667 | |
Akeem G. Abodunrin | a6053d7 | 2013-01-29 10:15:10 +0000 | [diff] [blame] | 668 | if (ret_val) |
| 669 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 670 | |
Carolyn Wyborny | 6b78bb1 | 2011-01-20 06:40:45 +0000 | [diff] [blame] | 671 | /* if part supports SR-IOV then initialize mailbox parameters */ |
| 672 | switch (mac->type) { |
| 673 | case e1000_82576: |
| 674 | case e1000_i350: |
Alexander Duyck | a0c9860 | 2009-07-23 18:10:43 +0000 | [diff] [blame] | 675 | igb_init_mbx_params_pf(hw); |
Carolyn Wyborny | 6b78bb1 | 2011-01-20 06:40:45 +0000 | [diff] [blame] | 676 | break; |
| 677 | default: |
| 678 | break; |
| 679 | } |
Alexander Duyck | a0c9860 | 2009-07-23 18:10:43 +0000 | [diff] [blame] | 680 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 681 | /* setup PHY parameters */ |
Akeem G. Abodunrin | a6053d7 | 2013-01-29 10:15:10 +0000 | [diff] [blame] | 682 | ret_val = igb_init_phy_params_82575(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 683 | |
Akeem G. Abodunrin | a6053d7 | 2013-01-29 10:15:10 +0000 | [diff] [blame] | 684 | out: |
| 685 | return ret_val; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 686 | } |
| 687 | |
| 688 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 689 | * igb_acquire_phy_82575 - Acquire rights to access PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 690 | * @hw: pointer to the HW structure |
| 691 | * |
| 692 | * Acquire access rights to the correct PHY. This is a |
| 693 | * function pointer entry point called by the api module. |
| 694 | **/ |
| 695 | static s32 igb_acquire_phy_82575(struct e1000_hw *hw) |
| 696 | { |
Alexander Duyck | 008c342 | 2009-10-05 06:32:07 +0000 | [diff] [blame] | 697 | u16 mask = E1000_SWFW_PHY0_SM; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 698 | |
Alexander Duyck | 008c342 | 2009-10-05 06:32:07 +0000 | [diff] [blame] | 699 | if (hw->bus.func == E1000_FUNC_1) |
| 700 | mask = E1000_SWFW_PHY1_SM; |
Nick Nunley | ede3ef0 | 2010-07-01 13:37:54 +0000 | [diff] [blame] | 701 | else if (hw->bus.func == E1000_FUNC_2) |
| 702 | mask = E1000_SWFW_PHY2_SM; |
| 703 | else if (hw->bus.func == E1000_FUNC_3) |
| 704 | mask = E1000_SWFW_PHY3_SM; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 705 | |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 706 | return hw->mac.ops.acquire_swfw_sync(hw, mask); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 710 | * igb_release_phy_82575 - Release rights to access PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 711 | * @hw: pointer to the HW structure |
| 712 | * |
| 713 | * A wrapper to release access rights to the correct PHY. This is a |
| 714 | * function pointer entry point called by the api module. |
| 715 | **/ |
| 716 | static void igb_release_phy_82575(struct e1000_hw *hw) |
| 717 | { |
Alexander Duyck | 008c342 | 2009-10-05 06:32:07 +0000 | [diff] [blame] | 718 | u16 mask = E1000_SWFW_PHY0_SM; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 719 | |
Alexander Duyck | 008c342 | 2009-10-05 06:32:07 +0000 | [diff] [blame] | 720 | if (hw->bus.func == E1000_FUNC_1) |
| 721 | mask = E1000_SWFW_PHY1_SM; |
Nick Nunley | ede3ef0 | 2010-07-01 13:37:54 +0000 | [diff] [blame] | 722 | else if (hw->bus.func == E1000_FUNC_2) |
| 723 | mask = E1000_SWFW_PHY2_SM; |
| 724 | else if (hw->bus.func == E1000_FUNC_3) |
| 725 | mask = E1000_SWFW_PHY3_SM; |
Alexander Duyck | 008c342 | 2009-10-05 06:32:07 +0000 | [diff] [blame] | 726 | |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 727 | hw->mac.ops.release_swfw_sync(hw, mask); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 728 | } |
| 729 | |
| 730 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 731 | * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 732 | * @hw: pointer to the HW structure |
| 733 | * @offset: register offset to be read |
| 734 | * @data: pointer to the read data |
| 735 | * |
| 736 | * Reads the PHY register at offset using the serial gigabit media independent |
| 737 | * interface and stores the retrieved information in data. |
| 738 | **/ |
| 739 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, |
| 740 | u16 *data) |
| 741 | { |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 742 | s32 ret_val = -E1000_ERR_PARAM; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 743 | |
| 744 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 745 | hw_dbg("PHY Address %u is out of range\n", offset); |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 746 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 747 | } |
| 748 | |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 749 | ret_val = hw->phy.ops.acquire(hw); |
| 750 | if (ret_val) |
| 751 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 752 | |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 753 | ret_val = igb_read_phy_reg_i2c(hw, offset, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 754 | |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 755 | hw->phy.ops.release(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 756 | |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 757 | out: |
| 758 | return ret_val; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 762 | * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 763 | * @hw: pointer to the HW structure |
| 764 | * @offset: register offset to write to |
| 765 | * @data: data to write at register offset |
| 766 | * |
| 767 | * Writes the data to PHY register at the offset using the serial gigabit |
| 768 | * media independent interface. |
| 769 | **/ |
| 770 | static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, |
| 771 | u16 data) |
| 772 | { |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 773 | s32 ret_val = -E1000_ERR_PARAM; |
| 774 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 775 | |
| 776 | if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 777 | hw_dbg("PHY Address %d is out of range\n", offset); |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 778 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 779 | } |
| 780 | |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 781 | ret_val = hw->phy.ops.acquire(hw); |
| 782 | if (ret_val) |
| 783 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 784 | |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 785 | ret_val = igb_write_phy_reg_i2c(hw, offset, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 786 | |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 787 | hw->phy.ops.release(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 788 | |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 789 | out: |
| 790 | return ret_val; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 791 | } |
| 792 | |
| 793 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 794 | * igb_get_phy_id_82575 - Retrieve PHY addr and id |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 795 | * @hw: pointer to the HW structure |
| 796 | * |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 797 | * Retrieves the PHY address and ID for both PHY's which do and do not use |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 798 | * sgmi interface. |
| 799 | **/ |
| 800 | static s32 igb_get_phy_id_82575(struct e1000_hw *hw) |
| 801 | { |
| 802 | struct e1000_phy_info *phy = &hw->phy; |
| 803 | s32 ret_val = 0; |
| 804 | u16 phy_id; |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 805 | u32 ctrl_ext; |
Nick Nunley | 4085f74 | 2010-07-26 13:15:06 +0000 | [diff] [blame] | 806 | u32 mdic; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 807 | |
Carolyn Wyborny | bb1d18d | 2013-09-10 11:57:16 -0700 | [diff] [blame] | 808 | /* Extra read required for some PHY's on i354 */ |
| 809 | if (hw->mac.type == e1000_i354) |
| 810 | igb_get_phy_id(hw); |
| 811 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 812 | /* For SGMII PHYs, we try the list of possible addresses until |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 813 | * we find one that works. For non-SGMII PHYs |
| 814 | * (e.g. integrated copper PHYs), an address of 1 should |
| 815 | * work. The result of this function should mean phy->phy_addr |
| 816 | * and phy->id are set correctly. |
| 817 | */ |
| 818 | if (!(igb_sgmii_active_82575(hw))) { |
| 819 | phy->addr = 1; |
| 820 | ret_val = igb_get_phy_id(hw); |
| 821 | goto out; |
| 822 | } |
| 823 | |
Nick Nunley | 4085f74 | 2010-07-26 13:15:06 +0000 | [diff] [blame] | 824 | if (igb_sgmii_uses_mdio_82575(hw)) { |
| 825 | switch (hw->mac.type) { |
| 826 | case e1000_82575: |
| 827 | case e1000_82576: |
| 828 | mdic = rd32(E1000_MDIC); |
| 829 | mdic &= E1000_MDIC_PHY_MASK; |
| 830 | phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; |
| 831 | break; |
| 832 | case e1000_82580: |
| 833 | case e1000_i350: |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 834 | case e1000_i354: |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 835 | case e1000_i210: |
| 836 | case e1000_i211: |
Nick Nunley | 4085f74 | 2010-07-26 13:15:06 +0000 | [diff] [blame] | 837 | mdic = rd32(E1000_MDICNFG); |
| 838 | mdic &= E1000_MDICNFG_PHY_MASK; |
| 839 | phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; |
| 840 | break; |
| 841 | default: |
| 842 | ret_val = -E1000_ERR_PHY; |
| 843 | goto out; |
| 844 | break; |
| 845 | } |
| 846 | ret_val = igb_get_phy_id(hw); |
| 847 | goto out; |
| 848 | } |
| 849 | |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 850 | /* Power on sgmii phy if it is disabled */ |
| 851 | ctrl_ext = rd32(E1000_CTRL_EXT); |
| 852 | wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); |
| 853 | wrfl(); |
| 854 | msleep(300); |
| 855 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 856 | /* The address field in the I2CCMD register is 3 bits and 0 is invalid. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 857 | * Therefore, we need to test 1-7 |
| 858 | */ |
| 859 | for (phy->addr = 1; phy->addr < 8; phy->addr++) { |
| 860 | ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); |
| 861 | if (ret_val == 0) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 862 | hw_dbg("Vendor ID 0x%08X read at address %u\n", |
| 863 | phy_id, phy->addr); |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 864 | /* At the time of this writing, The M88 part is |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 865 | * the only supported SGMII PHY product. |
| 866 | */ |
| 867 | if (phy_id == M88_VENDOR) |
| 868 | break; |
| 869 | } else { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 870 | hw_dbg("PHY address %u was unreadable\n", phy->addr); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 871 | } |
| 872 | } |
| 873 | |
| 874 | /* A valid PHY type couldn't be found. */ |
| 875 | if (phy->addr == 8) { |
| 876 | phy->addr = 0; |
| 877 | ret_val = -E1000_ERR_PHY; |
| 878 | goto out; |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 879 | } else { |
| 880 | ret_val = igb_get_phy_id(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 881 | } |
| 882 | |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 883 | /* restore previous sfp cage power state */ |
| 884 | wr32(E1000_CTRL_EXT, ctrl_ext); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 885 | |
| 886 | out: |
| 887 | return ret_val; |
| 888 | } |
| 889 | |
| 890 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 891 | * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 892 | * @hw: pointer to the HW structure |
| 893 | * |
| 894 | * Resets the PHY using the serial gigabit media independent interface. |
| 895 | **/ |
| 896 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) |
| 897 | { |
| 898 | s32 ret_val; |
| 899 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 900 | /* This isn't a true "hard" reset, but is the only reset |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 901 | * available to us at this time. |
| 902 | */ |
| 903 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 904 | hw_dbg("Soft resetting SGMII attached PHY...\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 905 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 906 | /* SFP documentation requires the following to configure the SPF module |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 907 | * to work on SGMII. No further documentation is given. |
| 908 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 909 | ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 910 | if (ret_val) |
| 911 | goto out; |
| 912 | |
| 913 | ret_val = igb_phy_sw_reset(hw); |
| 914 | |
| 915 | out: |
| 916 | return ret_val; |
| 917 | } |
| 918 | |
| 919 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 920 | * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 921 | * @hw: pointer to the HW structure |
| 922 | * @active: true to enable LPLU, false to disable |
| 923 | * |
| 924 | * Sets the LPLU D0 state according to the active flag. When |
| 925 | * activating LPLU this function also disables smart speed |
| 926 | * and vice versa. LPLU will not be activated unless the |
| 927 | * device autonegotiation advertisement meets standards of |
| 928 | * either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 929 | * This is a function pointer entry point only called by |
| 930 | * PHY setup routines. |
| 931 | **/ |
| 932 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) |
| 933 | { |
| 934 | struct e1000_phy_info *phy = &hw->phy; |
| 935 | s32 ret_val; |
| 936 | u16 data; |
| 937 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 938 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 939 | if (ret_val) |
| 940 | goto out; |
| 941 | |
| 942 | if (active) { |
| 943 | data |= IGP02E1000_PM_D0_LPLU; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 944 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 945 | data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 946 | if (ret_val) |
| 947 | goto out; |
| 948 | |
| 949 | /* When LPLU is enabled, we should disable SmartSpeed */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 950 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 951 | &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 952 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 953 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 954 | data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 955 | if (ret_val) |
| 956 | goto out; |
| 957 | } else { |
| 958 | data &= ~IGP02E1000_PM_D0_LPLU; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 959 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 960 | data); |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 961 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 962 | * during Dx states where the power conservation is most |
| 963 | * important. During driver activity we should enable |
| 964 | * SmartSpeed, so performance is maintained. |
| 965 | */ |
| 966 | if (phy->smart_speed == e1000_smart_speed_on) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 967 | ret_val = phy->ops.read_reg(hw, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 968 | IGP01E1000_PHY_PORT_CONFIG, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 969 | if (ret_val) |
| 970 | goto out; |
| 971 | |
| 972 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 973 | ret_val = phy->ops.write_reg(hw, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 974 | IGP01E1000_PHY_PORT_CONFIG, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 975 | if (ret_val) |
| 976 | goto out; |
| 977 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 978 | ret_val = phy->ops.read_reg(hw, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 979 | IGP01E1000_PHY_PORT_CONFIG, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 980 | if (ret_val) |
| 981 | goto out; |
| 982 | |
| 983 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 984 | ret_val = phy->ops.write_reg(hw, |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 985 | IGP01E1000_PHY_PORT_CONFIG, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 986 | if (ret_val) |
| 987 | goto out; |
| 988 | } |
| 989 | } |
| 990 | |
| 991 | out: |
| 992 | return ret_val; |
| 993 | } |
| 994 | |
| 995 | /** |
Carolyn Wyborny | da02cde | 2012-03-04 03:26:26 +0000 | [diff] [blame] | 996 | * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state |
| 997 | * @hw: pointer to the HW structure |
| 998 | * @active: true to enable LPLU, false to disable |
| 999 | * |
| 1000 | * Sets the LPLU D0 state according to the active flag. When |
| 1001 | * activating LPLU this function also disables smart speed |
| 1002 | * and vice versa. LPLU will not be activated unless the |
| 1003 | * device autonegotiation advertisement meets standards of |
| 1004 | * either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 1005 | * This is a function pointer entry point only called by |
| 1006 | * PHY setup routines. |
| 1007 | **/ |
| 1008 | static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) |
| 1009 | { |
| 1010 | struct e1000_phy_info *phy = &hw->phy; |
| 1011 | s32 ret_val = 0; |
| 1012 | u16 data; |
| 1013 | |
| 1014 | data = rd32(E1000_82580_PHY_POWER_MGMT); |
| 1015 | |
| 1016 | if (active) { |
| 1017 | data |= E1000_82580_PM_D0_LPLU; |
| 1018 | |
| 1019 | /* When LPLU is enabled, we should disable SmartSpeed */ |
| 1020 | data &= ~E1000_82580_PM_SPD; |
| 1021 | } else { |
| 1022 | data &= ~E1000_82580_PM_D0_LPLU; |
| 1023 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1024 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Carolyn Wyborny | da02cde | 2012-03-04 03:26:26 +0000 | [diff] [blame] | 1025 | * during Dx states where the power conservation is most |
| 1026 | * important. During driver activity we should enable |
| 1027 | * SmartSpeed, so performance is maintained. |
| 1028 | */ |
| 1029 | if (phy->smart_speed == e1000_smart_speed_on) |
| 1030 | data |= E1000_82580_PM_SPD; |
| 1031 | else if (phy->smart_speed == e1000_smart_speed_off) |
| 1032 | data &= ~E1000_82580_PM_SPD; } |
| 1033 | |
| 1034 | wr32(E1000_82580_PHY_POWER_MGMT, data); |
| 1035 | return ret_val; |
| 1036 | } |
| 1037 | |
| 1038 | /** |
| 1039 | * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 |
| 1040 | * @hw: pointer to the HW structure |
| 1041 | * @active: boolean used to enable/disable lplu |
| 1042 | * |
| 1043 | * Success returns 0, Failure returns 1 |
| 1044 | * |
| 1045 | * The low power link up (lplu) state is set to the power management level D3 |
| 1046 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 |
| 1047 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
| 1048 | * is used during Dx states where the power conservation is most important. |
| 1049 | * During driver activity, SmartSpeed should be enabled so performance is |
| 1050 | * maintained. |
| 1051 | **/ |
Akeem G. Abodunrin | c826892 | 2013-02-16 07:09:06 +0000 | [diff] [blame] | 1052 | static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) |
Carolyn Wyborny | da02cde | 2012-03-04 03:26:26 +0000 | [diff] [blame] | 1053 | { |
| 1054 | struct e1000_phy_info *phy = &hw->phy; |
| 1055 | s32 ret_val = 0; |
| 1056 | u16 data; |
| 1057 | |
| 1058 | data = rd32(E1000_82580_PHY_POWER_MGMT); |
| 1059 | |
| 1060 | if (!active) { |
| 1061 | data &= ~E1000_82580_PM_D3_LPLU; |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1062 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Carolyn Wyborny | da02cde | 2012-03-04 03:26:26 +0000 | [diff] [blame] | 1063 | * during Dx states where the power conservation is most |
| 1064 | * important. During driver activity we should enable |
| 1065 | * SmartSpeed, so performance is maintained. |
| 1066 | */ |
| 1067 | if (phy->smart_speed == e1000_smart_speed_on) |
| 1068 | data |= E1000_82580_PM_SPD; |
| 1069 | else if (phy->smart_speed == e1000_smart_speed_off) |
| 1070 | data &= ~E1000_82580_PM_SPD; |
| 1071 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
| 1072 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
| 1073 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
| 1074 | data |= E1000_82580_PM_D3_LPLU; |
| 1075 | /* When LPLU is enabled, we should disable SmartSpeed */ |
| 1076 | data &= ~E1000_82580_PM_SPD; |
| 1077 | } |
| 1078 | |
| 1079 | wr32(E1000_82580_PHY_POWER_MGMT, data); |
| 1080 | return ret_val; |
| 1081 | } |
| 1082 | |
| 1083 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1084 | * igb_acquire_nvm_82575 - Request for access to EEPROM |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1085 | * @hw: pointer to the HW structure |
| 1086 | * |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1087 | * Acquire the necessary semaphores for exclusive access to the EEPROM. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1088 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. |
| 1089 | * Return successful if access grant bit set, else clear the request for |
| 1090 | * EEPROM access and return -E1000_ERR_NVM (-1). |
| 1091 | **/ |
| 1092 | static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) |
| 1093 | { |
| 1094 | s32 ret_val; |
| 1095 | |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1096 | ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1097 | if (ret_val) |
| 1098 | goto out; |
| 1099 | |
| 1100 | ret_val = igb_acquire_nvm(hw); |
| 1101 | |
| 1102 | if (ret_val) |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1103 | hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1104 | |
| 1105 | out: |
| 1106 | return ret_val; |
| 1107 | } |
| 1108 | |
| 1109 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1110 | * igb_release_nvm_82575 - Release exclusive access to EEPROM |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1111 | * @hw: pointer to the HW structure |
| 1112 | * |
| 1113 | * Stop any current commands to the EEPROM and clear the EEPROM request bit, |
| 1114 | * then release the semaphores acquired. |
| 1115 | **/ |
| 1116 | static void igb_release_nvm_82575(struct e1000_hw *hw) |
| 1117 | { |
| 1118 | igb_release_nvm(hw); |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1119 | hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1120 | } |
| 1121 | |
| 1122 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1123 | * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1124 | * @hw: pointer to the HW structure |
| 1125 | * @mask: specifies which semaphore to acquire |
| 1126 | * |
| 1127 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask |
| 1128 | * will also specify which port we're acquiring the lock for. |
| 1129 | **/ |
| 1130 | static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) |
| 1131 | { |
| 1132 | u32 swfw_sync; |
| 1133 | u32 swmask = mask; |
| 1134 | u32 fwmask = mask << 16; |
| 1135 | s32 ret_val = 0; |
| 1136 | s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ |
| 1137 | |
| 1138 | while (i < timeout) { |
| 1139 | if (igb_get_hw_semaphore(hw)) { |
| 1140 | ret_val = -E1000_ERR_SWFW_SYNC; |
| 1141 | goto out; |
| 1142 | } |
| 1143 | |
| 1144 | swfw_sync = rd32(E1000_SW_FW_SYNC); |
| 1145 | if (!(swfw_sync & (fwmask | swmask))) |
| 1146 | break; |
| 1147 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1148 | /* Firmware currently using resource (fwmask) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1149 | * or other software thread using resource (swmask) |
| 1150 | */ |
| 1151 | igb_put_hw_semaphore(hw); |
| 1152 | mdelay(5); |
| 1153 | i++; |
| 1154 | } |
| 1155 | |
| 1156 | if (i == timeout) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1157 | hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1158 | ret_val = -E1000_ERR_SWFW_SYNC; |
| 1159 | goto out; |
| 1160 | } |
| 1161 | |
| 1162 | swfw_sync |= swmask; |
| 1163 | wr32(E1000_SW_FW_SYNC, swfw_sync); |
| 1164 | |
| 1165 | igb_put_hw_semaphore(hw); |
| 1166 | |
| 1167 | out: |
| 1168 | return ret_val; |
| 1169 | } |
| 1170 | |
| 1171 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1172 | * igb_release_swfw_sync_82575 - Release SW/FW semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1173 | * @hw: pointer to the HW structure |
| 1174 | * @mask: specifies which semaphore to acquire |
| 1175 | * |
| 1176 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask |
| 1177 | * will also specify which port we're releasing the lock for. |
| 1178 | **/ |
| 1179 | static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) |
| 1180 | { |
| 1181 | u32 swfw_sync; |
| 1182 | |
| 1183 | while (igb_get_hw_semaphore(hw) != 0); |
| 1184 | /* Empty */ |
| 1185 | |
| 1186 | swfw_sync = rd32(E1000_SW_FW_SYNC); |
| 1187 | swfw_sync &= ~mask; |
| 1188 | wr32(E1000_SW_FW_SYNC, swfw_sync); |
| 1189 | |
| 1190 | igb_put_hw_semaphore(hw); |
| 1191 | } |
| 1192 | |
| 1193 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1194 | * igb_get_cfg_done_82575 - Read config done bit |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1195 | * @hw: pointer to the HW structure |
| 1196 | * |
| 1197 | * Read the management control register for the config done bit for |
| 1198 | * completion status. NOTE: silicon which is EEPROM-less will fail trying |
| 1199 | * to read the config done bit, so an error is *ONLY* logged and returns |
| 1200 | * 0. If we were to return with error, EEPROM-less silicon |
| 1201 | * would not be able to be reset or change link. |
| 1202 | **/ |
| 1203 | static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) |
| 1204 | { |
| 1205 | s32 timeout = PHY_CFG_TIMEOUT; |
| 1206 | s32 ret_val = 0; |
| 1207 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; |
| 1208 | |
| 1209 | if (hw->bus.func == 1) |
| 1210 | mask = E1000_NVM_CFG_DONE_PORT_1; |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1211 | else if (hw->bus.func == E1000_FUNC_2) |
| 1212 | mask = E1000_NVM_CFG_DONE_PORT_2; |
| 1213 | else if (hw->bus.func == E1000_FUNC_3) |
| 1214 | mask = E1000_NVM_CFG_DONE_PORT_3; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1215 | |
| 1216 | while (timeout) { |
| 1217 | if (rd32(E1000_EEMNGCTL) & mask) |
| 1218 | break; |
| 1219 | msleep(1); |
| 1220 | timeout--; |
| 1221 | } |
| 1222 | if (!timeout) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1223 | hw_dbg("MNG configuration cycle has not completed.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1224 | |
| 1225 | /* If EEPROM is not marked present, init the PHY manually */ |
| 1226 | if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && |
| 1227 | (hw->phy.type == e1000_phy_igp_3)) |
| 1228 | igb_phy_init_script_igp3(hw); |
| 1229 | |
| 1230 | return ret_val; |
| 1231 | } |
| 1232 | |
| 1233 | /** |
Akeem G Abodunrin | f6878e3 | 2013-08-28 02:23:09 +0000 | [diff] [blame] | 1234 | * igb_get_link_up_info_82575 - Get link speed/duplex info |
| 1235 | * @hw: pointer to the HW structure |
| 1236 | * @speed: stores the current speed |
| 1237 | * @duplex: stores the current duplex |
| 1238 | * |
| 1239 | * This is a wrapper function, if using the serial gigabit media independent |
| 1240 | * interface, use PCS to retrieve the link speed and duplex information. |
| 1241 | * Otherwise, use the generic function to get the link speed and duplex info. |
| 1242 | **/ |
| 1243 | static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, |
| 1244 | u16 *duplex) |
| 1245 | { |
| 1246 | s32 ret_val; |
| 1247 | |
| 1248 | if (hw->phy.media_type != e1000_media_type_copper) |
| 1249 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, |
| 1250 | duplex); |
| 1251 | else |
| 1252 | ret_val = igb_get_speed_and_duplex_copper(hw, speed, |
| 1253 | duplex); |
| 1254 | |
| 1255 | return ret_val; |
| 1256 | } |
| 1257 | |
| 1258 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1259 | * igb_check_for_link_82575 - Check for link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1260 | * @hw: pointer to the HW structure |
| 1261 | * |
| 1262 | * If sgmii is enabled, then use the pcs register to determine link, otherwise |
| 1263 | * use the generic interface for determining link. |
| 1264 | **/ |
| 1265 | static s32 igb_check_for_link_82575(struct e1000_hw *hw) |
| 1266 | { |
| 1267 | s32 ret_val; |
| 1268 | u16 speed, duplex; |
| 1269 | |
Alexander Duyck | 70d92f8 | 2009-10-05 06:31:47 +0000 | [diff] [blame] | 1270 | if (hw->phy.media_type != e1000_media_type_copper) { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1271 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 1272 | &duplex); |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1273 | /* Use this flag to determine if link needs to be checked or |
Alexander Duyck | 5d0932a | 2009-01-31 00:53:18 -0800 | [diff] [blame] | 1274 | * not. If we have link clear the flag so that we do not |
| 1275 | * continue to check for link. |
| 1276 | */ |
| 1277 | hw->mac.get_link_status = !hw->mac.serdes_has_link; |
Carolyn Wyborny | daf56e4 | 2012-10-23 12:54:33 +0000 | [diff] [blame] | 1278 | |
| 1279 | /* Configure Flow Control now that Auto-Neg has completed. |
| 1280 | * First, we need to restore the desired flow control |
| 1281 | * settings because we may have had to re-autoneg with a |
| 1282 | * different link partner. |
| 1283 | */ |
| 1284 | ret_val = igb_config_fc_after_link_up(hw); |
| 1285 | if (ret_val) |
| 1286 | hw_dbg("Error configuring flow control\n"); |
Alexander Duyck | 5d0932a | 2009-01-31 00:53:18 -0800 | [diff] [blame] | 1287 | } else { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1288 | ret_val = igb_check_for_copper_link(hw); |
Alexander Duyck | 5d0932a | 2009-01-31 00:53:18 -0800 | [diff] [blame] | 1289 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1290 | |
| 1291 | return ret_val; |
| 1292 | } |
Alexander Duyck | 70d92f8 | 2009-10-05 06:31:47 +0000 | [diff] [blame] | 1293 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1294 | /** |
Nick Nunley | 88a268c | 2010-02-17 01:01:59 +0000 | [diff] [blame] | 1295 | * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown |
| 1296 | * @hw: pointer to the HW structure |
| 1297 | **/ |
| 1298 | void igb_power_up_serdes_link_82575(struct e1000_hw *hw) |
| 1299 | { |
| 1300 | u32 reg; |
| 1301 | |
| 1302 | |
| 1303 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && |
| 1304 | !igb_sgmii_active_82575(hw)) |
| 1305 | return; |
| 1306 | |
| 1307 | /* Enable PCS to turn on link */ |
| 1308 | reg = rd32(E1000_PCS_CFG0); |
| 1309 | reg |= E1000_PCS_CFG_PCS_EN; |
| 1310 | wr32(E1000_PCS_CFG0, reg); |
| 1311 | |
| 1312 | /* Power up the laser */ |
| 1313 | reg = rd32(E1000_CTRL_EXT); |
| 1314 | reg &= ~E1000_CTRL_EXT_SDP3_DATA; |
| 1315 | wr32(E1000_CTRL_EXT, reg); |
| 1316 | |
| 1317 | /* flush the write to verify completion */ |
| 1318 | wrfl(); |
| 1319 | msleep(1); |
| 1320 | } |
| 1321 | |
| 1322 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1323 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1324 | * @hw: pointer to the HW structure |
| 1325 | * @speed: stores the current speed |
| 1326 | * @duplex: stores the current duplex |
| 1327 | * |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1328 | * Using the physical coding sub-layer (PCS), retrieve the current speed and |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1329 | * duplex, then store the values in the pointers provided. |
| 1330 | **/ |
| 1331 | static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, |
| 1332 | u16 *duplex) |
| 1333 | { |
| 1334 | struct e1000_mac_info *mac = &hw->mac; |
Akeem G Abodunrin | f1b4d62 | 2013-08-28 02:23:04 +0000 | [diff] [blame] | 1335 | u32 pcs, status; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1336 | |
| 1337 | /* Set up defaults for the return values of this function */ |
| 1338 | mac->serdes_has_link = false; |
| 1339 | *speed = 0; |
| 1340 | *duplex = 0; |
| 1341 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1342 | /* Read the PCS Status register for link state. For non-copper mode, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1343 | * the status register is not accurate. The PCS status register is |
| 1344 | * used instead. |
| 1345 | */ |
| 1346 | pcs = rd32(E1000_PCS_LSTAT); |
| 1347 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1348 | /* The link up bit determines when link is up on autoneg. The sync ok |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1349 | * gets set once both sides sync up and agree upon link. Stable link |
| 1350 | * can be determined by checking for both link up and link sync ok |
| 1351 | */ |
| 1352 | if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { |
| 1353 | mac->serdes_has_link = true; |
| 1354 | |
| 1355 | /* Detect and store PCS speed */ |
Akeem G Abodunrin | f1b4d62 | 2013-08-28 02:23:04 +0000 | [diff] [blame] | 1356 | if (pcs & E1000_PCS_LSTS_SPEED_1000) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1357 | *speed = SPEED_1000; |
Akeem G Abodunrin | f1b4d62 | 2013-08-28 02:23:04 +0000 | [diff] [blame] | 1358 | else if (pcs & E1000_PCS_LSTS_SPEED_100) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1359 | *speed = SPEED_100; |
Akeem G Abodunrin | f1b4d62 | 2013-08-28 02:23:04 +0000 | [diff] [blame] | 1360 | else |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1361 | *speed = SPEED_10; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1362 | |
| 1363 | /* Detect and store PCS duplex */ |
Akeem G Abodunrin | f1b4d62 | 2013-08-28 02:23:04 +0000 | [diff] [blame] | 1364 | if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1365 | *duplex = FULL_DUPLEX; |
Akeem G Abodunrin | f1b4d62 | 2013-08-28 02:23:04 +0000 | [diff] [blame] | 1366 | else |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1367 | *duplex = HALF_DUPLEX; |
Akeem G Abodunrin | f1b4d62 | 2013-08-28 02:23:04 +0000 | [diff] [blame] | 1368 | |
| 1369 | /* Check if it is an I354 2.5Gb backplane connection. */ |
| 1370 | if (mac->type == e1000_i354) { |
| 1371 | status = rd32(E1000_STATUS); |
| 1372 | if ((status & E1000_STATUS_2P5_SKU) && |
| 1373 | !(status & E1000_STATUS_2P5_SKU_OVER)) { |
| 1374 | *speed = SPEED_2500; |
| 1375 | *duplex = FULL_DUPLEX; |
| 1376 | hw_dbg("2500 Mbs, "); |
| 1377 | hw_dbg("Full Duplex\n"); |
| 1378 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1379 | } |
Akeem G Abodunrin | f1b4d62 | 2013-08-28 02:23:04 +0000 | [diff] [blame] | 1380 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1381 | } |
| 1382 | |
| 1383 | return 0; |
| 1384 | } |
| 1385 | |
| 1386 | /** |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1387 | * igb_shutdown_serdes_link_82575 - Remove link during power down |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 1388 | * @hw: pointer to the HW structure |
| 1389 | * |
| 1390 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
| 1391 | * when management pass thru is not enabled. |
| 1392 | **/ |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1393 | void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 1394 | { |
| 1395 | u32 reg; |
| 1396 | |
Nick Nunley | 53c992f | 2010-02-17 01:01:40 +0000 | [diff] [blame] | 1397 | if (hw->phy.media_type != e1000_media_type_internal_serdes && |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1398 | igb_sgmii_active_82575(hw)) |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 1399 | return; |
| 1400 | |
Nick Nunley | 53c992f | 2010-02-17 01:01:40 +0000 | [diff] [blame] | 1401 | if (!igb_enable_mng_pass_thru(hw)) { |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 1402 | /* Disable PCS to turn off link */ |
| 1403 | reg = rd32(E1000_PCS_CFG0); |
| 1404 | reg &= ~E1000_PCS_CFG_PCS_EN; |
| 1405 | wr32(E1000_PCS_CFG0, reg); |
| 1406 | |
| 1407 | /* shutdown the laser */ |
| 1408 | reg = rd32(E1000_CTRL_EXT); |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1409 | reg |= E1000_CTRL_EXT_SDP3_DATA; |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 1410 | wr32(E1000_CTRL_EXT, reg); |
| 1411 | |
| 1412 | /* flush the write to verify completion */ |
| 1413 | wrfl(); |
| 1414 | msleep(1); |
| 1415 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1416 | } |
| 1417 | |
| 1418 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1419 | * igb_reset_hw_82575 - Reset hardware |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1420 | * @hw: pointer to the HW structure |
| 1421 | * |
| 1422 | * This resets the hardware into a known state. This is a |
| 1423 | * function pointer entry point called by the api module. |
| 1424 | **/ |
| 1425 | static s32 igb_reset_hw_82575(struct e1000_hw *hw) |
| 1426 | { |
Akeem G Abodunrin | e5c3370 | 2013-06-06 01:31:09 +0000 | [diff] [blame] | 1427 | u32 ctrl; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1428 | s32 ret_val; |
| 1429 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1430 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1431 | * on the last TLP read/write transaction when MAC is reset. |
| 1432 | */ |
| 1433 | ret_val = igb_disable_pcie_master(hw); |
| 1434 | if (ret_val) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1435 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1436 | |
Alexander Duyck | 009bc06 | 2009-07-23 18:08:35 +0000 | [diff] [blame] | 1437 | /* set the completion timeout for interface */ |
| 1438 | ret_val = igb_set_pcie_completion_timeout(hw); |
| 1439 | if (ret_val) { |
| 1440 | hw_dbg("PCI-E Set completion timeout has failed.\n"); |
| 1441 | } |
| 1442 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1443 | hw_dbg("Masking off all interrupts\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1444 | wr32(E1000_IMC, 0xffffffff); |
| 1445 | |
| 1446 | wr32(E1000_RCTL, 0); |
| 1447 | wr32(E1000_TCTL, E1000_TCTL_PSP); |
| 1448 | wrfl(); |
| 1449 | |
| 1450 | msleep(10); |
| 1451 | |
| 1452 | ctrl = rd32(E1000_CTRL); |
| 1453 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1454 | hw_dbg("Issuing a global reset to MAC\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1455 | wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); |
| 1456 | |
| 1457 | ret_val = igb_get_auto_rd_done(hw); |
| 1458 | if (ret_val) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1459 | /* When auto config read does not complete, do not |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1460 | * return with an error. This can happen in situations |
| 1461 | * where there is no eeprom and prevents getting link. |
| 1462 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1463 | hw_dbg("Auto Read Done did not complete\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1464 | } |
| 1465 | |
| 1466 | /* If EEPROM is not present, run manual init scripts */ |
| 1467 | if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) |
| 1468 | igb_reset_init_script_82575(hw); |
| 1469 | |
| 1470 | /* Clear any pending interrupt events. */ |
| 1471 | wr32(E1000_IMC, 0xffffffff); |
Akeem G Abodunrin | e5c3370 | 2013-06-06 01:31:09 +0000 | [diff] [blame] | 1472 | rd32(E1000_ICR); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1473 | |
Alexander Duyck | 5ac1665 | 2009-07-23 18:09:12 +0000 | [diff] [blame] | 1474 | /* Install any alternate MAC address into RAR0 */ |
| 1475 | ret_val = igb_check_alt_mac_addr(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1476 | |
| 1477 | return ret_val; |
| 1478 | } |
| 1479 | |
| 1480 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1481 | * igb_init_hw_82575 - Initialize hardware |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1482 | * @hw: pointer to the HW structure |
| 1483 | * |
| 1484 | * This inits the hardware readying it for operation. |
| 1485 | **/ |
| 1486 | static s32 igb_init_hw_82575(struct e1000_hw *hw) |
| 1487 | { |
| 1488 | struct e1000_mac_info *mac = &hw->mac; |
| 1489 | s32 ret_val; |
| 1490 | u16 i, rar_count = mac->rar_entry_count; |
| 1491 | |
| 1492 | /* Initialize identification LED */ |
| 1493 | ret_val = igb_id_led_init(hw); |
| 1494 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1495 | hw_dbg("Error initializing identification LED\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1496 | /* This is not fatal and we should not stop init due to this */ |
| 1497 | } |
| 1498 | |
| 1499 | /* Disabling VLAN filtering */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1500 | hw_dbg("Initializing the IEEE VLAN\n"); |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 1501 | if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) |
Carolyn Wyborny | 1128c75 | 2011-10-14 00:13:49 +0000 | [diff] [blame] | 1502 | igb_clear_vfta_i350(hw); |
| 1503 | else |
| 1504 | igb_clear_vfta(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1505 | |
| 1506 | /* Setup the receive address */ |
Alexander Duyck | 5ac1665 | 2009-07-23 18:09:12 +0000 | [diff] [blame] | 1507 | igb_init_rx_addrs(hw, rar_count); |
| 1508 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1509 | /* Zero out the Multicast HASH table */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1510 | hw_dbg("Zeroing the MTA\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1511 | for (i = 0; i < mac->mta_reg_count; i++) |
| 1512 | array_wr32(E1000_MTA, i, 0); |
| 1513 | |
Alexander Duyck | 68d480c | 2009-10-05 06:33:08 +0000 | [diff] [blame] | 1514 | /* Zero out the Unicast HASH table */ |
| 1515 | hw_dbg("Zeroing the UTA\n"); |
| 1516 | for (i = 0; i < mac->uta_reg_count; i++) |
| 1517 | array_wr32(E1000_UTA, i, 0); |
| 1518 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1519 | /* Setup link and flow control */ |
| 1520 | ret_val = igb_setup_link(hw); |
| 1521 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1522 | /* Clear all of the statistics registers (clear on read). It is |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1523 | * important that we do this after we have tried to establish link |
| 1524 | * because the symbol error count will increment wildly if there |
| 1525 | * is no link. |
| 1526 | */ |
| 1527 | igb_clear_hw_cntrs_82575(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1528 | return ret_val; |
| 1529 | } |
| 1530 | |
| 1531 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1532 | * igb_setup_copper_link_82575 - Configure copper link settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1533 | * @hw: pointer to the HW structure |
| 1534 | * |
| 1535 | * Configures the link for auto-neg or forced speed and duplex. Then we check |
| 1536 | * for link, once link is established calls to configure collision distance |
| 1537 | * and flow control are called. |
| 1538 | **/ |
| 1539 | static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) |
| 1540 | { |
Alexander Duyck | 12645a1 | 2009-07-23 18:08:16 +0000 | [diff] [blame] | 1541 | u32 ctrl; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1542 | s32 ret_val; |
Carolyn Wyborny | 867eb39 | 2012-11-13 04:03:20 +0000 | [diff] [blame] | 1543 | u32 phpm_reg; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1544 | |
| 1545 | ctrl = rd32(E1000_CTRL); |
| 1546 | ctrl |= E1000_CTRL_SLU; |
| 1547 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1548 | wr32(E1000_CTRL, ctrl); |
| 1549 | |
Akeem G Abodunrin | db476e8 | 2013-08-28 02:22:53 +0000 | [diff] [blame] | 1550 | /* Clear Go Link Disconnect bit on supported devices */ |
| 1551 | switch (hw->mac.type) { |
| 1552 | case e1000_82580: |
| 1553 | case e1000_i350: |
| 1554 | case e1000_i210: |
| 1555 | case e1000_i211: |
Carolyn Wyborny | 867eb39 | 2012-11-13 04:03:20 +0000 | [diff] [blame] | 1556 | phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT); |
| 1557 | phpm_reg &= ~E1000_82580_PM_GO_LINKD; |
| 1558 | wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg); |
Akeem G Abodunrin | db476e8 | 2013-08-28 02:22:53 +0000 | [diff] [blame] | 1559 | break; |
| 1560 | default: |
| 1561 | break; |
Carolyn Wyborny | 867eb39 | 2012-11-13 04:03:20 +0000 | [diff] [blame] | 1562 | } |
| 1563 | |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1564 | ret_val = igb_setup_serdes_link_82575(hw); |
| 1565 | if (ret_val) |
| 1566 | goto out; |
| 1567 | |
| 1568 | if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1569 | /* allow time for SFP cage time to power up phy */ |
| 1570 | msleep(300); |
| 1571 | |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1572 | ret_val = hw->phy.ops.reset(hw); |
| 1573 | if (ret_val) { |
| 1574 | hw_dbg("Error resetting the PHY.\n"); |
| 1575 | goto out; |
| 1576 | } |
| 1577 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1578 | switch (hw->phy.type) { |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1579 | case e1000_phy_i210: |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1580 | case e1000_phy_m88: |
Carolyn Wyborny | ed65bdd | 2013-02-06 03:35:27 +0000 | [diff] [blame] | 1581 | switch (hw->phy.id) { |
| 1582 | case I347AT4_E_PHY_ID: |
| 1583 | case M88E1112_E_PHY_ID: |
Akeem G Abodunrin | 99af472 | 2013-08-28 02:22:58 +0000 | [diff] [blame] | 1584 | case M88E1543_E_PHY_ID: |
Carolyn Wyborny | ed65bdd | 2013-02-06 03:35:27 +0000 | [diff] [blame] | 1585 | case I210_I_PHY_ID: |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1586 | ret_val = igb_copper_link_setup_m88_gen2(hw); |
Carolyn Wyborny | ed65bdd | 2013-02-06 03:35:27 +0000 | [diff] [blame] | 1587 | break; |
| 1588 | default: |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1589 | ret_val = igb_copper_link_setup_m88(hw); |
Carolyn Wyborny | ed65bdd | 2013-02-06 03:35:27 +0000 | [diff] [blame] | 1590 | break; |
| 1591 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1592 | break; |
| 1593 | case e1000_phy_igp_3: |
| 1594 | ret_val = igb_copper_link_setup_igp(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1595 | break; |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1596 | case e1000_phy_82580: |
| 1597 | ret_val = igb_copper_link_setup_82580(hw); |
| 1598 | break; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1599 | default: |
| 1600 | ret_val = -E1000_ERR_PHY; |
| 1601 | break; |
| 1602 | } |
| 1603 | |
| 1604 | if (ret_val) |
| 1605 | goto out; |
| 1606 | |
Alexander Duyck | 81fadd8 | 2009-10-05 06:35:03 +0000 | [diff] [blame] | 1607 | ret_val = igb_setup_copper_link(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1608 | out: |
| 1609 | return ret_val; |
| 1610 | } |
| 1611 | |
| 1612 | /** |
Alexander Duyck | 70d92f8 | 2009-10-05 06:31:47 +0000 | [diff] [blame] | 1613 | * igb_setup_serdes_link_82575 - Setup link for serdes |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1614 | * @hw: pointer to the HW structure |
| 1615 | * |
Alexander Duyck | 70d92f8 | 2009-10-05 06:31:47 +0000 | [diff] [blame] | 1616 | * Configure the physical coding sub-layer (PCS) link. The PCS link is |
| 1617 | * used on copper connections where the serialized gigabit media independent |
| 1618 | * interface (sgmii), or serdes fiber is being used. Configures the link |
| 1619 | * for auto-negotiation or forces speed/duplex. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1620 | **/ |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1621 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1622 | { |
Carolyn Wyborny | daf56e4 | 2012-10-23 12:54:33 +0000 | [diff] [blame] | 1623 | u32 ctrl_ext, ctrl_reg, reg, anadv_reg; |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1624 | bool pcs_autoneg; |
Carolyn Wyborny | 2c670b5 | 2011-05-24 06:52:51 +0000 | [diff] [blame] | 1625 | s32 ret_val = E1000_SUCCESS; |
| 1626 | u16 data; |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1627 | |
| 1628 | if ((hw->phy.media_type != e1000_media_type_internal_serdes) && |
| 1629 | !igb_sgmii_active_82575(hw)) |
Carolyn Wyborny | 2c670b5 | 2011-05-24 06:52:51 +0000 | [diff] [blame] | 1630 | return ret_val; |
| 1631 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1632 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1633 | /* On the 82575, SerDes loopback mode persists until it is |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1634 | * explicitly turned off or a power cycle is performed. A read to |
| 1635 | * the register does not indicate its status. Therefore, we ensure |
| 1636 | * loopback mode is disabled during initialization. |
| 1637 | */ |
| 1638 | wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
| 1639 | |
Akeem G. Abodunrin | e00bf60 | 2013-01-29 10:15:26 +0000 | [diff] [blame] | 1640 | /* power on the sfp cage if present and turn on I2C */ |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1641 | ctrl_ext = rd32(E1000_CTRL_EXT); |
| 1642 | ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; |
Akeem G. Abodunrin | e00bf60 | 2013-01-29 10:15:26 +0000 | [diff] [blame] | 1643 | ctrl_ext |= E1000_CTRL_I2C_ENA; |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1644 | wr32(E1000_CTRL_EXT, ctrl_ext); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1645 | |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1646 | ctrl_reg = rd32(E1000_CTRL); |
| 1647 | ctrl_reg |= E1000_CTRL_SLU; |
| 1648 | |
| 1649 | if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { |
| 1650 | /* set both sw defined pins */ |
| 1651 | ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; |
| 1652 | |
| 1653 | /* Set switch control to serdes energy detect */ |
| 1654 | reg = rd32(E1000_CONNSW); |
| 1655 | reg |= E1000_CONNSW_ENRGSRC; |
| 1656 | wr32(E1000_CONNSW, reg); |
Alexander Duyck | 921aa74 | 2009-01-21 14:42:28 -0800 | [diff] [blame] | 1657 | } |
| 1658 | |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1659 | reg = rd32(E1000_PCS_LCTL); |
| 1660 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1661 | /* default pcs_autoneg to the same setting as mac autoneg */ |
| 1662 | pcs_autoneg = hw->mac.autoneg; |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1663 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1664 | switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { |
| 1665 | case E1000_CTRL_EXT_LINK_MODE_SGMII: |
| 1666 | /* sgmii mode lets the phy handle forcing speed/duplex */ |
| 1667 | pcs_autoneg = true; |
| 1668 | /* autoneg time out should be disabled for SGMII mode */ |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1669 | reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1670 | break; |
| 1671 | case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: |
| 1672 | /* disable PCS autoneg and support parallel detect only */ |
| 1673 | pcs_autoneg = false; |
| 1674 | default: |
Carolyn Wyborny | 2c670b5 | 2011-05-24 06:52:51 +0000 | [diff] [blame] | 1675 | if (hw->mac.type == e1000_82575 || |
| 1676 | hw->mac.type == e1000_82576) { |
| 1677 | ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); |
| 1678 | if (ret_val) { |
Carolyn Wyborny | c75c4ed | 2014-04-11 01:45:17 +0000 | [diff] [blame^] | 1679 | hw_dbg(KERN_DEBUG "NVM Read Error\n\n"); |
Carolyn Wyborny | 2c670b5 | 2011-05-24 06:52:51 +0000 | [diff] [blame] | 1680 | return ret_val; |
| 1681 | } |
| 1682 | |
| 1683 | if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) |
| 1684 | pcs_autoneg = false; |
| 1685 | } |
| 1686 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1687 | /* non-SGMII modes only supports a speed of 1000/Full for the |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1688 | * link so it is best to just force the MAC and let the pcs |
| 1689 | * link either autoneg or be forced to 1000/Full |
| 1690 | */ |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1691 | ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | |
| 1692 | E1000_CTRL_FD | E1000_CTRL_FRCDPX; |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1693 | |
| 1694 | /* set speed of 1000/Full if speed/duplex is forced */ |
| 1695 | reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; |
| 1696 | break; |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1697 | } |
| 1698 | |
| 1699 | wr32(E1000_CTRL, ctrl_reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1700 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1701 | /* New SerDes mode allows for forcing speed or autonegotiating speed |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1702 | * at 1gb. Autoneg should be default set by most drivers. This is the |
| 1703 | * mode that will be compatible with older link partners and switches. |
| 1704 | * However, both are supported by the hardware and some drivers/tools. |
| 1705 | */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1706 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
| 1707 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); |
| 1708 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1709 | if (pcs_autoneg) { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1710 | /* Set PCS register for autoneg */ |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1711 | reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ |
Alexander Duyck | 70d92f8 | 2009-10-05 06:31:47 +0000 | [diff] [blame] | 1712 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ |
Carolyn Wyborny | daf56e4 | 2012-10-23 12:54:33 +0000 | [diff] [blame] | 1713 | |
| 1714 | /* Disable force flow control for autoneg */ |
| 1715 | reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; |
| 1716 | |
| 1717 | /* Configure flow control advertisement for autoneg */ |
| 1718 | anadv_reg = rd32(E1000_PCS_ANADV); |
| 1719 | anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); |
| 1720 | switch (hw->fc.requested_mode) { |
| 1721 | case e1000_fc_full: |
| 1722 | case e1000_fc_rx_pause: |
| 1723 | anadv_reg |= E1000_TXCW_ASM_DIR; |
| 1724 | anadv_reg |= E1000_TXCW_PAUSE; |
| 1725 | break; |
| 1726 | case e1000_fc_tx_pause: |
| 1727 | anadv_reg |= E1000_TXCW_ASM_DIR; |
| 1728 | break; |
| 1729 | default: |
| 1730 | break; |
| 1731 | } |
| 1732 | wr32(E1000_PCS_ANADV, anadv_reg); |
| 1733 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1734 | hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1735 | } else { |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1736 | /* Set PCS register for forced link */ |
Alexander Duyck | d68caec | 2009-12-23 13:20:47 +0000 | [diff] [blame] | 1737 | reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ |
Alexander Duyck | 70d92f8 | 2009-10-05 06:31:47 +0000 | [diff] [blame] | 1738 | |
Carolyn Wyborny | daf56e4 | 2012-10-23 12:54:33 +0000 | [diff] [blame] | 1739 | /* Force flow control for forced link */ |
| 1740 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; |
| 1741 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 1742 | hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1743 | } |
Alexander Duyck | 726c09e | 2008-08-04 14:59:56 -0700 | [diff] [blame] | 1744 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1745 | wr32(E1000_PCS_LCTL, reg); |
| 1746 | |
Carolyn Wyborny | daf56e4 | 2012-10-23 12:54:33 +0000 | [diff] [blame] | 1747 | if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1748 | igb_force_mac_fc(hw); |
| 1749 | |
Carolyn Wyborny | 2c670b5 | 2011-05-24 06:52:51 +0000 | [diff] [blame] | 1750 | return ret_val; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1751 | } |
| 1752 | |
| 1753 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1754 | * igb_sgmii_active_82575 - Return sgmii state |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1755 | * @hw: pointer to the HW structure |
| 1756 | * |
| 1757 | * 82575 silicon has a serialized gigabit media independent interface (sgmii) |
| 1758 | * which can be enabled for use in the embedded applications. Simply |
| 1759 | * return the current state of the sgmii interface. |
| 1760 | **/ |
| 1761 | static bool igb_sgmii_active_82575(struct e1000_hw *hw) |
| 1762 | { |
Alexander Duyck | c1889bf | 2009-02-06 23:16:45 +0000 | [diff] [blame] | 1763 | struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; |
Alexander Duyck | c1889bf | 2009-02-06 23:16:45 +0000 | [diff] [blame] | 1764 | return dev_spec->sgmii_active; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1765 | } |
| 1766 | |
| 1767 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1768 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1769 | * @hw: pointer to the HW structure |
| 1770 | * |
| 1771 | * Inits recommended HW defaults after a reset when there is no EEPROM |
| 1772 | * detected. This is only for the 82575. |
| 1773 | **/ |
| 1774 | static s32 igb_reset_init_script_82575(struct e1000_hw *hw) |
| 1775 | { |
| 1776 | if (hw->mac.type == e1000_82575) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1777 | hw_dbg("Running reset init script for 82575\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1778 | /* SerDes configuration via SERDESCTRL */ |
| 1779 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); |
| 1780 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); |
| 1781 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); |
| 1782 | igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); |
| 1783 | |
| 1784 | /* CCM configuration via CCMCTL register */ |
| 1785 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); |
| 1786 | igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); |
| 1787 | |
| 1788 | /* PCIe lanes configuration */ |
| 1789 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); |
| 1790 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); |
| 1791 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); |
| 1792 | igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); |
| 1793 | |
| 1794 | /* PCIe PLL Configuration */ |
| 1795 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); |
| 1796 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); |
| 1797 | igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); |
| 1798 | } |
| 1799 | |
| 1800 | return 0; |
| 1801 | } |
| 1802 | |
| 1803 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1804 | * igb_read_mac_addr_82575 - Read device MAC address |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1805 | * @hw: pointer to the HW structure |
| 1806 | **/ |
| 1807 | static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) |
| 1808 | { |
| 1809 | s32 ret_val = 0; |
| 1810 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1811 | /* If there's an alternate MAC address place it in RAR0 |
Alexander Duyck | 2289663 | 2009-10-05 06:34:25 +0000 | [diff] [blame] | 1812 | * so that it will override the Si installed default perm |
| 1813 | * address. |
| 1814 | */ |
| 1815 | ret_val = igb_check_alt_mac_addr(hw); |
| 1816 | if (ret_val) |
| 1817 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1818 | |
Alexander Duyck | 2289663 | 2009-10-05 06:34:25 +0000 | [diff] [blame] | 1819 | ret_val = igb_read_mac_addr(hw); |
| 1820 | |
| 1821 | out: |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1822 | return ret_val; |
| 1823 | } |
| 1824 | |
| 1825 | /** |
Nick Nunley | 88a268c | 2010-02-17 01:01:59 +0000 | [diff] [blame] | 1826 | * igb_power_down_phy_copper_82575 - Remove link during PHY power down |
| 1827 | * @hw: pointer to the HW structure |
| 1828 | * |
| 1829 | * In the case of a PHY power down to save power, or to turn off link during a |
| 1830 | * driver unload, or wake on lan is not enabled, remove the link. |
| 1831 | **/ |
| 1832 | void igb_power_down_phy_copper_82575(struct e1000_hw *hw) |
| 1833 | { |
| 1834 | /* If the management interface is not enabled, then power down */ |
| 1835 | if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) |
| 1836 | igb_power_down_phy_copper(hw); |
Nick Nunley | 88a268c | 2010-02-17 01:01:59 +0000 | [diff] [blame] | 1837 | } |
| 1838 | |
| 1839 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1840 | * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1841 | * @hw: pointer to the HW structure |
| 1842 | * |
| 1843 | * Clears the hardware counters by reading the counter registers. |
| 1844 | **/ |
| 1845 | static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) |
| 1846 | { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1847 | igb_clear_hw_cntrs_base(hw); |
| 1848 | |
Alexander Duyck | cc9073b | 2009-10-05 06:31:25 +0000 | [diff] [blame] | 1849 | rd32(E1000_PRC64); |
| 1850 | rd32(E1000_PRC127); |
| 1851 | rd32(E1000_PRC255); |
| 1852 | rd32(E1000_PRC511); |
| 1853 | rd32(E1000_PRC1023); |
| 1854 | rd32(E1000_PRC1522); |
| 1855 | rd32(E1000_PTC64); |
| 1856 | rd32(E1000_PTC127); |
| 1857 | rd32(E1000_PTC255); |
| 1858 | rd32(E1000_PTC511); |
| 1859 | rd32(E1000_PTC1023); |
| 1860 | rd32(E1000_PTC1522); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1861 | |
Alexander Duyck | cc9073b | 2009-10-05 06:31:25 +0000 | [diff] [blame] | 1862 | rd32(E1000_ALGNERRC); |
| 1863 | rd32(E1000_RXERRC); |
| 1864 | rd32(E1000_TNCRS); |
| 1865 | rd32(E1000_CEXTERR); |
| 1866 | rd32(E1000_TSCTC); |
| 1867 | rd32(E1000_TSCTFC); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1868 | |
Alexander Duyck | cc9073b | 2009-10-05 06:31:25 +0000 | [diff] [blame] | 1869 | rd32(E1000_MGTPRC); |
| 1870 | rd32(E1000_MGTPDC); |
| 1871 | rd32(E1000_MGTPTC); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1872 | |
Alexander Duyck | cc9073b | 2009-10-05 06:31:25 +0000 | [diff] [blame] | 1873 | rd32(E1000_IAC); |
| 1874 | rd32(E1000_ICRXOC); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1875 | |
Alexander Duyck | cc9073b | 2009-10-05 06:31:25 +0000 | [diff] [blame] | 1876 | rd32(E1000_ICRXPTC); |
| 1877 | rd32(E1000_ICRXATC); |
| 1878 | rd32(E1000_ICTXPTC); |
| 1879 | rd32(E1000_ICTXATC); |
| 1880 | rd32(E1000_ICTXQEC); |
| 1881 | rd32(E1000_ICTXQMTC); |
| 1882 | rd32(E1000_ICRXDMTC); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1883 | |
Alexander Duyck | cc9073b | 2009-10-05 06:31:25 +0000 | [diff] [blame] | 1884 | rd32(E1000_CBTMPC); |
| 1885 | rd32(E1000_HTDPMC); |
| 1886 | rd32(E1000_CBRMPC); |
| 1887 | rd32(E1000_RPTHC); |
| 1888 | rd32(E1000_HGPTC); |
| 1889 | rd32(E1000_HTCBDPC); |
| 1890 | rd32(E1000_HGORCL); |
| 1891 | rd32(E1000_HGORCH); |
| 1892 | rd32(E1000_HGOTCL); |
| 1893 | rd32(E1000_HGOTCH); |
| 1894 | rd32(E1000_LENERRS); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1895 | |
| 1896 | /* This register should not be read in copper configurations */ |
Alexander Duyck | 2fb02a2 | 2009-09-14 08:22:54 +0000 | [diff] [blame] | 1897 | if (hw->phy.media_type == e1000_media_type_internal_serdes || |
| 1898 | igb_sgmii_active_82575(hw)) |
Alexander Duyck | cc9073b | 2009-10-05 06:31:25 +0000 | [diff] [blame] | 1899 | rd32(E1000_SCVPC); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1900 | } |
| 1901 | |
Alexander Duyck | 662d720 | 2008-06-27 11:00:29 -0700 | [diff] [blame] | 1902 | /** |
| 1903 | * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable |
| 1904 | * @hw: pointer to the HW structure |
| 1905 | * |
| 1906 | * After rx enable if managability is enabled then there is likely some |
| 1907 | * bad data at the start of the fifo and possibly in the DMA fifo. This |
| 1908 | * function clears the fifos and flushes any packets that came in as rx was |
| 1909 | * being enabled. |
| 1910 | **/ |
| 1911 | void igb_rx_fifo_flush_82575(struct e1000_hw *hw) |
| 1912 | { |
| 1913 | u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; |
| 1914 | int i, ms_wait; |
| 1915 | |
| 1916 | if (hw->mac.type != e1000_82575 || |
| 1917 | !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) |
| 1918 | return; |
| 1919 | |
| 1920 | /* Disable all RX queues */ |
| 1921 | for (i = 0; i < 4; i++) { |
| 1922 | rxdctl[i] = rd32(E1000_RXDCTL(i)); |
| 1923 | wr32(E1000_RXDCTL(i), |
| 1924 | rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); |
| 1925 | } |
| 1926 | /* Poll all queues to verify they have shut down */ |
| 1927 | for (ms_wait = 0; ms_wait < 10; ms_wait++) { |
| 1928 | msleep(1); |
| 1929 | rx_enabled = 0; |
| 1930 | for (i = 0; i < 4; i++) |
| 1931 | rx_enabled |= rd32(E1000_RXDCTL(i)); |
| 1932 | if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) |
| 1933 | break; |
| 1934 | } |
| 1935 | |
| 1936 | if (ms_wait == 10) |
| 1937 | hw_dbg("Queue disable timed out after 10ms\n"); |
| 1938 | |
| 1939 | /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all |
| 1940 | * incoming packets are rejected. Set enable and wait 2ms so that |
| 1941 | * any packet that was coming in as RCTL.EN was set is flushed |
| 1942 | */ |
| 1943 | rfctl = rd32(E1000_RFCTL); |
| 1944 | wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); |
| 1945 | |
| 1946 | rlpml = rd32(E1000_RLPML); |
| 1947 | wr32(E1000_RLPML, 0); |
| 1948 | |
| 1949 | rctl = rd32(E1000_RCTL); |
| 1950 | temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); |
| 1951 | temp_rctl |= E1000_RCTL_LPE; |
| 1952 | |
| 1953 | wr32(E1000_RCTL, temp_rctl); |
| 1954 | wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); |
| 1955 | wrfl(); |
| 1956 | msleep(2); |
| 1957 | |
| 1958 | /* Enable RX queues that were previously enabled and restore our |
| 1959 | * previous state |
| 1960 | */ |
| 1961 | for (i = 0; i < 4; i++) |
| 1962 | wr32(E1000_RXDCTL(i), rxdctl[i]); |
| 1963 | wr32(E1000_RCTL, rctl); |
| 1964 | wrfl(); |
| 1965 | |
| 1966 | wr32(E1000_RLPML, rlpml); |
| 1967 | wr32(E1000_RFCTL, rfctl); |
| 1968 | |
| 1969 | /* Flush receive errors generated by workaround */ |
| 1970 | rd32(E1000_ROC); |
| 1971 | rd32(E1000_RNBC); |
| 1972 | rd32(E1000_MPC); |
| 1973 | } |
| 1974 | |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 1975 | /** |
Alexander Duyck | 009bc06 | 2009-07-23 18:08:35 +0000 | [diff] [blame] | 1976 | * igb_set_pcie_completion_timeout - set pci-e completion timeout |
| 1977 | * @hw: pointer to the HW structure |
| 1978 | * |
| 1979 | * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, |
| 1980 | * however the hardware default for these parts is 500us to 1ms which is less |
| 1981 | * than the 10ms recommended by the pci-e spec. To address this we need to |
| 1982 | * increase the value to either 10ms to 200ms for capability version 1 config, |
| 1983 | * or 16ms to 55ms for version 2. |
| 1984 | **/ |
| 1985 | static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) |
| 1986 | { |
| 1987 | u32 gcr = rd32(E1000_GCR); |
| 1988 | s32 ret_val = 0; |
| 1989 | u16 pcie_devctl2; |
| 1990 | |
| 1991 | /* only take action if timeout value is defaulted to 0 */ |
| 1992 | if (gcr & E1000_GCR_CMPL_TMOUT_MASK) |
| 1993 | goto out; |
| 1994 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1995 | /* if capabilities version is type 1 we can write the |
Alexander Duyck | 009bc06 | 2009-07-23 18:08:35 +0000 | [diff] [blame] | 1996 | * timeout of 10ms to 200ms through the GCR register |
| 1997 | */ |
| 1998 | if (!(gcr & E1000_GCR_CAP_VER2)) { |
| 1999 | gcr |= E1000_GCR_CMPL_TMOUT_10ms; |
| 2000 | goto out; |
| 2001 | } |
| 2002 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2003 | /* for version 2 capabilities we need to write the config space |
Alexander Duyck | 009bc06 | 2009-07-23 18:08:35 +0000 | [diff] [blame] | 2004 | * directly in order to set the completion timeout value for |
| 2005 | * 16ms to 55ms |
| 2006 | */ |
| 2007 | ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, |
| 2008 | &pcie_devctl2); |
| 2009 | if (ret_val) |
| 2010 | goto out; |
| 2011 | |
| 2012 | pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; |
| 2013 | |
| 2014 | ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, |
| 2015 | &pcie_devctl2); |
| 2016 | out: |
| 2017 | /* disable completion timeout resend */ |
| 2018 | gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; |
| 2019 | |
| 2020 | wr32(E1000_GCR, gcr); |
| 2021 | return ret_val; |
| 2022 | } |
| 2023 | |
| 2024 | /** |
Greg Rose | 1380046 | 2010-11-06 02:08:26 +0000 | [diff] [blame] | 2025 | * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing |
| 2026 | * @hw: pointer to the hardware struct |
| 2027 | * @enable: state to enter, either enabled or disabled |
| 2028 | * @pf: Physical Function pool - do not set anti-spoofing for the PF |
| 2029 | * |
| 2030 | * enables/disables L2 switch anti-spoofing functionality. |
| 2031 | **/ |
| 2032 | void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) |
| 2033 | { |
Lior Levy | 22c1275 | 2013-03-12 15:49:32 +0000 | [diff] [blame] | 2034 | u32 reg_val, reg_offset; |
Greg Rose | 1380046 | 2010-11-06 02:08:26 +0000 | [diff] [blame] | 2035 | |
| 2036 | switch (hw->mac.type) { |
| 2037 | case e1000_82576: |
Lior Levy | 22c1275 | 2013-03-12 15:49:32 +0000 | [diff] [blame] | 2038 | reg_offset = E1000_DTXSWC; |
| 2039 | break; |
Greg Rose | 1380046 | 2010-11-06 02:08:26 +0000 | [diff] [blame] | 2040 | case e1000_i350: |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2041 | case e1000_i354: |
Lior Levy | 22c1275 | 2013-03-12 15:49:32 +0000 | [diff] [blame] | 2042 | reg_offset = E1000_TXSWC; |
Greg Rose | 1380046 | 2010-11-06 02:08:26 +0000 | [diff] [blame] | 2043 | break; |
| 2044 | default: |
Lior Levy | 22c1275 | 2013-03-12 15:49:32 +0000 | [diff] [blame] | 2045 | return; |
Greg Rose | 1380046 | 2010-11-06 02:08:26 +0000 | [diff] [blame] | 2046 | } |
Lior Levy | 22c1275 | 2013-03-12 15:49:32 +0000 | [diff] [blame] | 2047 | |
| 2048 | reg_val = rd32(reg_offset); |
| 2049 | if (enable) { |
| 2050 | reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | |
| 2051 | E1000_DTXSWC_VLAN_SPOOF_MASK); |
| 2052 | /* The PF can spoof - it has to in order to |
| 2053 | * support emulation mode NICs |
| 2054 | */ |
| 2055 | reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); |
| 2056 | } else { |
| 2057 | reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | |
| 2058 | E1000_DTXSWC_VLAN_SPOOF_MASK); |
| 2059 | } |
| 2060 | wr32(reg_offset, reg_val); |
Greg Rose | 1380046 | 2010-11-06 02:08:26 +0000 | [diff] [blame] | 2061 | } |
| 2062 | |
| 2063 | /** |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 2064 | * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback |
| 2065 | * @hw: pointer to the hardware struct |
| 2066 | * @enable: state to enter, either enabled or disabled |
| 2067 | * |
| 2068 | * enables/disables L2 switch loopback functionality. |
| 2069 | **/ |
| 2070 | void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) |
| 2071 | { |
Akeem G. Abodunrin | ca2e3e7 | 2011-09-08 20:39:48 +0000 | [diff] [blame] | 2072 | u32 dtxswc; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 2073 | |
Akeem G. Abodunrin | ca2e3e7 | 2011-09-08 20:39:48 +0000 | [diff] [blame] | 2074 | switch (hw->mac.type) { |
| 2075 | case e1000_82576: |
| 2076 | dtxswc = rd32(E1000_DTXSWC); |
| 2077 | if (enable) |
| 2078 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; |
| 2079 | else |
| 2080 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; |
| 2081 | wr32(E1000_DTXSWC, dtxswc); |
| 2082 | break; |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2083 | case e1000_i354: |
Akeem G. Abodunrin | ca2e3e7 | 2011-09-08 20:39:48 +0000 | [diff] [blame] | 2084 | case e1000_i350: |
| 2085 | dtxswc = rd32(E1000_TXSWC); |
| 2086 | if (enable) |
| 2087 | dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; |
| 2088 | else |
| 2089 | dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; |
| 2090 | wr32(E1000_TXSWC, dtxswc); |
| 2091 | break; |
| 2092 | default: |
| 2093 | /* Currently no other hardware supports loopback */ |
| 2094 | break; |
| 2095 | } |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 2096 | |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 2097 | } |
| 2098 | |
| 2099 | /** |
| 2100 | * igb_vmdq_set_replication_pf - enable or disable vmdq replication |
| 2101 | * @hw: pointer to the hardware struct |
| 2102 | * @enable: state to enter, either enabled or disabled |
| 2103 | * |
| 2104 | * enables/disables replication of packets across multiple pools. |
| 2105 | **/ |
| 2106 | void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) |
| 2107 | { |
| 2108 | u32 vt_ctl = rd32(E1000_VT_CTL); |
| 2109 | |
| 2110 | if (enable) |
| 2111 | vt_ctl |= E1000_VT_CTL_VM_REPL_EN; |
| 2112 | else |
| 2113 | vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; |
| 2114 | |
| 2115 | wr32(E1000_VT_CTL, vt_ctl); |
| 2116 | } |
| 2117 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2118 | /** |
| 2119 | * igb_read_phy_reg_82580 - Read 82580 MDI control register |
| 2120 | * @hw: pointer to the HW structure |
| 2121 | * @offset: register offset to be read |
| 2122 | * @data: pointer to the read data |
| 2123 | * |
| 2124 | * Reads the MDI control register in the PHY at offset and stores the |
| 2125 | * information read to data. |
| 2126 | **/ |
| 2127 | static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2128 | { |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2129 | s32 ret_val; |
| 2130 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2131 | ret_val = hw->phy.ops.acquire(hw); |
| 2132 | if (ret_val) |
| 2133 | goto out; |
| 2134 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2135 | ret_val = igb_read_phy_reg_mdic(hw, offset, data); |
| 2136 | |
| 2137 | hw->phy.ops.release(hw); |
| 2138 | |
| 2139 | out: |
| 2140 | return ret_val; |
| 2141 | } |
| 2142 | |
| 2143 | /** |
| 2144 | * igb_write_phy_reg_82580 - Write 82580 MDI control register |
| 2145 | * @hw: pointer to the HW structure |
| 2146 | * @offset: register offset to write to |
| 2147 | * @data: data to write to register at offset |
| 2148 | * |
| 2149 | * Writes data to MDI control register in the PHY at offset. |
| 2150 | **/ |
| 2151 | static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) |
| 2152 | { |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2153 | s32 ret_val; |
| 2154 | |
| 2155 | |
| 2156 | ret_val = hw->phy.ops.acquire(hw); |
| 2157 | if (ret_val) |
| 2158 | goto out; |
| 2159 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2160 | ret_val = igb_write_phy_reg_mdic(hw, offset, data); |
| 2161 | |
| 2162 | hw->phy.ops.release(hw); |
| 2163 | |
| 2164 | out: |
| 2165 | return ret_val; |
| 2166 | } |
| 2167 | |
| 2168 | /** |
Nick Nunley | 08451e2 | 2010-07-26 13:15:29 +0000 | [diff] [blame] | 2169 | * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits |
| 2170 | * @hw: pointer to the HW structure |
| 2171 | * |
| 2172 | * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on |
| 2173 | * the values found in the EEPROM. This addresses an issue in which these |
| 2174 | * bits are not restored from EEPROM after reset. |
| 2175 | **/ |
| 2176 | static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) |
| 2177 | { |
| 2178 | s32 ret_val = 0; |
| 2179 | u32 mdicnfg; |
Gasparakis, Joseph | 1b5dda3 | 2010-12-09 01:41:01 +0000 | [diff] [blame] | 2180 | u16 nvm_data = 0; |
Nick Nunley | 08451e2 | 2010-07-26 13:15:29 +0000 | [diff] [blame] | 2181 | |
| 2182 | if (hw->mac.type != e1000_82580) |
| 2183 | goto out; |
| 2184 | if (!igb_sgmii_active_82575(hw)) |
| 2185 | goto out; |
| 2186 | |
| 2187 | ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + |
| 2188 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, |
| 2189 | &nvm_data); |
| 2190 | if (ret_val) { |
| 2191 | hw_dbg("NVM Read Error\n"); |
| 2192 | goto out; |
| 2193 | } |
| 2194 | |
| 2195 | mdicnfg = rd32(E1000_MDICNFG); |
| 2196 | if (nvm_data & NVM_WORD24_EXT_MDIO) |
| 2197 | mdicnfg |= E1000_MDICNFG_EXT_MDIO; |
| 2198 | if (nvm_data & NVM_WORD24_COM_MDIO) |
| 2199 | mdicnfg |= E1000_MDICNFG_COM_MDIO; |
| 2200 | wr32(E1000_MDICNFG, mdicnfg); |
| 2201 | out: |
| 2202 | return ret_val; |
| 2203 | } |
| 2204 | |
| 2205 | /** |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2206 | * igb_reset_hw_82580 - Reset hardware |
| 2207 | * @hw: pointer to the HW structure |
| 2208 | * |
| 2209 | * This resets function or entire device (all ports, etc.) |
| 2210 | * to a known state. |
| 2211 | **/ |
| 2212 | static s32 igb_reset_hw_82580(struct e1000_hw *hw) |
| 2213 | { |
| 2214 | s32 ret_val = 0; |
| 2215 | /* BH SW mailbox bit in SW_FW_SYNC */ |
| 2216 | u16 swmbsw_mask = E1000_SW_SYNCH_MB; |
Akeem G Abodunrin | e5c3370 | 2013-06-06 01:31:09 +0000 | [diff] [blame] | 2217 | u32 ctrl; |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2218 | bool global_device_reset = hw->dev_spec._82575.global_device_reset; |
| 2219 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2220 | hw->dev_spec._82575.global_device_reset = false; |
| 2221 | |
Carolyn Wyborny | a0483e2 | 2012-11-22 01:24:08 +0000 | [diff] [blame] | 2222 | /* due to hw errata, global device reset doesn't always |
| 2223 | * work on 82580 |
| 2224 | */ |
| 2225 | if (hw->mac.type == e1000_82580) |
| 2226 | global_device_reset = false; |
| 2227 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2228 | /* Get current control state. */ |
| 2229 | ctrl = rd32(E1000_CTRL); |
| 2230 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2231 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2232 | * on the last TLP read/write transaction when MAC is reset. |
| 2233 | */ |
| 2234 | ret_val = igb_disable_pcie_master(hw); |
| 2235 | if (ret_val) |
| 2236 | hw_dbg("PCI-E Master disable polling has failed.\n"); |
| 2237 | |
| 2238 | hw_dbg("Masking off all interrupts\n"); |
| 2239 | wr32(E1000_IMC, 0xffffffff); |
| 2240 | wr32(E1000_RCTL, 0); |
| 2241 | wr32(E1000_TCTL, E1000_TCTL_PSP); |
| 2242 | wrfl(); |
| 2243 | |
| 2244 | msleep(10); |
| 2245 | |
| 2246 | /* Determine whether or not a global dev reset is requested */ |
| 2247 | if (global_device_reset && |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 2248 | hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2249 | global_device_reset = false; |
| 2250 | |
| 2251 | if (global_device_reset && |
| 2252 | !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) |
| 2253 | ctrl |= E1000_CTRL_DEV_RST; |
| 2254 | else |
| 2255 | ctrl |= E1000_CTRL_RST; |
| 2256 | |
| 2257 | wr32(E1000_CTRL, ctrl); |
Carolyn Wyborny | 064b433 | 2011-06-25 13:18:12 +0000 | [diff] [blame] | 2258 | wrfl(); |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2259 | |
| 2260 | /* Add delay to insure DEV_RST has time to complete */ |
| 2261 | if (global_device_reset) |
| 2262 | msleep(5); |
| 2263 | |
| 2264 | ret_val = igb_get_auto_rd_done(hw); |
| 2265 | if (ret_val) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2266 | /* When auto config read does not complete, do not |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2267 | * return with an error. This can happen in situations |
| 2268 | * where there is no eeprom and prevents getting link. |
| 2269 | */ |
| 2270 | hw_dbg("Auto Read Done did not complete\n"); |
| 2271 | } |
| 2272 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2273 | /* clear global device reset status bit */ |
| 2274 | wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); |
| 2275 | |
| 2276 | /* Clear any pending interrupt events. */ |
| 2277 | wr32(E1000_IMC, 0xffffffff); |
Akeem G Abodunrin | e5c3370 | 2013-06-06 01:31:09 +0000 | [diff] [blame] | 2278 | rd32(E1000_ICR); |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2279 | |
Nick Nunley | 08451e2 | 2010-07-26 13:15:29 +0000 | [diff] [blame] | 2280 | ret_val = igb_reset_mdicnfg_82580(hw); |
| 2281 | if (ret_val) |
| 2282 | hw_dbg("Could not reset MDICNFG based on EEPROM\n"); |
| 2283 | |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2284 | /* Install any alternate MAC address into RAR0 */ |
| 2285 | ret_val = igb_check_alt_mac_addr(hw); |
| 2286 | |
| 2287 | /* Release semaphore */ |
| 2288 | if (global_device_reset) |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 2289 | hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2290 | |
| 2291 | return ret_val; |
| 2292 | } |
| 2293 | |
| 2294 | /** |
| 2295 | * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size |
| 2296 | * @data: data received by reading RXPBS register |
| 2297 | * |
| 2298 | * The 82580 uses a table based approach for packet buffer allocation sizes. |
| 2299 | * This function converts the retrieved value into the correct table value |
| 2300 | * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 |
| 2301 | * 0x0 36 72 144 1 2 4 8 16 |
| 2302 | * 0x8 35 70 140 rsv rsv rsv rsv rsv |
| 2303 | */ |
| 2304 | u16 igb_rxpbs_adjust_82580(u32 data) |
| 2305 | { |
| 2306 | u16 ret_val = 0; |
| 2307 | |
Todd Fujinaka | 72b3672 | 2014-03-04 02:25:22 +0000 | [diff] [blame] | 2308 | if (data < ARRAY_SIZE(e1000_82580_rxpbs_table)) |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2309 | ret_val = e1000_82580_rxpbs_table[data]; |
| 2310 | |
| 2311 | return ret_val; |
| 2312 | } |
| 2313 | |
Carolyn Wyborny | 09b068d | 2011-03-11 20:42:13 -0800 | [diff] [blame] | 2314 | /** |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 2315 | * igb_validate_nvm_checksum_with_offset - Validate EEPROM |
| 2316 | * checksum |
| 2317 | * @hw: pointer to the HW structure |
| 2318 | * @offset: offset in words of the checksum protected region |
| 2319 | * |
| 2320 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
| 2321 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. |
| 2322 | **/ |
Emil Tantilov | bed45a6 | 2011-08-30 06:35:04 +0000 | [diff] [blame] | 2323 | static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, |
| 2324 | u16 offset) |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 2325 | { |
| 2326 | s32 ret_val = 0; |
| 2327 | u16 checksum = 0; |
| 2328 | u16 i, nvm_data; |
| 2329 | |
| 2330 | for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { |
| 2331 | ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); |
| 2332 | if (ret_val) { |
| 2333 | hw_dbg("NVM Read Error\n"); |
| 2334 | goto out; |
| 2335 | } |
| 2336 | checksum += nvm_data; |
| 2337 | } |
| 2338 | |
| 2339 | if (checksum != (u16) NVM_SUM) { |
| 2340 | hw_dbg("NVM Checksum Invalid\n"); |
| 2341 | ret_val = -E1000_ERR_NVM; |
| 2342 | goto out; |
| 2343 | } |
| 2344 | |
| 2345 | out: |
| 2346 | return ret_val; |
| 2347 | } |
| 2348 | |
| 2349 | /** |
| 2350 | * igb_update_nvm_checksum_with_offset - Update EEPROM |
| 2351 | * checksum |
| 2352 | * @hw: pointer to the HW structure |
| 2353 | * @offset: offset in words of the checksum protected region |
| 2354 | * |
| 2355 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM |
| 2356 | * up to the checksum. Then calculates the EEPROM checksum and writes the |
| 2357 | * value to the EEPROM. |
| 2358 | **/ |
Emil Tantilov | bed45a6 | 2011-08-30 06:35:04 +0000 | [diff] [blame] | 2359 | static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 2360 | { |
| 2361 | s32 ret_val; |
| 2362 | u16 checksum = 0; |
| 2363 | u16 i, nvm_data; |
| 2364 | |
| 2365 | for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { |
| 2366 | ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); |
| 2367 | if (ret_val) { |
| 2368 | hw_dbg("NVM Read Error while updating checksum.\n"); |
| 2369 | goto out; |
| 2370 | } |
| 2371 | checksum += nvm_data; |
| 2372 | } |
| 2373 | checksum = (u16) NVM_SUM - checksum; |
| 2374 | ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, |
| 2375 | &checksum); |
| 2376 | if (ret_val) |
| 2377 | hw_dbg("NVM Write Error while updating checksum.\n"); |
| 2378 | |
| 2379 | out: |
| 2380 | return ret_val; |
| 2381 | } |
| 2382 | |
| 2383 | /** |
| 2384 | * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum |
| 2385 | * @hw: pointer to the HW structure |
| 2386 | * |
| 2387 | * Calculates the EEPROM section checksum by reading/adding each word of |
| 2388 | * the EEPROM and then verifies that the sum of the EEPROM is |
| 2389 | * equal to 0xBABA. |
| 2390 | **/ |
| 2391 | static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) |
| 2392 | { |
| 2393 | s32 ret_val = 0; |
| 2394 | u16 eeprom_regions_count = 1; |
| 2395 | u16 j, nvm_data; |
| 2396 | u16 nvm_offset; |
| 2397 | |
| 2398 | ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); |
| 2399 | if (ret_val) { |
| 2400 | hw_dbg("NVM Read Error\n"); |
| 2401 | goto out; |
| 2402 | } |
| 2403 | |
| 2404 | if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { |
Stefan Assmann | 34a0326 | 2011-04-05 04:27:05 +0000 | [diff] [blame] | 2405 | /* if checksums compatibility bit is set validate checksums |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2406 | * for all 4 ports. |
| 2407 | */ |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 2408 | eeprom_regions_count = 4; |
| 2409 | } |
| 2410 | |
| 2411 | for (j = 0; j < eeprom_regions_count; j++) { |
| 2412 | nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); |
| 2413 | ret_val = igb_validate_nvm_checksum_with_offset(hw, |
| 2414 | nvm_offset); |
| 2415 | if (ret_val != 0) |
| 2416 | goto out; |
| 2417 | } |
| 2418 | |
| 2419 | out: |
| 2420 | return ret_val; |
| 2421 | } |
| 2422 | |
| 2423 | /** |
| 2424 | * igb_update_nvm_checksum_82580 - Update EEPROM checksum |
| 2425 | * @hw: pointer to the HW structure |
| 2426 | * |
| 2427 | * Updates the EEPROM section checksums for all 4 ports by reading/adding |
| 2428 | * each word of the EEPROM up to the checksum. Then calculates the EEPROM |
| 2429 | * checksum and writes the value to the EEPROM. |
| 2430 | **/ |
| 2431 | static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) |
| 2432 | { |
| 2433 | s32 ret_val; |
| 2434 | u16 j, nvm_data; |
| 2435 | u16 nvm_offset; |
| 2436 | |
| 2437 | ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); |
| 2438 | if (ret_val) { |
Carolyn Wyborny | c75c4ed | 2014-04-11 01:45:17 +0000 | [diff] [blame^] | 2439 | hw_dbg("NVM Read Error while updating checksum compatibility bit.\n"); |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 2440 | goto out; |
| 2441 | } |
| 2442 | |
| 2443 | if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { |
| 2444 | /* set compatibility bit to validate checksums appropriately */ |
| 2445 | nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; |
| 2446 | ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, |
| 2447 | &nvm_data); |
| 2448 | if (ret_val) { |
Carolyn Wyborny | c75c4ed | 2014-04-11 01:45:17 +0000 | [diff] [blame^] | 2449 | hw_dbg("NVM Write Error while updating checksum compatibility bit.\n"); |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 2450 | goto out; |
| 2451 | } |
| 2452 | } |
| 2453 | |
| 2454 | for (j = 0; j < 4; j++) { |
| 2455 | nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); |
| 2456 | ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); |
| 2457 | if (ret_val) |
| 2458 | goto out; |
| 2459 | } |
| 2460 | |
| 2461 | out: |
| 2462 | return ret_val; |
| 2463 | } |
| 2464 | |
| 2465 | /** |
| 2466 | * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum |
| 2467 | * @hw: pointer to the HW structure |
| 2468 | * |
| 2469 | * Calculates the EEPROM section checksum by reading/adding each word of |
| 2470 | * the EEPROM and then verifies that the sum of the EEPROM is |
| 2471 | * equal to 0xBABA. |
| 2472 | **/ |
| 2473 | static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) |
| 2474 | { |
| 2475 | s32 ret_val = 0; |
| 2476 | u16 j; |
| 2477 | u16 nvm_offset; |
| 2478 | |
| 2479 | for (j = 0; j < 4; j++) { |
| 2480 | nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); |
| 2481 | ret_val = igb_validate_nvm_checksum_with_offset(hw, |
| 2482 | nvm_offset); |
| 2483 | if (ret_val != 0) |
| 2484 | goto out; |
| 2485 | } |
| 2486 | |
| 2487 | out: |
| 2488 | return ret_val; |
| 2489 | } |
| 2490 | |
| 2491 | /** |
| 2492 | * igb_update_nvm_checksum_i350 - Update EEPROM checksum |
| 2493 | * @hw: pointer to the HW structure |
| 2494 | * |
| 2495 | * Updates the EEPROM section checksums for all 4 ports by reading/adding |
| 2496 | * each word of the EEPROM up to the checksum. Then calculates the EEPROM |
| 2497 | * checksum and writes the value to the EEPROM. |
| 2498 | **/ |
| 2499 | static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) |
| 2500 | { |
| 2501 | s32 ret_val = 0; |
| 2502 | u16 j; |
| 2503 | u16 nvm_offset; |
| 2504 | |
| 2505 | for (j = 0; j < 4; j++) { |
| 2506 | nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); |
| 2507 | ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); |
| 2508 | if (ret_val != 0) |
| 2509 | goto out; |
| 2510 | } |
| 2511 | |
| 2512 | out: |
| 2513 | return ret_val; |
| 2514 | } |
Stefan Assmann | 34a0326 | 2011-04-05 04:27:05 +0000 | [diff] [blame] | 2515 | |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 2516 | /** |
Matthew Vick | 87371b9 | 2013-02-21 03:32:52 +0000 | [diff] [blame] | 2517 | * __igb_access_emi_reg - Read/write EMI register |
| 2518 | * @hw: pointer to the HW structure |
| 2519 | * @addr: EMI address to program |
| 2520 | * @data: pointer to value to read/write from/to the EMI address |
| 2521 | * @read: boolean flag to indicate read or write |
| 2522 | **/ |
| 2523 | static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, |
| 2524 | u16 *data, bool read) |
| 2525 | { |
| 2526 | s32 ret_val = E1000_SUCCESS; |
| 2527 | |
| 2528 | ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); |
| 2529 | if (ret_val) |
| 2530 | return ret_val; |
| 2531 | |
| 2532 | if (read) |
| 2533 | ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); |
| 2534 | else |
| 2535 | ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); |
| 2536 | |
| 2537 | return ret_val; |
| 2538 | } |
| 2539 | |
| 2540 | /** |
| 2541 | * igb_read_emi_reg - Read Extended Management Interface register |
| 2542 | * @hw: pointer to the HW structure |
| 2543 | * @addr: EMI address to program |
| 2544 | * @data: value to be read from the EMI address |
| 2545 | **/ |
| 2546 | s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) |
| 2547 | { |
| 2548 | return __igb_access_emi_reg(hw, addr, data, true); |
| 2549 | } |
| 2550 | |
| 2551 | /** |
Carolyn Wyborny | 09b068d | 2011-03-11 20:42:13 -0800 | [diff] [blame] | 2552 | * igb_set_eee_i350 - Enable/disable EEE support |
| 2553 | * @hw: pointer to the HW structure |
| 2554 | * |
| 2555 | * Enable/disable EEE based on setting in dev_spec structure. |
| 2556 | * |
| 2557 | **/ |
| 2558 | s32 igb_set_eee_i350(struct e1000_hw *hw) |
| 2559 | { |
| 2560 | s32 ret_val = 0; |
Akeem G. Abodunrin | e546111 | 2012-09-06 01:28:31 +0000 | [diff] [blame] | 2561 | u32 ipcnfg, eeer; |
Carolyn Wyborny | 09b068d | 2011-03-11 20:42:13 -0800 | [diff] [blame] | 2562 | |
Akeem G. Abodunrin | e546111 | 2012-09-06 01:28:31 +0000 | [diff] [blame] | 2563 | if ((hw->mac.type < e1000_i350) || |
| 2564 | (hw->phy.media_type != e1000_media_type_copper)) |
Carolyn Wyborny | 09b068d | 2011-03-11 20:42:13 -0800 | [diff] [blame] | 2565 | goto out; |
| 2566 | ipcnfg = rd32(E1000_IPCNFG); |
| 2567 | eeer = rd32(E1000_EEER); |
| 2568 | |
| 2569 | /* enable or disable per user setting */ |
| 2570 | if (!(hw->dev_spec._82575.eee_disable)) { |
Carolyn Wyborny | 40b2012 | 2012-10-19 05:31:43 +0000 | [diff] [blame] | 2571 | u32 eee_su = rd32(E1000_EEE_SU); |
| 2572 | |
| 2573 | ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); |
| 2574 | eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | |
Carolyn Wyborny | 09b068d | 2011-03-11 20:42:13 -0800 | [diff] [blame] | 2575 | E1000_EEER_LPI_FC); |
| 2576 | |
Carolyn Wyborny | 40b2012 | 2012-10-19 05:31:43 +0000 | [diff] [blame] | 2577 | /* This bit should not be set in normal operation. */ |
| 2578 | if (eee_su & E1000_EEE_SU_LPI_CLK_STP) |
| 2579 | hw_dbg("LPI Clock Stop Bit should not be set!\n"); |
| 2580 | |
Carolyn Wyborny | 09b068d | 2011-03-11 20:42:13 -0800 | [diff] [blame] | 2581 | } else { |
| 2582 | ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | |
| 2583 | E1000_IPCNFG_EEE_100M_AN); |
| 2584 | eeer &= ~(E1000_EEER_TX_LPI_EN | |
| 2585 | E1000_EEER_RX_LPI_EN | |
| 2586 | E1000_EEER_LPI_FC); |
| 2587 | } |
| 2588 | wr32(E1000_IPCNFG, ipcnfg); |
| 2589 | wr32(E1000_EEER, eeer); |
Akeem G. Abodunrin | e546111 | 2012-09-06 01:28:31 +0000 | [diff] [blame] | 2590 | rd32(E1000_IPCNFG); |
| 2591 | rd32(E1000_EEER); |
Carolyn Wyborny | 09b068d | 2011-03-11 20:42:13 -0800 | [diff] [blame] | 2592 | out: |
| 2593 | |
| 2594 | return ret_val; |
| 2595 | } |
Carolyn Wyborny | 4322e56 | 2011-03-11 20:43:18 -0800 | [diff] [blame] | 2596 | |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2597 | /** |
| 2598 | * igb_set_eee_i354 - Enable/disable EEE support |
| 2599 | * @hw: pointer to the HW structure |
| 2600 | * |
| 2601 | * Enable/disable EEE legacy mode based on setting in dev_spec structure. |
| 2602 | * |
| 2603 | **/ |
| 2604 | s32 igb_set_eee_i354(struct e1000_hw *hw) |
| 2605 | { |
| 2606 | struct e1000_phy_info *phy = &hw->phy; |
| 2607 | s32 ret_val = 0; |
| 2608 | u16 phy_data; |
| 2609 | |
| 2610 | if ((hw->phy.media_type != e1000_media_type_copper) || |
Akeem G Abodunrin | 99af472 | 2013-08-28 02:22:58 +0000 | [diff] [blame] | 2611 | (phy->id != M88E1543_E_PHY_ID)) |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2612 | goto out; |
| 2613 | |
| 2614 | if (!hw->dev_spec._82575.eee_disable) { |
| 2615 | /* Switch to PHY page 18. */ |
Akeem G Abodunrin | 99af472 | 2013-08-28 02:22:58 +0000 | [diff] [blame] | 2616 | ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2617 | if (ret_val) |
| 2618 | goto out; |
| 2619 | |
Akeem G Abodunrin | 99af472 | 2013-08-28 02:22:58 +0000 | [diff] [blame] | 2620 | ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2621 | &phy_data); |
| 2622 | if (ret_val) |
| 2623 | goto out; |
| 2624 | |
Akeem G Abodunrin | 99af472 | 2013-08-28 02:22:58 +0000 | [diff] [blame] | 2625 | phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; |
| 2626 | ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2627 | phy_data); |
| 2628 | if (ret_val) |
| 2629 | goto out; |
| 2630 | |
| 2631 | /* Return the PHY to page 0. */ |
Akeem G Abodunrin | 99af472 | 2013-08-28 02:22:58 +0000 | [diff] [blame] | 2632 | ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2633 | if (ret_val) |
| 2634 | goto out; |
| 2635 | |
| 2636 | /* Turn on EEE advertisement. */ |
| 2637 | ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, |
| 2638 | E1000_EEE_ADV_DEV_I354, |
| 2639 | &phy_data); |
| 2640 | if (ret_val) |
| 2641 | goto out; |
| 2642 | |
| 2643 | phy_data |= E1000_EEE_ADV_100_SUPPORTED | |
| 2644 | E1000_EEE_ADV_1000_SUPPORTED; |
| 2645 | ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, |
| 2646 | E1000_EEE_ADV_DEV_I354, |
| 2647 | phy_data); |
| 2648 | } else { |
| 2649 | /* Turn off EEE advertisement. */ |
| 2650 | ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, |
| 2651 | E1000_EEE_ADV_DEV_I354, |
| 2652 | &phy_data); |
| 2653 | if (ret_val) |
| 2654 | goto out; |
| 2655 | |
| 2656 | phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | |
| 2657 | E1000_EEE_ADV_1000_SUPPORTED); |
| 2658 | ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, |
| 2659 | E1000_EEE_ADV_DEV_I354, |
| 2660 | phy_data); |
| 2661 | } |
| 2662 | |
| 2663 | out: |
| 2664 | return ret_val; |
| 2665 | } |
| 2666 | |
| 2667 | /** |
| 2668 | * igb_get_eee_status_i354 - Get EEE status |
| 2669 | * @hw: pointer to the HW structure |
| 2670 | * @status: EEE status |
| 2671 | * |
| 2672 | * Get EEE status by guessing based on whether Tx or Rx LPI indications have |
| 2673 | * been received. |
| 2674 | **/ |
| 2675 | s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) |
| 2676 | { |
| 2677 | struct e1000_phy_info *phy = &hw->phy; |
| 2678 | s32 ret_val = 0; |
| 2679 | u16 phy_data; |
| 2680 | |
| 2681 | /* Check if EEE is supported on this device. */ |
| 2682 | if ((hw->phy.media_type != e1000_media_type_copper) || |
Akeem G Abodunrin | 99af472 | 2013-08-28 02:22:58 +0000 | [diff] [blame] | 2683 | (phy->id != M88E1543_E_PHY_ID)) |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 2684 | goto out; |
| 2685 | |
| 2686 | ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, |
| 2687 | E1000_PCS_STATUS_DEV_I354, |
| 2688 | &phy_data); |
| 2689 | if (ret_val) |
| 2690 | goto out; |
| 2691 | |
| 2692 | *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | |
| 2693 | E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false; |
| 2694 | |
| 2695 | out: |
| 2696 | return ret_val; |
| 2697 | } |
| 2698 | |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 2699 | static const u8 e1000_emc_temp_data[4] = { |
| 2700 | E1000_EMC_INTERNAL_DATA, |
| 2701 | E1000_EMC_DIODE1_DATA, |
| 2702 | E1000_EMC_DIODE2_DATA, |
| 2703 | E1000_EMC_DIODE3_DATA |
| 2704 | }; |
| 2705 | static const u8 e1000_emc_therm_limit[4] = { |
| 2706 | E1000_EMC_INTERNAL_THERM_LIMIT, |
| 2707 | E1000_EMC_DIODE1_THERM_LIMIT, |
| 2708 | E1000_EMC_DIODE2_THERM_LIMIT, |
| 2709 | E1000_EMC_DIODE3_THERM_LIMIT |
| 2710 | }; |
| 2711 | |
Jeff Kirsher | 9b143d1 | 2014-03-06 05:28:06 +0000 | [diff] [blame] | 2712 | #ifdef CONFIG_IGB_HWMON |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2713 | /** |
| 2714 | * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 2715 | * @hw: pointer to hardware structure |
| 2716 | * |
| 2717 | * Updates the temperatures in mac.thermal_sensor_data |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2718 | **/ |
Jeff Kirsher | 167f3f7 | 2014-02-25 17:58:56 -0800 | [diff] [blame] | 2719 | static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 2720 | { |
| 2721 | s32 status = E1000_SUCCESS; |
| 2722 | u16 ets_offset; |
| 2723 | u16 ets_cfg; |
| 2724 | u16 ets_sensor; |
| 2725 | u8 num_sensors; |
| 2726 | u8 sensor_index; |
| 2727 | u8 sensor_location; |
| 2728 | u8 i; |
| 2729 | struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; |
| 2730 | |
| 2731 | if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) |
| 2732 | return E1000_NOT_IMPLEMENTED; |
| 2733 | |
| 2734 | data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); |
| 2735 | |
| 2736 | /* Return the internal sensor only if ETS is unsupported */ |
| 2737 | hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); |
| 2738 | if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) |
| 2739 | return status; |
| 2740 | |
| 2741 | hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); |
| 2742 | if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) |
| 2743 | != NVM_ETS_TYPE_EMC) |
| 2744 | return E1000_NOT_IMPLEMENTED; |
| 2745 | |
| 2746 | num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); |
| 2747 | if (num_sensors > E1000_MAX_SENSORS) |
| 2748 | num_sensors = E1000_MAX_SENSORS; |
| 2749 | |
| 2750 | for (i = 1; i < num_sensors; i++) { |
| 2751 | hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); |
| 2752 | sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> |
| 2753 | NVM_ETS_DATA_INDEX_SHIFT); |
| 2754 | sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> |
| 2755 | NVM_ETS_DATA_LOC_SHIFT); |
| 2756 | |
| 2757 | if (sensor_location != 0) |
| 2758 | hw->phy.ops.read_i2c_byte(hw, |
| 2759 | e1000_emc_temp_data[sensor_index], |
| 2760 | E1000_I2C_THERMAL_SENSOR_ADDR, |
| 2761 | &data->sensor[i].temp); |
| 2762 | } |
| 2763 | return status; |
| 2764 | } |
| 2765 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2766 | /** |
| 2767 | * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 2768 | * @hw: pointer to hardware structure |
| 2769 | * |
| 2770 | * Sets the thermal sensor thresholds according to the NVM map |
| 2771 | * and save off the threshold and location values into mac.thermal_sensor_data |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2772 | **/ |
Jeff Kirsher | 167f3f7 | 2014-02-25 17:58:56 -0800 | [diff] [blame] | 2773 | static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 2774 | { |
| 2775 | s32 status = E1000_SUCCESS; |
| 2776 | u16 ets_offset; |
| 2777 | u16 ets_cfg; |
| 2778 | u16 ets_sensor; |
| 2779 | u8 low_thresh_delta; |
| 2780 | u8 num_sensors; |
| 2781 | u8 sensor_index; |
| 2782 | u8 sensor_location; |
| 2783 | u8 therm_limit; |
| 2784 | u8 i; |
| 2785 | struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; |
| 2786 | |
| 2787 | if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) |
| 2788 | return E1000_NOT_IMPLEMENTED; |
| 2789 | |
| 2790 | memset(data, 0, sizeof(struct e1000_thermal_sensor_data)); |
| 2791 | |
| 2792 | data->sensor[0].location = 0x1; |
| 2793 | data->sensor[0].caution_thresh = |
| 2794 | (rd32(E1000_THHIGHTC) & 0xFF); |
| 2795 | data->sensor[0].max_op_thresh = |
| 2796 | (rd32(E1000_THLOWTC) & 0xFF); |
| 2797 | |
| 2798 | /* Return the internal sensor only if ETS is unsupported */ |
| 2799 | hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); |
| 2800 | if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) |
| 2801 | return status; |
| 2802 | |
| 2803 | hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); |
| 2804 | if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) |
| 2805 | != NVM_ETS_TYPE_EMC) |
| 2806 | return E1000_NOT_IMPLEMENTED; |
| 2807 | |
| 2808 | low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >> |
| 2809 | NVM_ETS_LTHRES_DELTA_SHIFT); |
| 2810 | num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); |
| 2811 | |
| 2812 | for (i = 1; i <= num_sensors; i++) { |
| 2813 | hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); |
| 2814 | sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> |
| 2815 | NVM_ETS_DATA_INDEX_SHIFT); |
| 2816 | sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> |
| 2817 | NVM_ETS_DATA_LOC_SHIFT); |
| 2818 | therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK; |
| 2819 | |
| 2820 | hw->phy.ops.write_i2c_byte(hw, |
| 2821 | e1000_emc_therm_limit[sensor_index], |
| 2822 | E1000_I2C_THERMAL_SENSOR_ADDR, |
| 2823 | therm_limit); |
| 2824 | |
| 2825 | if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) { |
| 2826 | data->sensor[i].location = sensor_location; |
| 2827 | data->sensor[i].caution_thresh = therm_limit; |
| 2828 | data->sensor[i].max_op_thresh = therm_limit - |
| 2829 | low_thresh_delta; |
| 2830 | } |
| 2831 | } |
| 2832 | return status; |
| 2833 | } |
| 2834 | |
Jeff Kirsher | 9b143d1 | 2014-03-06 05:28:06 +0000 | [diff] [blame] | 2835 | #endif |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2836 | static struct e1000_mac_operations e1000_mac_ops_82575 = { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2837 | .init_hw = igb_init_hw_82575, |
| 2838 | .check_for_link = igb_check_for_link_82575, |
Alexander Duyck | 2d064c0 | 2008-07-08 15:10:12 -0700 | [diff] [blame] | 2839 | .rar_set = igb_rar_set, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2840 | .read_mac_addr = igb_read_mac_addr_82575, |
Akeem G Abodunrin | f6878e3 | 2013-08-28 02:23:09 +0000 | [diff] [blame] | 2841 | .get_speed_and_duplex = igb_get_link_up_info_82575, |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 2842 | #ifdef CONFIG_IGB_HWMON |
| 2843 | .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic, |
| 2844 | .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic, |
| 2845 | #endif |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2846 | }; |
| 2847 | |
| 2848 | static struct e1000_phy_operations e1000_phy_ops_82575 = { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2849 | .acquire = igb_acquire_phy_82575, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2850 | .get_cfg_done = igb_get_cfg_done_82575, |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2851 | .release = igb_release_phy_82575, |
Carolyn Wyborny | 441fc6f | 2012-12-07 03:00:30 +0000 | [diff] [blame] | 2852 | .write_i2c_byte = igb_write_i2c_byte, |
| 2853 | .read_i2c_byte = igb_read_i2c_byte, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2854 | }; |
| 2855 | |
| 2856 | static struct e1000_nvm_operations e1000_nvm_ops_82575 = { |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 2857 | .acquire = igb_acquire_nvm_82575, |
| 2858 | .read = igb_read_nvm_eerd, |
| 2859 | .release = igb_release_nvm_82575, |
| 2860 | .write = igb_write_nvm_spi, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2861 | }; |
| 2862 | |
| 2863 | const struct e1000_info e1000_82575_info = { |
| 2864 | .get_invariants = igb_get_invariants_82575, |
| 2865 | .mac_ops = &e1000_mac_ops_82575, |
| 2866 | .phy_ops = &e1000_phy_ops_82575, |
| 2867 | .nvm_ops = &e1000_nvm_ops_82575, |
| 2868 | }; |
| 2869 | |