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Andrew Vasquezfa90c542005-10-27 11:10:08 -07001/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
Andrew Vasquezabbd8872005-07-06 10:30:05 -070023#include <linux/interrupt.h>
James.Smart@Emulex.Com19a7b4a2005-10-18 12:03:35 -040024#include <linux/workqueue.h>
Andrew Vasquez54333832005-11-09 15:49:04 -080025#include <linux/firmware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/semaphore.h>
27
28#include <scsi/scsi.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_device.h>
31#include <scsi/scsi_cmnd.h>
andrew.vasquez@qlogic.com392e2f62006-01-31 16:05:02 -080032#include <scsi/scsi_transport_fc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
Andrew Vasquezcb630672006-05-17 15:09:45 -070034#define QLA2XXX_DRIVER_NAME "qla2xxx"
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036/*
37 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
38 * but that's fine as we don't look at the last 24 ones for
39 * ISP2100 HBAs.
40 */
41#define MAILBOX_REGISTER_COUNT_2100 8
42#define MAILBOX_REGISTER_COUNT 32
43
44#define QLA2200A_RISC_ROM_VER 4
45#define FPM_2300 6
46#define FPM_2310 7
47
48#include "qla_settings.h"
49
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -070050/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 * Data bit definitions
52 */
53#define BIT_0 0x1
54#define BIT_1 0x2
55#define BIT_2 0x4
56#define BIT_3 0x8
57#define BIT_4 0x10
58#define BIT_5 0x20
59#define BIT_6 0x40
60#define BIT_7 0x80
61#define BIT_8 0x100
62#define BIT_9 0x200
63#define BIT_10 0x400
64#define BIT_11 0x800
65#define BIT_12 0x1000
66#define BIT_13 0x2000
67#define BIT_14 0x4000
68#define BIT_15 0x8000
69#define BIT_16 0x10000
70#define BIT_17 0x20000
71#define BIT_18 0x40000
72#define BIT_19 0x80000
73#define BIT_20 0x100000
74#define BIT_21 0x200000
75#define BIT_22 0x400000
76#define BIT_23 0x800000
77#define BIT_24 0x1000000
78#define BIT_25 0x2000000
79#define BIT_26 0x4000000
80#define BIT_27 0x8000000
81#define BIT_28 0x10000000
82#define BIT_29 0x20000000
83#define BIT_30 0x40000000
84#define BIT_31 0x80000000
85
86#define LSB(x) ((uint8_t)(x))
87#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
88
89#define LSW(x) ((uint16_t)(x))
90#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
91
92#define LSD(x) ((uint32_t)((uint64_t)(x)))
93#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
94
95
96/*
97 * I/O register
98*/
99
100#define RD_REG_BYTE(addr) readb(addr)
101#define RD_REG_WORD(addr) readw(addr)
102#define RD_REG_DWORD(addr) readl(addr)
103#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
104#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
105#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
106#define WRT_REG_BYTE(addr, data) writeb(data,addr)
107#define WRT_REG_WORD(addr, data) writew(data,addr)
108#define WRT_REG_DWORD(addr, data) writel(data,addr)
109
110/*
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800111 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
112 * 133Mhz slot.
113 */
114#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
115#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
116
117/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 * Fibre Channel device definitions.
119 */
120#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
121#define MAX_FIBRE_DEVICES 512
Andrew Vasquezcc4731f2005-07-06 10:32:37 -0700122#define MAX_FIBRE_LUNS 0xFFFF
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123#define MAX_RSCN_COUNT 32
124#define MAX_HOST_COUNT 16
125
126/*
127 * Host adapter default definitions.
128 */
129#define MAX_BUSES 1 /* We only have one bus today */
130#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
131#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132#define MIN_LUNS 8
133#define MAX_LUNS MAX_FIBRE_LUNS
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700134#define MAX_CMDS_PER_LUN 255
135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136/*
137 * Fibre Channel device definitions.
138 */
139#define SNS_LAST_LOOP_ID_2100 0xfe
140#define SNS_LAST_LOOP_ID_2300 0x7ff
141
142#define LAST_LOCAL_LOOP_ID 0x7d
143#define SNS_FL_PORT 0x7e
144#define FABRIC_CONTROLLER 0x7f
145#define SIMPLE_NAME_SERVER 0x80
146#define SNS_FIRST_LOOP_ID 0x81
147#define MANAGEMENT_SERVER 0xfe
148#define BROADCAST 0xff
149
Andrew Vasquez3d716442005-07-06 10:30:26 -0700150/*
151 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
152 * valid range of an N-PORT id is 0 through 0x7ef.
153 */
154#define NPH_LAST_HANDLE 0x7ef
Andrew Vasquezcca53352005-08-26 19:08:30 -0700155#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700156#define NPH_SNS 0x7fc /* FFFFFC */
157#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
158#define NPH_F_PORT 0x7fe /* FFFFFE */
159#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
160
161#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
162#include "qla_fw.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163
164/*
165 * Timeout timer counts in seconds
166 */
8482e1182005-04-17 15:04:54 -0500167#define PORT_RETRY_TIME 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168#define LOOP_DOWN_TIMEOUT 60
169#define LOOP_DOWN_TIME 255 /* 240 */
170#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
171
172/* Maximum outstanding commands in ISP queues (1-65535) */
173#define MAX_OUTSTANDING_COMMANDS 1024
174
175/* ISP request and response entry counts (37-65535) */
176#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
177#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
178#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700179#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
181#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
182
183/*
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700184 * SCSI Request Block
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 */
186typedef struct srb {
187 struct list_head list;
188
189 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79622005-04-17 15:06:53 -0500190 struct fc_port *fcport;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
193
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 uint16_t flags;
195
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 /* Single transfer DMA context */
197 dma_addr_t dma_handle;
198
199 uint32_t request_sense_length;
200 uint8_t *request_sense_ptr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201} srb_t;
202
203/*
204 * SRB flag definitions
205 */
206#define SRB_TIMEOUT BIT_0 /* Command timed out */
207#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
208#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
209#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
210
211#define SRB_ABORTED BIT_4 /* Command aborted command already */
212#define SRB_RETRY BIT_5 /* Command needs retrying */
213#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
214#define SRB_FAILOVER BIT_7 /* Command in failover state */
215
216#define SRB_BUSY BIT_8 /* Command is in busy retry state */
217#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
218#define SRB_IOCTL BIT_10 /* IOCTL command. */
219#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
220
221/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 * ISP I/O Register Set structure definitions.
223 */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700224struct device_reg_2xxx {
225 uint16_t flash_address; /* Flash BIOS address */
226 uint16_t flash_data; /* Flash BIOS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227 uint16_t unused_1[1]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700228 uint16_t ctrl_status; /* Control/Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700229#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
231#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
232
Andrew Vasquez3d716442005-07-06 10:30:26 -0700233 uint16_t ictrl; /* Interrupt control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
235#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
236
Andrew Vasquez3d716442005-07-06 10:30:26 -0700237 uint16_t istatus; /* Interrupt status */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238#define ISR_RISC_INT BIT_3 /* RISC interrupt */
239
Andrew Vasquez3d716442005-07-06 10:30:26 -0700240 uint16_t semaphore; /* Semaphore */
241 uint16_t nvram; /* NVRAM register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242#define NVR_DESELECT 0
243#define NVR_BUSY BIT_15
244#define NVR_WRT_ENABLE BIT_14 /* Write enable */
245#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
246#define NVR_DATA_IN BIT_3
247#define NVR_DATA_OUT BIT_2
248#define NVR_SELECT BIT_1
249#define NVR_CLOCK BIT_0
250
Ravi Anand45aeaf12006-05-17 15:08:49 -0700251#define NVR_WAIT_CNT 20000
252
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 union {
254 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700255 uint16_t mailbox0;
256 uint16_t mailbox1;
257 uint16_t mailbox2;
258 uint16_t mailbox3;
259 uint16_t mailbox4;
260 uint16_t mailbox5;
261 uint16_t mailbox6;
262 uint16_t mailbox7;
263 uint16_t unused_2[59]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 } __attribute__((packed)) isp2100;
265 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700266 /* Request Queue */
267 uint16_t req_q_in; /* In-Pointer */
268 uint16_t req_q_out; /* Out-Pointer */
269 /* Response Queue */
270 uint16_t rsp_q_in; /* In-Pointer */
271 uint16_t rsp_q_out; /* Out-Pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272
273 /* RISC to Host Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700274 uint32_t host_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275#define HSR_RISC_INT BIT_15 /* RISC interrupt */
276#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
277
278 /* Host to Host Semaphore */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700279 uint16_t host_semaphore;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700280 uint16_t unused_3[17]; /* Gap */
281 uint16_t mailbox0;
282 uint16_t mailbox1;
283 uint16_t mailbox2;
284 uint16_t mailbox3;
285 uint16_t mailbox4;
286 uint16_t mailbox5;
287 uint16_t mailbox6;
288 uint16_t mailbox7;
289 uint16_t mailbox8;
290 uint16_t mailbox9;
291 uint16_t mailbox10;
292 uint16_t mailbox11;
293 uint16_t mailbox12;
294 uint16_t mailbox13;
295 uint16_t mailbox14;
296 uint16_t mailbox15;
297 uint16_t mailbox16;
298 uint16_t mailbox17;
299 uint16_t mailbox18;
300 uint16_t mailbox19;
301 uint16_t mailbox20;
302 uint16_t mailbox21;
303 uint16_t mailbox22;
304 uint16_t mailbox23;
305 uint16_t mailbox24;
306 uint16_t mailbox25;
307 uint16_t mailbox26;
308 uint16_t mailbox27;
309 uint16_t mailbox28;
310 uint16_t mailbox29;
311 uint16_t mailbox30;
312 uint16_t mailbox31;
313 uint16_t fb_cmd;
314 uint16_t unused_4[10]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 } __attribute__((packed)) isp2300;
316 } u;
317
Andrew Vasquez3d716442005-07-06 10:30:26 -0700318 uint16_t fpm_diag_config;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 uint16_t unused_5[0x6]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700320 uint16_t pcr; /* Processor Control Register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 uint16_t unused_6[0x5]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700322 uint16_t mctr; /* Memory Configuration and Timing. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 uint16_t unused_7[0x3]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700324 uint16_t fb_cmd_2100; /* Unused on 23XX */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 uint16_t unused_8[0x3]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700326 uint16_t hccr; /* Host command & control register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
328#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
329 /* HCCR commands */
330#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
331#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
332#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
333#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
334#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
335#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
336#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
337#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
338
339 uint16_t unused_9[5]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700340 uint16_t gpiod; /* GPIO Data register. */
341 uint16_t gpioe; /* GPIO Enable register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342#define GPIO_LED_MASK 0x00C0
343#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
344#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
345#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
346#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800347#define GPIO_LED_ALL_OFF 0x0000
348#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
349#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350
351 union {
352 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700353 uint16_t unused_10[8]; /* Gap */
354 uint16_t mailbox8;
355 uint16_t mailbox9;
356 uint16_t mailbox10;
357 uint16_t mailbox11;
358 uint16_t mailbox12;
359 uint16_t mailbox13;
360 uint16_t mailbox14;
361 uint16_t mailbox15;
362 uint16_t mailbox16;
363 uint16_t mailbox17;
364 uint16_t mailbox18;
365 uint16_t mailbox19;
366 uint16_t mailbox20;
367 uint16_t mailbox21;
368 uint16_t mailbox22;
369 uint16_t mailbox23; /* Also probe reg. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 } __attribute__((packed)) isp2200;
371 } u_end;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700372};
373
Andrew Morton9a168bd2005-07-26 14:11:28 -0700374typedef union {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700375 struct device_reg_2xxx isp;
376 struct device_reg_24xx isp24;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377} device_reg_t;
378
379#define ISP_REQ_Q_IN(ha, reg) \
380 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
381 &(reg)->u.isp2100.mailbox4 : \
382 &(reg)->u.isp2300.req_q_in)
383#define ISP_REQ_Q_OUT(ha, reg) \
384 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
385 &(reg)->u.isp2100.mailbox4 : \
386 &(reg)->u.isp2300.req_q_out)
387#define ISP_RSP_Q_IN(ha, reg) \
388 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
389 &(reg)->u.isp2100.mailbox5 : \
390 &(reg)->u.isp2300.rsp_q_in)
391#define ISP_RSP_Q_OUT(ha, reg) \
392 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
393 &(reg)->u.isp2100.mailbox5 : \
394 &(reg)->u.isp2300.rsp_q_out)
395
396#define MAILBOX_REG(ha, reg, num) \
397 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
398 (num < 8 ? \
399 &(reg)->u.isp2100.mailbox0 + (num) : \
400 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
401 &(reg)->u.isp2300.mailbox0 + (num))
402#define RD_MAILBOX_REG(ha, reg, num) \
403 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
404#define WRT_MAILBOX_REG(ha, reg, num, data) \
405 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
406
407#define FB_CMD_REG(ha, reg) \
408 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
409 &(reg)->fb_cmd_2100 : \
410 &(reg)->u.isp2300.fb_cmd)
411#define RD_FB_CMD_REG(ha, reg) \
412 RD_REG_WORD(FB_CMD_REG(ha, reg))
413#define WRT_FB_CMD_REG(ha, reg, data) \
414 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
415
416typedef struct {
417 uint32_t out_mb; /* outbound from driver */
418 uint32_t in_mb; /* Incoming from RISC */
419 uint16_t mb[MAILBOX_REGISTER_COUNT];
420 long buf_size;
421 void *bufp;
422 uint32_t tov;
423 uint8_t flags;
424#define MBX_DMA_IN BIT_0
425#define MBX_DMA_OUT BIT_1
426#define IOCTL_CMD BIT_2
427} mbx_cmd_t;
428
429#define MBX_TOV_SECONDS 30
430
431/*
432 * ISP product identification definitions in mailboxes after reset.
433 */
434#define PROD_ID_1 0x4953
435#define PROD_ID_2 0x0000
436#define PROD_ID_2a 0x5020
437#define PROD_ID_3 0x2020
438
439/*
440 * ISP mailbox Self-Test status codes
441 */
442#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
443#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
444#define MBS_BUSY 4 /* Busy. */
445
446/*
447 * ISP mailbox command complete status codes
448 */
449#define MBS_COMMAND_COMPLETE 0x4000
450#define MBS_INVALID_COMMAND 0x4001
451#define MBS_HOST_INTERFACE_ERROR 0x4002
452#define MBS_TEST_FAILED 0x4003
453#define MBS_COMMAND_ERROR 0x4005
454#define MBS_COMMAND_PARAMETER_ERROR 0x4006
455#define MBS_PORT_ID_USED 0x4007
456#define MBS_LOOP_ID_USED 0x4008
457#define MBS_ALL_IDS_IN_USE 0x4009
458#define MBS_NOT_LOGGED_IN 0x400A
Andrew Vasquez3d716442005-07-06 10:30:26 -0700459#define MBS_LINK_DOWN_ERROR 0x400B
460#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461
462/*
463 * ISP mailbox asynchronous event status codes
464 */
465#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
466#define MBA_RESET 0x8001 /* Reset Detected. */
467#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
468#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
469#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
470#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
471#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
472 /* occurred. */
473#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
474#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
475#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
476#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
477#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
478#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
479#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
480#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
481#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
482#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
483#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
484#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
485#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
486#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
487#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
488#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
489 /* used. */
Andrew Vasquez45ebeb52006-08-01 13:48:14 -0700490#define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
492#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
493#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
494#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
495#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
496#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
497#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
498#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
499#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
500#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
501#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
502#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
503#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
504
505/*
506 * Firmware options 1, 2, 3.
507 */
508#define FO1_AE_ON_LIPF8 BIT_0
509#define FO1_AE_ALL_LIP_RESET BIT_1
510#define FO1_CTIO_RETRY BIT_3
511#define FO1_DISABLE_LIP_F7_SW BIT_4
512#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
Andrew Vasquez3d716442005-07-06 10:30:26 -0700513#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
515#define FO1_SET_EMPHASIS_SWING BIT_8
516#define FO1_AE_AUTO_BYPASS BIT_9
517#define FO1_ENABLE_PURE_IOCB BIT_10
518#define FO1_AE_PLOGI_RJT BIT_11
519#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
520#define FO1_AE_QUEUE_FULL BIT_13
521
522#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
523#define FO2_REV_LOOPBACK BIT_1
524
525#define FO3_ENABLE_EMERG_IOCB BIT_0
526#define FO3_AE_RND_ERROR BIT_1
527
Andrew Vasquez3d716442005-07-06 10:30:26 -0700528/* 24XX additional firmware options */
529#define ADD_FO_COUNT 3
530#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
531#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
532
533#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
534
535#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
536
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537/*
538 * ISP mailbox commands
539 */
540#define MBC_LOAD_RAM 1 /* Load RAM. */
541#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
542#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
543#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
544#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
545#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
546#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
547#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
548#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
549#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
550#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
551#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
552#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
553#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
Andrew Vasquezf6ef3b12005-08-26 19:10:20 -0700554#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
556#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
557#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
558#define MBC_RESET 0x18 /* Reset. */
559#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
560#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
561#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
562#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
563#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
564#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
565#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
566#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
567#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
568#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
569#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
570#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
571#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
572#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
573#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
574#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
575#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
576#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
577#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
578#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
579#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
580#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
581 /* Initialization Procedure */
582#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
583#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
584#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
585#define MBC_TARGET_RESET 0x66 /* Target Reset. */
586#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
587#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
588#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
589#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
590#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
591#define MBC_LIP_RESET 0x6c /* LIP reset. */
592#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
593 /* commandd. */
594#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
595#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
596#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
597#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
598#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
599#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
600#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
601#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
602#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
603#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
604#define MBC_LUN_RESET 0x7E /* Send LUN reset */
605
Andrew Vasquez3d716442005-07-06 10:30:26 -0700606/*
607 * ISP24xx mailbox commands
608 */
609#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
610#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
Andrew Vasquezd8b45212006-10-02 12:00:43 -0700611#define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700612#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -0700613#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700614#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
Andrew Vasquez88729e52006-06-23 16:10:50 -0700615#define MBC_READ_SFP 0x31 /* Read SFP Data. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700616#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
617#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
618#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
619#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
620#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
621#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
622#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
623#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
624
Andrew Vasqueza7a167b2006-06-23 16:10:29 -0700625#define TC_ENABLE 4
626#define TC_DISABLE 5
627
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628/* Firmware return data sizes */
629#define FCAL_MAP_SIZE 128
630
631/* Mailbox bit definitions for out_mb and in_mb */
632#define MBX_31 BIT_31
633#define MBX_30 BIT_30
634#define MBX_29 BIT_29
635#define MBX_28 BIT_28
636#define MBX_27 BIT_27
637#define MBX_26 BIT_26
638#define MBX_25 BIT_25
639#define MBX_24 BIT_24
640#define MBX_23 BIT_23
641#define MBX_22 BIT_22
642#define MBX_21 BIT_21
643#define MBX_20 BIT_20
644#define MBX_19 BIT_19
645#define MBX_18 BIT_18
646#define MBX_17 BIT_17
647#define MBX_16 BIT_16
648#define MBX_15 BIT_15
649#define MBX_14 BIT_14
650#define MBX_13 BIT_13
651#define MBX_12 BIT_12
652#define MBX_11 BIT_11
653#define MBX_10 BIT_10
654#define MBX_9 BIT_9
655#define MBX_8 BIT_8
656#define MBX_7 BIT_7
657#define MBX_6 BIT_6
658#define MBX_5 BIT_5
659#define MBX_4 BIT_4
660#define MBX_3 BIT_3
661#define MBX_2 BIT_2
662#define MBX_1 BIT_1
663#define MBX_0 BIT_0
664
665/*
666 * Firmware state codes from get firmware state mailbox command
667 */
668#define FSTATE_CONFIG_WAIT 0
669#define FSTATE_WAIT_AL_PA 1
670#define FSTATE_WAIT_LOGIN 2
671#define FSTATE_READY 3
672#define FSTATE_LOSS_OF_SYNC 4
673#define FSTATE_ERROR 5
674#define FSTATE_REINIT 6
675#define FSTATE_NON_PART 7
676
677#define FSTATE_CONFIG_CORRECT 0
678#define FSTATE_P2P_RCV_LIP 1
679#define FSTATE_P2P_CHOOSE_LOOP 2
680#define FSTATE_P2P_RCV_UNIDEN_LIP 3
681#define FSTATE_FATAL_ERROR 4
682#define FSTATE_LOOP_BACK_CONN 5
683
684/*
685 * Port Database structure definition
686 * Little endian except where noted.
687 */
688#define PORT_DATABASE_SIZE 128 /* bytes */
689typedef struct {
690 uint8_t options;
691 uint8_t control;
692 uint8_t master_state;
693 uint8_t slave_state;
694 uint8_t reserved[2];
695 uint8_t hard_address;
696 uint8_t reserved_1;
697 uint8_t port_id[4];
698 uint8_t node_name[WWN_SIZE];
699 uint8_t port_name[WWN_SIZE];
700 uint16_t execution_throttle;
701 uint16_t execution_count;
702 uint8_t reset_count;
703 uint8_t reserved_2;
704 uint16_t resource_allocation;
705 uint16_t current_allocation;
706 uint16_t queue_head;
707 uint16_t queue_tail;
708 uint16_t transmit_execution_list_next;
709 uint16_t transmit_execution_list_previous;
710 uint16_t common_features;
711 uint16_t total_concurrent_sequences;
712 uint16_t RO_by_information_category;
713 uint8_t recipient;
714 uint8_t initiator;
715 uint16_t receive_data_size;
716 uint16_t concurrent_sequences;
717 uint16_t open_sequences_per_exchange;
718 uint16_t lun_abort_flags;
719 uint16_t lun_stop_flags;
720 uint16_t stop_queue_head;
721 uint16_t stop_queue_tail;
722 uint16_t port_retry_timer;
723 uint16_t next_sequence_id;
724 uint16_t frame_count;
725 uint16_t PRLI_payload_length;
726 uint8_t prli_svc_param_word_0[2]; /* Big endian */
727 /* Bits 15-0 of word 0 */
728 uint8_t prli_svc_param_word_3[2]; /* Big endian */
729 /* Bits 15-0 of word 3 */
730 uint16_t loop_id;
731 uint16_t extended_lun_info_list_pointer;
732 uint16_t extended_lun_stop_list_pointer;
733} port_database_t;
734
735/*
736 * Port database slave/master states
737 */
738#define PD_STATE_DISCOVERY 0
739#define PD_STATE_WAIT_DISCOVERY_ACK 1
740#define PD_STATE_PORT_LOGIN 2
741#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
742#define PD_STATE_PROCESS_LOGIN 4
743#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
744#define PD_STATE_PORT_LOGGED_IN 6
745#define PD_STATE_PORT_UNAVAILABLE 7
746#define PD_STATE_PROCESS_LOGOUT 8
747#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
748#define PD_STATE_PORT_LOGOUT 10
749#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
750
751
Andrew Vasquez4fdfefe2005-10-27 11:09:48 -0700752#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
753#define QLA_ZIO_DISABLED 0
754#define QLA_ZIO_DEFAULT_TIMER 2
755
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756/*
757 * ISP Initialization Control Block.
758 * Little endian except where noted.
759 */
760#define ICB_VERSION 1
761typedef struct {
762 uint8_t version;
763 uint8_t reserved_1;
764
765 /*
766 * LSB BIT 0 = Enable Hard Loop Id
767 * LSB BIT 1 = Enable Fairness
768 * LSB BIT 2 = Enable Full-Duplex
769 * LSB BIT 3 = Enable Fast Posting
770 * LSB BIT 4 = Enable Target Mode
771 * LSB BIT 5 = Disable Initiator Mode
772 * LSB BIT 6 = Enable ADISC
773 * LSB BIT 7 = Enable Target Inquiry Data
774 *
775 * MSB BIT 0 = Enable PDBC Notify
776 * MSB BIT 1 = Non Participating LIP
777 * MSB BIT 2 = Descending Loop ID Search
778 * MSB BIT 3 = Acquire Loop ID in LIPA
779 * MSB BIT 4 = Stop PortQ on Full Status
780 * MSB BIT 5 = Full Login after LIP
781 * MSB BIT 6 = Node Name Option
782 * MSB BIT 7 = Ext IFWCB enable bit
783 */
784 uint8_t firmware_options[2];
785
786 uint16_t frame_payload_size;
787 uint16_t max_iocb_allocation;
788 uint16_t execution_throttle;
789 uint8_t retry_count;
790 uint8_t retry_delay; /* unused */
791 uint8_t port_name[WWN_SIZE]; /* Big endian. */
792 uint16_t hard_address;
793 uint8_t inquiry_data;
794 uint8_t login_timeout;
795 uint8_t node_name[WWN_SIZE]; /* Big endian. */
796
797 uint16_t request_q_outpointer;
798 uint16_t response_q_inpointer;
799 uint16_t request_q_length;
800 uint16_t response_q_length;
801 uint32_t request_q_address[2];
802 uint32_t response_q_address[2];
803
804 uint16_t lun_enables;
805 uint8_t command_resource_count;
806 uint8_t immediate_notify_resource_count;
807 uint16_t timeout;
808 uint8_t reserved_2[2];
809
810 /*
811 * LSB BIT 0 = Timer Operation mode bit 0
812 * LSB BIT 1 = Timer Operation mode bit 1
813 * LSB BIT 2 = Timer Operation mode bit 2
814 * LSB BIT 3 = Timer Operation mode bit 3
815 * LSB BIT 4 = Init Config Mode bit 0
816 * LSB BIT 5 = Init Config Mode bit 1
817 * LSB BIT 6 = Init Config Mode bit 2
818 * LSB BIT 7 = Enable Non part on LIHA failure
819 *
820 * MSB BIT 0 = Enable class 2
821 * MSB BIT 1 = Enable ACK0
822 * MSB BIT 2 =
823 * MSB BIT 3 =
824 * MSB BIT 4 = FC Tape Enable
825 * MSB BIT 5 = Enable FC Confirm
826 * MSB BIT 6 = Enable command queuing in target mode
827 * MSB BIT 7 = No Logo On Link Down
828 */
829 uint8_t add_firmware_options[2];
830
831 uint8_t response_accumulation_timer;
832 uint8_t interrupt_delay_timer;
833
834 /*
835 * LSB BIT 0 = Enable Read xfr_rdy
836 * LSB BIT 1 = Soft ID only
837 * LSB BIT 2 =
838 * LSB BIT 3 =
839 * LSB BIT 4 = FCP RSP Payload [0]
840 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
841 * LSB BIT 6 = Enable Out-of-Order frame handling
842 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
843 *
844 * MSB BIT 0 = Sbus enable - 2300
845 * MSB BIT 1 =
846 * MSB BIT 2 =
847 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -0700848 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849 * MSB BIT 5 = enable 50 ohm termination
850 * MSB BIT 6 = Data Rate (2300 only)
851 * MSB BIT 7 = Data Rate (2300 only)
852 */
853 uint8_t special_options[2];
854
855 uint8_t reserved_3[26];
856} init_cb_t;
857
858/*
859 * Get Link Status mailbox command return buffer.
860 */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700861#define GLSO_SEND_RPS BIT_0
862#define GLSO_USE_DID BIT_3
863
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864typedef struct {
865 uint32_t link_fail_cnt;
866 uint32_t loss_sync_cnt;
867 uint32_t loss_sig_cnt;
868 uint32_t prim_seq_err_cnt;
869 uint32_t inval_xmit_word_cnt;
870 uint32_t inval_crc_cnt;
871} link_stat_t;
872
873/*
874 * NVRAM Command values.
875 */
876#define NV_START_BIT BIT_2
877#define NV_WRITE_OP (BIT_26+BIT_24)
878#define NV_READ_OP (BIT_26+BIT_25)
879#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
880#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
881#define NV_DELAY_COUNT 10
882
883/*
884 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
885 */
886typedef struct {
887 /*
888 * NVRAM header
889 */
890 uint8_t id[4];
891 uint8_t nvram_version;
892 uint8_t reserved_0;
893
894 /*
895 * NVRAM RISC parameter block
896 */
897 uint8_t parameter_block_version;
898 uint8_t reserved_1;
899
900 /*
901 * LSB BIT 0 = Enable Hard Loop Id
902 * LSB BIT 1 = Enable Fairness
903 * LSB BIT 2 = Enable Full-Duplex
904 * LSB BIT 3 = Enable Fast Posting
905 * LSB BIT 4 = Enable Target Mode
906 * LSB BIT 5 = Disable Initiator Mode
907 * LSB BIT 6 = Enable ADISC
908 * LSB BIT 7 = Enable Target Inquiry Data
909 *
910 * MSB BIT 0 = Enable PDBC Notify
911 * MSB BIT 1 = Non Participating LIP
912 * MSB BIT 2 = Descending Loop ID Search
913 * MSB BIT 3 = Acquire Loop ID in LIPA
914 * MSB BIT 4 = Stop PortQ on Full Status
915 * MSB BIT 5 = Full Login after LIP
916 * MSB BIT 6 = Node Name Option
917 * MSB BIT 7 = Ext IFWCB enable bit
918 */
919 uint8_t firmware_options[2];
920
921 uint16_t frame_payload_size;
922 uint16_t max_iocb_allocation;
923 uint16_t execution_throttle;
924 uint8_t retry_count;
925 uint8_t retry_delay; /* unused */
926 uint8_t port_name[WWN_SIZE]; /* Big endian. */
927 uint16_t hard_address;
928 uint8_t inquiry_data;
929 uint8_t login_timeout;
930 uint8_t node_name[WWN_SIZE]; /* Big endian. */
931
932 /*
933 * LSB BIT 0 = Timer Operation mode bit 0
934 * LSB BIT 1 = Timer Operation mode bit 1
935 * LSB BIT 2 = Timer Operation mode bit 2
936 * LSB BIT 3 = Timer Operation mode bit 3
937 * LSB BIT 4 = Init Config Mode bit 0
938 * LSB BIT 5 = Init Config Mode bit 1
939 * LSB BIT 6 = Init Config Mode bit 2
940 * LSB BIT 7 = Enable Non part on LIHA failure
941 *
942 * MSB BIT 0 = Enable class 2
943 * MSB BIT 1 = Enable ACK0
944 * MSB BIT 2 =
945 * MSB BIT 3 =
946 * MSB BIT 4 = FC Tape Enable
947 * MSB BIT 5 = Enable FC Confirm
948 * MSB BIT 6 = Enable command queuing in target mode
949 * MSB BIT 7 = No Logo On Link Down
950 */
951 uint8_t add_firmware_options[2];
952
953 uint8_t response_accumulation_timer;
954 uint8_t interrupt_delay_timer;
955
956 /*
957 * LSB BIT 0 = Enable Read xfr_rdy
958 * LSB BIT 1 = Soft ID only
959 * LSB BIT 2 =
960 * LSB BIT 3 =
961 * LSB BIT 4 = FCP RSP Payload [0]
962 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
963 * LSB BIT 6 = Enable Out-of-Order frame handling
964 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
965 *
966 * MSB BIT 0 = Sbus enable - 2300
967 * MSB BIT 1 =
968 * MSB BIT 2 =
969 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -0700970 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971 * MSB BIT 5 = enable 50 ohm termination
972 * MSB BIT 6 = Data Rate (2300 only)
973 * MSB BIT 7 = Data Rate (2300 only)
974 */
975 uint8_t special_options[2];
976
977 /* Reserved for expanded RISC parameter block */
978 uint8_t reserved_2[22];
979
980 /*
981 * LSB BIT 0 = Tx Sensitivity 1G bit 0
982 * LSB BIT 1 = Tx Sensitivity 1G bit 1
983 * LSB BIT 2 = Tx Sensitivity 1G bit 2
984 * LSB BIT 3 = Tx Sensitivity 1G bit 3
985 * LSB BIT 4 = Rx Sensitivity 1G bit 0
986 * LSB BIT 5 = Rx Sensitivity 1G bit 1
987 * LSB BIT 6 = Rx Sensitivity 1G bit 2
988 * LSB BIT 7 = Rx Sensitivity 1G bit 3
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700989 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 * MSB BIT 0 = Tx Sensitivity 2G bit 0
991 * MSB BIT 1 = Tx Sensitivity 2G bit 1
992 * MSB BIT 2 = Tx Sensitivity 2G bit 2
993 * MSB BIT 3 = Tx Sensitivity 2G bit 3
994 * MSB BIT 4 = Rx Sensitivity 2G bit 0
995 * MSB BIT 5 = Rx Sensitivity 2G bit 1
996 * MSB BIT 6 = Rx Sensitivity 2G bit 2
997 * MSB BIT 7 = Rx Sensitivity 2G bit 3
998 *
999 * LSB BIT 0 = Output Swing 1G bit 0
1000 * LSB BIT 1 = Output Swing 1G bit 1
1001 * LSB BIT 2 = Output Swing 1G bit 2
1002 * LSB BIT 3 = Output Emphasis 1G bit 0
1003 * LSB BIT 4 = Output Emphasis 1G bit 1
1004 * LSB BIT 5 = Output Swing 2G bit 0
1005 * LSB BIT 6 = Output Swing 2G bit 1
1006 * LSB BIT 7 = Output Swing 2G bit 2
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001007 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008 * MSB BIT 0 = Output Emphasis 2G bit 0
1009 * MSB BIT 1 = Output Emphasis 2G bit 1
1010 * MSB BIT 2 = Output Enable
1011 * MSB BIT 3 =
1012 * MSB BIT 4 =
1013 * MSB BIT 5 =
1014 * MSB BIT 6 =
1015 * MSB BIT 7 =
1016 */
1017 uint8_t seriallink_options[4];
1018
1019 /*
1020 * NVRAM host parameter block
1021 *
1022 * LSB BIT 0 = Enable spinup delay
1023 * LSB BIT 1 = Disable BIOS
1024 * LSB BIT 2 = Enable Memory Map BIOS
1025 * LSB BIT 3 = Enable Selectable Boot
1026 * LSB BIT 4 = Disable RISC code load
1027 * LSB BIT 5 = Set cache line size 1
1028 * LSB BIT 6 = PCI Parity Disable
1029 * LSB BIT 7 = Enable extended logging
1030 *
1031 * MSB BIT 0 = Enable 64bit addressing
1032 * MSB BIT 1 = Enable lip reset
1033 * MSB BIT 2 = Enable lip full login
1034 * MSB BIT 3 = Enable target reset
1035 * MSB BIT 4 = Enable database storage
1036 * MSB BIT 5 = Enable cache flush read
1037 * MSB BIT 6 = Enable database load
1038 * MSB BIT 7 = Enable alternate WWN
1039 */
1040 uint8_t host_p[2];
1041
1042 uint8_t boot_node_name[WWN_SIZE];
1043 uint8_t boot_lun_number;
1044 uint8_t reset_delay;
1045 uint8_t port_down_retry_count;
1046 uint8_t boot_id_number;
1047 uint16_t max_luns_per_target;
1048 uint8_t fcode_boot_port_name[WWN_SIZE];
1049 uint8_t alternate_port_name[WWN_SIZE];
1050 uint8_t alternate_node_name[WWN_SIZE];
1051
1052 /*
1053 * BIT 0 = Selective Login
1054 * BIT 1 = Alt-Boot Enable
1055 * BIT 2 =
1056 * BIT 3 = Boot Order List
1057 * BIT 4 =
1058 * BIT 5 = Selective LUN
1059 * BIT 6 =
1060 * BIT 7 = unused
1061 */
1062 uint8_t efi_parameters;
1063
1064 uint8_t link_down_timeout;
1065
Andrew Vasquezcca53352005-08-26 19:08:30 -07001066 uint8_t adapter_id[16];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067
1068 uint8_t alt1_boot_node_name[WWN_SIZE];
1069 uint16_t alt1_boot_lun_number;
1070 uint8_t alt2_boot_node_name[WWN_SIZE];
1071 uint16_t alt2_boot_lun_number;
1072 uint8_t alt3_boot_node_name[WWN_SIZE];
1073 uint16_t alt3_boot_lun_number;
1074 uint8_t alt4_boot_node_name[WWN_SIZE];
1075 uint16_t alt4_boot_lun_number;
1076 uint8_t alt5_boot_node_name[WWN_SIZE];
1077 uint16_t alt5_boot_lun_number;
1078 uint8_t alt6_boot_node_name[WWN_SIZE];
1079 uint16_t alt6_boot_lun_number;
1080 uint8_t alt7_boot_node_name[WWN_SIZE];
1081 uint16_t alt7_boot_lun_number;
1082
1083 uint8_t reserved_3[2];
1084
1085 /* Offset 200-215 : Model Number */
1086 uint8_t model_number[16];
1087
1088 /* OEM related items */
1089 uint8_t oem_specific[16];
1090
1091 /*
1092 * NVRAM Adapter Features offset 232-239
1093 *
1094 * LSB BIT 0 = External GBIC
1095 * LSB BIT 1 = Risc RAM parity
1096 * LSB BIT 2 = Buffer Plus Module
1097 * LSB BIT 3 = Multi Chip Adapter
1098 * LSB BIT 4 = Internal connector
1099 * LSB BIT 5 =
1100 * LSB BIT 6 =
1101 * LSB BIT 7 =
1102 *
1103 * MSB BIT 0 =
1104 * MSB BIT 1 =
1105 * MSB BIT 2 =
1106 * MSB BIT 3 =
1107 * MSB BIT 4 =
1108 * MSB BIT 5 =
1109 * MSB BIT 6 =
1110 * MSB BIT 7 =
1111 */
1112 uint8_t adapter_features[2];
1113
1114 uint8_t reserved_4[16];
1115
1116 /* Subsystem vendor ID for ISP2200 */
1117 uint16_t subsystem_vendor_id_2200;
1118
1119 /* Subsystem device ID for ISP2200 */
1120 uint16_t subsystem_device_id_2200;
1121
1122 uint8_t reserved_5;
1123 uint8_t checksum;
1124} nvram_t;
1125
1126/*
1127 * ISP queue - response queue entry definition.
1128 */
1129typedef struct {
1130 uint8_t data[60];
1131 uint32_t signature;
1132#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1133} response_t;
1134
1135typedef union {
1136 uint16_t extended;
1137 struct {
1138 uint8_t reserved;
1139 uint8_t standard;
1140 } id;
1141} target_id_t;
1142
1143#define SET_TARGET_ID(ha, to, from) \
1144do { \
1145 if (HAS_EXTENDED_IDS(ha)) \
1146 to.extended = cpu_to_le16(from); \
1147 else \
1148 to.id.standard = (uint8_t)from; \
1149} while (0)
1150
1151/*
1152 * ISP queue - command entry structure definition.
1153 */
1154#define COMMAND_TYPE 0x11 /* Command entry */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001155typedef struct {
1156 uint8_t entry_type; /* Entry type. */
1157 uint8_t entry_count; /* Entry count. */
1158 uint8_t sys_define; /* System defined. */
1159 uint8_t entry_status; /* Entry Status. */
1160 uint32_t handle; /* System handle. */
1161 target_id_t target; /* SCSI ID */
1162 uint16_t lun; /* SCSI LUN */
1163 uint16_t control_flags; /* Control flags. */
1164#define CF_WRITE BIT_6
1165#define CF_READ BIT_5
1166#define CF_SIMPLE_TAG BIT_3
1167#define CF_ORDERED_TAG BIT_2
1168#define CF_HEAD_TAG BIT_1
1169 uint16_t reserved_1;
1170 uint16_t timeout; /* Command timeout. */
1171 uint16_t dseg_count; /* Data segment count. */
1172 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1173 uint32_t byte_count; /* Total byte count. */
1174 uint32_t dseg_0_address; /* Data segment 0 address. */
1175 uint32_t dseg_0_length; /* Data segment 0 length. */
1176 uint32_t dseg_1_address; /* Data segment 1 address. */
1177 uint32_t dseg_1_length; /* Data segment 1 length. */
1178 uint32_t dseg_2_address; /* Data segment 2 address. */
1179 uint32_t dseg_2_length; /* Data segment 2 length. */
1180} cmd_entry_t;
1181
1182/*
1183 * ISP queue - 64-Bit addressing, command entry structure definition.
1184 */
1185#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1186typedef struct {
1187 uint8_t entry_type; /* Entry type. */
1188 uint8_t entry_count; /* Entry count. */
1189 uint8_t sys_define; /* System defined. */
1190 uint8_t entry_status; /* Entry Status. */
1191 uint32_t handle; /* System handle. */
1192 target_id_t target; /* SCSI ID */
1193 uint16_t lun; /* SCSI LUN */
1194 uint16_t control_flags; /* Control flags. */
1195 uint16_t reserved_1;
1196 uint16_t timeout; /* Command timeout. */
1197 uint16_t dseg_count; /* Data segment count. */
1198 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1199 uint32_t byte_count; /* Total byte count. */
1200 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1201 uint32_t dseg_0_length; /* Data segment 0 length. */
1202 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1203 uint32_t dseg_1_length; /* Data segment 1 length. */
1204} cmd_a64_entry_t, request_t;
1205
1206/*
1207 * ISP queue - continuation entry structure definition.
1208 */
1209#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1210typedef struct {
1211 uint8_t entry_type; /* Entry type. */
1212 uint8_t entry_count; /* Entry count. */
1213 uint8_t sys_define; /* System defined. */
1214 uint8_t entry_status; /* Entry Status. */
1215 uint32_t reserved;
1216 uint32_t dseg_0_address; /* Data segment 0 address. */
1217 uint32_t dseg_0_length; /* Data segment 0 length. */
1218 uint32_t dseg_1_address; /* Data segment 1 address. */
1219 uint32_t dseg_1_length; /* Data segment 1 length. */
1220 uint32_t dseg_2_address; /* Data segment 2 address. */
1221 uint32_t dseg_2_length; /* Data segment 2 length. */
1222 uint32_t dseg_3_address; /* Data segment 3 address. */
1223 uint32_t dseg_3_length; /* Data segment 3 length. */
1224 uint32_t dseg_4_address; /* Data segment 4 address. */
1225 uint32_t dseg_4_length; /* Data segment 4 length. */
1226 uint32_t dseg_5_address; /* Data segment 5 address. */
1227 uint32_t dseg_5_length; /* Data segment 5 length. */
1228 uint32_t dseg_6_address; /* Data segment 6 address. */
1229 uint32_t dseg_6_length; /* Data segment 6 length. */
1230} cont_entry_t;
1231
1232/*
1233 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1234 */
1235#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1236typedef struct {
1237 uint8_t entry_type; /* Entry type. */
1238 uint8_t entry_count; /* Entry count. */
1239 uint8_t sys_define; /* System defined. */
1240 uint8_t entry_status; /* Entry Status. */
1241 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1242 uint32_t dseg_0_length; /* Data segment 0 length. */
1243 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1244 uint32_t dseg_1_length; /* Data segment 1 length. */
1245 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1246 uint32_t dseg_2_length; /* Data segment 2 length. */
1247 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1248 uint32_t dseg_3_length; /* Data segment 3 length. */
1249 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1250 uint32_t dseg_4_length; /* Data segment 4 length. */
1251} cont_a64_entry_t;
1252
1253/*
1254 * ISP queue - status entry structure definition.
1255 */
1256#define STATUS_TYPE 0x03 /* Status entry. */
1257typedef struct {
1258 uint8_t entry_type; /* Entry type. */
1259 uint8_t entry_count; /* Entry count. */
1260 uint8_t sys_define; /* System defined. */
1261 uint8_t entry_status; /* Entry Status. */
1262 uint32_t handle; /* System handle. */
1263 uint16_t scsi_status; /* SCSI status. */
1264 uint16_t comp_status; /* Completion status. */
1265 uint16_t state_flags; /* State flags. */
1266 uint16_t status_flags; /* Status flags. */
1267 uint16_t rsp_info_len; /* Response Info Length. */
1268 uint16_t req_sense_length; /* Request sense data length. */
1269 uint32_t residual_length; /* Residual transfer length. */
1270 uint8_t rsp_info[8]; /* FCP response information. */
1271 uint8_t req_sense_data[32]; /* Request sense data. */
1272} sts_entry_t;
1273
1274/*
1275 * Status entry entry status
1276 */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001277#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1279#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1280#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1281#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1282#define RF_BUSY BIT_1 /* Busy */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001283#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1284 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1285#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1286 RF_INV_E_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287
1288/*
1289 * Status entry SCSI status bit definitions.
1290 */
1291#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1292#define SS_RESIDUAL_UNDER BIT_11
1293#define SS_RESIDUAL_OVER BIT_10
1294#define SS_SENSE_LEN_VALID BIT_9
1295#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1296
1297#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1298#define SS_BUSY_CONDITION BIT_3
1299#define SS_CONDITION_MET BIT_2
1300#define SS_CHECK_CONDITION BIT_1
1301
1302/*
1303 * Status entry completion status
1304 */
1305#define CS_COMPLETE 0x0 /* No errors */
1306#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1307#define CS_DMA 0x2 /* A DMA direction error. */
1308#define CS_TRANSPORT 0x3 /* Transport error. */
1309#define CS_RESET 0x4 /* SCSI bus reset occurred */
1310#define CS_ABORTED 0x5 /* System aborted command. */
1311#define CS_TIMEOUT 0x6 /* Timeout error. */
1312#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1313
1314#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1315#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1316#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1317 /* (selection timeout) */
1318#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1319#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1320#define CS_PORT_BUSY 0x2B /* Port Busy */
1321#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1322#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1323#define CS_UNKNOWN 0x81 /* Driver defined */
1324#define CS_RETRY 0x82 /* Driver defined */
1325#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1326
1327/*
1328 * Status entry status flags
1329 */
1330#define SF_ABTS_TERMINATED BIT_10
1331#define SF_LOGOUT_SENT BIT_13
1332
1333/*
1334 * ISP queue - status continuation entry structure definition.
1335 */
1336#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1337typedef struct {
1338 uint8_t entry_type; /* Entry type. */
1339 uint8_t entry_count; /* Entry count. */
1340 uint8_t sys_define; /* System defined. */
1341 uint8_t entry_status; /* Entry Status. */
1342 uint8_t data[60]; /* data */
1343} sts_cont_entry_t;
1344
1345/*
1346 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1347 * structure definition.
1348 */
1349#define STATUS_TYPE_21 0x21 /* Status entry. */
1350typedef struct {
1351 uint8_t entry_type; /* Entry type. */
1352 uint8_t entry_count; /* Entry count. */
1353 uint8_t handle_count; /* Handle count. */
1354 uint8_t entry_status; /* Entry Status. */
1355 uint32_t handle[15]; /* System handles. */
1356} sts21_entry_t;
1357
1358/*
1359 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1360 * structure definition.
1361 */
1362#define STATUS_TYPE_22 0x22 /* Status entry. */
1363typedef struct {
1364 uint8_t entry_type; /* Entry type. */
1365 uint8_t entry_count; /* Entry count. */
1366 uint8_t handle_count; /* Handle count. */
1367 uint8_t entry_status; /* Entry Status. */
1368 uint16_t handle[30]; /* System handles. */
1369} sts22_entry_t;
1370
1371/*
1372 * ISP queue - marker entry structure definition.
1373 */
1374#define MARKER_TYPE 0x04 /* Marker entry. */
1375typedef struct {
1376 uint8_t entry_type; /* Entry type. */
1377 uint8_t entry_count; /* Entry count. */
1378 uint8_t handle_count; /* Handle count. */
1379 uint8_t entry_status; /* Entry Status. */
1380 uint32_t sys_define_2; /* System defined. */
1381 target_id_t target; /* SCSI ID */
1382 uint8_t modifier; /* Modifier (7-0). */
1383#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1384#define MK_SYNC_ID 1 /* Synchronize ID */
1385#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1386#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1387 /* clear port changed, */
1388 /* use sequence number. */
1389 uint8_t reserved_1;
1390 uint16_t sequence_number; /* Sequence number of event */
1391 uint16_t lun; /* SCSI LUN */
1392 uint8_t reserved_2[48];
1393} mrk_entry_t;
1394
1395/*
1396 * ISP queue - Management Server entry structure definition.
1397 */
1398#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1399typedef struct {
1400 uint8_t entry_type; /* Entry type. */
1401 uint8_t entry_count; /* Entry count. */
1402 uint8_t handle_count; /* Handle count. */
1403 uint8_t entry_status; /* Entry Status. */
1404 uint32_t handle1; /* System handle. */
1405 target_id_t loop_id;
1406 uint16_t status;
1407 uint16_t control_flags; /* Control flags. */
1408 uint16_t reserved2;
1409 uint16_t timeout;
1410 uint16_t cmd_dsd_count;
1411 uint16_t total_dsd_count;
1412 uint8_t type;
1413 uint8_t r_ctl;
1414 uint16_t rx_id;
1415 uint16_t reserved3;
1416 uint32_t handle2;
1417 uint32_t rsp_bytecount;
1418 uint32_t req_bytecount;
1419 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1420 uint32_t dseg_req_length; /* Data segment 0 length. */
1421 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1422 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1423} ms_iocb_entry_t;
1424
1425
1426/*
1427 * ISP queue - Mailbox Command entry structure definition.
1428 */
1429#define MBX_IOCB_TYPE 0x39
1430struct mbx_entry {
1431 uint8_t entry_type;
1432 uint8_t entry_count;
1433 uint8_t sys_define1;
1434 /* Use sys_define1 for source type */
1435#define SOURCE_SCSI 0x00
1436#define SOURCE_IP 0x01
1437#define SOURCE_VI 0x02
1438#define SOURCE_SCTP 0x03
1439#define SOURCE_MP 0x04
1440#define SOURCE_MPIOCTL 0x05
1441#define SOURCE_ASYNC_IOCB 0x07
1442
1443 uint8_t entry_status;
1444
1445 uint32_t handle;
1446 target_id_t loop_id;
1447
1448 uint16_t status;
1449 uint16_t state_flags;
1450 uint16_t status_flags;
1451
1452 uint32_t sys_define2[2];
1453
1454 uint16_t mb0;
1455 uint16_t mb1;
1456 uint16_t mb2;
1457 uint16_t mb3;
1458 uint16_t mb6;
1459 uint16_t mb7;
1460 uint16_t mb9;
1461 uint16_t mb10;
1462 uint32_t reserved_2[2];
1463 uint8_t node_name[WWN_SIZE];
1464 uint8_t port_name[WWN_SIZE];
1465};
1466
1467/*
1468 * ISP request and response queue entry sizes
1469 */
1470#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1471#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1472
1473
1474/*
1475 * 24 bit port ID type definition.
1476 */
1477typedef union {
1478 uint32_t b24 : 24;
1479
1480 struct {
Malahal Nainenib889d532007-03-12 10:41:26 -07001481#ifdef __BIG_ENDIAN
1482 uint8_t domain;
1483 uint8_t area;
1484 uint8_t al_pa;
1485#elif __LITTLE_ENDIAN
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486 uint8_t al_pa;
1487 uint8_t area;
1488 uint8_t domain;
Malahal Nainenib889d532007-03-12 10:41:26 -07001489#else
1490#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1491#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492 uint8_t rsvd_1;
1493 } b;
1494} port_id_t;
1495#define INVALID_PORT_ID 0xFFFFFF
1496
1497/*
1498 * Switch info gathering structure.
1499 */
1500typedef struct {
1501 port_id_t d_id;
1502 uint8_t node_name[WWN_SIZE];
1503 uint8_t port_name[WWN_SIZE];
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001504 uint8_t fabric_port_name[WWN_SIZE];
1505 uint16_t fp_speeds;
1506 uint16_t fp_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001507} sw_info_t;
1508
1509/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001510 * Fibre channel port type.
1511 */
1512 typedef enum {
1513 FCT_UNKNOWN,
1514 FCT_RSCN,
1515 FCT_SWITCH,
1516 FCT_BROADCAST,
1517 FCT_INITIATOR,
1518 FCT_TARGET
1519} fc_port_type_t;
1520
1521/*
1522 * Fibre channel port structure.
1523 */
1524typedef struct fc_port {
1525 struct list_head list;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526 struct scsi_qla_host *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527
1528 uint8_t node_name[WWN_SIZE];
1529 uint8_t port_name[WWN_SIZE];
1530 port_id_t d_id;
1531 uint16_t loop_id;
1532 uint16_t old_loop_id;
1533
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001534 uint8_t fabric_port_name[WWN_SIZE];
1535 uint16_t fp_speed;
1536
Linus Torvalds1da177e2005-04-16 15:20:36 -07001537 fc_port_type_t port_type;
1538
1539 atomic_t state;
1540 uint32_t flags;
1541
bdf79622005-04-17 15:06:53 -05001542 unsigned int os_target_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544 int port_login_retry_count;
1545 int login_retry;
1546 atomic_t port_down_timer;
1547
andrew.vasquez@qlogic.comd97994d2006-01-20 14:53:13 -08001548 spinlock_t rport_lock;
1549 struct fc_rport *rport, *drport;
Andrew Vasquezad3e0ed2005-08-26 19:08:10 -07001550 u32 supported_classes;
Andrew Vasquezdf7baa52006-10-13 09:33:39 -07001551
1552 unsigned long last_queue_full;
1553 unsigned long last_ramp_up;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07001554
1555 struct list_head vp_fcport;
1556 uint16_t vp_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001557} fc_port_t;
1558
1559/*
1560 * Fibre channel port/lun states.
1561 */
1562#define FCS_UNCONFIGURED 1
1563#define FCS_DEVICE_DEAD 2
1564#define FCS_DEVICE_LOST 3
1565#define FCS_ONLINE 4
1566#define FCS_NOT_SUPPORTED 5
1567#define FCS_FAILOVER 6
1568#define FCS_FAILOVER_FAILED 7
1569
1570/*
1571 * FC port flags.
1572 */
1573#define FCF_FABRIC_DEVICE BIT_0
1574#define FCF_LOGIN_NEEDED BIT_1
1575#define FCF_FO_MASKED BIT_2
1576#define FCF_FAILOVER_NEEDED BIT_3
1577#define FCF_RESET_NEEDED BIT_4
1578#define FCF_PERSISTENT_BOUND BIT_5
1579#define FCF_TAPE_PRESENT BIT_6
1580#define FCF_FARP_DONE BIT_7
1581#define FCF_FARP_FAILED BIT_8
1582#define FCF_FARP_REPLY_NEEDED BIT_9
1583#define FCF_AUTH_REQ BIT_10
1584#define FCF_SEND_AUTH_REQ BIT_11
1585#define FCF_RECEIVE_AUTH_REQ BIT_12
1586#define FCF_AUTH_SUCCESS BIT_13
1587#define FCF_RLC_SUPPORT BIT_14
1588#define FCF_CONFIG BIT_15 /* Needed? */
1589#define FCF_RESCAN_NEEDED BIT_16
1590#define FCF_XP_DEVICE BIT_17
1591#define FCF_MSA_DEVICE BIT_18
1592#define FCF_EVA_DEVICE BIT_19
1593#define FCF_MSA_PORT_ACTIVE BIT_20
1594#define FCF_FAILBACK_DISABLE BIT_21
1595#define FCF_FAILOVER_DISABLE BIT_22
1596#define FCF_DSXXX_DEVICE BIT_23
1597#define FCF_AA_EVA_DEVICE BIT_24
Andrew Vasquez3d716442005-07-06 10:30:26 -07001598#define FCF_AA_MSA_DEVICE BIT_25
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599
1600/* No loop ID flag. */
1601#define FC_NO_LOOP_ID 0x1000
1602
1603/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604 * FC-CT interface
1605 *
1606 * NOTE: All structures are big-endian in form.
1607 */
1608
1609#define CT_REJECT_RESPONSE 0x8001
1610#define CT_ACCEPT_RESPONSE 0x8002
Andrew Vasquez4346b142006-12-13 19:20:28 -08001611#define CT_REASON_INVALID_COMMAND_CODE 0x01
Andrew Vasquezcca53352005-08-26 19:08:30 -07001612#define CT_REASON_CANNOT_PERFORM 0x09
1613#define CT_EXPL_ALREADY_REGISTERED 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614
1615#define NS_N_PORT_TYPE 0x01
1616#define NS_NL_PORT_TYPE 0x02
1617#define NS_NX_PORT_TYPE 0x7F
1618
1619#define GA_NXT_CMD 0x100
1620#define GA_NXT_REQ_SIZE (16 + 4)
1621#define GA_NXT_RSP_SIZE (16 + 620)
1622
1623#define GID_PT_CMD 0x1A1
1624#define GID_PT_REQ_SIZE (16 + 4)
1625#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1626
1627#define GPN_ID_CMD 0x112
1628#define GPN_ID_REQ_SIZE (16 + 4)
1629#define GPN_ID_RSP_SIZE (16 + 8)
1630
1631#define GNN_ID_CMD 0x113
1632#define GNN_ID_REQ_SIZE (16 + 4)
1633#define GNN_ID_RSP_SIZE (16 + 8)
1634
1635#define GFT_ID_CMD 0x117
1636#define GFT_ID_REQ_SIZE (16 + 4)
1637#define GFT_ID_RSP_SIZE (16 + 32)
1638
1639#define RFT_ID_CMD 0x217
1640#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1641#define RFT_ID_RSP_SIZE 16
1642
1643#define RFF_ID_CMD 0x21F
1644#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1645#define RFF_ID_RSP_SIZE 16
1646
1647#define RNN_ID_CMD 0x213
1648#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1649#define RNN_ID_RSP_SIZE 16
1650
1651#define RSNN_NN_CMD 0x239
1652#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1653#define RSNN_NN_RSP_SIZE 16
1654
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001655#define GFPN_ID_CMD 0x11C
1656#define GFPN_ID_REQ_SIZE (16 + 4)
1657#define GFPN_ID_RSP_SIZE (16 + 8)
1658
1659#define GPSC_CMD 0x127
1660#define GPSC_REQ_SIZE (16 + 8)
1661#define GPSC_RSP_SIZE (16 + 2 + 2)
1662
1663
Andrew Vasquezcca53352005-08-26 19:08:30 -07001664/*
1665 * HBA attribute types.
1666 */
1667#define FDMI_HBA_ATTR_COUNT 9
1668#define FDMI_HBA_NODE_NAME 1
1669#define FDMI_HBA_MANUFACTURER 2
1670#define FDMI_HBA_SERIAL_NUMBER 3
1671#define FDMI_HBA_MODEL 4
1672#define FDMI_HBA_MODEL_DESCRIPTION 5
1673#define FDMI_HBA_HARDWARE_VERSION 6
1674#define FDMI_HBA_DRIVER_VERSION 7
1675#define FDMI_HBA_OPTION_ROM_VERSION 8
1676#define FDMI_HBA_FIRMWARE_VERSION 9
1677#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1678#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1679
1680struct ct_fdmi_hba_attr {
1681 uint16_t type;
1682 uint16_t len;
1683 union {
1684 uint8_t node_name[WWN_SIZE];
1685 uint8_t manufacturer[32];
1686 uint8_t serial_num[8];
1687 uint8_t model[16];
1688 uint8_t model_desc[80];
1689 uint8_t hw_version[16];
1690 uint8_t driver_version[32];
1691 uint8_t orom_version[16];
1692 uint8_t fw_version[16];
1693 uint8_t os_version[128];
1694 uint8_t max_ct_len[4];
1695 } a;
1696};
1697
1698struct ct_fdmi_hba_attributes {
1699 uint32_t count;
1700 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1701};
1702
1703/*
1704 * Port attribute types.
1705 */
1706#define FDMI_PORT_ATTR_COUNT 5
1707#define FDMI_PORT_FC4_TYPES 1
1708#define FDMI_PORT_SUPPORT_SPEED 2
1709#define FDMI_PORT_CURRENT_SPEED 3
1710#define FDMI_PORT_MAX_FRAME_SIZE 4
1711#define FDMI_PORT_OS_DEVICE_NAME 5
1712#define FDMI_PORT_HOST_NAME 6
1713
1714struct ct_fdmi_port_attr {
1715 uint16_t type;
1716 uint16_t len;
1717 union {
1718 uint8_t fc4_types[32];
1719 uint32_t sup_speed;
1720 uint32_t cur_speed;
1721 uint32_t max_frame_size;
1722 uint8_t os_dev_name[32];
1723 uint8_t host_name[32];
1724 } a;
1725};
1726
1727/*
1728 * Port Attribute Block.
1729 */
1730struct ct_fdmi_port_attributes {
1731 uint32_t count;
1732 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1733};
1734
1735/* FDMI definitions. */
1736#define GRHL_CMD 0x100
1737#define GHAT_CMD 0x101
1738#define GRPL_CMD 0x102
1739#define GPAT_CMD 0x110
1740
1741#define RHBA_CMD 0x200
1742#define RHBA_RSP_SIZE 16
1743
1744#define RHAT_CMD 0x201
1745#define RPRT_CMD 0x210
1746
1747#define RPA_CMD 0x211
1748#define RPA_RSP_SIZE 16
1749
1750#define DHBA_CMD 0x300
1751#define DHBA_REQ_SIZE (16 + 8)
1752#define DHBA_RSP_SIZE 16
1753
1754#define DHAT_CMD 0x301
1755#define DPRT_CMD 0x310
1756#define DPA_CMD 0x311
1757
Linus Torvalds1da177e2005-04-16 15:20:36 -07001758/* CT command header -- request/response common fields */
1759struct ct_cmd_hdr {
1760 uint8_t revision;
1761 uint8_t in_id[3];
1762 uint8_t gs_type;
1763 uint8_t gs_subtype;
1764 uint8_t options;
1765 uint8_t reserved;
1766};
1767
1768/* CT command request */
1769struct ct_sns_req {
1770 struct ct_cmd_hdr header;
1771 uint16_t command;
1772 uint16_t max_rsp_size;
1773 uint8_t fragment_id;
1774 uint8_t reserved[3];
1775
1776 union {
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001777 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001778 struct {
1779 uint8_t reserved;
1780 uint8_t port_id[3];
1781 } port_id;
1782
1783 struct {
1784 uint8_t port_type;
1785 uint8_t domain;
1786 uint8_t area;
1787 uint8_t reserved;
1788 } gid_pt;
1789
1790 struct {
1791 uint8_t reserved;
1792 uint8_t port_id[3];
1793 uint8_t fc4_types[32];
1794 } rft_id;
1795
1796 struct {
1797 uint8_t reserved;
1798 uint8_t port_id[3];
1799 uint16_t reserved2;
1800 uint8_t fc4_feature;
1801 uint8_t fc4_type;
1802 } rff_id;
1803
1804 struct {
1805 uint8_t reserved;
1806 uint8_t port_id[3];
1807 uint8_t node_name[8];
1808 } rnn_id;
1809
1810 struct {
1811 uint8_t node_name[8];
1812 uint8_t name_len;
1813 uint8_t sym_node_name[255];
1814 } rsnn_nn;
Andrew Vasquezcca53352005-08-26 19:08:30 -07001815
1816 struct {
1817 uint8_t hba_indentifier[8];
1818 } ghat;
1819
1820 struct {
1821 uint8_t hba_identifier[8];
1822 uint32_t entry_count;
1823 uint8_t port_name[8];
1824 struct ct_fdmi_hba_attributes attrs;
1825 } rhba;
1826
1827 struct {
1828 uint8_t hba_identifier[8];
1829 struct ct_fdmi_hba_attributes attrs;
1830 } rhat;
1831
1832 struct {
1833 uint8_t port_name[8];
1834 struct ct_fdmi_port_attributes attrs;
1835 } rpa;
1836
1837 struct {
1838 uint8_t port_name[8];
1839 } dhba;
1840
1841 struct {
1842 uint8_t port_name[8];
1843 } dhat;
1844
1845 struct {
1846 uint8_t port_name[8];
1847 } dprt;
1848
1849 struct {
1850 uint8_t port_name[8];
1851 } dpa;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001852
1853 struct {
1854 uint8_t port_name[8];
1855 } gpsc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001856 } req;
1857};
1858
1859/* CT command response header */
1860struct ct_rsp_hdr {
1861 struct ct_cmd_hdr header;
1862 uint16_t response;
1863 uint16_t residual;
1864 uint8_t fragment_id;
1865 uint8_t reason_code;
1866 uint8_t explanation_code;
1867 uint8_t vendor_unique;
1868};
1869
1870struct ct_sns_gid_pt_data {
1871 uint8_t control_byte;
1872 uint8_t port_id[3];
1873};
1874
1875struct ct_sns_rsp {
1876 struct ct_rsp_hdr header;
1877
1878 union {
1879 struct {
1880 uint8_t port_type;
1881 uint8_t port_id[3];
1882 uint8_t port_name[8];
1883 uint8_t sym_port_name_len;
1884 uint8_t sym_port_name[255];
1885 uint8_t node_name[8];
1886 uint8_t sym_node_name_len;
1887 uint8_t sym_node_name[255];
1888 uint8_t init_proc_assoc[8];
1889 uint8_t node_ip_addr[16];
1890 uint8_t class_of_service[4];
1891 uint8_t fc4_types[32];
1892 uint8_t ip_address[16];
1893 uint8_t fabric_port_name[8];
1894 uint8_t reserved;
1895 uint8_t hard_address[3];
1896 } ga_nxt;
1897
1898 struct {
1899 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1900 } gid_pt;
1901
1902 struct {
1903 uint8_t port_name[8];
1904 } gpn_id;
1905
1906 struct {
1907 uint8_t node_name[8];
1908 } gnn_id;
1909
1910 struct {
1911 uint8_t fc4_types[32];
1912 } gft_id;
Andrew Vasquezcca53352005-08-26 19:08:30 -07001913
1914 struct {
1915 uint32_t entry_count;
1916 uint8_t port_name[8];
1917 struct ct_fdmi_hba_attributes attrs;
1918 } ghat;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001919
1920 struct {
1921 uint8_t port_name[8];
1922 } gfpn_id;
1923
1924 struct {
1925 uint16_t speeds;
1926 uint16_t speed;
1927 } gpsc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001928 } rsp;
1929};
1930
1931struct ct_sns_pkt {
1932 union {
1933 struct ct_sns_req req;
1934 struct ct_sns_rsp rsp;
1935 } p;
1936};
1937
1938/*
1939 * SNS command structures -- for 2200 compatability.
1940 */
1941#define RFT_ID_SNS_SCMD_LEN 22
1942#define RFT_ID_SNS_CMD_SIZE 60
1943#define RFT_ID_SNS_DATA_SIZE 16
1944
1945#define RNN_ID_SNS_SCMD_LEN 10
1946#define RNN_ID_SNS_CMD_SIZE 36
1947#define RNN_ID_SNS_DATA_SIZE 16
1948
1949#define GA_NXT_SNS_SCMD_LEN 6
1950#define GA_NXT_SNS_CMD_SIZE 28
1951#define GA_NXT_SNS_DATA_SIZE (620 + 16)
1952
1953#define GID_PT_SNS_SCMD_LEN 6
1954#define GID_PT_SNS_CMD_SIZE 28
1955#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1956
1957#define GPN_ID_SNS_SCMD_LEN 6
1958#define GPN_ID_SNS_CMD_SIZE 28
1959#define GPN_ID_SNS_DATA_SIZE (8 + 16)
1960
1961#define GNN_ID_SNS_SCMD_LEN 6
1962#define GNN_ID_SNS_CMD_SIZE 28
1963#define GNN_ID_SNS_DATA_SIZE (8 + 16)
1964
1965struct sns_cmd_pkt {
1966 union {
1967 struct {
1968 uint16_t buffer_length;
1969 uint16_t reserved_1;
1970 uint32_t buffer_address[2];
1971 uint16_t subcommand_length;
1972 uint16_t reserved_2;
1973 uint16_t subcommand;
1974 uint16_t size;
1975 uint32_t reserved_3;
1976 uint8_t param[36];
1977 } cmd;
1978
1979 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1980 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1981 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1982 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1983 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1984 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1985 } p;
1986};
1987
Andrew Vasquez54333832005-11-09 15:49:04 -08001988struct fw_blob {
1989 char *name;
1990 uint32_t segs[4];
1991 const struct firmware *fw;
1992};
1993
Linus Torvalds1da177e2005-04-16 15:20:36 -07001994/* Return data from MBC_GET_ID_LIST call. */
1995struct gid_list_info {
1996 uint8_t al_pa;
1997 uint8_t area;
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001998 uint8_t domain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001999 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2000 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07002001 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002002};
2003#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2004
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002005/* NPIV */
2006typedef struct vport_info {
2007 uint8_t port_name[WWN_SIZE];
2008 uint8_t node_name[WWN_SIZE];
2009 int vp_id;
2010 uint16_t loop_id;
2011 unsigned long host_no;
2012 uint8_t port_id[3];
2013 int loop_state;
2014} vport_info_t;
2015
2016typedef struct vport_params {
2017 uint8_t port_name[WWN_SIZE];
2018 uint8_t node_name[WWN_SIZE];
2019 uint32_t options;
2020#define VP_OPTS_RETRY_ENABLE BIT_0
2021#define VP_OPTS_VP_DISABLE BIT_1
2022} vport_params_t;
2023
2024/* NPIV - return codes of VP create and modify */
2025#define VP_RET_CODE_OK 0
2026#define VP_RET_CODE_FATAL 1
2027#define VP_RET_CODE_WRONG_ID 2
2028#define VP_RET_CODE_WWPN 3
2029#define VP_RET_CODE_RESOURCES 4
2030#define VP_RET_CODE_NO_MEM 5
2031#define VP_RET_CODE_NOT_FOUND 6
2032
2033#define to_qla_parent(x) (((x)->parent) ? (x)->parent : (x))
2034
Linus Torvalds1da177e2005-04-16 15:20:36 -07002035/*
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002036 * ISP operations
2037 */
2038struct isp_operations {
2039
2040 int (*pci_config) (struct scsi_qla_host *);
2041 void (*reset_chip) (struct scsi_qla_host *);
2042 int (*chip_diag) (struct scsi_qla_host *);
2043 void (*config_rings) (struct scsi_qla_host *);
2044 void (*reset_adapter) (struct scsi_qla_host *);
2045 int (*nvram_config) (struct scsi_qla_host *);
2046 void (*update_fw_options) (struct scsi_qla_host *);
2047 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2048
2049 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2050 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2051
David Howells7d12e782006-10-05 14:55:46 +01002052 irq_handler_t intr_handler;
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002053 void (*enable_intrs) (struct scsi_qla_host *);
2054 void (*disable_intrs) (struct scsi_qla_host *);
2055
2056 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2057 int (*abort_target) (struct fc_port *);
2058 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2059 uint8_t, uint8_t, uint16_t *, uint8_t);
Andrew Vasquez1c7c6352005-07-06 10:30:57 -07002060 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2061 uint8_t, uint8_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002062
2063 uint16_t (*calc_req_entries) (uint16_t);
2064 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
Andrew Vasquez8c958a92005-07-06 10:30:47 -07002065 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
Andrew Vasquezcca53352005-08-26 19:08:30 -07002066 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2067 uint32_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002068
2069 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2070 uint32_t, uint32_t);
2071 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2072 uint32_t);
2073
2074 void (*fw_dump) (struct scsi_qla_host *, int);
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08002075
2076 int (*beacon_on) (struct scsi_qla_host *);
2077 int (*beacon_off) (struct scsi_qla_host *);
2078 void (*beacon_blink) (struct scsi_qla_host *);
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002079
2080 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2081 uint32_t, uint32_t);
2082 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2083 uint32_t);
Andrew Vasquez30c47662007-01-29 10:22:21 -08002084
2085 int (*get_flash_version) (struct scsi_qla_host *, void *);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002086};
2087
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002088/* MSI-X Support *************************************************************/
2089
2090#define QLA_MSIX_CHIP_REV_24XX 3
2091#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2092#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2093
2094#define QLA_MSIX_DEFAULT 0x00
2095#define QLA_MSIX_RSP_Q 0x01
2096
2097#define QLA_MSIX_ENTRIES 2
2098#define QLA_MIDX_DEFAULT 0
2099#define QLA_MIDX_RSP_Q 1
2100
2101struct scsi_qla_host;
2102
2103struct qla_msix_entry {
2104 int have_irq;
2105 uint16_t msix_vector;
2106 uint16_t msix_entry;
2107};
2108
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002109#define WATCH_INTERVAL 1 /* number of seconds */
2110
2111/* NPIV */
2112#define MAX_MULTI_ID_LOOP 126
2113#define MAX_MULTI_ID_FABRIC 64
2114#define MAX_NUM_VPORT_LOOP (MAX_MULTI_ID_LOOP - 1)
2115#define MAX_NUM_VPORT_FABRIC (MAX_MULTI_ID_FABRIC - 1)
2116#define MAX_NUM_VHBA_LOOP (MAX_MULTI_ID_LOOP - 1)
2117#define MAX_NUM_VHBA_FABRIC (MAX_MULTI_ID_FABRIC - 1)
2118
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002119/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002120 * Linux Host Adapter structure
2121 */
2122typedef struct scsi_qla_host {
2123 struct list_head list;
2124
2125 /* Commonly used flags and state information. */
2126 struct Scsi_Host *host;
2127 struct pci_dev *pdev;
2128
2129 unsigned long host_no;
2130 unsigned long instance;
2131
2132 volatile struct {
2133 uint32_t init_done :1;
2134 uint32_t online :1;
2135 uint32_t mbox_int :1;
2136 uint32_t mbox_busy :1;
2137 uint32_t rscn_queue_overflow :1;
2138 uint32_t reset_active :1;
2139
2140 uint32_t management_server_logged_in :1;
2141 uint32_t process_response_queue :1;
2142
2143 uint32_t disable_risc_code_load :1;
2144 uint32_t enable_64bit_addressing :1;
2145 uint32_t enable_lip_reset :1;
2146 uint32_t enable_lip_full_login :1;
2147 uint32_t enable_target_reset :1;
2148 uint32_t enable_led_scheme :1;
Andrew Vasquezd88021a2007-01-29 10:22:20 -08002149 uint32_t inta_enabled :1;
Andrew Vasquez3d716442005-07-06 10:30:26 -07002150 uint32_t msi_enabled :1;
2151 uint32_t msix_enabled :1;
Andrew Vasquezd4c760c2006-06-23 16:10:39 -07002152 uint32_t disable_serdes :1;
Andrew Vasquez4346b142006-12-13 19:20:28 -08002153 uint32_t gpsc_supported :1;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002154 uint32_t vsan_enabled :1;
2155 uint32_t npiv_supported :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002156 } flags;
2157
2158 atomic_t loop_state;
2159#define LOOP_TIMEOUT 1
2160#define LOOP_DOWN 2
2161#define LOOP_UP 3
2162#define LOOP_UPDATE 4
2163#define LOOP_READY 5
2164#define LOOP_DEAD 6
2165
2166 unsigned long dpc_flags;
2167#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2168#define RESET_ACTIVE 1
2169#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2170#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2171#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2172#define LOOP_RESYNC_ACTIVE 5
2173#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2174#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2175#define MAILBOX_RETRY 8
2176#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2177#define FAILOVER_EVENT_NEEDED 10
2178#define FAILOVER_EVENT 11
2179#define FAILOVER_NEEDED 12
2180#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2181#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2182#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2183#define ABORT_QUEUES_NEEDED 16
2184#define RELOGIN_NEEDED 17
2185#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2186#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2187#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2188#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2189#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002190#define IOCTL_ERROR_RECOVERY 23
Linus Torvalds1da177e2005-04-16 15:20:36 -07002191#define LOOP_RESET_NEEDED 24
Andrew Vasquez3d716442005-07-06 10:30:26 -07002192#define BEACON_BLINK_NEEDED 25
Andrew Vasquezcca53352005-08-26 19:08:30 -07002193#define REGISTER_FDMI_NEEDED 26
andrew.vasquez@qlogic.comd97994d2006-01-20 14:53:13 -08002194#define FCPORT_UPDATE_NEEDED 27
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002195#define VP_DPC_NEEDED 28 /* wake up for VP dpc handling */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002196
2197 uint32_t device_flags;
2198#define DFLG_LOCAL_DEVICES BIT_0
2199#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2200#define DFLG_FABRIC_DEVICES BIT_2
2201#define SWITCH_FOUND BIT_3
2202#define DFLG_NO_CABLE BIT_4
2203
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002204 uint32_t device_type;
2205#define DT_ISP2100 BIT_0
2206#define DT_ISP2200 BIT_1
2207#define DT_ISP2300 BIT_2
2208#define DT_ISP2312 BIT_3
2209#define DT_ISP2322 BIT_4
2210#define DT_ISP6312 BIT_5
2211#define DT_ISP6322 BIT_6
2212#define DT_ISP2422 BIT_7
2213#define DT_ISP2432 BIT_8
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002214#define DT_ISP5422 BIT_9
2215#define DT_ISP5432 BIT_10
2216#define DT_ISP_LAST (DT_ISP5432 << 1)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002217
Andrew Vasquezc76f2c02007-07-19 15:05:57 -07002218#define DT_IIDMA BIT_26
Andrew Vasqueze4289242007-07-19 15:05:56 -07002219#define DT_FWI2 BIT_27
andrew.vasquez@qlogic.com4a59f712006-03-09 14:27:39 -08002220#define DT_ZIO_SUPPORTED BIT_28
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002221#define DT_OEM_001 BIT_29
2222#define DT_ISP2200A BIT_30
2223#define DT_EXTENDED_IDS BIT_31
2224
2225#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2226#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2227#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2228#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2229#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2230#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2231#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2232#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2233#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2234#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002235#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2236#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002237
2238#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2239 IS_QLA6312(ha) || IS_QLA6322(ha))
2240#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002241#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002242
Andrew Vasquezc76f2c02007-07-19 15:05:57 -07002243#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
Andrew Vasqueze4289242007-07-19 15:05:56 -07002244#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
andrew.vasquez@qlogic.com4a59f712006-03-09 14:27:39 -08002245#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002246#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2247#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2248
Linus Torvalds1da177e2005-04-16 15:20:36 -07002249 /* SRB cache. */
2250#define SRB_MIN_REQ 128
2251 mempool_t *srb_mempool;
2252
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002253 /* This spinlock is used to protect "io transactions", you must
Adrian Bunk04187262006-06-30 18:23:04 +02002254 * acquire it before doing any IO to the card, eg with RD_REG*() and
Linus Torvalds1da177e2005-04-16 15:20:36 -07002255 * WRT_REG*() for the duration of your entire commandtransaction.
2256 *
2257 * This spinlock is of lower priority than the io request lock.
2258 */
2259
2260 spinlock_t hardware_lock ____cacheline_aligned;
2261
2262 device_reg_t __iomem *iobase; /* Base I/O address */
2263 unsigned long pio_address;
2264 unsigned long pio_length;
2265#define MIN_IOBASE_LEN 0x100
2266
2267 /* ISP ring lock, rings, and indexes */
2268 dma_addr_t request_dma; /* Physical address. */
2269 request_t *request_ring; /* Base virtual address */
2270 request_t *request_ring_ptr; /* Current address. */
2271 uint16_t req_ring_index; /* Current index. */
2272 uint16_t req_q_cnt; /* Number of available entries. */
2273 uint16_t request_q_length;
2274
2275 dma_addr_t response_dma; /* Physical address. */
2276 response_t *response_ring; /* Base virtual address */
2277 response_t *response_ring_ptr; /* Current address. */
2278 uint16_t rsp_ring_index; /* Current index. */
2279 uint16_t response_q_length;
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002280
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002281 struct isp_operations isp_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002282
2283 /* Outstandings ISP commands. */
2284 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002285 uint32_t current_outstanding_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002286 srb_t *status_srb; /* Status continuation entry. */
2287
Linus Torvalds1da177e2005-04-16 15:20:36 -07002288 /* ISP configuration data. */
2289 uint16_t loop_id; /* Host adapter loop id */
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002290 uint16_t switch_cap;
2291#define FLOGI_SEQ_DEL BIT_8
2292#define FLOGI_MID_SUPPORT BIT_10
2293#define FLOGI_VSAN_SUPPORT BIT_12
2294#define FLOGI_SP_SUPPORT BIT_13
Linus Torvalds1da177e2005-04-16 15:20:36 -07002295 uint16_t fb_rev;
2296
2297 port_id_t d_id; /* Host adapter port id */
2298 uint16_t max_public_loop_ids;
2299 uint16_t min_external_loopid; /* First external loop Id */
2300
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002301#define PORT_SPEED_UNKNOWN 0xFFFF
2302#define PORT_SPEED_1GB 0x00
2303#define PORT_SPEED_2GB 0x01
2304#define PORT_SPEED_4GB 0x03
Linus Torvalds1da177e2005-04-16 15:20:36 -07002305 uint16_t link_data_rate; /* F/W operating speed */
2306
2307 uint8_t current_topology;
2308 uint8_t prev_topology;
2309#define ISP_CFG_NL 1
2310#define ISP_CFG_N 2
2311#define ISP_CFG_FL 4
2312#define ISP_CFG_F 8
2313
2314 uint8_t operating_mode; /* F/W operating mode */
2315#define LOOP 0
2316#define P2P 1
2317#define LOOP_P2P 2
2318#define P2P_LOOP 3
2319
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002320 uint8_t marker_needed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002321
2322 uint8_t interrupts_on;
2323
2324 /* HBA serial number */
2325 uint8_t serial0;
2326 uint8_t serial1;
2327 uint8_t serial2;
2328
2329 /* NVRAM configuration data */
Andrew Vasquez3d716442005-07-06 10:30:26 -07002330 uint16_t nvram_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002331 uint16_t nvram_base;
andrew.vasquez@qlogic.com6f641792006-03-09 14:27:34 -08002332 uint16_t vpd_size;
2333 uint16_t vpd_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002334
2335 uint16_t loop_reset_delay;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002336 uint8_t retry_count;
2337 uint8_t login_timeout;
2338 uint16_t r_a_tov;
2339 int port_down_retry_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002340 uint8_t mbx_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002341 uint16_t last_loop_id;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002342 uint16_t mgmt_svr_loop_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002343
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002344 uint32_t login_retry_count;
Andrew Vasquezdf7baa52006-10-13 09:33:39 -07002345 int max_q_depth;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002346
2347 /* Fibre Channel Device List. */
2348 struct list_head fcports;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002349
Linus Torvalds1da177e2005-04-16 15:20:36 -07002350 /* RSCN queue. */
2351 uint32_t rscn_queue[MAX_RSCN_COUNT];
2352 uint8_t rscn_in_ptr;
2353 uint8_t rscn_out_ptr;
2354
2355 /* SNS command interfaces. */
2356 ms_iocb_entry_t *ms_iocb;
2357 dma_addr_t ms_iocb_dma;
2358 struct ct_sns_pkt *ct_sns;
2359 dma_addr_t ct_sns_dma;
2360 /* SNS command interfaces for 2200. */
2361 struct sns_cmd_pkt *sns_cmd;
2362 dma_addr_t sns_cmd_dma;
2363
Andrew Vasquez88729e52006-06-23 16:10:50 -07002364#define SFP_DEV_SIZE 256
2365#define SFP_BLOCK_SIZE 64
2366 void *sfp_data;
2367 dma_addr_t sfp_data_dma;
2368
Christoph Hellwig39a11242006-02-14 18:46:22 +01002369 struct task_struct *dpc_thread;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002370 uint8_t dpc_active; /* DPC routine is active */
2371
2372 /* Timeout timers. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002373 uint8_t loop_down_abort_time; /* port down timer */
2374 atomic_t loop_down_timer; /* loop down timer */
2375 uint8_t link_down_timeout; /* link down timeout */
2376
2377 uint32_t timer_active;
2378 struct timer_list timer;
2379
2380 dma_addr_t gid_list_dma;
2381 struct gid_list_info *gid_list;
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002382 int gid_list_info_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002383
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002384 /* Small DMA pool allocations -- maximum 256 bytes in length. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002385#define DMA_POOL_SIZE 256
2386 struct dma_pool *s_dma_pool;
2387
2388 dma_addr_t init_cb_dma;
Andrew Vasquez3d716442005-07-06 10:30:26 -07002389 init_cb_t *init_cb;
2390 int init_cb_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002391
Linus Torvalds1da177e2005-04-16 15:20:36 -07002392 /* These are used by mailbox operations. */
2393 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2394
2395 mbx_cmd_t *mcp;
2396 unsigned long mbx_cmd_flags;
2397#define MBX_INTERRUPT 1
2398#define MBX_INTR_WAIT 2
2399#define MBX_UPDATE_FLASH_ACTIVE 3
2400
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002402 struct semaphore vport_sem; /* Virtual port synchronization */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002403 struct semaphore mbx_intr_sem; /* Used for completion notification */
2404
2405 uint32_t mbx_flags;
2406#define MBX_IN_PROGRESS BIT_0
2407#define MBX_BUSY BIT_1 /* Got the Access */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002408#define MBX_SLEEPING_ON_SEM BIT_2
Linus Torvalds1da177e2005-04-16 15:20:36 -07002409#define MBX_POLLING_FOR_COMP BIT_3
2410#define MBX_COMPLETED BIT_4
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002411#define MBX_TIMEDOUT BIT_5
Linus Torvalds1da177e2005-04-16 15:20:36 -07002412#define MBX_ACCESS_TIMEDOUT BIT_6
2413
2414 mbx_cmd_t mc;
2415
Linus Torvalds1da177e2005-04-16 15:20:36 -07002416 /* Basic firmware related information. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002417 uint16_t fw_major_version;
2418 uint16_t fw_minor_version;
2419 uint16_t fw_subminor_version;
2420 uint16_t fw_attributes;
2421 uint32_t fw_memory_size;
2422 uint32_t fw_transfer_size;
Andrew Vasquez441d1072006-05-17 15:09:34 -07002423 uint32_t fw_srisc_address;
2424#define RISC_START_ADDRESS_2100 0x1000
2425#define RISC_START_ADDRESS_2300 0x800
2426#define RISC_START_ADDRESS_2400 0x100000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002427
2428 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2429 uint8_t fw_seriallink_options[4];
Andrew Vasquez3d716442005-07-06 10:30:26 -07002430 uint16_t fw_seriallink_options24[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002431
2432 /* Firmware dump information. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07002433 struct qla2xxx_fw_dump *fw_dump;
2434 uint32_t fw_dump_len;
Andrew Vasquezd4e3e042006-05-17 15:09:50 -07002435 int fw_dumped;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002436 int fw_dump_reading;
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07002437 dma_addr_t eft_dma;
2438 void *eft;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002439
2440 uint8_t host_str[16];
Andrew Vasquez3d716442005-07-06 10:30:26 -07002441 uint32_t pci_attr;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002442 uint16_t chip_revision;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002443
2444 uint16_t product_id[4];
2445
2446 uint8_t model_number[16+1];
2447#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2448 char *model_desc;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002449 uint8_t adapter_id[16+1];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002450
Andrew Vasquez3d716442005-07-06 10:30:26 -07002451 uint8_t *node_name;
2452 uint8_t *port_name;
Andrew Vasquez90991c82006-10-02 12:00:46 -07002453 uint8_t fabric_node_name[WWN_SIZE];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454 uint32_t isp_abort_cnt;
2455
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002456 /* Option ROM information. */
2457 char *optrom_buffer;
2458 uint32_t optrom_size;
2459 int optrom_state;
2460#define QLA_SWAITING 0
2461#define QLA_SREADING 1
2462#define QLA_SWRITING 2
2463
Andrew Vasquez30c47662007-01-29 10:22:21 -08002464 /* PCI expansion ROM image information. */
2465#define ROM_CODE_TYPE_BIOS 0
2466#define ROM_CODE_TYPE_FCODE 1
2467#define ROM_CODE_TYPE_EFI 3
2468 uint8_t bios_revision[2];
2469 uint8_t efi_revision[2];
2470 uint8_t fcode_revision[16];
2471 uint32_t fw_revision[4];
2472
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473 /* Needed for BEACON */
2474 uint16_t beacon_blink_led;
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08002475 uint8_t beacon_color_state;
2476#define QLA_LED_GRN_ON 0x01
2477#define QLA_LED_YLW_ON 0x02
2478#define QLA_LED_ABR_ON 0x04
2479#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2480 /* ISP2322: red, green, amber. */
Andrew Vasquez4fdfefe2005-10-27 11:09:48 -07002481
2482 uint16_t zio_mode;
2483 uint16_t zio_timer;
andrew.vasquez@qlogic.com392e2f62006-01-31 16:05:02 -08002484 struct fc_host_statistics fc_host_stat;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002485
2486 struct qla_msix_entry msix_entries[QLA_MSIX_ENTRIES];
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002487
2488 struct list_head vp_list; /* list of VP */
2489 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2490 uint8_t vp_idx_map[16];
2491 uint16_t num_vhosts; /* number of vports created */
2492 uint16_t num_vsans; /* number of vsan created */
2493 uint16_t vp_idx; /* vport ID */
2494
2495 struct scsi_qla_host *parent; /* holds pport */
2496 unsigned long vp_flags;
2497 struct list_head vp_fcports; /* list of fcports */
2498#define VP_IDX_ACQUIRED 0 /* bit no 0 */
2499#define VP_CREATE_NEEDED 1
2500#define VP_BIND_NEEDED 2
2501#define VP_DELETE_NEEDED 3
2502#define VP_SCR_NEEDED 4 /* State Change Request registration */
2503 atomic_t vp_state;
2504#define VP_OFFLINE 0
2505#define VP_ACTIVE 1
2506#define VP_FAILED 2
2507// #define VP_DISABLE 3
2508 uint16_t vp_err_state;
2509 uint16_t vp_prev_err_state;
2510#define VP_ERR_UNKWN 0
2511#define VP_ERR_PORTDWN 1
2512#define VP_ERR_FAB_UNSUPPORTED 2
2513#define VP_ERR_FAB_NORESOURCES 3
2514#define VP_ERR_FAB_LOGOUT 4
2515#define VP_ERR_ADAP_NORESOURCES 5
2516 int max_npiv_vports; /* 63 or 125 per topoloty */
2517 int cur_vport_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002518} scsi_qla_host_t;
2519
2520
2521/*
2522 * Macros to help code, maintain, etc.
2523 */
2524#define LOOP_TRANSITION(ha) \
2525 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
Andrew Vasquez23443b12005-12-06 10:57:06 -08002526 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
Linus Torvalds1da177e2005-04-16 15:20:36 -07002527 atomic_read(&ha->loop_state) == LOOP_DOWN)
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002528
Linus Torvalds1da177e2005-04-16 15:20:36 -07002529#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2530
2531#define qla_printk(level, ha, format, arg...) \
2532 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2533
2534/*
2535 * qla2x00 local function return status codes
2536 */
2537#define MBS_MASK 0x3fff
2538
2539#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2540#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2541#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2542#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2543#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2544#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2545#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2546#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2547#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2548#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2549
2550#define QLA_FUNCTION_TIMEOUT 0x100
2551#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2552#define QLA_FUNCTION_FAILED 0x102
2553#define QLA_MEMORY_ALLOC_FAILED 0x103
2554#define QLA_LOCK_TIMEOUT 0x104
2555#define QLA_ABORTED 0x105
2556#define QLA_SUSPENDED 0x106
2557#define QLA_BUSY 0x107
2558#define QLA_RSCNS_HANDLED 0x108
Andrew Vasquezcca53352005-08-26 19:08:30 -07002559#define QLA_ALREADY_REGISTERED 0x109
Linus Torvalds1da177e2005-04-16 15:20:36 -07002560
Linus Torvalds1da177e2005-04-16 15:20:36 -07002561#define NVRAM_DELAY() udelay(10)
2562
2563#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2564
2565/*
2566 * Flash support definitions
2567 */
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002568#define OPTROM_SIZE_2300 0x20000
2569#define OPTROM_SIZE_2322 0x100000
2570#define OPTROM_SIZE_24XX 0x100000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002571
2572#include "qla_gbl.h"
2573#include "qla_dbg.h"
2574#include "qla_inline.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -07002575
Linus Torvalds1da177e2005-04-16 15:20:36 -07002576#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2577#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2578#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2579#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2580#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2581#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2582
2583#endif