blob: 1e7bdcdcb2955d22e0c9492d55b29eb11255cd1b [file] [log] [blame]
Clemens Ladisch3c57e892009-12-16 21:38:25 +01001/*
Wei Hu30b146d2013-08-23 13:14:03 -07002 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
Clemens Ladisch3c57e892009-12-16 21:38:25 +01003 *
4 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This driver is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 * See the GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/err.h>
21#include <linux/hwmon.h>
22#include <linux/hwmon-sysfs.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <asm/processor.h>
27
Andre Przywara9e581312011-05-25 20:43:31 +020028MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
Clemens Ladisch3c57e892009-12-16 21:38:25 +010029MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
30MODULE_LICENSE("GPL");
31
32static bool force;
33module_param(force, bool, 0444);
34MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
35
Aravind Gopalakrishnanf89ce272014-08-14 18:15:27 -050036/* Provide lock for writing to NB_SMU_IND_ADDR */
37static DEFINE_MUTEX(nb_smu_ind_mutex);
38
Clemens Ladischc5114a12010-01-10 20:52:34 +010039/* CPUID function 0x80000001, ebx */
40#define CPUID_PKGTYPE_MASK 0xf0000000
41#define CPUID_PKGTYPE_F 0x00000000
42#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
43
44/* DRAM controller (PCI function 2) */
45#define REG_DCT0_CONFIG_HIGH 0x094
46#define DDR3_MODE 0x00000100
47
48/* miscellaneous (PCI function 3) */
Clemens Ladisch3c57e892009-12-16 21:38:25 +010049#define REG_HARDWARE_THERMAL_CONTROL 0x64
50#define HTC_ENABLE 0x00000001
51
52#define REG_REPORTED_TEMPERATURE 0xa4
53
54#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
55#define NB_CAP_HTC 0x00000400
56
Aravind Gopalakrishnanf89ce272014-08-14 18:15:27 -050057/*
58 * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
59 * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
60 * Control]
61 */
62#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
63#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3 0x1573
64
65static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
66 int offset, u32 *val)
67{
68 mutex_lock(&nb_smu_ind_mutex);
69 pci_bus_write_config_dword(pdev->bus, devfn,
70 0xb8, offset);
71 pci_bus_read_config_dword(pdev->bus, devfn,
72 0xbc, val);
73 mutex_unlock(&nb_smu_ind_mutex);
74}
75
Clemens Ladisch3c57e892009-12-16 21:38:25 +010076static ssize_t show_temp(struct device *dev,
77 struct device_attribute *attr, char *buf)
78{
79 u32 regval;
Guenter Roeck3e3e1022014-08-15 09:27:03 -070080 struct pci_dev *pdev = dev_get_drvdata(dev);
Clemens Ladisch3c57e892009-12-16 21:38:25 +010081
Aravind Gopalakrishnanf89ce272014-08-14 18:15:27 -050082 if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
83 amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
84 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
85 &regval);
86 } else {
87 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
88 }
Clemens Ladisch3c57e892009-12-16 21:38:25 +010089 return sprintf(buf, "%u\n", (regval >> 21) * 125);
90}
91
92static ssize_t show_temp_max(struct device *dev,
93 struct device_attribute *attr, char *buf)
94{
95 return sprintf(buf, "%d\n", 70 * 1000);
96}
97
98static ssize_t show_temp_crit(struct device *dev,
99 struct device_attribute *devattr, char *buf)
100{
101 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
102 int show_hyst = attr->index;
103 u32 regval;
104 int value;
105
Guenter Roeck3e3e1022014-08-15 09:27:03 -0700106 pci_read_config_dword(dev_get_drvdata(dev),
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100107 REG_HARDWARE_THERMAL_CONTROL, &regval);
108 value = ((regval >> 16) & 0x7f) * 500 + 52000;
109 if (show_hyst)
110 value -= ((regval >> 24) & 0xf) * 500;
111 return sprintf(buf, "%d\n", value);
112}
113
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100114static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL);
115static DEVICE_ATTR(temp1_max, S_IRUGO, show_temp_max, NULL);
116static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
117static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
Guenter Roeck3e3e1022014-08-15 09:27:03 -0700118
119static umode_t k10temp_is_visible(struct kobject *kobj,
120 struct attribute *attr, int index)
121{
122 struct device *dev = container_of(kobj, struct device, kobj);
123 struct pci_dev *pdev = dev_get_drvdata(dev);
124
125 if (index >= 2) {
126 u32 reg_caps, reg_htc;
127
128 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
129 &reg_caps);
130 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
131 &reg_htc);
132 if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
133 return 0;
134 }
135 return attr->mode;
136}
137
138static struct attribute *k10temp_attrs[] = {
139 &dev_attr_temp1_input.attr,
140 &dev_attr_temp1_max.attr,
141 &sensor_dev_attr_temp1_crit.dev_attr.attr,
142 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
143 NULL
144};
145
146static const struct attribute_group k10temp_group = {
147 .attrs = k10temp_attrs,
148 .is_visible = k10temp_is_visible,
149};
150__ATTRIBUTE_GROUPS(k10temp);
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100151
Bill Pemberton6c931ae2012-11-19 13:22:35 -0500152static bool has_erratum_319(struct pci_dev *pdev)
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100153{
Clemens Ladischc5114a12010-01-10 20:52:34 +0100154 u32 pkg_type, reg_dram_cfg;
155
156 if (boot_cpu_data.x86 != 0x10)
157 return false;
158
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100159 /*
Clemens Ladischc5114a12010-01-10 20:52:34 +0100160 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
161 * may be unreliable.
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100162 */
Clemens Ladischc5114a12010-01-10 20:52:34 +0100163 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
164 if (pkg_type == CPUID_PKGTYPE_F)
165 return true;
166 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
167 return false;
168
Jean Delvareeefc2d92010-06-20 09:22:31 +0200169 /* DDR3 memory implies socket AM3, which is good */
Clemens Ladischc5114a12010-01-10 20:52:34 +0100170 pci_bus_read_config_dword(pdev->bus,
171 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
172 REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
Jean Delvareeefc2d92010-06-20 09:22:31 +0200173 if (reg_dram_cfg & DDR3_MODE)
174 return false;
175
176 /*
177 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
178 * memory. We blacklist all the cores which do exist in socket AM2+
179 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
180 * and AM3 formats, but that's the best we can do.
181 */
182 return boot_cpu_data.x86_model < 4 ||
183 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100184}
185
Bill Pemberton6c931ae2012-11-19 13:22:35 -0500186static int k10temp_probe(struct pci_dev *pdev,
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100187 const struct pci_device_id *id)
188{
Clemens Ladischc5114a12010-01-10 20:52:34 +0100189 int unreliable = has_erratum_319(pdev);
Guenter Roeck3e3e1022014-08-15 09:27:03 -0700190 struct device *dev = &pdev->dev;
191 struct device *hwmon_dev;
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100192
Guenter Roeck3e3e1022014-08-15 09:27:03 -0700193 if (unreliable) {
194 if (!force) {
195 dev_err(dev,
196 "unreliable CPU thermal sensor; monitoring disabled\n");
197 return -ENODEV;
198 }
199 dev_warn(dev,
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100200 "unreliable CPU thermal sensor; check erratum 319\n");
Guenter Roeck3e3e1022014-08-15 09:27:03 -0700201 }
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100202
Guenter Roeck3e3e1022014-08-15 09:27:03 -0700203 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", pdev,
204 k10temp_groups);
205 return PTR_ERR_OR_ZERO(hwmon_dev);
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100206}
207
Jingoo Hancd9bb052013-12-03 07:10:29 +0000208static const struct pci_device_id k10temp_id_table[] = {
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100209 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
210 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
Clemens Ladischaa4790a2011-02-17 03:22:40 -0500211 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
Andre Przywara9e581312011-05-25 20:43:31 +0200212 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
Borislav Petkov24214442012-05-04 18:28:21 +0200213 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
Phil Pokornyd303b1b2014-01-14 10:46:46 -0800214 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
Aravind Gopalakrishnanf89ce272014-08-14 18:15:27 -0500215 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
Wei Hu30b146d2013-08-23 13:14:03 -0700216 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
Aravind Gopalakrishnanec015952014-03-11 16:25:59 -0500217 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100218 {}
219};
220MODULE_DEVICE_TABLE(pci, k10temp_id_table);
221
222static struct pci_driver k10temp_driver = {
223 .name = "k10temp",
224 .id_table = k10temp_id_table,
225 .probe = k10temp_probe,
Clemens Ladisch3c57e892009-12-16 21:38:25 +0100226};
227
Axel Linf71f5a52012-04-02 21:25:46 -0400228module_pci_driver(k10temp_driver);