blob: a29afb37c48ca865f5cc6815e7a038956a519dc7 [file] [log] [blame]
Carlo Caioned00680e2013-07-30 21:20:46 +02001/*
2 * sunxi Watchdog Driver
3 *
4 * Copyright (c) 2013 Carlo Caione
5 * 2012 Henrik Nordstrom
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * Based on xen_wdt.c
13 * (c) Copyright 2010 Novell, Inc.
14 */
15
16#include <linux/clk.h>
Maxime Ripard440e96b2014-05-06 21:44:19 -050017#include <linux/delay.h>
Carlo Caioned00680e2013-07-30 21:20:46 +020018#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/moduleparam.h>
Guenter Roeckd20a1d92014-09-26 00:03:17 +000024#include <linux/notifier.h>
Carlo Caioned00680e2013-07-30 21:20:46 +020025#include <linux/of.h>
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +080026#include <linux/of_device.h>
Carlo Caioned00680e2013-07-30 21:20:46 +020027#include <linux/platform_device.h>
Maxime Ripard440e96b2014-05-06 21:44:19 -050028#include <linux/reboot.h>
Carlo Caioned00680e2013-07-30 21:20:46 +020029#include <linux/types.h>
30#include <linux/watchdog.h>
31
32#define WDT_MAX_TIMEOUT 16
33#define WDT_MIN_TIMEOUT 1
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +080034#define WDT_TIMEOUT_MASK 0x0F
Carlo Caioned00680e2013-07-30 21:20:46 +020035
Carlo Caioned00680e2013-07-30 21:20:46 +020036#define WDT_CTRL_RELOAD ((1 << 0) | (0x0a57 << 1))
37
Carlo Caioned00680e2013-07-30 21:20:46 +020038#define WDT_MODE_EN (1 << 0)
Carlo Caioned00680e2013-07-30 21:20:46 +020039
40#define DRV_NAME "sunxi-wdt"
41#define DRV_VERSION "1.0"
42
43static bool nowayout = WATCHDOG_NOWAYOUT;
44static unsigned int timeout = WDT_MAX_TIMEOUT;
45
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +080046/*
47 * This structure stores the register offsets for different variants
48 * of Allwinner's watchdog hardware.
49 */
50struct sunxi_wdt_reg {
51 u8 wdt_ctrl;
52 u8 wdt_cfg;
53 u8 wdt_mode;
54 u8 wdt_timeout_shift;
55 u8 wdt_reset_mask;
56 u8 wdt_reset_val;
57};
58
Carlo Caioned00680e2013-07-30 21:20:46 +020059struct sunxi_wdt_dev {
60 struct watchdog_device wdt_dev;
61 void __iomem *wdt_base;
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +080062 const struct sunxi_wdt_reg *wdt_regs;
Guenter Roeckd20a1d92014-09-26 00:03:17 +000063 struct notifier_block restart_handler;
Carlo Caioned00680e2013-07-30 21:20:46 +020064};
65
66/*
67 * wdt_timeout_map maps the watchdog timer interval value in seconds to
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +080068 * the value of the register WDT_MODE at bits .wdt_timeout_shift ~ +3
Carlo Caioned00680e2013-07-30 21:20:46 +020069 *
70 * [timeout seconds] = register value
71 *
72 */
73
74static const int wdt_timeout_map[] = {
Emilio López51ee34a2014-04-04 14:24:25 -030075 [1] = 0x1, /* 1s */
76 [2] = 0x2, /* 2s */
77 [3] = 0x3, /* 3s */
78 [4] = 0x4, /* 4s */
79 [5] = 0x5, /* 5s */
80 [6] = 0x6, /* 6s */
81 [8] = 0x7, /* 8s */
82 [10] = 0x8, /* 10s */
83 [12] = 0x9, /* 12s */
84 [14] = 0xA, /* 14s */
85 [16] = 0xB, /* 16s */
Carlo Caioned00680e2013-07-30 21:20:46 +020086};
87
Maxime Ripard440e96b2014-05-06 21:44:19 -050088
Guenter Roeckd20a1d92014-09-26 00:03:17 +000089static int sunxi_restart_handle(struct notifier_block *this, unsigned long mode,
90 void *cmd)
Maxime Ripard440e96b2014-05-06 21:44:19 -050091{
Guenter Roeckd20a1d92014-09-26 00:03:17 +000092 struct sunxi_wdt_dev *sunxi_wdt = container_of(this,
93 struct sunxi_wdt_dev,
94 restart_handler);
95 void __iomem *wdt_base = sunxi_wdt->wdt_base;
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +080096 const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
97 u32 val;
Guenter Roeckd20a1d92014-09-26 00:03:17 +000098
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +080099 /* Set system reset function */
100 val = readl(wdt_base + regs->wdt_cfg);
101 val &= ~(regs->wdt_reset_mask);
102 val |= regs->wdt_reset_val;
103 writel(val, wdt_base + regs->wdt_cfg);
104
105 /* Set lowest timeout and enable watchdog */
106 val = readl(wdt_base + regs->wdt_mode);
107 val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
108 val |= WDT_MODE_EN;
109 writel(val, wdt_base + regs->wdt_mode);
Maxime Ripard440e96b2014-05-06 21:44:19 -0500110
111 /*
112 * Restart the watchdog. The default (and lowest) interval
113 * value for the watchdog is 0.5s.
114 */
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800115 writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
Maxime Ripard440e96b2014-05-06 21:44:19 -0500116
117 while (1) {
118 mdelay(5);
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800119 val = readl(wdt_base + regs->wdt_mode);
120 val |= WDT_MODE_EN;
121 writel(val, wdt_base + regs->wdt_mode);
Maxime Ripard440e96b2014-05-06 21:44:19 -0500122 }
Guenter Roeckd20a1d92014-09-26 00:03:17 +0000123 return NOTIFY_DONE;
Maxime Ripard440e96b2014-05-06 21:44:19 -0500124}
125
Carlo Caioned00680e2013-07-30 21:20:46 +0200126static int sunxi_wdt_ping(struct watchdog_device *wdt_dev)
127{
128 struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
129 void __iomem *wdt_base = sunxi_wdt->wdt_base;
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800130 const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
Carlo Caioned00680e2013-07-30 21:20:46 +0200131
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800132 writel(WDT_CTRL_RELOAD, wdt_base + regs->wdt_ctrl);
Carlo Caioned00680e2013-07-30 21:20:46 +0200133
134 return 0;
135}
136
137static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev,
138 unsigned int timeout)
139{
140 struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
141 void __iomem *wdt_base = sunxi_wdt->wdt_base;
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800142 const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
Carlo Caioned00680e2013-07-30 21:20:46 +0200143 u32 reg;
144
145 if (wdt_timeout_map[timeout] == 0)
146 timeout++;
147
148 sunxi_wdt->wdt_dev.timeout = timeout;
149
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800150 reg = readl(wdt_base + regs->wdt_mode);
151 reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
152 reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
153 writel(reg, wdt_base + regs->wdt_mode);
Carlo Caioned00680e2013-07-30 21:20:46 +0200154
155 sunxi_wdt_ping(wdt_dev);
156
157 return 0;
158}
159
160static int sunxi_wdt_stop(struct watchdog_device *wdt_dev)
161{
162 struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
163 void __iomem *wdt_base = sunxi_wdt->wdt_base;
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800164 const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
Carlo Caioned00680e2013-07-30 21:20:46 +0200165
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800166 writel(0, wdt_base + regs->wdt_mode);
Carlo Caioned00680e2013-07-30 21:20:46 +0200167
168 return 0;
169}
170
171static int sunxi_wdt_start(struct watchdog_device *wdt_dev)
172{
173 u32 reg;
174 struct sunxi_wdt_dev *sunxi_wdt = watchdog_get_drvdata(wdt_dev);
175 void __iomem *wdt_base = sunxi_wdt->wdt_base;
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800176 const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
Carlo Caioned00680e2013-07-30 21:20:46 +0200177 int ret;
178
179 ret = sunxi_wdt_set_timeout(&sunxi_wdt->wdt_dev,
180 sunxi_wdt->wdt_dev.timeout);
181 if (ret < 0)
182 return ret;
183
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800184 /* Set system reset function */
185 reg = readl(wdt_base + regs->wdt_cfg);
186 reg &= ~(regs->wdt_reset_mask);
187 reg |= ~(regs->wdt_reset_val);
188 writel(reg, wdt_base + regs->wdt_cfg);
189
190 /* Enable watchdog */
191 reg = readl(wdt_base + regs->wdt_mode);
192 reg |= WDT_MODE_EN;
193 writel(reg, wdt_base + regs->wdt_mode);
Carlo Caioned00680e2013-07-30 21:20:46 +0200194
195 return 0;
196}
197
198static const struct watchdog_info sunxi_wdt_info = {
199 .identity = DRV_NAME,
200 .options = WDIOF_SETTIMEOUT |
201 WDIOF_KEEPALIVEPING |
202 WDIOF_MAGICCLOSE,
203};
204
205static const struct watchdog_ops sunxi_wdt_ops = {
206 .owner = THIS_MODULE,
207 .start = sunxi_wdt_start,
208 .stop = sunxi_wdt_stop,
209 .ping = sunxi_wdt_ping,
210 .set_timeout = sunxi_wdt_set_timeout,
211};
212
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800213static const struct sunxi_wdt_reg sun4i_wdt_reg = {
214 .wdt_ctrl = 0x00,
215 .wdt_cfg = 0x04,
216 .wdt_mode = 0x04,
217 .wdt_timeout_shift = 3,
218 .wdt_reset_mask = 0x02,
219 .wdt_reset_val = 0x02,
220};
221
Chen-Yu Tsaic5ec6182014-09-22 00:05:19 +0800222static const struct sunxi_wdt_reg sun6i_wdt_reg = {
223 .wdt_ctrl = 0x10,
224 .wdt_cfg = 0x14,
225 .wdt_mode = 0x18,
226 .wdt_timeout_shift = 4,
227 .wdt_reset_mask = 0x03,
228 .wdt_reset_val = 0x01,
229};
230
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800231static const struct of_device_id sunxi_wdt_dt_ids[] = {
232 { .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
Chen-Yu Tsaic5ec6182014-09-22 00:05:19 +0800233 { .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800234 { /* sentinel */ }
235};
236MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
237
Maxime Ripard1d5898b2013-10-05 16:20:17 +0200238static int sunxi_wdt_probe(struct platform_device *pdev)
Carlo Caioned00680e2013-07-30 21:20:46 +0200239{
240 struct sunxi_wdt_dev *sunxi_wdt;
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800241 const struct of_device_id *device;
Carlo Caioned00680e2013-07-30 21:20:46 +0200242 struct resource *res;
243 int err;
244
245 sunxi_wdt = devm_kzalloc(&pdev->dev, sizeof(*sunxi_wdt), GFP_KERNEL);
246 if (!sunxi_wdt)
247 return -EINVAL;
248
249 platform_set_drvdata(pdev, sunxi_wdt);
250
Chen-Yu Tsaif2147de2014-09-22 00:05:18 +0800251 device = of_match_device(sunxi_wdt_dt_ids, &pdev->dev);
252 if (!device)
253 return -ENODEV;
254
255 sunxi_wdt->wdt_regs = device->data;
256
Carlo Caioned00680e2013-07-30 21:20:46 +0200257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
258 sunxi_wdt->wdt_base = devm_ioremap_resource(&pdev->dev, res);
259 if (IS_ERR(sunxi_wdt->wdt_base))
260 return PTR_ERR(sunxi_wdt->wdt_base);
261
262 sunxi_wdt->wdt_dev.info = &sunxi_wdt_info;
263 sunxi_wdt->wdt_dev.ops = &sunxi_wdt_ops;
264 sunxi_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
265 sunxi_wdt->wdt_dev.max_timeout = WDT_MAX_TIMEOUT;
266 sunxi_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
267 sunxi_wdt->wdt_dev.parent = &pdev->dev;
268
269 watchdog_init_timeout(&sunxi_wdt->wdt_dev, timeout, &pdev->dev);
270 watchdog_set_nowayout(&sunxi_wdt->wdt_dev, nowayout);
271
272 watchdog_set_drvdata(&sunxi_wdt->wdt_dev, sunxi_wdt);
273
274 sunxi_wdt_stop(&sunxi_wdt->wdt_dev);
275
276 err = watchdog_register_device(&sunxi_wdt->wdt_dev);
277 if (unlikely(err))
278 return err;
279
Guenter Roeckd20a1d92014-09-26 00:03:17 +0000280 sunxi_wdt->restart_handler.notifier_call = sunxi_restart_handle;
281 sunxi_wdt->restart_handler.priority = 128;
282 err = register_restart_handler(&sunxi_wdt->restart_handler);
283 if (err)
284 dev_err(&pdev->dev,
285 "cannot register restart handler (err=%d)\n", err);
Maxime Ripard440e96b2014-05-06 21:44:19 -0500286
Carlo Caioned00680e2013-07-30 21:20:46 +0200287 dev_info(&pdev->dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)",
288 sunxi_wdt->wdt_dev.timeout, nowayout);
289
290 return 0;
291}
292
Maxime Ripard1d5898b2013-10-05 16:20:17 +0200293static int sunxi_wdt_remove(struct platform_device *pdev)
Carlo Caioned00680e2013-07-30 21:20:46 +0200294{
295 struct sunxi_wdt_dev *sunxi_wdt = platform_get_drvdata(pdev);
296
Guenter Roeckd20a1d92014-09-26 00:03:17 +0000297 unregister_restart_handler(&sunxi_wdt->restart_handler);
Maxime Ripard440e96b2014-05-06 21:44:19 -0500298
Carlo Caioned00680e2013-07-30 21:20:46 +0200299 watchdog_unregister_device(&sunxi_wdt->wdt_dev);
300 watchdog_set_drvdata(&sunxi_wdt->wdt_dev, NULL);
301
302 return 0;
303}
304
305static void sunxi_wdt_shutdown(struct platform_device *pdev)
306{
307 struct sunxi_wdt_dev *sunxi_wdt = platform_get_drvdata(pdev);
308
309 sunxi_wdt_stop(&sunxi_wdt->wdt_dev);
310}
311
Carlo Caioned00680e2013-07-30 21:20:46 +0200312static struct platform_driver sunxi_wdt_driver = {
313 .probe = sunxi_wdt_probe,
314 .remove = sunxi_wdt_remove,
315 .shutdown = sunxi_wdt_shutdown,
316 .driver = {
Carlo Caioned00680e2013-07-30 21:20:46 +0200317 .name = DRV_NAME,
Sachin Kamat85eee812013-09-30 10:12:51 +0530318 .of_match_table = sunxi_wdt_dt_ids,
Carlo Caioned00680e2013-07-30 21:20:46 +0200319 },
320};
321
322module_platform_driver(sunxi_wdt_driver);
323
324module_param(timeout, uint, 0);
325MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
326
327module_param(nowayout, bool, 0);
328MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
329 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
330
331MODULE_LICENSE("GPL");
332MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
333MODULE_AUTHOR("Henrik Nordstrom <henrik@henriknordstrom.net>");
334MODULE_DESCRIPTION("sunxi WatchDog Timer Driver");
335MODULE_VERSION(DRV_VERSION);