Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1 | /* |
| 2 | * MUSB OTG driver host support |
| 3 | * |
| 4 | * Copyright 2005 Mentor Graphics Corporation |
| 5 | * Copyright (C) 2005-2006 by Texas Instruments |
| 6 | * Copyright (C) 2006-2007 Nokia Corporation |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame^] | 7 | * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * version 2 as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 21 | * 02110-1301 USA |
| 22 | * |
| 23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 33 | * |
| 34 | */ |
| 35 | |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/kernel.h> |
| 38 | #include <linux/delay.h> |
| 39 | #include <linux/sched.h> |
| 40 | #include <linux/slab.h> |
| 41 | #include <linux/errno.h> |
| 42 | #include <linux/init.h> |
| 43 | #include <linux/list.h> |
| 44 | |
| 45 | #include "musb_core.h" |
| 46 | #include "musb_host.h" |
| 47 | |
| 48 | |
| 49 | /* MUSB HOST status 22-mar-2006 |
| 50 | * |
| 51 | * - There's still lots of partial code duplication for fault paths, so |
| 52 | * they aren't handled as consistently as they need to be. |
| 53 | * |
| 54 | * - PIO mostly behaved when last tested. |
| 55 | * + including ep0, with all usbtest cases 9, 10 |
| 56 | * + usbtest 14 (ep0out) doesn't seem to run at all |
| 57 | * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest |
| 58 | * configurations, but otherwise double buffering passes basic tests. |
| 59 | * + for 2.6.N, for N > ~10, needs API changes for hcd framework. |
| 60 | * |
| 61 | * - DMA (CPPI) ... partially behaves, not currently recommended |
| 62 | * + about 1/15 the speed of typical EHCI implementations (PCI) |
| 63 | * + RX, all too often reqpkt seems to misbehave after tx |
| 64 | * + TX, no known issues (other than evident silicon issue) |
| 65 | * |
| 66 | * - DMA (Mentor/OMAP) ...has at least toggle update problems |
| 67 | * |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 68 | * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet |
| 69 | * starvation ... nothing yet for TX, interrupt, or bulk. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 70 | * |
| 71 | * - Not tested with HNP, but some SRP paths seem to behave. |
| 72 | * |
| 73 | * NOTE 24-August-2006: |
| 74 | * |
| 75 | * - Bulk traffic finally uses both sides of hardware ep1, freeing up an |
| 76 | * extra endpoint for periodic use enabling hub + keybd + mouse. That |
| 77 | * mostly works, except that with "usbnet" it's easy to trigger cases |
| 78 | * with "ping" where RX loses. (a) ping to davinci, even "ping -f", |
| 79 | * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses |
| 80 | * although ARP RX wins. (That test was done with a full speed link.) |
| 81 | */ |
| 82 | |
| 83 | |
| 84 | /* |
| 85 | * NOTE on endpoint usage: |
| 86 | * |
| 87 | * CONTROL transfers all go through ep0. BULK ones go through dedicated IN |
| 88 | * and OUT endpoints ... hardware is dedicated for those "async" queue(s). |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 89 | * (Yes, bulk _could_ use more of the endpoints than that, and would even |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 90 | * benefit from it.) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 91 | * |
| 92 | * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. |
| 93 | * So far that scheduling is both dumb and optimistic: the endpoint will be |
| 94 | * "claimed" until its software queue is no longer refilled. No multiplexing |
| 95 | * of transfers between endpoints, or anything clever. |
| 96 | */ |
| 97 | |
| 98 | |
| 99 | static void musb_ep_program(struct musb *musb, u8 epnum, |
| 100 | struct urb *urb, unsigned int nOut, |
| 101 | u8 *buf, u32 len); |
| 102 | |
| 103 | /* |
| 104 | * Clear TX fifo. Needed to avoid BABBLE errors. |
| 105 | */ |
David Brownell | c767c1c | 2008-09-11 11:53:23 +0300 | [diff] [blame] | 106 | static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 107 | { |
| 108 | void __iomem *epio = ep->regs; |
| 109 | u16 csr; |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 110 | u16 lastcsr = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 111 | int retries = 1000; |
| 112 | |
| 113 | csr = musb_readw(epio, MUSB_TXCSR); |
| 114 | while (csr & MUSB_TXCSR_FIFONOTEMPTY) { |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 115 | if (csr != lastcsr) |
| 116 | DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); |
| 117 | lastcsr = csr; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 118 | csr |= MUSB_TXCSR_FLUSHFIFO; |
| 119 | musb_writew(epio, MUSB_TXCSR, csr); |
| 120 | csr = musb_readw(epio, MUSB_TXCSR); |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 121 | if (WARN(retries-- < 1, |
| 122 | "Could not flush host TX%d fifo: csr: %04x\n", |
| 123 | ep->epnum, csr)) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 124 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 125 | mdelay(1); |
| 126 | } |
| 127 | } |
| 128 | |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 129 | static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) |
| 130 | { |
| 131 | void __iomem *epio = ep->regs; |
| 132 | u16 csr; |
| 133 | int retries = 5; |
| 134 | |
| 135 | /* scrub any data left in the fifo */ |
| 136 | do { |
| 137 | csr = musb_readw(epio, MUSB_TXCSR); |
| 138 | if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) |
| 139 | break; |
| 140 | musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); |
| 141 | csr = musb_readw(epio, MUSB_TXCSR); |
| 142 | udelay(10); |
| 143 | } while (--retries); |
| 144 | |
| 145 | WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", |
| 146 | ep->epnum, csr); |
| 147 | |
| 148 | /* and reset for the next transfer */ |
| 149 | musb_writew(epio, MUSB_TXCSR, 0); |
| 150 | } |
| 151 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 152 | /* |
| 153 | * Start transmit. Caller is responsible for locking shared resources. |
| 154 | * musb must be locked. |
| 155 | */ |
| 156 | static inline void musb_h_tx_start(struct musb_hw_ep *ep) |
| 157 | { |
| 158 | u16 txcsr; |
| 159 | |
| 160 | /* NOTE: no locks here; caller should lock and select EP */ |
| 161 | if (ep->epnum) { |
| 162 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); |
| 163 | txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; |
| 164 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); |
| 165 | } else { |
| 166 | txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; |
| 167 | musb_writew(ep->regs, MUSB_CSR0, txcsr); |
| 168 | } |
| 169 | |
| 170 | } |
| 171 | |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame^] | 172 | static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 173 | { |
| 174 | u16 txcsr; |
| 175 | |
| 176 | /* NOTE: no locks here; caller should lock and select EP */ |
| 177 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); |
| 178 | txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame^] | 179 | if (is_cppi_enabled()) |
| 180 | txcsr |= MUSB_TXCSR_DMAMODE; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 181 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); |
| 182 | } |
| 183 | |
| 184 | /* |
| 185 | * Start the URB at the front of an endpoint's queue |
| 186 | * end must be claimed from the caller. |
| 187 | * |
| 188 | * Context: controller locked, irqs blocked |
| 189 | */ |
| 190 | static void |
| 191 | musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) |
| 192 | { |
| 193 | u16 frame; |
| 194 | u32 len; |
| 195 | void *buf; |
| 196 | void __iomem *mbase = musb->mregs; |
| 197 | struct urb *urb = next_urb(qh); |
| 198 | struct musb_hw_ep *hw_ep = qh->hw_ep; |
| 199 | unsigned pipe = urb->pipe; |
| 200 | u8 address = usb_pipedevice(pipe); |
| 201 | int epnum = hw_ep->epnum; |
| 202 | |
| 203 | /* initialize software qh state */ |
| 204 | qh->offset = 0; |
| 205 | qh->segsize = 0; |
| 206 | |
| 207 | /* gather right source of data */ |
| 208 | switch (qh->type) { |
| 209 | case USB_ENDPOINT_XFER_CONTROL: |
| 210 | /* control transfers always start with SETUP */ |
| 211 | is_in = 0; |
| 212 | hw_ep->out_qh = qh; |
| 213 | musb->ep0_stage = MUSB_EP0_START; |
| 214 | buf = urb->setup_packet; |
| 215 | len = 8; |
| 216 | break; |
| 217 | case USB_ENDPOINT_XFER_ISOC: |
| 218 | qh->iso_idx = 0; |
| 219 | qh->frame = 0; |
| 220 | buf = urb->transfer_buffer + urb->iso_frame_desc[0].offset; |
| 221 | len = urb->iso_frame_desc[0].length; |
| 222 | break; |
| 223 | default: /* bulk, interrupt */ |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 224 | /* actual_length may be nonzero on retry paths */ |
| 225 | buf = urb->transfer_buffer + urb->actual_length; |
| 226 | len = urb->transfer_buffer_length - urb->actual_length; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", |
| 230 | qh, urb, address, qh->epnum, |
| 231 | is_in ? "in" : "out", |
| 232 | ({char *s; switch (qh->type) { |
| 233 | case USB_ENDPOINT_XFER_CONTROL: s = ""; break; |
| 234 | case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; |
| 235 | case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; |
| 236 | default: s = "-intr"; break; |
| 237 | }; s; }), |
| 238 | epnum, buf, len); |
| 239 | |
| 240 | /* Configure endpoint */ |
| 241 | if (is_in || hw_ep->is_shared_fifo) |
| 242 | hw_ep->in_qh = qh; |
| 243 | else |
| 244 | hw_ep->out_qh = qh; |
| 245 | musb_ep_program(musb, epnum, urb, !is_in, buf, len); |
| 246 | |
| 247 | /* transmit may have more work: start it when it is time */ |
| 248 | if (is_in) |
| 249 | return; |
| 250 | |
| 251 | /* determine if the time is right for a periodic transfer */ |
| 252 | switch (qh->type) { |
| 253 | case USB_ENDPOINT_XFER_ISOC: |
| 254 | case USB_ENDPOINT_XFER_INT: |
| 255 | DBG(3, "check whether there's still time for periodic Tx\n"); |
| 256 | qh->iso_idx = 0; |
| 257 | frame = musb_readw(mbase, MUSB_FRAME); |
| 258 | /* FIXME this doesn't implement that scheduling policy ... |
| 259 | * or handle framecounter wrapping |
| 260 | */ |
| 261 | if ((urb->transfer_flags & URB_ISO_ASAP) |
| 262 | || (frame >= urb->start_frame)) { |
| 263 | /* REVISIT the SOF irq handler shouldn't duplicate |
| 264 | * this code; and we don't init urb->start_frame... |
| 265 | */ |
| 266 | qh->frame = 0; |
| 267 | goto start; |
| 268 | } else { |
| 269 | qh->frame = urb->start_frame; |
| 270 | /* enable SOF interrupt so we can count down */ |
| 271 | DBG(1, "SOF for %d\n", epnum); |
| 272 | #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ |
| 273 | musb_writeb(mbase, MUSB_INTRUSBE, 0xff); |
| 274 | #endif |
| 275 | } |
| 276 | break; |
| 277 | default: |
| 278 | start: |
| 279 | DBG(4, "Start TX%d %s\n", epnum, |
| 280 | hw_ep->tx_channel ? "dma" : "pio"); |
| 281 | |
| 282 | if (!hw_ep->tx_channel) |
| 283 | musb_h_tx_start(hw_ep); |
| 284 | else if (is_cppi_enabled() || tusb_dma_omap()) |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame^] | 285 | musb_h_tx_dma_start(hw_ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 286 | } |
| 287 | } |
| 288 | |
| 289 | /* caller owns controller lock, irqs are blocked */ |
| 290 | static void |
| 291 | __musb_giveback(struct musb *musb, struct urb *urb, int status) |
| 292 | __releases(musb->lock) |
| 293 | __acquires(musb->lock) |
| 294 | { |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 295 | DBG(({ int level; switch (status) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 296 | case 0: |
| 297 | level = 4; |
| 298 | break; |
| 299 | /* common/boring faults */ |
| 300 | case -EREMOTEIO: |
| 301 | case -ESHUTDOWN: |
| 302 | case -ECONNRESET: |
| 303 | case -EPIPE: |
| 304 | level = 3; |
| 305 | break; |
| 306 | default: |
| 307 | level = 2; |
| 308 | break; |
| 309 | }; level; }), |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 310 | "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", |
| 311 | urb, urb->complete, status, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 312 | usb_pipedevice(urb->pipe), |
| 313 | usb_pipeendpoint(urb->pipe), |
| 314 | usb_pipein(urb->pipe) ? "in" : "out", |
| 315 | urb->actual_length, urb->transfer_buffer_length |
| 316 | ); |
| 317 | |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 318 | usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 319 | spin_unlock(&musb->lock); |
| 320 | usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); |
| 321 | spin_lock(&musb->lock); |
| 322 | } |
| 323 | |
| 324 | /* for bulk/interrupt endpoints only */ |
| 325 | static inline void |
| 326 | musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb) |
| 327 | { |
| 328 | struct usb_device *udev = urb->dev; |
| 329 | u16 csr; |
| 330 | void __iomem *epio = ep->regs; |
| 331 | struct musb_qh *qh; |
| 332 | |
| 333 | /* FIXME: the current Mentor DMA code seems to have |
| 334 | * problems getting toggle correct. |
| 335 | */ |
| 336 | |
| 337 | if (is_in || ep->is_shared_fifo) |
| 338 | qh = ep->in_qh; |
| 339 | else |
| 340 | qh = ep->out_qh; |
| 341 | |
| 342 | if (!is_in) { |
| 343 | csr = musb_readw(epio, MUSB_TXCSR); |
| 344 | usb_settoggle(udev, qh->epnum, 1, |
| 345 | (csr & MUSB_TXCSR_H_DATATOGGLE) |
| 346 | ? 1 : 0); |
| 347 | } else { |
| 348 | csr = musb_readw(epio, MUSB_RXCSR); |
| 349 | usb_settoggle(udev, qh->epnum, 0, |
| 350 | (csr & MUSB_RXCSR_H_DATATOGGLE) |
| 351 | ? 1 : 0); |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | /* caller owns controller lock, irqs are blocked */ |
| 356 | static struct musb_qh * |
| 357 | musb_giveback(struct musb_qh *qh, struct urb *urb, int status) |
| 358 | { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 359 | struct musb_hw_ep *ep = qh->hw_ep; |
| 360 | struct musb *musb = ep->musb; |
Sergei Shtylyov | 51d9f3e | 2009-02-21 15:31:13 -0800 | [diff] [blame] | 361 | int is_in = usb_pipein(urb->pipe); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 362 | int ready = qh->is_ready; |
| 363 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 364 | /* save toggle eagerly, for paranoia */ |
| 365 | switch (qh->type) { |
| 366 | case USB_ENDPOINT_XFER_BULK: |
| 367 | case USB_ENDPOINT_XFER_INT: |
| 368 | musb_save_toggle(ep, is_in, urb); |
| 369 | break; |
| 370 | case USB_ENDPOINT_XFER_ISOC: |
| 371 | if (status == 0 && urb->error_count) |
| 372 | status = -EXDEV; |
| 373 | break; |
| 374 | } |
| 375 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 376 | qh->is_ready = 0; |
| 377 | __musb_giveback(musb, urb, status); |
| 378 | qh->is_ready = ready; |
| 379 | |
| 380 | /* reclaim resources (and bandwidth) ASAP; deschedule it, and |
| 381 | * invalidate qh as soon as list_empty(&hep->urb_list) |
| 382 | */ |
| 383 | if (list_empty(&qh->hep->urb_list)) { |
| 384 | struct list_head *head; |
| 385 | |
| 386 | if (is_in) |
| 387 | ep->rx_reinit = 1; |
| 388 | else |
| 389 | ep->tx_reinit = 1; |
| 390 | |
| 391 | /* clobber old pointers to this qh */ |
| 392 | if (is_in || ep->is_shared_fifo) |
| 393 | ep->in_qh = NULL; |
| 394 | else |
| 395 | ep->out_qh = NULL; |
| 396 | qh->hep->hcpriv = NULL; |
| 397 | |
| 398 | switch (qh->type) { |
| 399 | |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 400 | case USB_ENDPOINT_XFER_CONTROL: |
| 401 | case USB_ENDPOINT_XFER_BULK: |
| 402 | /* fifo policy for these lists, except that NAKing |
| 403 | * should rotate a qh to the end (for fairness). |
| 404 | */ |
| 405 | if (qh->mux == 1) { |
| 406 | head = qh->ring.prev; |
| 407 | list_del(&qh->ring); |
| 408 | kfree(qh); |
| 409 | qh = first_qh(head); |
| 410 | break; |
| 411 | } |
| 412 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 413 | case USB_ENDPOINT_XFER_ISOC: |
| 414 | case USB_ENDPOINT_XFER_INT: |
| 415 | /* this is where periodic bandwidth should be |
| 416 | * de-allocated if it's tracked and allocated; |
| 417 | * and where we'd update the schedule tree... |
| 418 | */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 419 | kfree(qh); |
| 420 | qh = NULL; |
| 421 | break; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 422 | } |
| 423 | } |
| 424 | return qh; |
| 425 | } |
| 426 | |
| 427 | /* |
| 428 | * Advance this hardware endpoint's queue, completing the specified urb and |
| 429 | * advancing to either the next urb queued to that qh, or else invalidating |
| 430 | * that qh and advancing to the next qh scheduled after the current one. |
| 431 | * |
| 432 | * Context: caller owns controller lock, irqs are blocked |
| 433 | */ |
| 434 | static void |
| 435 | musb_advance_schedule(struct musb *musb, struct urb *urb, |
| 436 | struct musb_hw_ep *hw_ep, int is_in) |
| 437 | { |
| 438 | struct musb_qh *qh; |
| 439 | |
| 440 | if (is_in || hw_ep->is_shared_fifo) |
| 441 | qh = hw_ep->in_qh; |
| 442 | else |
| 443 | qh = hw_ep->out_qh; |
| 444 | |
| 445 | if (urb->status == -EINPROGRESS) |
| 446 | qh = musb_giveback(qh, urb, 0); |
| 447 | else |
| 448 | qh = musb_giveback(qh, urb, urb->status); |
| 449 | |
Sergei Shtylyov | a2fd814 | 2009-02-21 15:30:45 -0800 | [diff] [blame] | 450 | if (qh != NULL && qh->is_ready) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 451 | DBG(4, "... next ep%d %cX urb %p\n", |
| 452 | hw_ep->epnum, is_in ? 'R' : 'T', |
| 453 | next_urb(qh)); |
| 454 | musb_start_urb(musb, is_in, qh); |
| 455 | } |
| 456 | } |
| 457 | |
David Brownell | c767c1c | 2008-09-11 11:53:23 +0300 | [diff] [blame] | 458 | static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 459 | { |
| 460 | /* we don't want fifo to fill itself again; |
| 461 | * ignore dma (various models), |
| 462 | * leave toggle alone (may not have been saved yet) |
| 463 | */ |
| 464 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; |
| 465 | csr &= ~(MUSB_RXCSR_H_REQPKT |
| 466 | | MUSB_RXCSR_H_AUTOREQ |
| 467 | | MUSB_RXCSR_AUTOCLEAR); |
| 468 | |
| 469 | /* write 2x to allow double buffering */ |
| 470 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 471 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 472 | |
| 473 | /* flush writebuffer */ |
| 474 | return musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 475 | } |
| 476 | |
| 477 | /* |
| 478 | * PIO RX for a packet (or part of it). |
| 479 | */ |
| 480 | static bool |
| 481 | musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) |
| 482 | { |
| 483 | u16 rx_count; |
| 484 | u8 *buf; |
| 485 | u16 csr; |
| 486 | bool done = false; |
| 487 | u32 length; |
| 488 | int do_flush = 0; |
| 489 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 490 | void __iomem *epio = hw_ep->regs; |
| 491 | struct musb_qh *qh = hw_ep->in_qh; |
| 492 | int pipe = urb->pipe; |
| 493 | void *buffer = urb->transfer_buffer; |
| 494 | |
| 495 | /* musb_ep_select(mbase, epnum); */ |
| 496 | rx_count = musb_readw(epio, MUSB_RXCOUNT); |
| 497 | DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, |
| 498 | urb->transfer_buffer, qh->offset, |
| 499 | urb->transfer_buffer_length); |
| 500 | |
| 501 | /* unload FIFO */ |
| 502 | if (usb_pipeisoc(pipe)) { |
| 503 | int status = 0; |
| 504 | struct usb_iso_packet_descriptor *d; |
| 505 | |
| 506 | if (iso_err) { |
| 507 | status = -EILSEQ; |
| 508 | urb->error_count++; |
| 509 | } |
| 510 | |
| 511 | d = urb->iso_frame_desc + qh->iso_idx; |
| 512 | buf = buffer + d->offset; |
| 513 | length = d->length; |
| 514 | if (rx_count > length) { |
| 515 | if (status == 0) { |
| 516 | status = -EOVERFLOW; |
| 517 | urb->error_count++; |
| 518 | } |
| 519 | DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); |
| 520 | do_flush = 1; |
| 521 | } else |
| 522 | length = rx_count; |
| 523 | urb->actual_length += length; |
| 524 | d->actual_length = length; |
| 525 | |
| 526 | d->status = status; |
| 527 | |
| 528 | /* see if we are done */ |
| 529 | done = (++qh->iso_idx >= urb->number_of_packets); |
| 530 | } else { |
| 531 | /* non-isoch */ |
| 532 | buf = buffer + qh->offset; |
| 533 | length = urb->transfer_buffer_length - qh->offset; |
| 534 | if (rx_count > length) { |
| 535 | if (urb->status == -EINPROGRESS) |
| 536 | urb->status = -EOVERFLOW; |
| 537 | DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); |
| 538 | do_flush = 1; |
| 539 | } else |
| 540 | length = rx_count; |
| 541 | urb->actual_length += length; |
| 542 | qh->offset += length; |
| 543 | |
| 544 | /* see if we are done */ |
| 545 | done = (urb->actual_length == urb->transfer_buffer_length) |
| 546 | || (rx_count < qh->maxpacket) |
| 547 | || (urb->status != -EINPROGRESS); |
| 548 | if (done |
| 549 | && (urb->status == -EINPROGRESS) |
| 550 | && (urb->transfer_flags & URB_SHORT_NOT_OK) |
| 551 | && (urb->actual_length |
| 552 | < urb->transfer_buffer_length)) |
| 553 | urb->status = -EREMOTEIO; |
| 554 | } |
| 555 | |
| 556 | musb_read_fifo(hw_ep, length, buf); |
| 557 | |
| 558 | csr = musb_readw(epio, MUSB_RXCSR); |
| 559 | csr |= MUSB_RXCSR_H_WZC_BITS; |
| 560 | if (unlikely(do_flush)) |
| 561 | musb_h_flush_rxfifo(hw_ep, csr); |
| 562 | else { |
| 563 | /* REVISIT this assumes AUTOCLEAR is never set */ |
| 564 | csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); |
| 565 | if (!done) |
| 566 | csr |= MUSB_RXCSR_H_REQPKT; |
| 567 | musb_writew(epio, MUSB_RXCSR, csr); |
| 568 | } |
| 569 | |
| 570 | return done; |
| 571 | } |
| 572 | |
| 573 | /* we don't always need to reinit a given side of an endpoint... |
| 574 | * when we do, use tx/rx reinit routine and then construct a new CSR |
| 575 | * to address data toggle, NYET, and DMA or PIO. |
| 576 | * |
| 577 | * it's possible that driver bugs (especially for DMA) or aborting a |
| 578 | * transfer might have left the endpoint busier than it should be. |
| 579 | * the busy/not-empty tests are basically paranoia. |
| 580 | */ |
| 581 | static void |
| 582 | musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) |
| 583 | { |
| 584 | u16 csr; |
| 585 | |
| 586 | /* NOTE: we know the "rx" fifo reinit never triggers for ep0. |
| 587 | * That always uses tx_reinit since ep0 repurposes TX register |
| 588 | * offsets; the initial SETUP packet is also a kind of OUT. |
| 589 | */ |
| 590 | |
| 591 | /* if programmed for Tx, put it in RX mode */ |
| 592 | if (ep->is_shared_fifo) { |
| 593 | csr = musb_readw(ep->regs, MUSB_TXCSR); |
| 594 | if (csr & MUSB_TXCSR_MODE) { |
| 595 | musb_h_tx_flush_fifo(ep); |
| 596 | musb_writew(ep->regs, MUSB_TXCSR, |
| 597 | MUSB_TXCSR_FRCDATATOG); |
| 598 | } |
| 599 | /* clear mode (and everything else) to enable Rx */ |
| 600 | musb_writew(ep->regs, MUSB_TXCSR, 0); |
| 601 | |
| 602 | /* scrub all previous state, clearing toggle */ |
| 603 | } else { |
| 604 | csr = musb_readw(ep->regs, MUSB_RXCSR); |
| 605 | if (csr & MUSB_RXCSR_RXPKTRDY) |
| 606 | WARNING("rx%d, packet/%d ready?\n", ep->epnum, |
| 607 | musb_readw(ep->regs, MUSB_RXCOUNT)); |
| 608 | |
| 609 | musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); |
| 610 | } |
| 611 | |
| 612 | /* target addr and (for multipoint) hub addr/port */ |
| 613 | if (musb->is_multipoint) { |
Bryan Wu | c6cf8b0 | 2008-12-02 21:33:48 +0200 | [diff] [blame] | 614 | musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); |
| 615 | musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); |
| 616 | musb_write_rxhubport(ep->target_regs, qh->h_port_reg); |
| 617 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 618 | } else |
| 619 | musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); |
| 620 | |
| 621 | /* protocol/endpoint, interval/NAKlimit, i/o size */ |
| 622 | musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); |
| 623 | musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); |
| 624 | /* NOTE: bulk combining rewrites high bits of maxpacket */ |
| 625 | musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket); |
| 626 | |
| 627 | ep->rx_reinit = 0; |
| 628 | } |
| 629 | |
| 630 | |
| 631 | /* |
| 632 | * Program an HDRC endpoint as per the given URB |
| 633 | * Context: irqs blocked, controller lock held |
| 634 | */ |
| 635 | static void musb_ep_program(struct musb *musb, u8 epnum, |
| 636 | struct urb *urb, unsigned int is_out, |
| 637 | u8 *buf, u32 len) |
| 638 | { |
| 639 | struct dma_controller *dma_controller; |
| 640 | struct dma_channel *dma_channel; |
| 641 | u8 dma_ok; |
| 642 | void __iomem *mbase = musb->mregs; |
| 643 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 644 | void __iomem *epio = hw_ep->regs; |
| 645 | struct musb_qh *qh; |
| 646 | u16 packet_sz; |
| 647 | |
| 648 | if (!is_out || hw_ep->is_shared_fifo) |
| 649 | qh = hw_ep->in_qh; |
| 650 | else |
| 651 | qh = hw_ep->out_qh; |
| 652 | |
| 653 | packet_sz = qh->maxpacket; |
| 654 | |
| 655 | DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s " |
| 656 | "h_addr%02x h_port%02x bytes %d\n", |
| 657 | is_out ? "-->" : "<--", |
| 658 | epnum, urb, urb->dev->speed, |
| 659 | qh->addr_reg, qh->epnum, is_out ? "out" : "in", |
| 660 | qh->h_addr_reg, qh->h_port_reg, |
| 661 | len); |
| 662 | |
| 663 | musb_ep_select(mbase, epnum); |
| 664 | |
| 665 | /* candidate for DMA? */ |
| 666 | dma_controller = musb->dma_controller; |
| 667 | if (is_dma_capable() && epnum && dma_controller) { |
| 668 | dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; |
| 669 | if (!dma_channel) { |
| 670 | dma_channel = dma_controller->channel_alloc( |
| 671 | dma_controller, hw_ep, is_out); |
| 672 | if (is_out) |
| 673 | hw_ep->tx_channel = dma_channel; |
| 674 | else |
| 675 | hw_ep->rx_channel = dma_channel; |
| 676 | } |
| 677 | } else |
| 678 | dma_channel = NULL; |
| 679 | |
| 680 | /* make sure we clear DMAEnab, autoSet bits from previous run */ |
| 681 | |
| 682 | /* OUT/transmit/EP0 or IN/receive? */ |
| 683 | if (is_out) { |
| 684 | u16 csr; |
| 685 | u16 int_txe; |
| 686 | u16 load_count; |
| 687 | |
| 688 | csr = musb_readw(epio, MUSB_TXCSR); |
| 689 | |
| 690 | /* disable interrupt in case we flush */ |
| 691 | int_txe = musb_readw(mbase, MUSB_INTRTXE); |
| 692 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); |
| 693 | |
| 694 | /* general endpoint setup */ |
| 695 | if (epnum) { |
| 696 | /* ASSERT: TXCSR_DMAENAB was already cleared */ |
| 697 | |
| 698 | /* flush all old state, set default */ |
| 699 | musb_h_tx_flush_fifo(hw_ep); |
| 700 | csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT |
| 701 | | MUSB_TXCSR_DMAMODE |
| 702 | | MUSB_TXCSR_FRCDATATOG |
| 703 | | MUSB_TXCSR_H_RXSTALL |
| 704 | | MUSB_TXCSR_H_ERROR |
| 705 | | MUSB_TXCSR_TXPKTRDY |
| 706 | ); |
| 707 | csr |= MUSB_TXCSR_MODE; |
| 708 | |
| 709 | if (usb_gettoggle(urb->dev, |
| 710 | qh->epnum, 1)) |
| 711 | csr |= MUSB_TXCSR_H_WR_DATATOGGLE |
| 712 | | MUSB_TXCSR_H_DATATOGGLE; |
| 713 | else |
| 714 | csr |= MUSB_TXCSR_CLRDATATOG; |
| 715 | |
| 716 | /* twice in case of double packet buffering */ |
| 717 | musb_writew(epio, MUSB_TXCSR, csr); |
| 718 | /* REVISIT may need to clear FLUSHFIFO ... */ |
| 719 | musb_writew(epio, MUSB_TXCSR, csr); |
| 720 | csr = musb_readw(epio, MUSB_TXCSR); |
| 721 | } else { |
| 722 | /* endpoint 0: just flush */ |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 723 | musb_h_ep0_flush_fifo(hw_ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 724 | } |
| 725 | |
| 726 | /* target addr and (for multipoint) hub addr/port */ |
| 727 | if (musb->is_multipoint) { |
Bryan Wu | c6cf8b0 | 2008-12-02 21:33:48 +0200 | [diff] [blame] | 728 | musb_write_txfunaddr(mbase, epnum, qh->addr_reg); |
| 729 | musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); |
| 730 | musb_write_txhubport(mbase, epnum, qh->h_port_reg); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 731 | /* FIXME if !epnum, do the same for RX ... */ |
| 732 | } else |
| 733 | musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); |
| 734 | |
| 735 | /* protocol/endpoint/interval/NAKlimit */ |
| 736 | if (epnum) { |
| 737 | musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); |
| 738 | if (can_bulk_split(musb, qh->type)) |
| 739 | musb_writew(epio, MUSB_TXMAXP, |
| 740 | packet_sz |
| 741 | | ((hw_ep->max_packet_sz_tx / |
| 742 | packet_sz) - 1) << 11); |
| 743 | else |
| 744 | musb_writew(epio, MUSB_TXMAXP, |
| 745 | packet_sz); |
| 746 | musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); |
| 747 | } else { |
| 748 | musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); |
| 749 | if (musb->is_multipoint) |
| 750 | musb_writeb(epio, MUSB_TYPE0, |
| 751 | qh->type_reg); |
| 752 | } |
| 753 | |
| 754 | if (can_bulk_split(musb, qh->type)) |
| 755 | load_count = min((u32) hw_ep->max_packet_sz_tx, |
| 756 | len); |
| 757 | else |
| 758 | load_count = min((u32) packet_sz, len); |
| 759 | |
| 760 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 761 | if (dma_channel) { |
| 762 | |
| 763 | /* clear previous state */ |
| 764 | csr = musb_readw(epio, MUSB_TXCSR); |
| 765 | csr &= ~(MUSB_TXCSR_AUTOSET |
| 766 | | MUSB_TXCSR_DMAMODE |
| 767 | | MUSB_TXCSR_DMAENAB); |
| 768 | csr |= MUSB_TXCSR_MODE; |
| 769 | musb_writew(epio, MUSB_TXCSR, |
| 770 | csr | MUSB_TXCSR_MODE); |
| 771 | |
| 772 | qh->segsize = min(len, dma_channel->max_len); |
| 773 | |
| 774 | if (qh->segsize <= packet_sz) |
| 775 | dma_channel->desired_mode = 0; |
| 776 | else |
| 777 | dma_channel->desired_mode = 1; |
| 778 | |
| 779 | |
| 780 | if (dma_channel->desired_mode == 0) { |
| 781 | csr &= ~(MUSB_TXCSR_AUTOSET |
| 782 | | MUSB_TXCSR_DMAMODE); |
| 783 | csr |= (MUSB_TXCSR_DMAENAB); |
| 784 | /* against programming guide */ |
| 785 | } else |
| 786 | csr |= (MUSB_TXCSR_AUTOSET |
| 787 | | MUSB_TXCSR_DMAENAB |
| 788 | | MUSB_TXCSR_DMAMODE); |
| 789 | |
| 790 | musb_writew(epio, MUSB_TXCSR, csr); |
| 791 | |
| 792 | dma_ok = dma_controller->channel_program( |
| 793 | dma_channel, packet_sz, |
| 794 | dma_channel->desired_mode, |
| 795 | urb->transfer_dma, |
| 796 | qh->segsize); |
| 797 | if (dma_ok) { |
| 798 | load_count = 0; |
| 799 | } else { |
| 800 | dma_controller->channel_release(dma_channel); |
| 801 | if (is_out) |
| 802 | hw_ep->tx_channel = NULL; |
| 803 | else |
| 804 | hw_ep->rx_channel = NULL; |
| 805 | dma_channel = NULL; |
| 806 | } |
| 807 | } |
| 808 | #endif |
| 809 | |
| 810 | /* candidate for DMA */ |
| 811 | if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { |
| 812 | |
| 813 | /* program endpoint CSRs first, then setup DMA. |
| 814 | * assume CPPI setup succeeds. |
| 815 | * defer enabling dma. |
| 816 | */ |
| 817 | csr = musb_readw(epio, MUSB_TXCSR); |
| 818 | csr &= ~(MUSB_TXCSR_AUTOSET |
| 819 | | MUSB_TXCSR_DMAMODE |
| 820 | | MUSB_TXCSR_DMAENAB); |
| 821 | csr |= MUSB_TXCSR_MODE; |
| 822 | musb_writew(epio, MUSB_TXCSR, |
| 823 | csr | MUSB_TXCSR_MODE); |
| 824 | |
| 825 | dma_channel->actual_len = 0L; |
| 826 | qh->segsize = len; |
| 827 | |
| 828 | /* TX uses "rndis" mode automatically, but needs help |
| 829 | * to identify the zero-length-final-packet case. |
| 830 | */ |
| 831 | dma_ok = dma_controller->channel_program( |
| 832 | dma_channel, packet_sz, |
| 833 | (urb->transfer_flags |
| 834 | & URB_ZERO_PACKET) |
| 835 | == URB_ZERO_PACKET, |
| 836 | urb->transfer_dma, |
| 837 | qh->segsize); |
| 838 | if (dma_ok) { |
| 839 | load_count = 0; |
| 840 | } else { |
| 841 | dma_controller->channel_release(dma_channel); |
| 842 | hw_ep->tx_channel = NULL; |
| 843 | dma_channel = NULL; |
| 844 | |
| 845 | /* REVISIT there's an error path here that |
| 846 | * needs handling: can't do dma, but |
| 847 | * there's no pio buffer address... |
| 848 | */ |
| 849 | } |
| 850 | } |
| 851 | |
| 852 | if (load_count) { |
| 853 | /* ASSERT: TXCSR_DMAENAB was already cleared */ |
| 854 | |
| 855 | /* PIO to load FIFO */ |
| 856 | qh->segsize = load_count; |
| 857 | musb_write_fifo(hw_ep, load_count, buf); |
| 858 | csr = musb_readw(epio, MUSB_TXCSR); |
| 859 | csr &= ~(MUSB_TXCSR_DMAENAB |
| 860 | | MUSB_TXCSR_DMAMODE |
| 861 | | MUSB_TXCSR_AUTOSET); |
| 862 | /* write CSR */ |
| 863 | csr |= MUSB_TXCSR_MODE; |
| 864 | |
| 865 | if (epnum) |
| 866 | musb_writew(epio, MUSB_TXCSR, csr); |
| 867 | } |
| 868 | |
| 869 | /* re-enable interrupt */ |
| 870 | musb_writew(mbase, MUSB_INTRTXE, int_txe); |
| 871 | |
| 872 | /* IN/receive */ |
| 873 | } else { |
| 874 | u16 csr; |
| 875 | |
| 876 | if (hw_ep->rx_reinit) { |
| 877 | musb_rx_reinit(musb, qh, hw_ep); |
| 878 | |
| 879 | /* init new state: toggle and NYET, maybe DMA later */ |
| 880 | if (usb_gettoggle(urb->dev, qh->epnum, 0)) |
| 881 | csr = MUSB_RXCSR_H_WR_DATATOGGLE |
| 882 | | MUSB_RXCSR_H_DATATOGGLE; |
| 883 | else |
| 884 | csr = 0; |
| 885 | if (qh->type == USB_ENDPOINT_XFER_INT) |
| 886 | csr |= MUSB_RXCSR_DISNYET; |
| 887 | |
| 888 | } else { |
| 889 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 890 | |
| 891 | if (csr & (MUSB_RXCSR_RXPKTRDY |
| 892 | | MUSB_RXCSR_DMAENAB |
| 893 | | MUSB_RXCSR_H_REQPKT)) |
| 894 | ERR("broken !rx_reinit, ep%d csr %04x\n", |
| 895 | hw_ep->epnum, csr); |
| 896 | |
| 897 | /* scrub any stale state, leaving toggle alone */ |
| 898 | csr &= MUSB_RXCSR_DISNYET; |
| 899 | } |
| 900 | |
| 901 | /* kick things off */ |
| 902 | |
| 903 | if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { |
| 904 | /* candidate for DMA */ |
| 905 | if (dma_channel) { |
| 906 | dma_channel->actual_len = 0L; |
| 907 | qh->segsize = len; |
| 908 | |
| 909 | /* AUTOREQ is in a DMA register */ |
| 910 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 911 | csr = musb_readw(hw_ep->regs, |
| 912 | MUSB_RXCSR); |
| 913 | |
| 914 | /* unless caller treats short rx transfers as |
| 915 | * errors, we dare not queue multiple transfers. |
| 916 | */ |
| 917 | dma_ok = dma_controller->channel_program( |
| 918 | dma_channel, packet_sz, |
| 919 | !(urb->transfer_flags |
| 920 | & URB_SHORT_NOT_OK), |
| 921 | urb->transfer_dma, |
| 922 | qh->segsize); |
| 923 | if (!dma_ok) { |
| 924 | dma_controller->channel_release( |
| 925 | dma_channel); |
| 926 | hw_ep->rx_channel = NULL; |
| 927 | dma_channel = NULL; |
| 928 | } else |
| 929 | csr |= MUSB_RXCSR_DMAENAB; |
| 930 | } |
| 931 | } |
| 932 | |
| 933 | csr |= MUSB_RXCSR_H_REQPKT; |
| 934 | DBG(7, "RXCSR%d := %04x\n", epnum, csr); |
| 935 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
| 936 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); |
| 937 | } |
| 938 | } |
| 939 | |
| 940 | |
| 941 | /* |
| 942 | * Service the default endpoint (ep0) as host. |
| 943 | * Return true until it's time to start the status stage. |
| 944 | */ |
| 945 | static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) |
| 946 | { |
| 947 | bool more = false; |
| 948 | u8 *fifo_dest = NULL; |
| 949 | u16 fifo_count = 0; |
| 950 | struct musb_hw_ep *hw_ep = musb->control_ep; |
| 951 | struct musb_qh *qh = hw_ep->in_qh; |
| 952 | struct usb_ctrlrequest *request; |
| 953 | |
| 954 | switch (musb->ep0_stage) { |
| 955 | case MUSB_EP0_IN: |
| 956 | fifo_dest = urb->transfer_buffer + urb->actual_length; |
Sergei Shtylyov | 3ecdb9a | 2009-02-21 15:31:23 -0800 | [diff] [blame] | 957 | fifo_count = min_t(size_t, len, urb->transfer_buffer_length - |
| 958 | urb->actual_length); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 959 | if (fifo_count < len) |
| 960 | urb->status = -EOVERFLOW; |
| 961 | |
| 962 | musb_read_fifo(hw_ep, fifo_count, fifo_dest); |
| 963 | |
| 964 | urb->actual_length += fifo_count; |
| 965 | if (len < qh->maxpacket) { |
| 966 | /* always terminate on short read; it's |
| 967 | * rarely reported as an error. |
| 968 | */ |
| 969 | } else if (urb->actual_length < |
| 970 | urb->transfer_buffer_length) |
| 971 | more = true; |
| 972 | break; |
| 973 | case MUSB_EP0_START: |
| 974 | request = (struct usb_ctrlrequest *) urb->setup_packet; |
| 975 | |
| 976 | if (!request->wLength) { |
| 977 | DBG(4, "start no-DATA\n"); |
| 978 | break; |
| 979 | } else if (request->bRequestType & USB_DIR_IN) { |
| 980 | DBG(4, "start IN-DATA\n"); |
| 981 | musb->ep0_stage = MUSB_EP0_IN; |
| 982 | more = true; |
| 983 | break; |
| 984 | } else { |
| 985 | DBG(4, "start OUT-DATA\n"); |
| 986 | musb->ep0_stage = MUSB_EP0_OUT; |
| 987 | more = true; |
| 988 | } |
| 989 | /* FALLTHROUGH */ |
| 990 | case MUSB_EP0_OUT: |
Sergei Shtylyov | 3ecdb9a | 2009-02-21 15:31:23 -0800 | [diff] [blame] | 991 | fifo_count = min_t(size_t, qh->maxpacket, |
| 992 | urb->transfer_buffer_length - |
| 993 | urb->actual_length); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 994 | if (fifo_count) { |
| 995 | fifo_dest = (u8 *) (urb->transfer_buffer |
| 996 | + urb->actual_length); |
David Brownell | bb1c9ef | 2008-11-24 13:06:50 +0200 | [diff] [blame] | 997 | DBG(3, "Sending %d byte%s to ep0 fifo %p\n", |
| 998 | fifo_count, |
| 999 | (fifo_count == 1) ? "" : "s", |
| 1000 | fifo_dest); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1001 | musb_write_fifo(hw_ep, fifo_count, fifo_dest); |
| 1002 | |
| 1003 | urb->actual_length += fifo_count; |
| 1004 | more = true; |
| 1005 | } |
| 1006 | break; |
| 1007 | default: |
| 1008 | ERR("bogus ep0 stage %d\n", musb->ep0_stage); |
| 1009 | break; |
| 1010 | } |
| 1011 | |
| 1012 | return more; |
| 1013 | } |
| 1014 | |
| 1015 | /* |
| 1016 | * Handle default endpoint interrupt as host. Only called in IRQ time |
David Brownell | c767c1c | 2008-09-11 11:53:23 +0300 | [diff] [blame] | 1017 | * from musb_interrupt(). |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1018 | * |
| 1019 | * called with controller irqlocked |
| 1020 | */ |
| 1021 | irqreturn_t musb_h_ep0_irq(struct musb *musb) |
| 1022 | { |
| 1023 | struct urb *urb; |
| 1024 | u16 csr, len; |
| 1025 | int status = 0; |
| 1026 | void __iomem *mbase = musb->mregs; |
| 1027 | struct musb_hw_ep *hw_ep = musb->control_ep; |
| 1028 | void __iomem *epio = hw_ep->regs; |
| 1029 | struct musb_qh *qh = hw_ep->in_qh; |
| 1030 | bool complete = false; |
| 1031 | irqreturn_t retval = IRQ_NONE; |
| 1032 | |
| 1033 | /* ep0 only has one queue, "in" */ |
| 1034 | urb = next_urb(qh); |
| 1035 | |
| 1036 | musb_ep_select(mbase, 0); |
| 1037 | csr = musb_readw(epio, MUSB_CSR0); |
| 1038 | len = (csr & MUSB_CSR0_RXPKTRDY) |
| 1039 | ? musb_readb(epio, MUSB_COUNT0) |
| 1040 | : 0; |
| 1041 | |
| 1042 | DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", |
| 1043 | csr, qh, len, urb, musb->ep0_stage); |
| 1044 | |
| 1045 | /* if we just did status stage, we are done */ |
| 1046 | if (MUSB_EP0_STATUS == musb->ep0_stage) { |
| 1047 | retval = IRQ_HANDLED; |
| 1048 | complete = true; |
| 1049 | } |
| 1050 | |
| 1051 | /* prepare status */ |
| 1052 | if (csr & MUSB_CSR0_H_RXSTALL) { |
| 1053 | DBG(6, "STALLING ENDPOINT\n"); |
| 1054 | status = -EPIPE; |
| 1055 | |
| 1056 | } else if (csr & MUSB_CSR0_H_ERROR) { |
| 1057 | DBG(2, "no response, csr0 %04x\n", csr); |
| 1058 | status = -EPROTO; |
| 1059 | |
| 1060 | } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { |
| 1061 | DBG(2, "control NAK timeout\n"); |
| 1062 | |
| 1063 | /* NOTE: this code path would be a good place to PAUSE a |
| 1064 | * control transfer, if another one is queued, so that |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1065 | * ep0 is more likely to stay busy. That's already done |
| 1066 | * for bulk RX transfers. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1067 | * |
| 1068 | * if (qh->ring.next != &musb->control), then |
| 1069 | * we have a candidate... NAKing is *NOT* an error |
| 1070 | */ |
| 1071 | musb_writew(epio, MUSB_CSR0, 0); |
| 1072 | retval = IRQ_HANDLED; |
| 1073 | } |
| 1074 | |
| 1075 | if (status) { |
| 1076 | DBG(6, "aborting\n"); |
| 1077 | retval = IRQ_HANDLED; |
| 1078 | if (urb) |
| 1079 | urb->status = status; |
| 1080 | complete = true; |
| 1081 | |
| 1082 | /* use the proper sequence to abort the transfer */ |
| 1083 | if (csr & MUSB_CSR0_H_REQPKT) { |
| 1084 | csr &= ~MUSB_CSR0_H_REQPKT; |
| 1085 | musb_writew(epio, MUSB_CSR0, csr); |
| 1086 | csr &= ~MUSB_CSR0_H_NAKTIMEOUT; |
| 1087 | musb_writew(epio, MUSB_CSR0, csr); |
| 1088 | } else { |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 1089 | musb_h_ep0_flush_fifo(hw_ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1090 | } |
| 1091 | |
| 1092 | musb_writeb(epio, MUSB_NAKLIMIT0, 0); |
| 1093 | |
| 1094 | /* clear it */ |
| 1095 | musb_writew(epio, MUSB_CSR0, 0); |
| 1096 | } |
| 1097 | |
| 1098 | if (unlikely(!urb)) { |
| 1099 | /* stop endpoint since we have no place for its data, this |
| 1100 | * SHOULD NEVER HAPPEN! */ |
| 1101 | ERR("no URB for end 0\n"); |
| 1102 | |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 1103 | musb_h_ep0_flush_fifo(hw_ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1104 | goto done; |
| 1105 | } |
| 1106 | |
| 1107 | if (!complete) { |
| 1108 | /* call common logic and prepare response */ |
| 1109 | if (musb_h_ep0_continue(musb, len, urb)) { |
| 1110 | /* more packets required */ |
| 1111 | csr = (MUSB_EP0_IN == musb->ep0_stage) |
| 1112 | ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; |
| 1113 | } else { |
| 1114 | /* data transfer complete; perform status phase */ |
| 1115 | if (usb_pipeout(urb->pipe) |
| 1116 | || !urb->transfer_buffer_length) |
| 1117 | csr = MUSB_CSR0_H_STATUSPKT |
| 1118 | | MUSB_CSR0_H_REQPKT; |
| 1119 | else |
| 1120 | csr = MUSB_CSR0_H_STATUSPKT |
| 1121 | | MUSB_CSR0_TXPKTRDY; |
| 1122 | |
| 1123 | /* flag status stage */ |
| 1124 | musb->ep0_stage = MUSB_EP0_STATUS; |
| 1125 | |
| 1126 | DBG(5, "ep0 STATUS, csr %04x\n", csr); |
| 1127 | |
| 1128 | } |
| 1129 | musb_writew(epio, MUSB_CSR0, csr); |
| 1130 | retval = IRQ_HANDLED; |
| 1131 | } else |
| 1132 | musb->ep0_stage = MUSB_EP0_IDLE; |
| 1133 | |
| 1134 | /* call completion handler if done */ |
| 1135 | if (complete) |
| 1136 | musb_advance_schedule(musb, urb, hw_ep, 1); |
| 1137 | done: |
| 1138 | return retval; |
| 1139 | } |
| 1140 | |
| 1141 | |
| 1142 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1143 | |
| 1144 | /* Host side TX (OUT) using Mentor DMA works as follows: |
| 1145 | submit_urb -> |
| 1146 | - if queue was empty, Program Endpoint |
| 1147 | - ... which starts DMA to fifo in mode 1 or 0 |
| 1148 | |
| 1149 | DMA Isr (transfer complete) -> TxAvail() |
| 1150 | - Stop DMA (~DmaEnab) (<--- Alert ... currently happens |
| 1151 | only in musb_cleanup_urb) |
| 1152 | - TxPktRdy has to be set in mode 0 or for |
| 1153 | short packets in mode 1. |
| 1154 | */ |
| 1155 | |
| 1156 | #endif |
| 1157 | |
| 1158 | /* Service a Tx-Available or dma completion irq for the endpoint */ |
| 1159 | void musb_host_tx(struct musb *musb, u8 epnum) |
| 1160 | { |
| 1161 | int pipe; |
| 1162 | bool done = false; |
| 1163 | u16 tx_csr; |
| 1164 | size_t wLength = 0; |
| 1165 | u8 *buf = NULL; |
| 1166 | struct urb *urb; |
| 1167 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 1168 | void __iomem *epio = hw_ep->regs; |
Dmitry Krivoschekov | b7bdcb7 | 2009-02-21 15:30:15 -0800 | [diff] [blame] | 1169 | struct musb_qh *qh = hw_ep->is_shared_fifo ? hw_ep->in_qh |
| 1170 | : hw_ep->out_qh; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1171 | u32 status = 0; |
| 1172 | void __iomem *mbase = musb->mregs; |
| 1173 | struct dma_channel *dma; |
| 1174 | |
| 1175 | urb = next_urb(qh); |
| 1176 | |
| 1177 | musb_ep_select(mbase, epnum); |
| 1178 | tx_csr = musb_readw(epio, MUSB_TXCSR); |
| 1179 | |
| 1180 | /* with CPPI, DMA sometimes triggers "extra" irqs */ |
| 1181 | if (!urb) { |
| 1182 | DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); |
| 1183 | goto finish; |
| 1184 | } |
| 1185 | |
| 1186 | pipe = urb->pipe; |
| 1187 | dma = is_dma_capable() ? hw_ep->tx_channel : NULL; |
| 1188 | DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, |
| 1189 | dma ? ", dma" : ""); |
| 1190 | |
| 1191 | /* check for errors */ |
| 1192 | if (tx_csr & MUSB_TXCSR_H_RXSTALL) { |
| 1193 | /* dma was disabled, fifo flushed */ |
| 1194 | DBG(3, "TX end %d stall\n", epnum); |
| 1195 | |
| 1196 | /* stall; record URB status */ |
| 1197 | status = -EPIPE; |
| 1198 | |
| 1199 | } else if (tx_csr & MUSB_TXCSR_H_ERROR) { |
| 1200 | /* (NON-ISO) dma was disabled, fifo flushed */ |
| 1201 | DBG(3, "TX 3strikes on ep=%d\n", epnum); |
| 1202 | |
| 1203 | status = -ETIMEDOUT; |
| 1204 | |
| 1205 | } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { |
| 1206 | DBG(6, "TX end=%d device not responding\n", epnum); |
| 1207 | |
| 1208 | /* NOTE: this code path would be a good place to PAUSE a |
| 1209 | * transfer, if there's some other (nonperiodic) tx urb |
| 1210 | * that could use this fifo. (dma complicates it...) |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1211 | * That's already done for bulk RX transfers. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1212 | * |
| 1213 | * if (bulk && qh->ring.next != &musb->out_bulk), then |
| 1214 | * we have a candidate... NAKing is *NOT* an error |
| 1215 | */ |
| 1216 | musb_ep_select(mbase, epnum); |
| 1217 | musb_writew(epio, MUSB_TXCSR, |
| 1218 | MUSB_TXCSR_H_WZC_BITS |
| 1219 | | MUSB_TXCSR_TXPKTRDY); |
| 1220 | goto finish; |
| 1221 | } |
| 1222 | |
| 1223 | if (status) { |
| 1224 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1225 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 1226 | (void) musb->dma_controller->channel_abort(dma); |
| 1227 | } |
| 1228 | |
| 1229 | /* do the proper sequence to abort the transfer in the |
| 1230 | * usb core; the dma engine should already be stopped. |
| 1231 | */ |
| 1232 | musb_h_tx_flush_fifo(hw_ep); |
| 1233 | tx_csr &= ~(MUSB_TXCSR_AUTOSET |
| 1234 | | MUSB_TXCSR_DMAENAB |
| 1235 | | MUSB_TXCSR_H_ERROR |
| 1236 | | MUSB_TXCSR_H_RXSTALL |
| 1237 | | MUSB_TXCSR_H_NAKTIMEOUT |
| 1238 | ); |
| 1239 | |
| 1240 | musb_ep_select(mbase, epnum); |
| 1241 | musb_writew(epio, MUSB_TXCSR, tx_csr); |
| 1242 | /* REVISIT may need to clear FLUSHFIFO ... */ |
| 1243 | musb_writew(epio, MUSB_TXCSR, tx_csr); |
| 1244 | musb_writeb(epio, MUSB_TXINTERVAL, 0); |
| 1245 | |
| 1246 | done = true; |
| 1247 | } |
| 1248 | |
| 1249 | /* second cppi case */ |
| 1250 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1251 | DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); |
| 1252 | goto finish; |
| 1253 | |
| 1254 | } |
| 1255 | |
Sergei Shtylyov | c7bbc05 | 2009-03-26 18:26:40 -0700 | [diff] [blame^] | 1256 | if (is_dma_capable() && dma && !status) { |
| 1257 | /* |
| 1258 | * DMA has completed. But if we're using DMA mode 1 (multi |
| 1259 | * packet DMA), we need a terminal TXPKTRDY interrupt before |
| 1260 | * we can consider this transfer completed, lest we trash |
| 1261 | * its last packet when writing the next URB's data. So we |
| 1262 | * switch back to mode 0 to get that interrupt; we'll come |
| 1263 | * back here once it happens. |
| 1264 | */ |
| 1265 | if (tx_csr & MUSB_TXCSR_DMAMODE) { |
| 1266 | /* |
| 1267 | * We shouldn't clear DMAMODE with DMAENAB set; so |
| 1268 | * clear them in a safe order. That should be OK |
| 1269 | * once TXPKTRDY has been set (and I've never seen |
| 1270 | * it being 0 at this moment -- DMA interrupt latency |
| 1271 | * is significant) but if it hasn't been then we have |
| 1272 | * no choice but to stop being polite and ignore the |
| 1273 | * programmer's guide... :-) |
| 1274 | * |
| 1275 | * Note that we must write TXCSR with TXPKTRDY cleared |
| 1276 | * in order not to re-trigger the packet send (this bit |
| 1277 | * can't be cleared by CPU), and there's another caveat: |
| 1278 | * TXPKTRDY may be set shortly and then cleared in the |
| 1279 | * double-buffered FIFO mode, so we do an extra TXCSR |
| 1280 | * read for debouncing... |
| 1281 | */ |
| 1282 | tx_csr &= musb_readw(epio, MUSB_TXCSR); |
| 1283 | if (tx_csr & MUSB_TXCSR_TXPKTRDY) { |
| 1284 | tx_csr &= ~(MUSB_TXCSR_DMAENAB | |
| 1285 | MUSB_TXCSR_TXPKTRDY); |
| 1286 | musb_writew(epio, MUSB_TXCSR, |
| 1287 | tx_csr | MUSB_TXCSR_H_WZC_BITS); |
| 1288 | } |
| 1289 | tx_csr &= ~(MUSB_TXCSR_DMAMODE | |
| 1290 | MUSB_TXCSR_TXPKTRDY); |
| 1291 | musb_writew(epio, MUSB_TXCSR, |
| 1292 | tx_csr | MUSB_TXCSR_H_WZC_BITS); |
| 1293 | |
| 1294 | /* |
| 1295 | * There is no guarantee that we'll get an interrupt |
| 1296 | * after clearing DMAMODE as we might have done this |
| 1297 | * too late (after TXPKTRDY was cleared by controller). |
| 1298 | * Re-read TXCSR as we have spoiled its previous value. |
| 1299 | */ |
| 1300 | tx_csr = musb_readw(epio, MUSB_TXCSR); |
| 1301 | } |
| 1302 | |
| 1303 | /* |
| 1304 | * We may get here from a DMA completion or TXPKTRDY interrupt. |
| 1305 | * In any case, we must check the FIFO status here and bail out |
| 1306 | * only if the FIFO still has data -- that should prevent the |
| 1307 | * "missed" TXPKTRDY interrupts and deal with double-buffered |
| 1308 | * FIFO mode too... |
| 1309 | */ |
| 1310 | if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { |
| 1311 | DBG(2, "DMA complete but packet still in FIFO, " |
| 1312 | "CSR %04x\n", tx_csr); |
| 1313 | return; |
| 1314 | } |
| 1315 | } |
| 1316 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1317 | /* REVISIT this looks wrong... */ |
| 1318 | if (!status || dma || usb_pipeisoc(pipe)) { |
| 1319 | if (dma) |
| 1320 | wLength = dma->actual_len; |
| 1321 | else |
| 1322 | wLength = qh->segsize; |
| 1323 | qh->offset += wLength; |
| 1324 | |
| 1325 | if (usb_pipeisoc(pipe)) { |
| 1326 | struct usb_iso_packet_descriptor *d; |
| 1327 | |
| 1328 | d = urb->iso_frame_desc + qh->iso_idx; |
| 1329 | d->actual_length = qh->segsize; |
| 1330 | if (++qh->iso_idx >= urb->number_of_packets) { |
| 1331 | done = true; |
| 1332 | } else { |
| 1333 | d++; |
| 1334 | buf = urb->transfer_buffer + d->offset; |
| 1335 | wLength = d->length; |
| 1336 | } |
| 1337 | } else if (dma) { |
| 1338 | done = true; |
| 1339 | } else { |
| 1340 | /* see if we need to send more data, or ZLP */ |
| 1341 | if (qh->segsize < qh->maxpacket) |
| 1342 | done = true; |
| 1343 | else if (qh->offset == urb->transfer_buffer_length |
| 1344 | && !(urb->transfer_flags |
| 1345 | & URB_ZERO_PACKET)) |
| 1346 | done = true; |
| 1347 | if (!done) { |
| 1348 | buf = urb->transfer_buffer |
| 1349 | + qh->offset; |
| 1350 | wLength = urb->transfer_buffer_length |
| 1351 | - qh->offset; |
| 1352 | } |
| 1353 | } |
| 1354 | } |
| 1355 | |
| 1356 | /* urb->status != -EINPROGRESS means request has been faulted, |
| 1357 | * so we must abort this transfer after cleanup |
| 1358 | */ |
| 1359 | if (urb->status != -EINPROGRESS) { |
| 1360 | done = true; |
| 1361 | if (status == 0) |
| 1362 | status = urb->status; |
| 1363 | } |
| 1364 | |
| 1365 | if (done) { |
| 1366 | /* set status */ |
| 1367 | urb->status = status; |
| 1368 | urb->actual_length = qh->offset; |
| 1369 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); |
| 1370 | |
| 1371 | } else if (!(tx_csr & MUSB_TXCSR_DMAENAB)) { |
| 1372 | /* WARN_ON(!buf); */ |
| 1373 | |
| 1374 | /* REVISIT: some docs say that when hw_ep->tx_double_buffered, |
| 1375 | * (and presumably, fifo is not half-full) we should write TWO |
| 1376 | * packets before updating TXCSR ... other docs disagree ... |
| 1377 | */ |
| 1378 | /* PIO: start next packet in this URB */ |
Sergei Shtylyov | 3ecdb9a | 2009-02-21 15:31:23 -0800 | [diff] [blame] | 1379 | if (wLength > qh->maxpacket) |
| 1380 | wLength = qh->maxpacket; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1381 | musb_write_fifo(hw_ep, wLength, buf); |
| 1382 | qh->segsize = wLength; |
| 1383 | |
| 1384 | musb_ep_select(mbase, epnum); |
| 1385 | musb_writew(epio, MUSB_TXCSR, |
| 1386 | MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); |
| 1387 | } else |
| 1388 | DBG(1, "not complete, but dma enabled?\n"); |
| 1389 | |
| 1390 | finish: |
| 1391 | return; |
| 1392 | } |
| 1393 | |
| 1394 | |
| 1395 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1396 | |
| 1397 | /* Host side RX (IN) using Mentor DMA works as follows: |
| 1398 | submit_urb -> |
| 1399 | - if queue was empty, ProgramEndpoint |
| 1400 | - first IN token is sent out (by setting ReqPkt) |
| 1401 | LinuxIsr -> RxReady() |
| 1402 | /\ => first packet is received |
| 1403 | | - Set in mode 0 (DmaEnab, ~ReqPkt) |
| 1404 | | -> DMA Isr (transfer complete) -> RxReady() |
| 1405 | | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) |
| 1406 | | - if urb not complete, send next IN token (ReqPkt) |
| 1407 | | | else complete urb. |
| 1408 | | | |
| 1409 | --------------------------- |
| 1410 | * |
| 1411 | * Nuances of mode 1: |
| 1412 | * For short packets, no ack (+RxPktRdy) is sent automatically |
| 1413 | * (even if AutoClear is ON) |
| 1414 | * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent |
| 1415 | * automatically => major problem, as collecting the next packet becomes |
| 1416 | * difficult. Hence mode 1 is not used. |
| 1417 | * |
| 1418 | * REVISIT |
| 1419 | * All we care about at this driver level is that |
| 1420 | * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; |
| 1421 | * (b) termination conditions are: short RX, or buffer full; |
| 1422 | * (c) fault modes include |
| 1423 | * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. |
| 1424 | * (and that endpoint's dma queue stops immediately) |
| 1425 | * - overflow (full, PLUS more bytes in the terminal packet) |
| 1426 | * |
| 1427 | * So for example, usb-storage sets URB_SHORT_NOT_OK, and would |
| 1428 | * thus be a great candidate for using mode 1 ... for all but the |
| 1429 | * last packet of one URB's transfer. |
| 1430 | */ |
| 1431 | |
| 1432 | #endif |
| 1433 | |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1434 | /* Schedule next QH from musb->in_bulk and move the current qh to |
| 1435 | * the end; avoids starvation for other endpoints. |
| 1436 | */ |
| 1437 | static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep) |
| 1438 | { |
| 1439 | struct dma_channel *dma; |
| 1440 | struct urb *urb; |
| 1441 | void __iomem *mbase = musb->mregs; |
| 1442 | void __iomem *epio = ep->regs; |
| 1443 | struct musb_qh *cur_qh, *next_qh; |
| 1444 | u16 rx_csr; |
| 1445 | |
| 1446 | musb_ep_select(mbase, ep->epnum); |
| 1447 | dma = is_dma_capable() ? ep->rx_channel : NULL; |
| 1448 | |
| 1449 | /* clear nak timeout bit */ |
| 1450 | rx_csr = musb_readw(epio, MUSB_RXCSR); |
| 1451 | rx_csr |= MUSB_RXCSR_H_WZC_BITS; |
| 1452 | rx_csr &= ~MUSB_RXCSR_DATAERROR; |
| 1453 | musb_writew(epio, MUSB_RXCSR, rx_csr); |
| 1454 | |
| 1455 | cur_qh = first_qh(&musb->in_bulk); |
| 1456 | if (cur_qh) { |
| 1457 | urb = next_urb(cur_qh); |
| 1458 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1459 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 1460 | musb->dma_controller->channel_abort(dma); |
| 1461 | urb->actual_length += dma->actual_len; |
| 1462 | dma->actual_len = 0L; |
| 1463 | } |
| 1464 | musb_save_toggle(ep, 1, urb); |
| 1465 | |
| 1466 | /* move cur_qh to end of queue */ |
| 1467 | list_move_tail(&cur_qh->ring, &musb->in_bulk); |
| 1468 | |
| 1469 | /* get the next qh from musb->in_bulk */ |
| 1470 | next_qh = first_qh(&musb->in_bulk); |
| 1471 | |
| 1472 | /* set rx_reinit and schedule the next qh */ |
| 1473 | ep->rx_reinit = 1; |
| 1474 | musb_start_urb(musb, 1, next_qh); |
| 1475 | } |
| 1476 | } |
| 1477 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1478 | /* |
| 1479 | * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, |
| 1480 | * and high-bandwidth IN transfer cases. |
| 1481 | */ |
| 1482 | void musb_host_rx(struct musb *musb, u8 epnum) |
| 1483 | { |
| 1484 | struct urb *urb; |
| 1485 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 1486 | void __iomem *epio = hw_ep->regs; |
| 1487 | struct musb_qh *qh = hw_ep->in_qh; |
| 1488 | size_t xfer_len; |
| 1489 | void __iomem *mbase = musb->mregs; |
| 1490 | int pipe; |
| 1491 | u16 rx_csr, val; |
| 1492 | bool iso_err = false; |
| 1493 | bool done = false; |
| 1494 | u32 status; |
| 1495 | struct dma_channel *dma; |
| 1496 | |
| 1497 | musb_ep_select(mbase, epnum); |
| 1498 | |
| 1499 | urb = next_urb(qh); |
| 1500 | dma = is_dma_capable() ? hw_ep->rx_channel : NULL; |
| 1501 | status = 0; |
| 1502 | xfer_len = 0; |
| 1503 | |
| 1504 | rx_csr = musb_readw(epio, MUSB_RXCSR); |
| 1505 | val = rx_csr; |
| 1506 | |
| 1507 | if (unlikely(!urb)) { |
| 1508 | /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least |
| 1509 | * usbtest #11 (unlinks) triggers it regularly, sometimes |
| 1510 | * with fifo full. (Only with DMA??) |
| 1511 | */ |
| 1512 | DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, |
| 1513 | musb_readw(epio, MUSB_RXCOUNT)); |
| 1514 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); |
| 1515 | return; |
| 1516 | } |
| 1517 | |
| 1518 | pipe = urb->pipe; |
| 1519 | |
| 1520 | DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", |
| 1521 | epnum, rx_csr, urb->actual_length, |
| 1522 | dma ? dma->actual_len : 0); |
| 1523 | |
| 1524 | /* check for errors, concurrent stall & unlink is not really |
| 1525 | * handled yet! */ |
| 1526 | if (rx_csr & MUSB_RXCSR_H_RXSTALL) { |
| 1527 | DBG(3, "RX end %d STALL\n", epnum); |
| 1528 | |
| 1529 | /* stall; record URB status */ |
| 1530 | status = -EPIPE; |
| 1531 | |
| 1532 | } else if (rx_csr & MUSB_RXCSR_H_ERROR) { |
| 1533 | DBG(3, "end %d RX proto error\n", epnum); |
| 1534 | |
| 1535 | status = -EPROTO; |
| 1536 | musb_writeb(epio, MUSB_RXINTERVAL, 0); |
| 1537 | |
| 1538 | } else if (rx_csr & MUSB_RXCSR_DATAERROR) { |
| 1539 | |
| 1540 | if (USB_ENDPOINT_XFER_ISOC != qh->type) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1541 | DBG(6, "RX end %d NAK timeout\n", epnum); |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1542 | |
| 1543 | /* NOTE: NAKing is *NOT* an error, so we want to |
| 1544 | * continue. Except ... if there's a request for |
| 1545 | * another QH, use that instead of starving it. |
| 1546 | * |
| 1547 | * Devices like Ethernet and serial adapters keep |
| 1548 | * reads posted at all times, which will starve |
| 1549 | * other devices without this logic. |
| 1550 | */ |
| 1551 | if (usb_pipebulk(urb->pipe) |
| 1552 | && qh->mux == 1 |
| 1553 | && !list_is_singular(&musb->in_bulk)) { |
| 1554 | musb_bulk_rx_nak_timeout(musb, hw_ep); |
| 1555 | return; |
| 1556 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1557 | musb_ep_select(mbase, epnum); |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1558 | rx_csr |= MUSB_RXCSR_H_WZC_BITS; |
| 1559 | rx_csr &= ~MUSB_RXCSR_DATAERROR; |
| 1560 | musb_writew(epio, MUSB_RXCSR, rx_csr); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1561 | |
| 1562 | goto finish; |
| 1563 | } else { |
| 1564 | DBG(4, "RX end %d ISO data error\n", epnum); |
| 1565 | /* packet error reported later */ |
| 1566 | iso_err = true; |
| 1567 | } |
| 1568 | } |
| 1569 | |
| 1570 | /* faults abort the transfer */ |
| 1571 | if (status) { |
| 1572 | /* clean up dma and collect transfer count */ |
| 1573 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1574 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 1575 | (void) musb->dma_controller->channel_abort(dma); |
| 1576 | xfer_len = dma->actual_len; |
| 1577 | } |
| 1578 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); |
| 1579 | musb_writeb(epio, MUSB_RXINTERVAL, 0); |
| 1580 | done = true; |
| 1581 | goto finish; |
| 1582 | } |
| 1583 | |
| 1584 | if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { |
| 1585 | /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ |
| 1586 | ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); |
| 1587 | goto finish; |
| 1588 | } |
| 1589 | |
| 1590 | /* thorough shutdown for now ... given more precise fault handling |
| 1591 | * and better queueing support, we might keep a DMA pipeline going |
| 1592 | * while processing this irq for earlier completions. |
| 1593 | */ |
| 1594 | |
| 1595 | /* FIXME this is _way_ too much in-line logic for Mentor DMA */ |
| 1596 | |
| 1597 | #ifndef CONFIG_USB_INVENTRA_DMA |
| 1598 | if (rx_csr & MUSB_RXCSR_H_REQPKT) { |
| 1599 | /* REVISIT this happened for a while on some short reads... |
| 1600 | * the cleanup still needs investigation... looks bad... |
| 1601 | * and also duplicates dma cleanup code above ... plus, |
| 1602 | * shouldn't this be the "half full" double buffer case? |
| 1603 | */ |
| 1604 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 1605 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; |
| 1606 | (void) musb->dma_controller->channel_abort(dma); |
| 1607 | xfer_len = dma->actual_len; |
| 1608 | done = true; |
| 1609 | } |
| 1610 | |
| 1611 | DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, |
| 1612 | xfer_len, dma ? ", dma" : ""); |
| 1613 | rx_csr &= ~MUSB_RXCSR_H_REQPKT; |
| 1614 | |
| 1615 | musb_ep_select(mbase, epnum); |
| 1616 | musb_writew(epio, MUSB_RXCSR, |
| 1617 | MUSB_RXCSR_H_WZC_BITS | rx_csr); |
| 1618 | } |
| 1619 | #endif |
| 1620 | if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { |
| 1621 | xfer_len = dma->actual_len; |
| 1622 | |
| 1623 | val &= ~(MUSB_RXCSR_DMAENAB |
| 1624 | | MUSB_RXCSR_H_AUTOREQ |
| 1625 | | MUSB_RXCSR_AUTOCLEAR |
| 1626 | | MUSB_RXCSR_RXPKTRDY); |
| 1627 | musb_writew(hw_ep->regs, MUSB_RXCSR, val); |
| 1628 | |
| 1629 | #ifdef CONFIG_USB_INVENTRA_DMA |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1630 | if (usb_pipeisoc(pipe)) { |
| 1631 | struct usb_iso_packet_descriptor *d; |
| 1632 | |
| 1633 | d = urb->iso_frame_desc + qh->iso_idx; |
| 1634 | d->actual_length = xfer_len; |
| 1635 | |
| 1636 | /* even if there was an error, we did the dma |
| 1637 | * for iso_frame_desc->length |
| 1638 | */ |
| 1639 | if (d->status != EILSEQ && d->status != -EOVERFLOW) |
| 1640 | d->status = 0; |
| 1641 | |
| 1642 | if (++qh->iso_idx >= urb->number_of_packets) |
| 1643 | done = true; |
| 1644 | else |
| 1645 | done = false; |
| 1646 | |
| 1647 | } else { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1648 | /* done if urb buffer is full or short packet is recd */ |
| 1649 | done = (urb->actual_length + xfer_len >= |
| 1650 | urb->transfer_buffer_length |
| 1651 | || dma->actual_len < qh->maxpacket); |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1652 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1653 | |
| 1654 | /* send IN token for next packet, without AUTOREQ */ |
| 1655 | if (!done) { |
| 1656 | val |= MUSB_RXCSR_H_REQPKT; |
| 1657 | musb_writew(epio, MUSB_RXCSR, |
| 1658 | MUSB_RXCSR_H_WZC_BITS | val); |
| 1659 | } |
| 1660 | |
| 1661 | DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, |
| 1662 | done ? "off" : "reset", |
| 1663 | musb_readw(epio, MUSB_RXCSR), |
| 1664 | musb_readw(epio, MUSB_RXCOUNT)); |
| 1665 | #else |
| 1666 | done = true; |
| 1667 | #endif |
| 1668 | } else if (urb->status == -EINPROGRESS) { |
| 1669 | /* if no errors, be sure a packet is ready for unloading */ |
| 1670 | if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { |
| 1671 | status = -EPROTO; |
| 1672 | ERR("Rx interrupt with no errors or packet!\n"); |
| 1673 | |
| 1674 | /* FIXME this is another "SHOULD NEVER HAPPEN" */ |
| 1675 | |
| 1676 | /* SCRUB (RX) */ |
| 1677 | /* do the proper sequence to abort the transfer */ |
| 1678 | musb_ep_select(mbase, epnum); |
| 1679 | val &= ~MUSB_RXCSR_H_REQPKT; |
| 1680 | musb_writew(epio, MUSB_RXCSR, val); |
| 1681 | goto finish; |
| 1682 | } |
| 1683 | |
| 1684 | /* we are expecting IN packets */ |
| 1685 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 1686 | if (dma) { |
| 1687 | struct dma_controller *c; |
| 1688 | u16 rx_count; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1689 | int ret, length; |
| 1690 | dma_addr_t buf; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1691 | |
| 1692 | rx_count = musb_readw(epio, MUSB_RXCOUNT); |
| 1693 | |
| 1694 | DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n", |
| 1695 | epnum, rx_count, |
| 1696 | urb->transfer_dma |
| 1697 | + urb->actual_length, |
| 1698 | qh->offset, |
| 1699 | urb->transfer_buffer_length); |
| 1700 | |
| 1701 | c = musb->dma_controller; |
| 1702 | |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1703 | if (usb_pipeisoc(pipe)) { |
| 1704 | int status = 0; |
| 1705 | struct usb_iso_packet_descriptor *d; |
| 1706 | |
| 1707 | d = urb->iso_frame_desc + qh->iso_idx; |
| 1708 | |
| 1709 | if (iso_err) { |
| 1710 | status = -EILSEQ; |
| 1711 | urb->error_count++; |
| 1712 | } |
| 1713 | if (rx_count > d->length) { |
| 1714 | if (status == 0) { |
| 1715 | status = -EOVERFLOW; |
| 1716 | urb->error_count++; |
| 1717 | } |
| 1718 | DBG(2, "** OVERFLOW %d into %d\n",\ |
| 1719 | rx_count, d->length); |
| 1720 | |
| 1721 | length = d->length; |
| 1722 | } else |
| 1723 | length = rx_count; |
| 1724 | d->status = status; |
| 1725 | buf = urb->transfer_dma + d->offset; |
| 1726 | } else { |
| 1727 | length = rx_count; |
| 1728 | buf = urb->transfer_dma + |
| 1729 | urb->actual_length; |
| 1730 | } |
| 1731 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1732 | dma->desired_mode = 0; |
| 1733 | #ifdef USE_MODE1 |
| 1734 | /* because of the issue below, mode 1 will |
| 1735 | * only rarely behave with correct semantics. |
| 1736 | */ |
| 1737 | if ((urb->transfer_flags & |
| 1738 | URB_SHORT_NOT_OK) |
| 1739 | && (urb->transfer_buffer_length - |
| 1740 | urb->actual_length) |
| 1741 | > qh->maxpacket) |
| 1742 | dma->desired_mode = 1; |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1743 | if (rx_count < hw_ep->max_packet_sz_rx) { |
| 1744 | length = rx_count; |
| 1745 | dma->bDesiredMode = 0; |
| 1746 | } else { |
| 1747 | length = urb->transfer_buffer_length; |
| 1748 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1749 | #endif |
| 1750 | |
| 1751 | /* Disadvantage of using mode 1: |
| 1752 | * It's basically usable only for mass storage class; essentially all |
| 1753 | * other protocols also terminate transfers on short packets. |
| 1754 | * |
| 1755 | * Details: |
| 1756 | * An extra IN token is sent at the end of the transfer (due to AUTOREQ) |
| 1757 | * If you try to use mode 1 for (transfer_buffer_length - 512), and try |
| 1758 | * to use the extra IN token to grab the last packet using mode 0, then |
| 1759 | * the problem is that you cannot be sure when the device will send the |
| 1760 | * last packet and RxPktRdy set. Sometimes the packet is recd too soon |
| 1761 | * such that it gets lost when RxCSR is re-set at the end of the mode 1 |
| 1762 | * transfer, while sometimes it is recd just a little late so that if you |
| 1763 | * try to configure for mode 0 soon after the mode 1 transfer is |
| 1764 | * completed, you will find rxcount 0. Okay, so you might think why not |
| 1765 | * wait for an interrupt when the pkt is recd. Well, you won't get any! |
| 1766 | */ |
| 1767 | |
| 1768 | val = musb_readw(epio, MUSB_RXCSR); |
| 1769 | val &= ~MUSB_RXCSR_H_REQPKT; |
| 1770 | |
| 1771 | if (dma->desired_mode == 0) |
| 1772 | val &= ~MUSB_RXCSR_H_AUTOREQ; |
| 1773 | else |
| 1774 | val |= MUSB_RXCSR_H_AUTOREQ; |
| 1775 | val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB; |
| 1776 | |
| 1777 | musb_writew(epio, MUSB_RXCSR, |
| 1778 | MUSB_RXCSR_H_WZC_BITS | val); |
| 1779 | |
| 1780 | /* REVISIT if when actual_length != 0, |
| 1781 | * transfer_buffer_length needs to be |
| 1782 | * adjusted first... |
| 1783 | */ |
| 1784 | ret = c->channel_program( |
| 1785 | dma, qh->maxpacket, |
Ajay Kumar Gupta | f82a689 | 2008-10-29 15:10:31 +0200 | [diff] [blame] | 1786 | dma->desired_mode, buf, length); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1787 | |
| 1788 | if (!ret) { |
| 1789 | c->channel_release(dma); |
| 1790 | hw_ep->rx_channel = NULL; |
| 1791 | dma = NULL; |
| 1792 | /* REVISIT reset CSR */ |
| 1793 | } |
| 1794 | } |
| 1795 | #endif /* Mentor DMA */ |
| 1796 | |
| 1797 | if (!dma) { |
| 1798 | done = musb_host_packet_rx(musb, urb, |
| 1799 | epnum, iso_err); |
| 1800 | DBG(6, "read %spacket\n", done ? "last " : ""); |
| 1801 | } |
| 1802 | } |
| 1803 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1804 | finish: |
| 1805 | urb->actual_length += xfer_len; |
| 1806 | qh->offset += xfer_len; |
| 1807 | if (done) { |
| 1808 | if (urb->status == -EINPROGRESS) |
| 1809 | urb->status = status; |
| 1810 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); |
| 1811 | } |
| 1812 | } |
| 1813 | |
| 1814 | /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. |
| 1815 | * the software schedule associates multiple such nodes with a given |
| 1816 | * host side hardware endpoint + direction; scheduling may activate |
| 1817 | * that hardware endpoint. |
| 1818 | */ |
| 1819 | static int musb_schedule( |
| 1820 | struct musb *musb, |
| 1821 | struct musb_qh *qh, |
| 1822 | int is_in) |
| 1823 | { |
| 1824 | int idle; |
| 1825 | int best_diff; |
| 1826 | int best_end, epnum; |
| 1827 | struct musb_hw_ep *hw_ep = NULL; |
| 1828 | struct list_head *head = NULL; |
| 1829 | |
| 1830 | /* use fixed hardware for control and bulk */ |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1831 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1832 | head = &musb->control; |
| 1833 | hw_ep = musb->control_ep; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1834 | goto success; |
| 1835 | } |
| 1836 | |
| 1837 | /* else, periodic transfers get muxed to other endpoints */ |
| 1838 | |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1839 | /* |
| 1840 | * We know this qh hasn't been scheduled, so all we need to do |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1841 | * is choose which hardware endpoint to put it on ... |
| 1842 | * |
| 1843 | * REVISIT what we really want here is a regular schedule tree |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1844 | * like e.g. OHCI uses. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1845 | */ |
| 1846 | best_diff = 4096; |
| 1847 | best_end = -1; |
| 1848 | |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1849 | for (epnum = 1, hw_ep = musb->endpoints + 1; |
| 1850 | epnum < musb->nr_endpoints; |
| 1851 | epnum++, hw_ep++) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1852 | int diff; |
| 1853 | |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1854 | if (is_in || hw_ep->is_shared_fifo) { |
| 1855 | if (hw_ep->in_qh != NULL) |
| 1856 | continue; |
| 1857 | } else if (hw_ep->out_qh != NULL) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1858 | continue; |
Sergei Shtylyov | 5d67a85 | 2009-02-24 15:23:34 -0800 | [diff] [blame] | 1859 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1860 | if (hw_ep == musb->bulk_ep) |
| 1861 | continue; |
| 1862 | |
| 1863 | if (is_in) |
| 1864 | diff = hw_ep->max_packet_sz_rx - qh->maxpacket; |
| 1865 | else |
| 1866 | diff = hw_ep->max_packet_sz_tx - qh->maxpacket; |
| 1867 | |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1868 | if (diff >= 0 && best_diff > diff) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1869 | best_diff = diff; |
| 1870 | best_end = epnum; |
| 1871 | } |
| 1872 | } |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1873 | /* use bulk reserved ep1 if no other ep is free */ |
Felipe Balbi | aa5cbbe | 2008-11-17 09:08:16 +0200 | [diff] [blame] | 1874 | if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1875 | hw_ep = musb->bulk_ep; |
| 1876 | if (is_in) |
| 1877 | head = &musb->in_bulk; |
| 1878 | else |
| 1879 | head = &musb->out_bulk; |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 1880 | |
| 1881 | /* Enable bulk RX NAK timeout scheme when bulk requests are |
| 1882 | * multiplexed. This scheme doen't work in high speed to full |
| 1883 | * speed scenario as NAK interrupts are not coming from a |
| 1884 | * full speed device connected to a high speed device. |
| 1885 | * NAK timeout interval is 8 (128 uframe or 16ms) for HS and |
| 1886 | * 4 (8 frame or 8ms) for FS device. |
| 1887 | */ |
| 1888 | if (is_in && qh->dev) |
| 1889 | qh->intv_reg = |
| 1890 | (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1891 | goto success; |
| 1892 | } else if (best_end < 0) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1893 | return -ENOSPC; |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1894 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1895 | |
| 1896 | idle = 1; |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1897 | qh->mux = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1898 | hw_ep = musb->endpoints + best_end; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1899 | DBG(4, "qh %p periodic slot %d\n", qh, best_end); |
| 1900 | success: |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 1901 | if (head) { |
| 1902 | idle = list_empty(head); |
| 1903 | list_add_tail(&qh->ring, head); |
| 1904 | qh->mux = 1; |
| 1905 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1906 | qh->hw_ep = hw_ep; |
| 1907 | qh->hep->hcpriv = qh; |
| 1908 | if (idle) |
| 1909 | musb_start_urb(musb, is_in, qh); |
| 1910 | return 0; |
| 1911 | } |
| 1912 | |
| 1913 | static int musb_urb_enqueue( |
| 1914 | struct usb_hcd *hcd, |
| 1915 | struct urb *urb, |
| 1916 | gfp_t mem_flags) |
| 1917 | { |
| 1918 | unsigned long flags; |
| 1919 | struct musb *musb = hcd_to_musb(hcd); |
| 1920 | struct usb_host_endpoint *hep = urb->ep; |
David Brownell | 74bb350 | 2009-03-26 17:36:57 -0700 | [diff] [blame] | 1921 | struct musb_qh *qh; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1922 | struct usb_endpoint_descriptor *epd = &hep->desc; |
| 1923 | int ret; |
| 1924 | unsigned type_reg; |
| 1925 | unsigned interval; |
| 1926 | |
| 1927 | /* host role must be active */ |
| 1928 | if (!is_host_active(musb) || !musb->is_active) |
| 1929 | return -ENODEV; |
| 1930 | |
| 1931 | spin_lock_irqsave(&musb->lock, flags); |
| 1932 | ret = usb_hcd_link_urb_to_ep(hcd, urb); |
David Brownell | 74bb350 | 2009-03-26 17:36:57 -0700 | [diff] [blame] | 1933 | qh = ret ? NULL : hep->hcpriv; |
| 1934 | if (qh) |
| 1935 | urb->hcpriv = qh; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1936 | spin_unlock_irqrestore(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1937 | |
| 1938 | /* DMA mapping was already done, if needed, and this urb is on |
David Brownell | 74bb350 | 2009-03-26 17:36:57 -0700 | [diff] [blame] | 1939 | * hep->urb_list now ... so we're done, unless hep wasn't yet |
| 1940 | * scheduled onto a live qh. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1941 | * |
| 1942 | * REVISIT best to keep hep->hcpriv valid until the endpoint gets |
| 1943 | * disabled, testing for empty qh->ring and avoiding qh setup costs |
| 1944 | * except for the first urb queued after a config change. |
| 1945 | */ |
David Brownell | 74bb350 | 2009-03-26 17:36:57 -0700 | [diff] [blame] | 1946 | if (qh || ret) |
| 1947 | return ret; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1948 | |
| 1949 | /* Allocate and initialize qh, minimizing the work done each time |
| 1950 | * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. |
| 1951 | * |
| 1952 | * REVISIT consider a dedicated qh kmem_cache, so it's harder |
| 1953 | * for bugs in other kernel code to break this driver... |
| 1954 | */ |
| 1955 | qh = kzalloc(sizeof *qh, mem_flags); |
| 1956 | if (!qh) { |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 1957 | spin_lock_irqsave(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1958 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 1959 | spin_unlock_irqrestore(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1960 | return -ENOMEM; |
| 1961 | } |
| 1962 | |
| 1963 | qh->hep = hep; |
| 1964 | qh->dev = urb->dev; |
| 1965 | INIT_LIST_HEAD(&qh->ring); |
| 1966 | qh->is_ready = 1; |
| 1967 | |
| 1968 | qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize); |
| 1969 | |
| 1970 | /* no high bandwidth support yet */ |
| 1971 | if (qh->maxpacket & ~0x7ff) { |
| 1972 | ret = -EMSGSIZE; |
| 1973 | goto done; |
| 1974 | } |
| 1975 | |
Julia Lawall | 96bcd09 | 2009-01-24 17:57:24 -0800 | [diff] [blame] | 1976 | qh->epnum = usb_endpoint_num(epd); |
| 1977 | qh->type = usb_endpoint_type(epd); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1978 | |
| 1979 | /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ |
| 1980 | qh->addr_reg = (u8) usb_pipedevice(urb->pipe); |
| 1981 | |
| 1982 | /* precompute rxtype/txtype/type0 register */ |
| 1983 | type_reg = (qh->type << 4) | qh->epnum; |
| 1984 | switch (urb->dev->speed) { |
| 1985 | case USB_SPEED_LOW: |
| 1986 | type_reg |= 0xc0; |
| 1987 | break; |
| 1988 | case USB_SPEED_FULL: |
| 1989 | type_reg |= 0x80; |
| 1990 | break; |
| 1991 | default: |
| 1992 | type_reg |= 0x40; |
| 1993 | } |
| 1994 | qh->type_reg = type_reg; |
| 1995 | |
Sergei Shtylyov | 136733d | 2009-02-21 15:31:35 -0800 | [diff] [blame] | 1996 | /* Precompute RXINTERVAL/TXINTERVAL register */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1997 | switch (qh->type) { |
| 1998 | case USB_ENDPOINT_XFER_INT: |
Sergei Shtylyov | 136733d | 2009-02-21 15:31:35 -0800 | [diff] [blame] | 1999 | /* |
| 2000 | * Full/low speeds use the linear encoding, |
| 2001 | * high speed uses the logarithmic encoding. |
| 2002 | */ |
| 2003 | if (urb->dev->speed <= USB_SPEED_FULL) { |
| 2004 | interval = max_t(u8, epd->bInterval, 1); |
| 2005 | break; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2006 | } |
| 2007 | /* FALLTHROUGH */ |
| 2008 | case USB_ENDPOINT_XFER_ISOC: |
Sergei Shtylyov | 136733d | 2009-02-21 15:31:35 -0800 | [diff] [blame] | 2009 | /* ISO always uses logarithmic encoding */ |
| 2010 | interval = min_t(u8, epd->bInterval, 16); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2011 | break; |
| 2012 | default: |
| 2013 | /* REVISIT we actually want to use NAK limits, hinting to the |
| 2014 | * transfer scheduling logic to try some other qh, e.g. try |
| 2015 | * for 2 msec first: |
| 2016 | * |
| 2017 | * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; |
| 2018 | * |
| 2019 | * The downside of disabling this is that transfer scheduling |
| 2020 | * gets VERY unfair for nonperiodic transfers; a misbehaving |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 2021 | * peripheral could make that hurt. That's perfectly normal |
| 2022 | * for reads from network or serial adapters ... so we have |
| 2023 | * partial NAKlimit support for bulk RX. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2024 | * |
Ajay Kumar Gupta | 1e0320f | 2009-02-24 15:26:13 -0800 | [diff] [blame] | 2025 | * The upside of disabling it is simpler transfer scheduling. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2026 | */ |
| 2027 | interval = 0; |
| 2028 | } |
| 2029 | qh->intv_reg = interval; |
| 2030 | |
| 2031 | /* precompute addressing for external hub/tt ports */ |
| 2032 | if (musb->is_multipoint) { |
| 2033 | struct usb_device *parent = urb->dev->parent; |
| 2034 | |
| 2035 | if (parent != hcd->self.root_hub) { |
| 2036 | qh->h_addr_reg = (u8) parent->devnum; |
| 2037 | |
| 2038 | /* set up tt info if needed */ |
| 2039 | if (urb->dev->tt) { |
| 2040 | qh->h_port_reg = (u8) urb->dev->ttport; |
Ajay Kumar Gupta | ae5ad29 | 2008-09-11 11:53:20 +0300 | [diff] [blame] | 2041 | if (urb->dev->tt->hub) |
| 2042 | qh->h_addr_reg = |
| 2043 | (u8) urb->dev->tt->hub->devnum; |
| 2044 | if (urb->dev->tt->multi) |
| 2045 | qh->h_addr_reg |= 0x80; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2046 | } |
| 2047 | } |
| 2048 | } |
| 2049 | |
| 2050 | /* invariant: hep->hcpriv is null OR the qh that's already scheduled. |
| 2051 | * until we get real dma queues (with an entry for each urb/buffer), |
| 2052 | * we only have work to do in the former case. |
| 2053 | */ |
| 2054 | spin_lock_irqsave(&musb->lock, flags); |
| 2055 | if (hep->hcpriv) { |
| 2056 | /* some concurrent activity submitted another urb to hep... |
| 2057 | * odd, rare, error prone, but legal. |
| 2058 | */ |
| 2059 | kfree(qh); |
| 2060 | ret = 0; |
| 2061 | } else |
| 2062 | ret = musb_schedule(musb, qh, |
| 2063 | epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); |
| 2064 | |
| 2065 | if (ret == 0) { |
| 2066 | urb->hcpriv = qh; |
| 2067 | /* FIXME set urb->start_frame for iso/intr, it's tested in |
| 2068 | * musb_start_urb(), but otherwise only konicawc cares ... |
| 2069 | */ |
| 2070 | } |
| 2071 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2072 | |
| 2073 | done: |
| 2074 | if (ret != 0) { |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 2075 | spin_lock_irqsave(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2076 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
Ajay Kumar Gupta | 2492e67 | 2008-09-11 11:53:21 +0300 | [diff] [blame] | 2077 | spin_unlock_irqrestore(&musb->lock, flags); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2078 | kfree(qh); |
| 2079 | } |
| 2080 | return ret; |
| 2081 | } |
| 2082 | |
| 2083 | |
| 2084 | /* |
| 2085 | * abort a transfer that's at the head of a hardware queue. |
| 2086 | * called with controller locked, irqs blocked |
| 2087 | * that hardware queue advances to the next transfer, unless prevented |
| 2088 | */ |
| 2089 | static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in) |
| 2090 | { |
| 2091 | struct musb_hw_ep *ep = qh->hw_ep; |
| 2092 | void __iomem *epio = ep->regs; |
| 2093 | unsigned hw_end = ep->epnum; |
| 2094 | void __iomem *regs = ep->musb->mregs; |
| 2095 | u16 csr; |
| 2096 | int status = 0; |
| 2097 | |
| 2098 | musb_ep_select(regs, hw_end); |
| 2099 | |
| 2100 | if (is_dma_capable()) { |
| 2101 | struct dma_channel *dma; |
| 2102 | |
| 2103 | dma = is_in ? ep->rx_channel : ep->tx_channel; |
| 2104 | if (dma) { |
| 2105 | status = ep->musb->dma_controller->channel_abort(dma); |
| 2106 | DBG(status ? 1 : 3, |
| 2107 | "abort %cX%d DMA for urb %p --> %d\n", |
| 2108 | is_in ? 'R' : 'T', ep->epnum, |
| 2109 | urb, status); |
| 2110 | urb->actual_length += dma->actual_len; |
| 2111 | } |
| 2112 | } |
| 2113 | |
| 2114 | /* turn off DMA requests, discard state, stop polling ... */ |
| 2115 | if (is_in) { |
| 2116 | /* giveback saves bulk toggle */ |
| 2117 | csr = musb_h_flush_rxfifo(ep, 0); |
| 2118 | |
| 2119 | /* REVISIT we still get an irq; should likely clear the |
| 2120 | * endpoint's irq status here to avoid bogus irqs. |
| 2121 | * clearing that status is platform-specific... |
| 2122 | */ |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 2123 | } else if (ep->epnum) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2124 | musb_h_tx_flush_fifo(ep); |
| 2125 | csr = musb_readw(epio, MUSB_TXCSR); |
| 2126 | csr &= ~(MUSB_TXCSR_AUTOSET |
| 2127 | | MUSB_TXCSR_DMAENAB |
| 2128 | | MUSB_TXCSR_H_RXSTALL |
| 2129 | | MUSB_TXCSR_H_NAKTIMEOUT |
| 2130 | | MUSB_TXCSR_H_ERROR |
| 2131 | | MUSB_TXCSR_TXPKTRDY); |
| 2132 | musb_writew(epio, MUSB_TXCSR, csr); |
| 2133 | /* REVISIT may need to clear FLUSHFIFO ... */ |
| 2134 | musb_writew(epio, MUSB_TXCSR, csr); |
| 2135 | /* flush cpu writebuffer */ |
| 2136 | csr = musb_readw(epio, MUSB_TXCSR); |
David Brownell | 78322c1 | 2009-03-26 17:38:30 -0700 | [diff] [blame] | 2137 | } else { |
| 2138 | musb_h_ep0_flush_fifo(ep); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2139 | } |
| 2140 | if (status == 0) |
| 2141 | musb_advance_schedule(ep->musb, urb, ep, is_in); |
| 2142 | return status; |
| 2143 | } |
| 2144 | |
| 2145 | static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
| 2146 | { |
| 2147 | struct musb *musb = hcd_to_musb(hcd); |
| 2148 | struct musb_qh *qh; |
| 2149 | struct list_head *sched; |
| 2150 | unsigned long flags; |
| 2151 | int ret; |
| 2152 | |
| 2153 | DBG(4, "urb=%p, dev%d ep%d%s\n", urb, |
| 2154 | usb_pipedevice(urb->pipe), |
| 2155 | usb_pipeendpoint(urb->pipe), |
| 2156 | usb_pipein(urb->pipe) ? "in" : "out"); |
| 2157 | |
| 2158 | spin_lock_irqsave(&musb->lock, flags); |
| 2159 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); |
| 2160 | if (ret) |
| 2161 | goto done; |
| 2162 | |
| 2163 | qh = urb->hcpriv; |
| 2164 | if (!qh) |
| 2165 | goto done; |
| 2166 | |
| 2167 | /* Any URB not actively programmed into endpoint hardware can be |
Sergei Shtylyov | a2fd814 | 2009-02-21 15:30:45 -0800 | [diff] [blame] | 2168 | * immediately given back; that's any URB not at the head of an |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2169 | * endpoint queue, unless someday we get real DMA queues. And even |
Sergei Shtylyov | a2fd814 | 2009-02-21 15:30:45 -0800 | [diff] [blame] | 2170 | * if it's at the head, it might not be known to the hardware... |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2171 | * |
| 2172 | * Otherwise abort current transfer, pending dma, etc.; urb->status |
| 2173 | * has already been updated. This is a synchronous abort; it'd be |
| 2174 | * OK to hold off until after some IRQ, though. |
| 2175 | */ |
| 2176 | if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list) |
| 2177 | ret = -EINPROGRESS; |
| 2178 | else { |
| 2179 | switch (qh->type) { |
| 2180 | case USB_ENDPOINT_XFER_CONTROL: |
| 2181 | sched = &musb->control; |
| 2182 | break; |
| 2183 | case USB_ENDPOINT_XFER_BULK: |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2184 | if (qh->mux == 1) { |
| 2185 | if (usb_pipein(urb->pipe)) |
| 2186 | sched = &musb->in_bulk; |
| 2187 | else |
| 2188 | sched = &musb->out_bulk; |
| 2189 | break; |
| 2190 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2191 | default: |
| 2192 | /* REVISIT when we get a schedule tree, periodic |
| 2193 | * transfers won't always be at the head of a |
| 2194 | * singleton queue... |
| 2195 | */ |
| 2196 | sched = NULL; |
| 2197 | break; |
| 2198 | } |
| 2199 | } |
| 2200 | |
| 2201 | /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ |
| 2202 | if (ret < 0 || (sched && qh != first_qh(sched))) { |
| 2203 | int ready = qh->is_ready; |
| 2204 | |
| 2205 | ret = 0; |
| 2206 | qh->is_ready = 0; |
| 2207 | __musb_giveback(musb, urb, 0); |
| 2208 | qh->is_ready = ready; |
Sergei Shtylyov | a2fd814 | 2009-02-21 15:30:45 -0800 | [diff] [blame] | 2209 | |
| 2210 | /* If nothing else (usually musb_giveback) is using it |
| 2211 | * and its URB list has emptied, recycle this qh. |
| 2212 | */ |
| 2213 | if (ready && list_empty(&qh->hep->urb_list)) { |
| 2214 | qh->hep->hcpriv = NULL; |
| 2215 | list_del(&qh->ring); |
| 2216 | kfree(qh); |
| 2217 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2218 | } else |
| 2219 | ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN); |
| 2220 | done: |
| 2221 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2222 | return ret; |
| 2223 | } |
| 2224 | |
| 2225 | /* disable an endpoint */ |
| 2226 | static void |
| 2227 | musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) |
| 2228 | { |
| 2229 | u8 epnum = hep->desc.bEndpointAddress; |
| 2230 | unsigned long flags; |
| 2231 | struct musb *musb = hcd_to_musb(hcd); |
| 2232 | u8 is_in = epnum & USB_DIR_IN; |
Sergei Shtylyov | dc61d23 | 2009-02-21 15:31:01 -0800 | [diff] [blame] | 2233 | struct musb_qh *qh; |
| 2234 | struct urb *urb; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2235 | struct list_head *sched; |
| 2236 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2237 | spin_lock_irqsave(&musb->lock, flags); |
| 2238 | |
Sergei Shtylyov | dc61d23 | 2009-02-21 15:31:01 -0800 | [diff] [blame] | 2239 | qh = hep->hcpriv; |
| 2240 | if (qh == NULL) |
| 2241 | goto exit; |
| 2242 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2243 | switch (qh->type) { |
| 2244 | case USB_ENDPOINT_XFER_CONTROL: |
| 2245 | sched = &musb->control; |
| 2246 | break; |
| 2247 | case USB_ENDPOINT_XFER_BULK: |
Ajay Kumar Gupta | 23d15e0 | 2008-10-29 15:10:35 +0200 | [diff] [blame] | 2248 | if (qh->mux == 1) { |
| 2249 | if (is_in) |
| 2250 | sched = &musb->in_bulk; |
| 2251 | else |
| 2252 | sched = &musb->out_bulk; |
| 2253 | break; |
| 2254 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2255 | default: |
| 2256 | /* REVISIT when we get a schedule tree, periodic transfers |
| 2257 | * won't always be at the head of a singleton queue... |
| 2258 | */ |
| 2259 | sched = NULL; |
| 2260 | break; |
| 2261 | } |
| 2262 | |
| 2263 | /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ |
| 2264 | |
| 2265 | /* kick first urb off the hardware, if needed */ |
| 2266 | qh->is_ready = 0; |
| 2267 | if (!sched || qh == first_qh(sched)) { |
| 2268 | urb = next_urb(qh); |
| 2269 | |
| 2270 | /* make software (then hardware) stop ASAP */ |
| 2271 | if (!urb->unlinked) |
| 2272 | urb->status = -ESHUTDOWN; |
| 2273 | |
| 2274 | /* cleanup */ |
| 2275 | musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2276 | |
Sergei Shtylyov | dc61d23 | 2009-02-21 15:31:01 -0800 | [diff] [blame] | 2277 | /* Then nuke all the others ... and advance the |
| 2278 | * queue on hw_ep (e.g. bulk ring) when we're done. |
| 2279 | */ |
| 2280 | while (!list_empty(&hep->urb_list)) { |
| 2281 | urb = next_urb(qh); |
| 2282 | urb->status = -ESHUTDOWN; |
| 2283 | musb_advance_schedule(musb, urb, qh->hw_ep, is_in); |
| 2284 | } |
| 2285 | } else { |
| 2286 | /* Just empty the queue; the hardware is busy with |
| 2287 | * other transfers, and since !qh->is_ready nothing |
| 2288 | * will activate any of these as it advances. |
| 2289 | */ |
| 2290 | while (!list_empty(&hep->urb_list)) |
| 2291 | __musb_giveback(musb, next_urb(qh), -ESHUTDOWN); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2292 | |
Sergei Shtylyov | dc61d23 | 2009-02-21 15:31:01 -0800 | [diff] [blame] | 2293 | hep->hcpriv = NULL; |
| 2294 | list_del(&qh->ring); |
| 2295 | kfree(qh); |
| 2296 | } |
| 2297 | exit: |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2298 | spin_unlock_irqrestore(&musb->lock, flags); |
| 2299 | } |
| 2300 | |
| 2301 | static int musb_h_get_frame_number(struct usb_hcd *hcd) |
| 2302 | { |
| 2303 | struct musb *musb = hcd_to_musb(hcd); |
| 2304 | |
| 2305 | return musb_readw(musb->mregs, MUSB_FRAME); |
| 2306 | } |
| 2307 | |
| 2308 | static int musb_h_start(struct usb_hcd *hcd) |
| 2309 | { |
| 2310 | struct musb *musb = hcd_to_musb(hcd); |
| 2311 | |
| 2312 | /* NOTE: musb_start() is called when the hub driver turns |
| 2313 | * on port power, or when (OTG) peripheral starts. |
| 2314 | */ |
| 2315 | hcd->state = HC_STATE_RUNNING; |
| 2316 | musb->port1_status = 0; |
| 2317 | return 0; |
| 2318 | } |
| 2319 | |
| 2320 | static void musb_h_stop(struct usb_hcd *hcd) |
| 2321 | { |
| 2322 | musb_stop(hcd_to_musb(hcd)); |
| 2323 | hcd->state = HC_STATE_HALT; |
| 2324 | } |
| 2325 | |
| 2326 | static int musb_bus_suspend(struct usb_hcd *hcd) |
| 2327 | { |
| 2328 | struct musb *musb = hcd_to_musb(hcd); |
| 2329 | |
| 2330 | if (musb->xceiv.state == OTG_STATE_A_SUSPEND) |
| 2331 | return 0; |
| 2332 | |
| 2333 | if (is_host_active(musb) && musb->is_active) { |
| 2334 | WARNING("trying to suspend as %s is_active=%i\n", |
| 2335 | otg_state_string(musb), musb->is_active); |
| 2336 | return -EBUSY; |
| 2337 | } else |
| 2338 | return 0; |
| 2339 | } |
| 2340 | |
| 2341 | static int musb_bus_resume(struct usb_hcd *hcd) |
| 2342 | { |
| 2343 | /* resuming child port does the work */ |
| 2344 | return 0; |
| 2345 | } |
| 2346 | |
| 2347 | const struct hc_driver musb_hc_driver = { |
| 2348 | .description = "musb-hcd", |
| 2349 | .product_desc = "MUSB HDRC host driver", |
| 2350 | .hcd_priv_size = sizeof(struct musb), |
| 2351 | .flags = HCD_USB2 | HCD_MEMORY, |
| 2352 | |
| 2353 | /* not using irq handler or reset hooks from usbcore, since |
| 2354 | * those must be shared with peripheral code for OTG configs |
| 2355 | */ |
| 2356 | |
| 2357 | .start = musb_h_start, |
| 2358 | .stop = musb_h_stop, |
| 2359 | |
| 2360 | .get_frame_number = musb_h_get_frame_number, |
| 2361 | |
| 2362 | .urb_enqueue = musb_urb_enqueue, |
| 2363 | .urb_dequeue = musb_urb_dequeue, |
| 2364 | .endpoint_disable = musb_h_disable, |
| 2365 | |
| 2366 | .hub_status_data = musb_hub_status_data, |
| 2367 | .hub_control = musb_hub_control, |
| 2368 | .bus_suspend = musb_bus_suspend, |
| 2369 | .bus_resume = musb_bus_resume, |
| 2370 | /* .start_port_reset = NULL, */ |
| 2371 | /* .hub_irq_enable = NULL, */ |
| 2372 | }; |