blob: 26fa6a795afe1d1a48710007a723f24ebd924c64 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080036#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/i915_drm.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Akshay Joshi0206e352011-08-16 15:34:10 -040044bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Daniel Vetter3dec0092010-08-20 21:40:52 +020045static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010046static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080047
48typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040049 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
Jesse Barnes79e53942008-11-07 14:24:08 -080058} intel_clock_t;
59
60typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040061 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080062} intel_range_t;
63
64typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040065 int dot_limit;
66 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080067} intel_p2_t;
68
69#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080070typedef struct intel_limit intel_limit_t;
71struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040072 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
Sean Paulcec2f352012-01-10 15:09:36 -080075 int, int, intel_clock_t *, intel_clock_t *);
Ma Lingd4906092009-03-18 20:13:27 +080076};
Jesse Barnes79e53942008-11-07 14:24:08 -080077
Jesse Barnes2377b742010-07-07 14:06:43 -070078/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
Daniel Vetterd2acd212012-10-20 20:57:43 +020081int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
Ma Lingd4906092009-03-18 20:13:27 +080091static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080093 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
Ma Lingd4906092009-03-18 20:13:27 +080095static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080097 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080099
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800104static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700108
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
Chris Wilson021357a2010-09-07 20:54:59 +0100114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
Chris Wilson8b99e682010-10-13 09:59:17 +0100117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100122}
123
Keith Packarde4b36692009-06-05 19:22:17 -0700124static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
Ma Lingd4906092009-03-18 20:13:27 +0800135 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800149 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700150};
Eric Anholt273e27c2011-03-30 13:01:10 -0700151
Keith Packarde4b36692009-06-05 19:22:17 -0700152static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800163 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800177 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700178};
179
Eric Anholt273e27c2011-03-30 13:01:10 -0700180
Keith Packarde4b36692009-06-05 19:22:17 -0700181static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800193 },
Ma Lingd4906092009-03-18 20:13:27 +0800194 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800208 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800222 },
Ma Lingd4906092009-03-18 20:13:27 +0800223 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800237 },
Ma Lingd4906092009-03-18 20:13:27 +0800238 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700251 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400252 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700253};
254
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500255static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700258 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700261 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
Shaohua Li61157072009-04-03 15:24:43 +0800268 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700269};
270
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500271static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
Shaohua Li61157072009-04-03 15:24:43 +0800282 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700283};
284
Eric Anholt273e27c2011-03-30 13:01:10 -0700285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800290static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
Zhao Yakui45476682009-12-31 16:06:04 +0800301 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700302};
303
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800304static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800329 .find_pll = intel_g4x_find_best_PLL,
330};
331
Eric Anholt273e27c2011-03-30 13:01:10 -0700332/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400341 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400355 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700371 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400372 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800373};
374
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
Vijay Purushothaman17dc9252012-09-27 19:13:09 +0530391 .vco = { .min = 4000000, .max = 5994000},
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700406 .n = { .min = 1, .max = 7 },
Vijay Purushothaman74a4dd22012-09-27 19:13:04 +0530407 .m = { .min = 22, .max = 450 },
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
Jesse Barnes57f350b2012-03-28 13:39:25 -0700417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440}
441
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700442static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462}
463
Jesse Barnes57f350b2012-03-28 13:39:25 -0700464static void vlv_init_dpio(struct drm_device *dev)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473}
474
Daniel Vetter618563e2012-04-01 13:38:50 +0200475static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476{
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479}
480
481static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491};
492
Takashi Iwaib0354382012-03-20 13:07:05 +0100493static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495{
496 unsigned int val;
497
Takashi Iwai121d5272012-03-20 13:07:06 +0100498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
Daniel Vetter618563e2012-04-01 13:38:50 +0200502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
Takashi Iwaib0354382012-03-20 13:07:05 +0100505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
Seth Forshee14d94a32012-06-13 13:46:58 -0500514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
Takashi Iwaib0354382012-03-20 13:07:05 +0100515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519}
520
Chris Wilson1b894b52010-12-14 20:04:54 +0000521static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800523{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800526 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Takashi Iwaib0354382012-03-20 13:07:05 +0100529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800530 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000531 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000536 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Jani Nikula547dc042012-11-02 11:24:03 +0200542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
Zhao Yakui45476682009-12-31 16:06:04 +0800543 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800544 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800545 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800546
547 return limit;
548}
549
Ma Ling044c7c42009-03-18 20:13:23 +0800550static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551{
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Takashi Iwaib0354382012-03-20 13:07:05 +0100557 if (is_dual_link_lvds(dev_priv, LVDS))
Ma Ling044c7c42009-03-18 20:13:23 +0800558 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700559 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800560 else
561 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700562 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700565 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700567 limit = &intel_limits_g4x_sdvo;
Akshay Joshi0206e352011-08-16 15:34:10 -0400568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700569 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800570 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700571 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800572
573 return limit;
574}
575
Chris Wilson1b894b52010-12-14 20:04:54 +0000576static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800577{
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
Eric Anholtbad720f2009-10-22 16:11:14 -0700581 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000582 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800583 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800584 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500585 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500587 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800588 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500589 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700604 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800605 else
Keith Packarde4b36692009-06-05 19:22:17 -0700606 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800607 }
608 return limit;
609}
610
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500611/* m1 is reserved as 0 in Pineview, n is a ring counter */
612static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800613{
Shaohua Li21778322009-02-23 15:19:16 +0800614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618}
619
620static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800624 return;
625 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630}
631
Jesse Barnes79e53942008-11-07 14:24:08 -0800632/**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100635bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800636{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100637 struct drm_device *dev = crtc->dev;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100638 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800639
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100642 return true;
643
644 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800645}
646
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800647#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800648/**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
Chris Wilson1b894b52010-12-14 20:04:54 +0000653static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800656{
Jesse Barnes79e53942008-11-07 14:24:08 -0800657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400658 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800659 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400660 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400662 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400664 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400666 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800667 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400668 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800669 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400670 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400672 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400677 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800678
679 return true;
680}
681
Ma Lingd4906092009-03-18 20:13:27 +0800682static bool
683intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800686
Jesse Barnes79e53942008-11-07 14:24:08 -0800687{
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800691 int err = target;
692
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800694 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800695 /*
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
699 * even can.
700 */
Takashi Iwaib0354382012-03-20 13:07:05 +0100701 if (is_dual_link_lvds(dev_priv, LVDS))
Jesse Barnes79e53942008-11-07 14:24:08 -0800702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
Akshay Joshi0206e352011-08-16 15:34:10 -0400712 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800713
Zhao Yakui42158662009-11-20 11:24:18 +0800714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800720 break;
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800725 int this_err;
726
Shaohua Li21778322009-02-23 15:19:16 +0800727 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000728 if (!intel_PLL_is_valid(dev, limit,
729 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800730 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800731 if (match_clock &&
732 clock.p != match_clock->p)
733 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800734
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
737 *best_clock = clock;
738 err = this_err;
739 }
740 }
741 }
742 }
743 }
744
745 return (err != target);
746}
747
Ma Lingd4906092009-03-18 20:13:27 +0800748static bool
749intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800752{
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 intel_clock_t clock;
756 int max_n;
757 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800760 found = false;
761
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800763 int lvds_reg;
764
Eric Anholtc619eed2010-01-28 16:45:52 -0800765 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800766 lvds_reg = PCH_LVDS;
767 else
768 lvds_reg = LVDS;
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800770 LVDS_CLKB_POWER_UP)
771 clock.p2 = limit->p2.p2_fast;
772 else
773 clock.p2 = limit->p2.p2_slow;
774 } else {
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
777 else
778 clock.p2 = limit->p2.p2_fast;
779 }
780
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200783 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200785 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
792 int this_err;
793
Shaohua Li21778322009-02-23 15:19:16 +0800794 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800797 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000801
802 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800813 return found;
814}
Ma Lingd4906092009-03-18 20:13:27 +0800815
Zhenyu Wang2c072452009-06-05 15:38:42 +0800816static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500817intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800820{
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800823
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800824 if (target < 200000) {
825 clock.n = 1;
826 clock.p1 = 2;
827 clock.p2 = 10;
828 clock.m1 = 12;
829 clock.m2 = 9;
830 } else {
831 clock.n = 2;
832 clock.p1 = 1;
833 clock.p2 = 10;
834 clock.m1 = 14;
835 clock.m2 = 8;
836 }
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 return true;
840}
841
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700842/* DisplayPort has only two frequencies, 162MHz and 270MHz */
843static bool
844intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700847{
Chris Wilson5eddb702010-09-11 13:48:45 +0100848 intel_clock_t clock;
849 if (target < 200000) {
850 clock.p1 = 2;
851 clock.p2 = 10;
852 clock.n = 2;
853 clock.m1 = 23;
854 clock.m2 = 8;
855 } else {
856 clock.p1 = 1;
857 clock.p2 = 10;
858 clock.n = 1;
859 clock.m1 = 14;
860 clock.m2 = 2;
861 }
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865 clock.vco = 0;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
867 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700868}
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700869static bool
870intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
873{
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875 u32 m, n, fastclk;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
878 int dotclk, flag;
879
Alan Coxaf447bd2012-07-25 13:49:18 +0100880 flag = 0;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700881 dotclk = target * 1000;
882 bestppm = 1000000;
883 ppm = absppm = 0;
884 fastclk = dotclk / (2*100);
885 updrate = 0;
886 minupdate = 19200;
887 fracbits = 1;
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896 if (p2 > 10)
897 p2 = p2 - 1;
898 p = p1 * p2;
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
903 m = m1 * m2;
904 vco = updrate * m;
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909 bestppm = 0;
910 flag = 1;
911 }
912 if (absppm < bestppm - 10) {
913 bestppm = absppm;
914 flag = 1;
915 }
916 if (flag) {
917 bestn = n;
918 bestm1 = m1;
919 bestm2 = m2;
920 bestp1 = p1;
921 bestp2 = p2;
922 flag = 0;
923 }
924 }
925 }
926 }
927 }
928 }
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
934
935 return true;
936}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700937
Paulo Zanonia5c961d2012-10-24 15:59:34 -0200938enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939 enum pipe pipe)
940{
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944 return intel_crtc->cpu_transcoder;
945}
946
Paulo Zanonia928d532012-05-04 17:18:15 -0300947static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948{
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
951
952 frame = I915_READ(frame_reg);
953
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
956}
957
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700958/**
959 * intel_wait_for_vblank - wait for vblank on a given pipe
960 * @dev: drm device
961 * @pipe: pipe to wait for
962 *
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
964 * mode setting code.
965 */
966void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800967{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700968 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800969 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700970
Paulo Zanonia928d532012-05-04 17:18:15 -0300971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
973 return;
974 }
975
Chris Wilson300387c2010-09-05 20:25:43 +0100976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
978 *
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
985 * vblanks...
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
988 */
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700992 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
995 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700996 DRM_DEBUG_KMS("vblank wait timed out\n");
997}
998
Keith Packardab7ad7f2010-10-03 00:33:06 -0700999/*
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001001 * @dev: drm device
1002 * @pipe: pipe to wait for
1003 *
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1007 *
Keith Packardab7ad7f2010-10-03 00:33:06 -07001008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1010 *
1011 * Otherwise:
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +01001014 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001015 */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001016void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020 pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001021
Keith Packardab7ad7f2010-10-03 00:33:06 -07001022 if (INTEL_INFO(dev)->gen >= 4) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001023 int reg = PIPECONF(cpu_transcoder);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001024
Keith Packardab7ad7f2010-10-03 00:33:06 -07001025 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027 100))
Daniel Vetter284637d2012-07-09 09:51:57 +02001028 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001029 } else {
Paulo Zanoni837ba002012-05-04 17:18:14 -03001030 u32 last_line, line_mask;
Chris Wilson58e10eb2010-10-03 10:56:11 +01001031 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -07001032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
Paulo Zanoni837ba002012-05-04 17:18:14 -03001034 if (IS_GEN2(dev))
1035 line_mask = DSL_LINEMASK_GEN2;
1036 else
1037 line_mask = DSL_LINEMASK_GEN3;
1038
Keith Packardab7ad7f2010-10-03 00:33:06 -07001039 /* Wait for the display line to settle */
1040 do {
Paulo Zanoni837ba002012-05-04 17:18:14 -03001041 last_line = I915_READ(reg) & line_mask;
Keith Packardab7ad7f2010-10-03 00:33:06 -07001042 mdelay(5);
Paulo Zanoni837ba002012-05-04 17:18:14 -03001043 } while (((I915_READ(reg) & line_mask) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -07001044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
Daniel Vetter284637d2012-07-09 09:51:57 +02001046 WARN(1, "pipe_off wait timed out\n");
Keith Packardab7ad7f2010-10-03 00:33:06 -07001047 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001048}
1049
Jesse Barnesb24e7172011-01-04 15:09:30 -08001050static const char *state_string(bool enabled)
1051{
1052 return enabled ? "on" : "off";
1053}
1054
1055/* Only for pre-ILK configs */
1056static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058{
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069}
1070#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
Jesse Barnes040484a2011-01-03 12:14:26 -08001073/* For ILK+ */
1074static void assert_pch_pll(struct drm_i915_private *dev_priv,
Chris Wilson92b27b02012-05-20 18:10:50 +01001075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1077 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001078{
Jesse Barnes040484a2011-01-03 12:14:26 -08001079 u32 val;
1080 bool cur_state;
1081
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 return;
1085 }
1086
Chris Wilson92b27b02012-05-20 18:10:50 +01001087 if (WARN (!pll,
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001089 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001090
Chris Wilson92b27b02012-05-20 18:10:50 +01001091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001099 u32 pch_dpll;
1100
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
Chris Wilson92b27b02012-05-20 18:10:50 +01001102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1111 crtc->pipe,
1112 val);
1113 }
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001114 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001115}
Chris Wilson92b27b02012-05-20 18:10:50 +01001116#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
Jesse Barnes040484a2011-01-03 12:14:26 -08001118
1119static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
Paulo Zanoniad80a812012-10-24 16:06:19 -02001125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126 pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001127
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
Paulo Zanoniad80a812012-10-24 16:06:19 -02001130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001131 val = I915_READ(reg);
Paulo Zanoniad80a812012-10-24 16:06:19 -02001132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001133 } else {
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147{
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
Paulo Zanonid63fa0d2012-11-20 13:27:35 -02001152 reg = FDI_RX_CTL(pipe);
1153 val = I915_READ(reg);
1154 cur_state = !!(val & FDI_RX_ENABLE);
Jesse Barnes040484a2011-01-03 12:14:26 -08001155 WARN(cur_state != state,
1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1157 state_string(state), state_string(cur_state));
1158}
1159#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164{
1165 int reg;
1166 u32 val;
1167
1168 /* ILK FDI PLL is always enabled */
1169 if (dev_priv->info->gen == 5)
1170 return;
1171
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001172 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173 if (IS_HASWELL(dev_priv->dev))
1174 return;
1175
Jesse Barnes040484a2011-01-03 12:14:26 -08001176 reg = FDI_TX_CTL(pipe);
1177 val = I915_READ(reg);
1178 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179}
1180
1181static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190}
1191
Jesse Barnesea0760c2011-01-04 15:09:32 -08001192static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194{
1195 int pp_reg, lvds_reg;
1196 u32 val;
1197 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001198 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001199
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1203 } else {
1204 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS;
1206 }
1207
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211 locked = false;
1212
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001218 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001219}
1220
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001221void assert_pipe(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001223{
1224 int reg;
1225 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001226 bool cur_state;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001227 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001229
Daniel Vetter8e636782012-01-22 01:36:48 +01001230 /* if we need the pipe A quirk it must be always on */
1231 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232 state = true;
1233
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001234 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001235 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001236 cur_state = !!(val & PIPECONF_ENABLE);
1237 WARN(cur_state != state,
1238 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001239 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001240}
1241
Chris Wilson931872f2012-01-16 23:01:13 +00001242static void assert_plane(struct drm_i915_private *dev_priv,
1243 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001244{
1245 int reg;
1246 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001247 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001248
1249 reg = DSPCNTR(plane);
1250 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001251 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252 WARN(cur_state != state,
1253 "plane %c assertion failure (expected %s, current %s)\n",
1254 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001255}
1256
Chris Wilson931872f2012-01-16 23:01:13 +00001257#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
Jesse Barnesb24e7172011-01-04 15:09:30 -08001260static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262{
1263 int reg, i;
1264 u32 val;
1265 int cur_pipe;
1266
Jesse Barnes19ec1352011-02-02 12:28:02 -08001267 /* Planes are fixed to pipes on ILK+ */
Adam Jackson28c057942011-10-07 14:38:42 -04001268 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269 reg = DSPCNTR(pipe);
1270 val = I915_READ(reg);
1271 WARN((val & DISPLAY_PLANE_ENABLE),
1272 "plane %c assertion failure, should be disabled but not\n",
1273 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001274 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001275 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001276
Jesse Barnesb24e7172011-01-04 15:09:30 -08001277 /* Need to check both planes against the pipe */
1278 for (i = 0; i < 2; i++) {
1279 reg = DSPCNTR(i);
1280 val = I915_READ(reg);
1281 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282 DISPPLANE_SEL_PIPE_SHIFT;
1283 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001284 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001286 }
1287}
1288
Jesse Barnes92f25842011-01-04 15:09:34 -08001289static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290{
1291 u32 val;
1292 bool enabled;
1293
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001294 if (HAS_PCH_LPT(dev_priv->dev)) {
1295 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296 return;
1297 }
1298
Jesse Barnes92f25842011-01-04 15:09:34 -08001299 val = I915_READ(PCH_DREF_CONTROL);
1300 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301 DREF_SUPERSPREAD_SOURCE_MASK));
1302 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303}
1304
1305static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe)
1307{
1308 int reg;
1309 u32 val;
1310 bool enabled;
1311
1312 reg = TRANSCONF(pipe);
1313 val = I915_READ(reg);
1314 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001315 WARN(enabled,
1316 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001318}
1319
Keith Packard4e634382011-08-06 10:39:45 -07001320static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001322{
1323 if ((val & DP_PORT_EN) == 0)
1324 return false;
1325
1326 if (HAS_PCH_CPT(dev_priv->dev)) {
1327 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330 return false;
1331 } else {
1332 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333 return false;
1334 }
1335 return true;
1336}
1337
Keith Packard1519b992011-08-06 10:35:34 -07001338static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, u32 val)
1340{
1341 if ((val & PORT_ENABLE) == 0)
1342 return false;
1343
1344 if (HAS_PCH_CPT(dev_priv->dev)) {
1345 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346 return false;
1347 } else {
1348 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349 return false;
1350 }
1351 return true;
1352}
1353
1354static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe, u32 val)
1356{
1357 if ((val & LVDS_PORT_EN) == 0)
1358 return false;
1359
1360 if (HAS_PCH_CPT(dev_priv->dev)) {
1361 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362 return false;
1363 } else {
1364 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365 return false;
1366 }
1367 return true;
1368}
1369
1370static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372{
1373 if ((val & ADPA_DAC_ENABLE) == 0)
1374 return false;
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377 return false;
1378 } else {
1379 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380 return false;
1381 }
1382 return true;
1383}
1384
Jesse Barnes291906f2011-02-02 12:28:03 -08001385static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001386 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001387{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001388 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001389 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001390 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001391 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001392
Daniel Vetter75c5da22012-09-10 21:58:29 +02001393 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394 && (val & DP_PIPEB_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001395 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001396}
1397
1398static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe, int reg)
1400{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001401 u32 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001402 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001403 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001404 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001405
Daniel Vetter75c5da22012-09-10 21:58:29 +02001406 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407 && (val & SDVO_PIPE_B_SELECT),
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001408 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001409}
1410
1411static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
1414 int reg;
1415 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001416
Keith Packardf0575e92011-07-25 22:12:43 -07001417 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001420
1421 reg = PCH_ADPA;
1422 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001423 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001424 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001425 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001426
1427 reg = PCH_LVDS;
1428 val = I915_READ(reg);
Xu, Anhuab70ad582012-08-13 03:08:33 +00001429 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001430 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001431 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001432
1433 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436}
1437
Jesse Barnesb24e7172011-01-04 15:09:30 -08001438/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001439 * intel_enable_pll - enable a PLL
1440 * @dev_priv: i915 private structure
1441 * @pipe: pipe PLL to enable
1442 *
1443 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444 * make sure the PLL reg is writable first though, since the panel write
1445 * protect mechanism may be enabled.
1446 *
1447 * Note! This is for pre-ILK only.
Thomas Richter7434a252012-07-18 19:22:30 +02001448 *
1449 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001450 */
1451static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452{
1453 int reg;
1454 u32 val;
1455
1456 /* No really, not for ILK+ */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07001457 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001458
1459 /* PLL is protected by panel, make sure we can write it */
1460 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461 assert_panel_unlocked(dev_priv, pipe);
1462
1463 reg = DPLL(pipe);
1464 val = I915_READ(reg);
1465 val |= DPLL_VCO_ENABLE;
1466
1467 /* We do this three times for luck */
1468 I915_WRITE(reg, val);
1469 POSTING_READ(reg);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg, val);
1472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg, val);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477}
1478
1479/**
1480 * intel_disable_pll - disable a PLL
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe PLL to disable
1483 *
1484 * Disable the PLL for @pipe, making sure the pipe is off first.
1485 *
1486 * Note! This is for pre-ILK only.
1487 */
1488static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489{
1490 int reg;
1491 u32 val;
1492
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495 return;
1496
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 reg = DPLL(pipe);
1501 val = I915_READ(reg);
1502 val &= ~DPLL_VCO_ENABLE;
1503 I915_WRITE(reg, val);
1504 POSTING_READ(reg);
1505}
1506
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001507/* SBI access */
1508static void
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001509intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1510 enum intel_sbi_destination destination)
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001511{
1512 unsigned long flags;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001513 u32 tmp;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001514
1515 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001516 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001517 DRM_ERROR("timeout waiting for SBI to become ready\n");
1518 goto out_unlock;
1519 }
1520
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001521 I915_WRITE(SBI_ADDR, (reg << 16));
1522 I915_WRITE(SBI_DATA, value);
1523
1524 if (destination == SBI_ICLK)
1525 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1526 else
1527 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1528 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001529
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001530 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001531 100)) {
1532 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1533 goto out_unlock;
1534 }
1535
1536out_unlock:
1537 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1538}
1539
1540static u32
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001543{
1544 unsigned long flags;
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001545 u32 value = 0;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001546
1547 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001548 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1550 goto out_unlock;
1551 }
1552
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02001553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001560
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1564 goto out_unlock;
1565 }
1566
1567 value = I915_READ(SBI_DATA);
1568
1569out_unlock:
1570 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1571 return value;
1572}
1573
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001574/**
Paulo Zanonib6b4e182012-10-31 18:12:38 -02001575 * ironlake_enable_pch_pll - enable PCH PLL
Jesse Barnes92f25842011-01-04 15:09:34 -08001576 * @dev_priv: i915 private structure
1577 * @pipe: pipe PLL to enable
1578 *
1579 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1580 * drives the transcoder clock.
1581 */
Paulo Zanonib6b4e182012-10-31 18:12:38 -02001582static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001583{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001584 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
Chris Wilson48da64a2012-05-13 20:16:12 +01001585 struct intel_pch_pll *pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001586 int reg;
1587 u32 val;
1588
Chris Wilson48da64a2012-05-13 20:16:12 +01001589 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001590 BUG_ON(dev_priv->info->gen < 5);
Chris Wilson48da64a2012-05-13 20:16:12 +01001591 pll = intel_crtc->pch_pll;
1592 if (pll == NULL)
1593 return;
1594
1595 if (WARN_ON(pll->refcount == 0))
1596 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001597
1598 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1599 pll->pll_reg, pll->active, pll->on,
1600 intel_crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001601
1602 /* PCH refclock must be enabled first */
1603 assert_pch_refclk_enabled(dev_priv);
1604
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001605 if (pll->active++ && pll->on) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001606 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001607 return;
1608 }
1609
1610 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1611
1612 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001613 val = I915_READ(reg);
1614 val |= DPLL_VCO_ENABLE;
1615 I915_WRITE(reg, val);
1616 POSTING_READ(reg);
1617 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001618
1619 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001620}
1621
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001622static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001623{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001624 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1625 struct intel_pch_pll *pll = intel_crtc->pch_pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001626 int reg;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001627 u32 val;
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001628
Jesse Barnes92f25842011-01-04 15:09:34 -08001629 /* PCH only available on ILK+ */
1630 BUG_ON(dev_priv->info->gen < 5);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001631 if (pll == NULL)
1632 return;
1633
Chris Wilson48da64a2012-05-13 20:16:12 +01001634 if (WARN_ON(pll->refcount == 0))
1635 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001636
1637 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1638 pll->pll_reg, pll->active, pll->on,
1639 intel_crtc->base.base.id);
1640
Chris Wilson48da64a2012-05-13 20:16:12 +01001641 if (WARN_ON(pll->active == 0)) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001642 assert_pch_pll_disabled(dev_priv, pll, NULL);
Chris Wilson48da64a2012-05-13 20:16:12 +01001643 return;
1644 }
1645
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001646 if (--pll->active) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001647 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001648 return;
1649 }
1650
1651 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
Jesse Barnes92f25842011-01-04 15:09:34 -08001652
1653 /* Make sure transcoder isn't still depending on us */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001654 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001655
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001656 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001657 val = I915_READ(reg);
1658 val &= ~DPLL_VCO_ENABLE;
1659 I915_WRITE(reg, val);
1660 POSTING_READ(reg);
1661 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001662
1663 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001664}
1665
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001666static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1667 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001668{
Daniel Vetter23670b322012-11-01 09:15:30 +01001669 struct drm_device *dev = dev_priv->dev;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001670 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Daniel Vetter23670b322012-11-01 09:15:30 +01001671 uint32_t reg, val, pipeconf_val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001672
1673 /* PCH only available on ILK+ */
1674 BUG_ON(dev_priv->info->gen < 5);
1675
1676 /* Make sure PCH DPLL is enabled */
Chris Wilson92b27b02012-05-20 18:10:50 +01001677 assert_pch_pll_enabled(dev_priv,
1678 to_intel_crtc(crtc)->pch_pll,
1679 to_intel_crtc(crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001680
1681 /* FDI must be feeding us bits for PCH ports */
1682 assert_fdi_tx_enabled(dev_priv, pipe);
1683 assert_fdi_rx_enabled(dev_priv, pipe);
1684
Daniel Vetter23670b322012-11-01 09:15:30 +01001685 if (HAS_PCH_CPT(dev)) {
1686 /* Workaround: Set the timing override bit before enabling the
1687 * pch transcoder. */
1688 reg = TRANS_CHICKEN2(pipe);
1689 val = I915_READ(reg);
1690 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1691 I915_WRITE(reg, val);
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001692 }
Daniel Vetter23670b322012-11-01 09:15:30 +01001693
Jesse Barnes040484a2011-01-03 12:14:26 -08001694 reg = TRANSCONF(pipe);
1695 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001696 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001697
1698 if (HAS_PCH_IBX(dev_priv->dev)) {
1699 /*
1700 * make the BPC in transcoder be consistent with
1701 * that in pipeconf reg.
1702 */
1703 val &= ~PIPE_BPC_MASK;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001704 val |= pipeconf_val & PIPE_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001705 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001706
1707 val &= ~TRANS_INTERLACE_MASK;
1708 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001709 if (HAS_PCH_IBX(dev_priv->dev) &&
1710 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1711 val |= TRANS_LEGACY_INTERLACED_ILK;
1712 else
1713 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001714 else
1715 val |= TRANS_PROGRESSIVE;
1716
Jesse Barnes040484a2011-01-03 12:14:26 -08001717 I915_WRITE(reg, val | TRANS_ENABLE);
1718 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1719 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1720}
1721
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001722static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
Paulo Zanoni937bb612012-10-31 18:12:47 -02001723 enum transcoder cpu_transcoder)
Jesse Barnes040484a2011-01-03 12:14:26 -08001724{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001725 u32 val, pipeconf_val;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001726
1727 /* PCH only available on ILK+ */
1728 BUG_ON(dev_priv->info->gen < 5);
1729
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001730 /* FDI must be feeding us bits for PCH ports */
Paulo Zanoni937bb612012-10-31 18:12:47 -02001731 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1732 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001733
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001734 /* Workaround: set timing override bit. */
1735 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001736 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001737 I915_WRITE(_TRANSA_CHICKEN2, val);
1738
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001739 val = TRANS_ENABLE;
Paulo Zanoni937bb612012-10-31 18:12:47 -02001740 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001741
Paulo Zanoni9a76b1c2012-10-31 18:12:48 -02001742 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1743 PIPECONF_INTERLACED_ILK)
Paulo Zanonia35f2672012-10-31 18:12:45 -02001744 val |= TRANS_INTERLACED;
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001745 else
1746 val |= TRANS_PROGRESSIVE;
1747
Paulo Zanoni25f3ef12012-10-31 18:12:49 -02001748 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
Paulo Zanoni937bb612012-10-31 18:12:47 -02001749 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1750 DRM_ERROR("Failed to enable PCH transcoder\n");
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001751}
1752
Paulo Zanonib8a4f402012-10-31 18:12:42 -02001753static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1754 enum pipe pipe)
Jesse Barnes040484a2011-01-03 12:14:26 -08001755{
Daniel Vetter23670b322012-11-01 09:15:30 +01001756 struct drm_device *dev = dev_priv->dev;
1757 uint32_t reg, val;
Jesse Barnes040484a2011-01-03 12:14:26 -08001758
1759 /* FDI relies on the transcoder */
1760 assert_fdi_tx_disabled(dev_priv, pipe);
1761 assert_fdi_rx_disabled(dev_priv, pipe);
1762
Jesse Barnes291906f2011-02-02 12:28:03 -08001763 /* Ports must be off as well */
1764 assert_pch_ports_disabled(dev_priv, pipe);
1765
Jesse Barnes040484a2011-01-03 12:14:26 -08001766 reg = TRANSCONF(pipe);
1767 val = I915_READ(reg);
1768 val &= ~TRANS_ENABLE;
1769 I915_WRITE(reg, val);
1770 /* wait for PCH transcoder off, transcoder state */
1771 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Jesse Barnes4c9c18c2011-10-13 09:46:32 -07001772 DRM_ERROR("failed to disable transcoder %d\n", pipe);
Daniel Vetter23670b322012-11-01 09:15:30 +01001773
1774 if (!HAS_PCH_IBX(dev)) {
1775 /* Workaround: Clear the timing override chicken bit again. */
1776 reg = TRANS_CHICKEN2(pipe);
1777 val = I915_READ(reg);
1778 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1779 I915_WRITE(reg, val);
1780 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001781}
1782
Paulo Zanoniab4d9662012-10-31 18:12:55 -02001783static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001784{
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001785 u32 val;
1786
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001787 val = I915_READ(_TRANSACONF);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001788 val &= ~TRANS_ENABLE;
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001789 I915_WRITE(_TRANSACONF, val);
Paulo Zanoni8fb033d2012-10-31 18:12:43 -02001790 /* wait for PCH transcoder off, transcoder state */
Paulo Zanoni8a52fd92012-10-31 18:12:51 -02001791 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1792 DRM_ERROR("Failed to disable PCH transcoder\n");
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001793
1794 /* Workaround: clear timing override bit. */
1795 val = I915_READ(_TRANSA_CHICKEN2);
Daniel Vetter23670b322012-11-01 09:15:30 +01001796 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
Paulo Zanoni223a6fd2012-10-31 18:12:52 -02001797 I915_WRITE(_TRANSA_CHICKEN2, val);
Jesse Barnes92f25842011-01-04 15:09:34 -08001798}
1799
1800/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001801 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001802 * @dev_priv: i915 private structure
1803 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001804 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001805 *
1806 * Enable @pipe, making sure that various hardware specific requirements
1807 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1808 *
1809 * @pipe should be %PIPE_A or %PIPE_B.
1810 *
1811 * Will wait until the pipe is actually running (i.e. first vblank) before
1812 * returning.
1813 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001814static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1815 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001816{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818 pipe);
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001819 enum transcoder pch_transcoder;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001820 int reg;
1821 u32 val;
1822
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001823 if (IS_HASWELL(dev_priv->dev))
1824 pch_transcoder = TRANSCODER_A;
1825 else
1826 pch_transcoder = pipe;
1827
Jesse Barnesb24e7172011-01-04 15:09:30 -08001828 /*
1829 * A pipe without a PLL won't actually be able to drive bits from
1830 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1831 * need the check.
1832 */
1833 if (!HAS_PCH_SPLIT(dev_priv->dev))
1834 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001835 else {
1836 if (pch_port) {
1837 /* if driving the PCH, we need FDI enabled */
Paulo Zanonicc391bb2012-11-20 13:27:37 -02001838 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1839 assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
Jesse Barnes040484a2011-01-03 12:14:26 -08001840 }
1841 /* FIXME: assert CPU port conditions for SNB+ */
1842 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001843
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001844 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001845 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001846 if (val & PIPECONF_ENABLE)
1847 return;
1848
1849 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001850 intel_wait_for_vblank(dev_priv->dev, pipe);
1851}
1852
1853/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001854 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001855 * @dev_priv: i915 private structure
1856 * @pipe: pipe to disable
1857 *
1858 * Disable @pipe, making sure that various hardware specific requirements
1859 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1860 *
1861 * @pipe should be %PIPE_A or %PIPE_B.
1862 *
1863 * Will wait until the pipe has shut down before returning.
1864 */
1865static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
1867{
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001868 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1869 pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001870 int reg;
1871 u32 val;
1872
1873 /*
1874 * Make sure planes won't keep trying to pump pixels to us,
1875 * or we might hang the display.
1876 */
1877 assert_planes_disabled(dev_priv, pipe);
1878
1879 /* Don't disable pipe A or pipe A PLLs if needed */
1880 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1881 return;
1882
Paulo Zanoni702e7a52012-10-23 18:29:59 -02001883 reg = PIPECONF(cpu_transcoder);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001884 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001885 if ((val & PIPECONF_ENABLE) == 0)
1886 return;
1887
1888 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001889 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1890}
1891
Keith Packardd74362c2011-07-28 14:47:14 -07001892/*
1893 * Plane regs are double buffered, going from enabled->disabled needs a
1894 * trigger in order to latch. The display address reg provides this.
1895 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03001896void intel_flush_display_plane(struct drm_i915_private *dev_priv,
Keith Packardd74362c2011-07-28 14:47:14 -07001897 enum plane plane)
1898{
Damien Lespiau14f86142012-10-29 15:24:49 +00001899 if (dev_priv->info->gen >= 4)
1900 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1901 else
1902 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
Keith Packardd74362c2011-07-28 14:47:14 -07001903}
1904
Jesse Barnesb24e7172011-01-04 15:09:30 -08001905/**
1906 * intel_enable_plane - enable a display plane on a given pipe
1907 * @dev_priv: i915 private structure
1908 * @plane: plane to enable
1909 * @pipe: pipe being fed
1910 *
1911 * Enable @plane on @pipe, making sure that @pipe is running first.
1912 */
1913static void intel_enable_plane(struct drm_i915_private *dev_priv,
1914 enum plane plane, enum pipe pipe)
1915{
1916 int reg;
1917 u32 val;
1918
1919 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1920 assert_pipe_enabled(dev_priv, pipe);
1921
1922 reg = DSPCNTR(plane);
1923 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001924 if (val & DISPLAY_PLANE_ENABLE)
1925 return;
1926
1927 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001928 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001929 intel_wait_for_vblank(dev_priv->dev, pipe);
1930}
1931
Jesse Barnesb24e7172011-01-04 15:09:30 -08001932/**
1933 * intel_disable_plane - disable a display plane
1934 * @dev_priv: i915 private structure
1935 * @plane: plane to disable
1936 * @pipe: pipe consuming the data
1937 *
1938 * Disable @plane; should be an independent operation.
1939 */
1940static void intel_disable_plane(struct drm_i915_private *dev_priv,
1941 enum plane plane, enum pipe pipe)
1942{
1943 int reg;
1944 u32 val;
1945
1946 reg = DSPCNTR(plane);
1947 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001948 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1949 return;
1950
1951 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001952 intel_flush_display_plane(dev_priv, plane);
1953 intel_wait_for_vblank(dev_priv->dev, pipe);
1954}
1955
Chris Wilson127bd2a2010-07-23 23:32:05 +01001956int
Chris Wilson48b956c2010-09-14 12:50:34 +01001957intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001958 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001959 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001960{
Chris Wilsonce453d82011-02-21 14:43:56 +00001961 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001962 u32 alignment;
1963 int ret;
1964
Chris Wilson05394f32010-11-08 19:18:58 +00001965 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001966 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001967 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1968 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001969 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001970 alignment = 4 * 1024;
1971 else
1972 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001973 break;
1974 case I915_TILING_X:
1975 /* pin() will align the object as required by fence */
1976 alignment = 0;
1977 break;
1978 case I915_TILING_Y:
1979 /* FIXME: Is this true? */
1980 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1981 return -EINVAL;
1982 default:
1983 BUG();
1984 }
1985
Chris Wilsonce453d82011-02-21 14:43:56 +00001986 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001987 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001988 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001989 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001990
1991 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1992 * fence, whereas 965+ only requires a fence if using
1993 * framebuffer compression. For simplicity, we always install
1994 * a fence as the cost is not that onerous.
1995 */
Chris Wilson06d98132012-04-17 15:31:24 +01001996 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001997 if (ret)
1998 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001999
Chris Wilson9a5a53b2012-03-22 15:10:00 +00002000 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002001
Chris Wilsonce453d82011-02-21 14:43:56 +00002002 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002003 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002004
2005err_unpin:
2006 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002007err_interruptible:
2008 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002009 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002010}
2011
Chris Wilson1690e1e2011-12-14 13:57:08 +01002012void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2013{
2014 i915_gem_object_unpin_fence(obj);
2015 i915_gem_object_unpin(obj);
2016}
2017
Daniel Vetterc2c75132012-07-05 12:17:30 +02002018/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2019 * is assumed to be a power-of-two. */
Damien Lespiau5a35e992012-10-26 18:20:12 +01002020unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2021 unsigned int bpp,
2022 unsigned int pitch)
Daniel Vetterc2c75132012-07-05 12:17:30 +02002023{
2024 int tile_rows, tiles;
2025
2026 tile_rows = *y / 8;
2027 *y %= 8;
2028 tiles = *x / (512/bpp);
2029 *x %= 512/bpp;
2030
2031 return tile_rows * pitch * 8 + tiles * 4096;
2032}
2033
Jesse Barnes17638cd2011-06-24 12:19:23 -07002034static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2035 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002036{
2037 struct drm_device *dev = crtc->dev;
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2040 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002041 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002042 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002043 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002044 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002045 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002046
2047 switch (plane) {
2048 case 0:
2049 case 1:
2050 break;
2051 default:
2052 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2053 return -EINVAL;
2054 }
2055
2056 intel_fb = to_intel_framebuffer(fb);
2057 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002058
Chris Wilson5eddb702010-09-11 13:48:45 +01002059 reg = DSPCNTR(plane);
2060 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002061 /* Mask out pixel format bits in case we change it */
2062 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002063 switch (fb->pixel_format) {
2064 case DRM_FORMAT_C8:
Jesse Barnes81255562010-08-02 12:07:50 -07002065 dspcntr |= DISPPLANE_8BPP;
2066 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002067 case DRM_FORMAT_XRGB1555:
2068 case DRM_FORMAT_ARGB1555:
2069 dspcntr |= DISPPLANE_BGRX555;
Jesse Barnes81255562010-08-02 12:07:50 -07002070 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002071 case DRM_FORMAT_RGB565:
2072 dspcntr |= DISPPLANE_BGRX565;
2073 break;
2074 case DRM_FORMAT_XRGB8888:
2075 case DRM_FORMAT_ARGB8888:
2076 dspcntr |= DISPPLANE_BGRX888;
2077 break;
2078 case DRM_FORMAT_XBGR8888:
2079 case DRM_FORMAT_ABGR8888:
2080 dspcntr |= DISPPLANE_RGBX888;
2081 break;
2082 case DRM_FORMAT_XRGB2101010:
2083 case DRM_FORMAT_ARGB2101010:
2084 dspcntr |= DISPPLANE_BGRX101010;
2085 break;
2086 case DRM_FORMAT_XBGR2101010:
2087 case DRM_FORMAT_ABGR2101010:
2088 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes81255562010-08-02 12:07:50 -07002089 break;
2090 default:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002091 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
Jesse Barnes81255562010-08-02 12:07:50 -07002092 return -EINVAL;
2093 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02002094
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002095 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002096 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002097 dspcntr |= DISPPLANE_TILED;
2098 else
2099 dspcntr &= ~DISPPLANE_TILED;
2100 }
2101
Chris Wilson5eddb702010-09-11 13:48:45 +01002102 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002103
Daniel Vettere506a0c2012-07-05 12:17:29 +02002104 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002105
Daniel Vetterc2c75132012-07-05 12:17:30 +02002106 if (INTEL_INFO(dev)->gen >= 4) {
2107 intel_crtc->dspaddr_offset =
Damien Lespiau5a35e992012-10-26 18:20:12 +01002108 intel_gen4_compute_offset_xtiled(&x, &y,
2109 fb->bits_per_pixel / 8,
2110 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002111 linear_offset -= intel_crtc->dspaddr_offset;
2112 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002113 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002114 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002115
2116 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002118 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002119 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02002120 I915_MODIFY_DISPBASE(DSPSURF(plane),
2121 obj->gtt_offset + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002122 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002123 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002124 } else
Daniel Vettere506a0c2012-07-05 12:17:29 +02002125 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002126 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002127
Jesse Barnes17638cd2011-06-24 12:19:23 -07002128 return 0;
2129}
2130
2131static int ironlake_update_plane(struct drm_crtc *crtc,
2132 struct drm_framebuffer *fb, int x, int y)
2133{
2134 struct drm_device *dev = crtc->dev;
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137 struct intel_framebuffer *intel_fb;
2138 struct drm_i915_gem_object *obj;
2139 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002140 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002141 u32 dspcntr;
2142 u32 reg;
2143
2144 switch (plane) {
2145 case 0:
2146 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002147 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002148 break;
2149 default:
2150 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2151 return -EINVAL;
2152 }
2153
2154 intel_fb = to_intel_framebuffer(fb);
2155 obj = intel_fb->obj;
2156
2157 reg = DSPCNTR(plane);
2158 dspcntr = I915_READ(reg);
2159 /* Mask out pixel format bits in case we change it */
2160 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002161 switch (fb->pixel_format) {
2162 case DRM_FORMAT_C8:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002163 dspcntr |= DISPPLANE_8BPP;
2164 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002165 case DRM_FORMAT_RGB565:
2166 dspcntr |= DISPPLANE_BGRX565;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002167 break;
Ville Syrjälä57779d02012-10-31 17:50:14 +02002168 case DRM_FORMAT_XRGB8888:
2169 case DRM_FORMAT_ARGB8888:
2170 dspcntr |= DISPPLANE_BGRX888;
2171 break;
2172 case DRM_FORMAT_XBGR8888:
2173 case DRM_FORMAT_ABGR8888:
2174 dspcntr |= DISPPLANE_RGBX888;
2175 break;
2176 case DRM_FORMAT_XRGB2101010:
2177 case DRM_FORMAT_ARGB2101010:
2178 dspcntr |= DISPPLANE_BGRX101010;
2179 break;
2180 case DRM_FORMAT_XBGR2101010:
2181 case DRM_FORMAT_ABGR2101010:
2182 dspcntr |= DISPPLANE_RGBX101010;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002183 break;
2184 default:
Ville Syrjälä57779d02012-10-31 17:50:14 +02002185 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002186 return -EINVAL;
2187 }
2188
2189 if (obj->tiling_mode != I915_TILING_NONE)
2190 dspcntr |= DISPPLANE_TILED;
2191 else
2192 dspcntr &= ~DISPPLANE_TILED;
2193
2194 /* must disable */
2195 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2196
2197 I915_WRITE(reg, dspcntr);
2198
Daniel Vettere506a0c2012-07-05 12:17:29 +02002199 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002200 intel_crtc->dspaddr_offset =
Damien Lespiau5a35e992012-10-26 18:20:12 +01002201 intel_gen4_compute_offset_xtiled(&x, &y,
2202 fb->bits_per_pixel / 8,
2203 fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002204 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002205
Daniel Vettere506a0c2012-07-05 12:17:29 +02002206 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2207 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002208 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002209 I915_MODIFY_DISPBASE(DSPSURF(plane),
2210 obj->gtt_offset + intel_crtc->dspaddr_offset);
Damien Lespiaubc1c91e2012-10-29 12:14:21 +00002211 if (IS_HASWELL(dev)) {
2212 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2213 } else {
2214 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2215 I915_WRITE(DSPLINOFF(plane), linear_offset);
2216 }
Jesse Barnes17638cd2011-06-24 12:19:23 -07002217 POSTING_READ(reg);
2218
2219 return 0;
2220}
2221
2222/* Assume fb object is pinned & idle & fenced and just update base pointers */
2223static int
2224intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2225 int x, int y, enum mode_set_atomic state)
2226{
2227 struct drm_device *dev = crtc->dev;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002229
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002230 if (dev_priv->display.disable_fbc)
2231 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002232 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002233
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002234 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002235}
2236
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002237static int
Chris Wilson14667a42012-04-03 17:58:35 +01002238intel_finish_fb(struct drm_framebuffer *old_fb)
2239{
2240 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2241 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2242 bool was_interruptible = dev_priv->mm.interruptible;
2243 int ret;
2244
2245 wait_event(dev_priv->pending_flip_queue,
2246 atomic_read(&dev_priv->mm.wedged) ||
2247 atomic_read(&obj->pending_flip) == 0);
2248
2249 /* Big Hammer, we also need to ensure that any pending
2250 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251 * current scanout is retired before unpinning the old
2252 * framebuffer.
2253 *
2254 * This should only fail upon a hung GPU, in which case we
2255 * can safely continue.
2256 */
2257 dev_priv->mm.interruptible = false;
2258 ret = i915_gem_object_finish_gpu(obj);
2259 dev_priv->mm.interruptible = was_interruptible;
2260
2261 return ret;
2262}
2263
Ville Syrjälä198598d2012-10-31 17:50:24 +02002264static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2265{
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_master_private *master_priv;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269
2270 if (!dev->primary->master)
2271 return;
2272
2273 master_priv = dev->primary->master->driver_priv;
2274 if (!master_priv->sarea_priv)
2275 return;
2276
2277 switch (intel_crtc->pipe) {
2278 case 0:
2279 master_priv->sarea_priv->pipeA_x = x;
2280 master_priv->sarea_priv->pipeA_y = y;
2281 break;
2282 case 1:
2283 master_priv->sarea_priv->pipeB_x = x;
2284 master_priv->sarea_priv->pipeB_y = y;
2285 break;
2286 default:
2287 break;
2288 }
2289}
2290
Chris Wilson14667a42012-04-03 17:58:35 +01002291static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002292intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002293 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002294{
2295 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002296 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter94352cf2012-07-05 22:51:56 +02002298 struct drm_framebuffer *old_fb;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002299 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002300
2301 /* no fb bound */
Daniel Vetter94352cf2012-07-05 22:51:56 +02002302 if (!fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002303 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002304 return 0;
2305 }
2306
Eugeni Dodonov5826eca2012-05-09 15:37:12 -03002307 if(intel_crtc->plane > dev_priv->num_pipe) {
2308 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2309 intel_crtc->plane,
2310 dev_priv->num_pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002311 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002312 }
2313
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002314 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002315 ret = intel_pin_and_fence_fb_obj(dev,
Daniel Vetter94352cf2012-07-05 22:51:56 +02002316 to_intel_framebuffer(fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002317 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002318 if (ret != 0) {
2319 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002320 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002321 return ret;
2322 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002323
Daniel Vetter94352cf2012-07-05 22:51:56 +02002324 if (crtc->fb)
2325 intel_finish_fb(crtc->fb);
Chris Wilson265db952010-09-20 15:41:01 +01002326
Daniel Vetter94352cf2012-07-05 22:51:56 +02002327 ret = dev_priv->display.update_plane(crtc, fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002328 if (ret) {
Daniel Vetter94352cf2012-07-05 22:51:56 +02002329 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002330 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002331 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002332 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002333 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002334
Daniel Vetter94352cf2012-07-05 22:51:56 +02002335 old_fb = crtc->fb;
2336 crtc->fb = fb;
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02002337 crtc->x = x;
2338 crtc->y = y;
Daniel Vetter94352cf2012-07-05 22:51:56 +02002339
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002340 if (old_fb) {
2341 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002342 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002343 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002344
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002345 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002346 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002347
Ville Syrjälä198598d2012-10-31 17:50:24 +02002348 intel_crtc_update_sarea_pos(crtc, x, y);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002349
2350 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002351}
2352
Chris Wilson5eddb702010-09-11 13:48:45 +01002353static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002354{
2355 struct drm_device *dev = crtc->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 u32 dpa_ctl;
2358
Zhao Yakui28c97732009-10-09 11:39:41 +08002359 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002360 dpa_ctl = I915_READ(DP_A);
2361 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2362
2363 if (clock < 200000) {
2364 u32 temp;
2365 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2366 /* workaround for 160Mhz:
2367 1) program 0x4600c bits 15:0 = 0x8124
2368 2) program 0x46010 bit 0 = 1
2369 3) program 0x46034 bit 24 = 1
2370 4) program 0x64000 bit 14 = 1
2371 */
2372 temp = I915_READ(0x4600c);
2373 temp &= 0xffff0000;
2374 I915_WRITE(0x4600c, temp | 0x8124);
2375
2376 temp = I915_READ(0x46010);
2377 I915_WRITE(0x46010, temp | 1);
2378
2379 temp = I915_READ(0x46034);
2380 I915_WRITE(0x46034, temp | (1 << 24));
2381 } else {
2382 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2383 }
2384 I915_WRITE(DP_A, dpa_ctl);
2385
Chris Wilson5eddb702010-09-11 13:48:45 +01002386 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002387 udelay(500);
2388}
2389
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002390static void intel_fdi_normal_train(struct drm_crtc *crtc)
2391{
2392 struct drm_device *dev = crtc->dev;
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2395 int pipe = intel_crtc->pipe;
2396 u32 reg, temp;
2397
2398 /* enable normal train */
2399 reg = FDI_TX_CTL(pipe);
2400 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002401 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002402 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2403 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002404 } else {
2405 temp &= ~FDI_LINK_TRAIN_NONE;
2406 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002407 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002408 I915_WRITE(reg, temp);
2409
2410 reg = FDI_RX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 if (HAS_PCH_CPT(dev)) {
2413 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2415 } else {
2416 temp &= ~FDI_LINK_TRAIN_NONE;
2417 temp |= FDI_LINK_TRAIN_NONE;
2418 }
2419 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2420
2421 /* wait one idle pattern time */
2422 POSTING_READ(reg);
2423 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002424
2425 /* IVB wants error correction enabled */
2426 if (IS_IVYBRIDGE(dev))
2427 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2428 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002429}
2430
Daniel Vetter01a415f2012-10-27 15:58:40 +02002431static void ivb_modeset_global_resources(struct drm_device *dev)
2432{
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct intel_crtc *pipe_B_crtc =
2435 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2436 struct intel_crtc *pipe_C_crtc =
2437 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2438 uint32_t temp;
2439
2440 /* When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. XXX: This misses the case where a pipe is not using
2442 * any pch resources and so doesn't need any fdi lanes. */
2443 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2444 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2445 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2446
2447 temp = I915_READ(SOUTH_CHICKEN1);
2448 temp &= ~FDI_BC_BIFURCATION_SELECT;
2449 DRM_DEBUG_KMS("disabling fdi C rx\n");
2450 I915_WRITE(SOUTH_CHICKEN1, temp);
2451 }
2452}
2453
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002454/* The FDI link training functions for ILK/Ibexpeak. */
2455static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2456{
2457 struct drm_device *dev = crtc->dev;
2458 struct drm_i915_private *dev_priv = dev->dev_private;
2459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2460 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002461 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002462 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002463
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002464 /* FDI needs bits from pipe & plane first */
2465 assert_pipe_enabled(dev_priv, pipe);
2466 assert_plane_enabled(dev_priv, plane);
2467
Adam Jacksone1a44742010-06-25 15:32:14 -04002468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002470 reg = FDI_RX_IMR(pipe);
2471 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002472 temp &= ~FDI_RX_SYMBOL_LOCK;
2473 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002474 I915_WRITE(reg, temp);
2475 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002476 udelay(150);
2477
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002478 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002481 temp &= ~(7 << 19);
2482 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002483 temp &= ~FDI_LINK_TRAIN_NONE;
2484 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002485 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002486
Chris Wilson5eddb702010-09-11 13:48:45 +01002487 reg = FDI_RX_CTL(pipe);
2488 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002491 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492
2493 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002494 udelay(150);
2495
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002496 /* Ironlake workaround, enable clock pointer after FDI enable*/
Daniel Vetter8f5718a2012-10-31 22:52:28 +01002497 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2498 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2499 FDI_RX_PHASE_SYNC_POINTER_EN);
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002500
Chris Wilson5eddb702010-09-11 13:48:45 +01002501 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002502 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002503 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505
2506 if ((temp & FDI_RX_BIT_LOCK)) {
2507 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002508 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002509 break;
2510 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002511 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002512 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002513 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002514
2515 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002520 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002521
Chris Wilson5eddb702010-09-11 13:48:45 +01002522 reg = FDI_RX_CTL(pipe);
2523 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002526 I915_WRITE(reg, temp);
2527
2528 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002529 udelay(150);
2530
Chris Wilson5eddb702010-09-11 13:48:45 +01002531 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002532 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002533 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539 break;
2540 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002541 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002542 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002543 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002544
2545 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002546
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002547}
2548
Akshay Joshi0206e352011-08-16 15:34:10 -04002549static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002550 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2551 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2552 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2553 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2554};
2555
2556/* The FDI link training functions for SNB/Cougarpoint. */
2557static void gen6_fdi_link_train(struct drm_crtc *crtc)
2558{
2559 struct drm_device *dev = crtc->dev;
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002563 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002564
Adam Jacksone1a44742010-06-25 15:32:14 -04002565 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2566 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002567 reg = FDI_RX_IMR(pipe);
2568 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002569 temp &= ~FDI_RX_SYMBOL_LOCK;
2570 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002571 I915_WRITE(reg, temp);
2572
2573 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002574 udelay(150);
2575
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002576 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002577 reg = FDI_TX_CTL(pipe);
2578 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002579 temp &= ~(7 << 19);
2580 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002581 temp &= ~FDI_LINK_TRAIN_NONE;
2582 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2584 /* SNB-B */
2585 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002586 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002587
Daniel Vetterd74cf322012-10-26 10:58:13 +02002588 I915_WRITE(FDI_RX_MISC(pipe),
2589 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2590
Chris Wilson5eddb702010-09-11 13:48:45 +01002591 reg = FDI_RX_CTL(pipe);
2592 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002593 if (HAS_PCH_CPT(dev)) {
2594 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2595 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2596 } else {
2597 temp &= ~FDI_LINK_TRAIN_NONE;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1;
2599 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002600 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2601
2602 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002603 udelay(150);
2604
Akshay Joshi0206e352011-08-16 15:34:10 -04002605 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002606 reg = FDI_TX_CTL(pipe);
2607 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002608 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2609 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002613 udelay(500);
2614
Sean Paulfa37d392012-03-02 12:53:39 -05002615 for (retry = 0; retry < 5; retry++) {
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619 if (temp & FDI_RX_BIT_LOCK) {
2620 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2621 DRM_DEBUG_KMS("FDI train 1 done.\n");
2622 break;
2623 }
2624 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002625 }
Sean Paulfa37d392012-03-02 12:53:39 -05002626 if (retry < 5)
2627 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002628 }
2629 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002630 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002631
2632 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002633 reg = FDI_TX_CTL(pipe);
2634 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002635 temp &= ~FDI_LINK_TRAIN_NONE;
2636 temp |= FDI_LINK_TRAIN_PATTERN_2;
2637 if (IS_GEN6(dev)) {
2638 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639 /* SNB-B */
2640 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002642 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002643
Chris Wilson5eddb702010-09-11 13:48:45 +01002644 reg = FDI_RX_CTL(pipe);
2645 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002646 if (HAS_PCH_CPT(dev)) {
2647 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2649 } else {
2650 temp &= ~FDI_LINK_TRAIN_NONE;
2651 temp |= FDI_LINK_TRAIN_PATTERN_2;
2652 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002656 udelay(150);
2657
Akshay Joshi0206e352011-08-16 15:34:10 -04002658 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002659 reg = FDI_TX_CTL(pipe);
2660 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002663 I915_WRITE(reg, temp);
2664
2665 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002666 udelay(500);
2667
Sean Paulfa37d392012-03-02 12:53:39 -05002668 for (retry = 0; retry < 5; retry++) {
2669 reg = FDI_RX_IIR(pipe);
2670 temp = I915_READ(reg);
2671 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2672 if (temp & FDI_RX_SYMBOL_LOCK) {
2673 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2674 DRM_DEBUG_KMS("FDI train 2 done.\n");
2675 break;
2676 }
2677 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002678 }
Sean Paulfa37d392012-03-02 12:53:39 -05002679 if (retry < 5)
2680 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002681 }
2682 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002683 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002684
2685 DRM_DEBUG_KMS("FDI train done.\n");
2686}
2687
Jesse Barnes357555c2011-04-28 15:09:55 -07002688/* Manual link training for Ivy Bridge A0 parts */
2689static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2690{
2691 struct drm_device *dev = crtc->dev;
2692 struct drm_i915_private *dev_priv = dev->dev_private;
2693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694 int pipe = intel_crtc->pipe;
2695 u32 reg, temp, i;
2696
2697 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2698 for train result */
2699 reg = FDI_RX_IMR(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_RX_SYMBOL_LOCK;
2702 temp &= ~FDI_RX_BIT_LOCK;
2703 I915_WRITE(reg, temp);
2704
2705 POSTING_READ(reg);
2706 udelay(150);
2707
Daniel Vetter01a415f2012-10-27 15:58:40 +02002708 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2709 I915_READ(FDI_RX_IIR(pipe)));
2710
Jesse Barnes357555c2011-04-28 15:09:55 -07002711 /* enable CPU FDI TX and PCH FDI RX */
2712 reg = FDI_TX_CTL(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~(7 << 19);
2715 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2716 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2717 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2718 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002720 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002721 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2722
Daniel Vetterd74cf322012-10-26 10:58:13 +02002723 I915_WRITE(FDI_RX_MISC(pipe),
2724 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2725
Jesse Barnes357555c2011-04-28 15:09:55 -07002726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~FDI_LINK_TRAIN_AUTO;
2729 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002731 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002732 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2733
2734 POSTING_READ(reg);
2735 udelay(150);
2736
Akshay Joshi0206e352011-08-16 15:34:10 -04002737 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741 temp |= snb_b_fdi_train_param[i];
2742 I915_WRITE(reg, temp);
2743
2744 POSTING_READ(reg);
2745 udelay(500);
2746
2747 reg = FDI_RX_IIR(pipe);
2748 temp = I915_READ(reg);
2749 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2750
2751 if (temp & FDI_RX_BIT_LOCK ||
2752 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2753 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Daniel Vetter01a415f2012-10-27 15:58:40 +02002754 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
Jesse Barnes357555c2011-04-28 15:09:55 -07002755 break;
2756 }
2757 }
2758 if (i == 4)
2759 DRM_ERROR("FDI train 1 fail!\n");
2760
2761 /* Train 2 */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2765 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2766 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2773 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2774 I915_WRITE(reg, temp);
2775
2776 POSTING_READ(reg);
2777 udelay(150);
2778
Akshay Joshi0206e352011-08-16 15:34:10 -04002779 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002780 reg = FDI_TX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783 temp |= snb_b_fdi_train_param[i];
2784 I915_WRITE(reg, temp);
2785
2786 POSTING_READ(reg);
2787 udelay(500);
2788
2789 reg = FDI_RX_IIR(pipe);
2790 temp = I915_READ(reg);
2791 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2792
2793 if (temp & FDI_RX_SYMBOL_LOCK) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Daniel Vetter01a415f2012-10-27 15:58:40 +02002795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
Jesse Barnes357555c2011-04-28 15:09:55 -07002796 break;
2797 }
2798 }
2799 if (i == 4)
2800 DRM_ERROR("FDI train 2 fail!\n");
2801
2802 DRM_DEBUG_KMS("FDI train done.\n");
2803}
2804
Daniel Vetter88cefb62012-08-12 19:27:14 +02002805static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002806{
Daniel Vetter88cefb62012-08-12 19:27:14 +02002807 struct drm_device *dev = intel_crtc->base.dev;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002808 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002809 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002810 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002811
Jesse Barnesc64e3112010-09-10 11:27:03 -07002812
Jesse Barnes0e23b992010-09-10 11:10:00 -07002813 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002817 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002818 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002822 udelay(200);
2823
2824 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002829 udelay(200);
2830
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03002831 /* On Haswell, the PLL configuration for ports and pipes is handled
2832 * separately, as part of DDI setup */
2833 if (!IS_HASWELL(dev)) {
2834 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835 reg = FDI_TX_CTL(pipe);
2836 temp = I915_READ(reg);
2837 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002839
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03002840 POSTING_READ(reg);
2841 udelay(100);
2842 }
Jesse Barnes0e23b992010-09-10 11:10:00 -07002843 }
2844}
2845
Daniel Vetter88cefb62012-08-12 19:27:14 +02002846static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847{
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp;
2852
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870 /* Wait for the clocks to turn off. */
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002875static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp;
2882
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887 POSTING_READ(reg);
2888
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
2892 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895 POSTING_READ(reg);
2896 udelay(100);
2897
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002901 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002902
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915 } else {
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 }
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
2921 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2922 I915_WRITE(reg, temp);
2923
2924 POSTING_READ(reg);
2925 udelay(100);
2926}
2927
Chris Wilson5bb61642012-09-27 21:25:58 +01002928static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929{
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 unsigned long flags;
2933 bool pending;
2934
2935 if (atomic_read(&dev_priv->mm.wedged))
2936 return false;
2937
2938 spin_lock_irqsave(&dev->event_lock, flags);
2939 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2940 spin_unlock_irqrestore(&dev->event_lock, flags);
2941
2942 return pending;
2943}
2944
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002945static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2946{
Chris Wilson0f911282012-04-17 10:05:38 +01002947 struct drm_device *dev = crtc->dev;
Chris Wilson5bb61642012-09-27 21:25:58 +01002948 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002949
2950 if (crtc->fb == NULL)
2951 return;
2952
Chris Wilson5bb61642012-09-27 21:25:58 +01002953 wait_event(dev_priv->pending_flip_queue,
2954 !intel_crtc_has_pending_flip(crtc));
2955
Chris Wilson0f911282012-04-17 10:05:38 +01002956 mutex_lock(&dev->struct_mutex);
2957 intel_finish_fb(crtc->fb);
2958 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002959}
2960
Paulo Zanonifc316cb2012-10-25 10:37:43 -02002961static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
Jesse Barnes040484a2011-01-03 12:14:26 -08002962{
2963 struct drm_device *dev = crtc->dev;
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002964 struct intel_encoder *intel_encoder;
Jesse Barnes040484a2011-01-03 12:14:26 -08002965
2966 /*
2967 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2968 * must be driven by its own crtc; no sharing is possible.
2969 */
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002970 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002971 switch (intel_encoder->type) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002972 case INTEL_OUTPUT_EDP:
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002973 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
Jesse Barnes040484a2011-01-03 12:14:26 -08002974 return false;
2975 continue;
2976 }
2977 }
2978
2979 return true;
2980}
2981
Paulo Zanonifc316cb2012-10-25 10:37:43 -02002982static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2983{
2984 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2985}
2986
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002987/* Program iCLKIP clock to the desired frequency */
2988static void lpt_program_iclkip(struct drm_crtc *crtc)
2989{
2990 struct drm_device *dev = crtc->dev;
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2993 u32 temp;
2994
2995 /* It is necessary to ungate the pixclk gate prior to programming
2996 * the divisors, and gate it back when it is done.
2997 */
2998 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2999
3000 /* Disable SSCCTL */
3001 intel_sbi_write(dev_priv, SBI_SSCCTL6,
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003002 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3003 SBI_SSCCTL_DISABLE,
3004 SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003005
3006 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007 if (crtc->mode.clock == 20000) {
3008 auxdiv = 1;
3009 divsel = 0x41;
3010 phaseinc = 0x20;
3011 } else {
3012 /* The iCLK virtual clock root frequency is in MHz,
3013 * but the crtc->mode.clock in in KHz. To get the divisors,
3014 * it is necessary to divide one by another, so we
3015 * convert the virtual clock precision to KHz here for higher
3016 * precision.
3017 */
3018 u32 iclk_virtual_root_freq = 172800 * 1000;
3019 u32 iclk_pi_range = 64;
3020 u32 desired_divisor, msb_divisor_value, pi_value;
3021
3022 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3023 msb_divisor_value = desired_divisor / iclk_pi_range;
3024 pi_value = desired_divisor % iclk_pi_range;
3025
3026 auxdiv = 0;
3027 divsel = msb_divisor_value - 2;
3028 phaseinc = pi_value;
3029 }
3030
3031 /* This should not happen with any sane values */
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3036
3037 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3038 crtc->mode.clock,
3039 auxdiv,
3040 divsel,
3041 phasedir,
3042 phaseinc);
3043
3044 /* Program SSCDIVINTPHASE6 */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003045 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003046 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003052 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003053
3054 /* Program SSCAUXDIV */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003055 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003056 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003058 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003059
3060 /* Enable modulator and associated divider */
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003061 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003062 temp &= ~SBI_SSCCTL_DISABLE;
Paulo Zanoni988d6ee2012-12-01 12:04:24 -02003063 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
Eugeni Dodonove615efe2012-05-09 15:37:26 -03003064
3065 /* Wait for initialization time */
3066 udelay(24);
3067
3068 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3069}
3070
Jesse Barnesf67a5592011-01-05 10:31:48 -08003071/*
3072 * Enable PCH resources required for PCH ports:
3073 * - PCH PLLs
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3077 * - transcoder
3078 */
3079static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003080{
3081 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003085 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003086
Chris Wilsone7e164d2012-05-11 09:21:25 +01003087 assert_transcoder_disabled(dev_priv, pipe);
3088
Daniel Vettercd986ab2012-10-26 10:58:12 +02003089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003094 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07003095 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003096
Daniel Vetter572deb32012-10-27 18:46:14 +02003097 /* XXX: pch pll's can be enabled any time before we enable the PCH
3098 * transcoder, and we actually should do this to not upset any PCH
3099 * transcoder that already use the clock when we share it.
3100 *
3101 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102 * unconditionally resets the pll - we need that to have the right LVDS
3103 * enable sequence. */
Paulo Zanonib6b4e182012-10-31 18:12:38 -02003104 ironlake_enable_pch_pll(intel_crtc);
Chris Wilson6f13b7b2012-05-13 09:54:09 +01003105
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003106 if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003107 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07003108
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003109 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003110 switch (pipe) {
3111 default:
3112 case 0:
3113 temp |= TRANSA_DPLL_ENABLE;
3114 sel = TRANSA_DPLLB_SEL;
3115 break;
3116 case 1:
3117 temp |= TRANSB_DPLL_ENABLE;
3118 sel = TRANSB_DPLLB_SEL;
3119 break;
3120 case 2:
3121 temp |= TRANSC_DPLL_ENABLE;
3122 sel = TRANSC_DPLLB_SEL;
3123 break;
Jesse Barnesd64311a2011-10-12 15:01:33 -07003124 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003125 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3126 temp |= sel;
3127 else
3128 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003129 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003130 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003131
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003132 /* set transcoder timing, panel must allow it */
3133 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01003134 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3137
3138 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003141 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003142
Paulo Zanoni303b81e2012-10-31 18:12:23 -02003143 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003144
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003145 /* For PCH DP, enable TRANS_DP_CTL */
3146 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003147 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003149 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003150 reg = TRANS_DP_CTL(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003153 TRANS_DP_SYNC_MASK |
3154 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003155 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003157 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003158
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003163
3164 switch (intel_trans_dp_port_sel(crtc)) {
3165 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003166 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003167 break;
3168 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003169 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003170 break;
3171 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003172 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003173 break;
3174 default:
Daniel Vettere95d41e2012-10-26 10:58:16 +02003175 BUG();
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003176 }
3177
Chris Wilson5eddb702010-09-11 13:48:45 +01003178 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003179 }
3180
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003181 ironlake_enable_pch_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003182}
3183
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003184static void lpt_pch_enable(struct drm_crtc *crtc)
3185{
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanonidaed2db2012-10-31 18:12:41 -02003189 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003190
Paulo Zanonidaed2db2012-10-31 18:12:41 -02003191 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003192
Paulo Zanoni8c52b5e2012-10-31 18:12:24 -02003193 lpt_program_iclkip(crtc);
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003194
Paulo Zanoni0540e482012-10-31 18:12:40 -02003195 /* Set transcoder timing. */
Paulo Zanonidaed2db2012-10-31 18:12:41 -02003196 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003199
Paulo Zanonidaed2db2012-10-31 18:12:41 -02003200 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003204
Paulo Zanoni937bb612012-10-31 18:12:47 -02003205 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003206}
3207
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003208static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3209{
3210 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3211
3212 if (pll == NULL)
3213 return;
3214
3215 if (pll->refcount == 0) {
3216 WARN(1, "bad PCH PLL refcount\n");
3217 return;
3218 }
3219
3220 --pll->refcount;
3221 intel_crtc->pch_pll = NULL;
3222}
3223
3224static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3225{
3226 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227 struct intel_pch_pll *pll;
3228 int i;
3229
3230 pll = intel_crtc->pch_pll;
3231 if (pll) {
3232 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233 intel_crtc->base.base.id, pll->pll_reg);
3234 goto prepare;
3235 }
3236
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003237 if (HAS_PCH_IBX(dev_priv->dev)) {
3238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239 i = intel_crtc->pipe;
3240 pll = &dev_priv->pch_plls[i];
3241
3242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243 intel_crtc->base.base.id, pll->pll_reg);
3244
3245 goto found;
3246 }
3247
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3250
3251 /* Only want to check enabled timings first */
3252 if (pll->refcount == 0)
3253 continue;
3254
3255 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256 fp == I915_READ(pll->fp0_reg)) {
3257 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258 intel_crtc->base.base.id,
3259 pll->pll_reg, pll->refcount, pll->active);
3260
3261 goto found;
3262 }
3263 }
3264
3265 /* Ok no matching timings, maybe there's a free one? */
3266 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267 pll = &dev_priv->pch_plls[i];
3268 if (pll->refcount == 0) {
3269 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270 intel_crtc->base.base.id, pll->pll_reg);
3271 goto found;
3272 }
3273 }
3274
3275 return NULL;
3276
3277found:
3278 intel_crtc->pch_pll = pll;
3279 pll->refcount++;
3280 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281prepare: /* separate function? */
3282 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003283
Chris Wilsone04c7352012-05-02 20:43:56 +01003284 /* Wait for the clocks to stabilize before rewriting the regs */
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003286 POSTING_READ(pll->pll_reg);
3287 udelay(150);
Chris Wilsone04c7352012-05-02 20:43:56 +01003288
3289 I915_WRITE(pll->fp0_reg, fp);
3290 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003291 pll->on = false;
3292 return pll;
3293}
3294
Jesse Barnesd4270e52011-10-11 10:43:02 -07003295void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3296{
3297 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter23670b322012-11-01 09:15:30 +01003298 int dslreg = PIPEDSL(pipe);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003299 u32 temp;
3300
3301 temp = I915_READ(dslreg);
3302 udelay(500);
3303 if (wait_for(I915_READ(dslreg) != temp, 5)) {
Jesse Barnesd4270e52011-10-11 10:43:02 -07003304 if (wait_for(I915_READ(dslreg) != temp, 5))
3305 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3306 }
3307}
3308
Jesse Barnesf67a5592011-01-05 10:31:48 -08003309static void ironlake_crtc_enable(struct drm_crtc *crtc)
3310{
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003314 struct intel_encoder *encoder;
Jesse Barnesf67a5592011-01-05 10:31:48 -08003315 int pipe = intel_crtc->pipe;
3316 int plane = intel_crtc->plane;
3317 u32 temp;
3318 bool is_pch_port;
3319
Daniel Vetter08a48462012-07-02 11:43:47 +02003320 WARN_ON(!crtc->enabled);
3321
Jesse Barnesf67a5592011-01-05 10:31:48 -08003322 if (intel_crtc->active)
3323 return;
3324
3325 intel_crtc->active = true;
3326 intel_update_watermarks(dev);
3327
3328 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3329 temp = I915_READ(PCH_LVDS);
3330 if ((temp & LVDS_PORT_EN) == 0)
3331 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3332 }
3333
Paulo Zanonifc316cb2012-10-25 10:37:43 -02003334 is_pch_port = ironlake_crtc_driving_pch(crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003335
Daniel Vetter46b6f812012-09-06 22:08:33 +02003336 if (is_pch_port) {
Daniel Vetterfff367c2012-10-27 15:50:28 +02003337 /* Note: FDI PLL enabling _must_ be done before we enable the
3338 * cpu pipes, hence this is separate from all the other fdi/pch
3339 * enabling. */
Daniel Vetter88cefb62012-08-12 19:27:14 +02003340 ironlake_fdi_pll_enable(intel_crtc);
Daniel Vetter46b6f812012-09-06 22:08:33 +02003341 } else {
3342 assert_fdi_tx_disabled(dev_priv, pipe);
3343 assert_fdi_rx_disabled(dev_priv, pipe);
3344 }
Jesse Barnesf67a5592011-01-05 10:31:48 -08003345
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003346 for_each_encoder_on_crtc(dev, crtc, encoder)
3347 if (encoder->pre_enable)
3348 encoder->pre_enable(encoder);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003349
3350 /* Enable panel fitting for LVDS */
3351 if (dev_priv->pch_pf_size &&
Jani Nikula547dc042012-11-02 11:24:03 +02003352 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3353 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Jesse Barnesf67a5592011-01-05 10:31:48 -08003354 /* Force use of hard-coded filter coefficients
3355 * as some pre-programmed values are broken,
3356 * e.g. x201.
3357 */
Paulo Zanoni13888d72012-11-20 13:27:41 -02003358 if (IS_IVYBRIDGE(dev))
3359 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3360 PF_PIPE_SEL_IVB(pipe));
3361 else
3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003363 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3364 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003365 }
3366
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003367 /*
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3369 * clocks enabled
3370 */
3371 intel_crtc_load_lut(crtc);
3372
Jesse Barnesf67a5592011-01-05 10:31:48 -08003373 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3374 intel_enable_plane(dev_priv, plane, pipe);
3375
3376 if (is_pch_port)
3377 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003378
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003379 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003380 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003381 mutex_unlock(&dev->struct_mutex);
3382
Chris Wilson6b383a72010-09-13 13:54:26 +01003383 intel_crtc_update_cursor(crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003384
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003385 for_each_encoder_on_crtc(dev, crtc, encoder)
3386 encoder->enable(encoder);
Daniel Vetter61b77dd2012-07-02 00:16:19 +02003387
3388 if (HAS_PCH_CPT(dev))
3389 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
Daniel Vetter6ce94102012-10-04 19:20:03 +02003390
3391 /*
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3397 * happening.
3398 */
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003400}
3401
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003402static void haswell_crtc_enable(struct drm_crtc *crtc)
3403{
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 struct intel_encoder *encoder;
3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003410 bool is_pch_port;
3411
3412 WARN_ON(!crtc->enabled);
3413
3414 if (intel_crtc->active)
3415 return;
3416
3417 intel_crtc->active = true;
3418 intel_update_watermarks(dev);
3419
Paulo Zanonifc316cb2012-10-25 10:37:43 -02003420 is_pch_port = haswell_crtc_driving_pch(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003421
Paulo Zanoni83616632012-10-23 18:29:54 -02003422 if (is_pch_port)
Paulo Zanoni04945642012-11-01 21:00:59 -02003423 dev_priv->display.fdi_link_train(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003424
3425 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 if (encoder->pre_enable)
3427 encoder->pre_enable(encoder);
3428
Paulo Zanoni1f544382012-10-24 11:32:00 -02003429 intel_ddi_enable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003430
Paulo Zanoni1f544382012-10-24 11:32:00 -02003431 /* Enable panel fitting for eDP */
Jani Nikula547dc042012-11-02 11:24:03 +02003432 if (dev_priv->pch_pf_size &&
3433 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003434 /* Force use of hard-coded filter coefficients
3435 * as some pre-programmed values are broken,
3436 * e.g. x201.
3437 */
Paulo Zanoni54075a72012-11-20 13:27:42 -02003438 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3439 PF_PIPE_SEL_IVB(pipe));
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003440 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3441 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3442 }
3443
3444 /*
3445 * On ILK+ LUT must be loaded before the pipe is running but with
3446 * clocks enabled
3447 */
3448 intel_crtc_load_lut(crtc);
3449
Paulo Zanoni1f544382012-10-24 11:32:00 -02003450 intel_ddi_set_pipe_settings(crtc);
3451 intel_ddi_enable_pipe_func(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003452
3453 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3454 intel_enable_plane(dev_priv, plane, pipe);
3455
3456 if (is_pch_port)
Paulo Zanoni1507e5b2012-10-31 18:12:22 -02003457 lpt_pch_enable(crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003458
3459 mutex_lock(&dev->struct_mutex);
3460 intel_update_fbc(dev);
3461 mutex_unlock(&dev->struct_mutex);
3462
3463 intel_crtc_update_cursor(crtc, true);
3464
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 encoder->enable(encoder);
3467
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003468 /*
3469 * There seems to be a race in PCH platform hw (at least on some
3470 * outputs) where an enabled pipe still completes any pageflip right
3471 * away (as if the pipe is off) instead of waiting for vblank. As soon
3472 * as the first vblank happend, everything works as expected. Hence just
3473 * wait for one vblank before returning to avoid strange things
3474 * happening.
3475 */
3476 intel_wait_for_vblank(dev, intel_crtc->pipe);
3477}
3478
Jesse Barnes6be4a602010-09-10 10:26:01 -07003479static void ironlake_crtc_disable(struct drm_crtc *crtc)
3480{
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003484 struct intel_encoder *encoder;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003485 int pipe = intel_crtc->pipe;
3486 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003487 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003488
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003489
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003490 if (!intel_crtc->active)
3491 return;
3492
Daniel Vetterea9d7582012-07-10 10:42:52 +02003493 for_each_encoder_on_crtc(dev, crtc, encoder)
3494 encoder->disable(encoder);
3495
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003496 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003497 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01003498 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01003499
Jesse Barnesb24e7172011-01-04 15:09:30 -08003500 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003501
Chris Wilson973d04f2011-07-08 12:22:37 +01003502 if (dev_priv->cfb_plane == plane)
3503 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003504
Jesse Barnesb24e7172011-01-04 15:09:30 -08003505 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003506
Jesse Barnes6be4a602010-09-10 10:26:01 -07003507 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003508 I915_WRITE(PF_CTL(pipe), 0);
3509 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003510
Daniel Vetterbf49ec82012-09-06 22:15:40 +02003511 for_each_encoder_on_crtc(dev, crtc, encoder)
3512 if (encoder->post_disable)
3513 encoder->post_disable(encoder);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003514
Chris Wilson5eddb702010-09-11 13:48:45 +01003515 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003516
Paulo Zanonib8a4f402012-10-31 18:12:42 -02003517 ironlake_disable_pch_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003518
3519 if (HAS_PCH_CPT(dev)) {
3520 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003521 reg = TRANS_DP_CTL(pipe);
3522 temp = I915_READ(reg);
3523 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08003524 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01003525 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003526
3527 /* disable DPLL_SEL */
3528 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003529 switch (pipe) {
3530 case 0:
Jesse Barnesd64311a2011-10-12 15:01:33 -07003531 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003532 break;
3533 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07003534 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003535 break;
3536 case 2:
Jesse Barnes4b645f12011-10-12 09:51:31 -07003537 /* C shares PLL A or B */
Jesse Barnesd64311a2011-10-12 15:01:33 -07003538 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003539 break;
3540 default:
3541 BUG(); /* wtf */
3542 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07003543 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003544 }
3545
3546 /* disable PCH DPLL */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003547 intel_disable_pch_pll(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003548
Daniel Vetter88cefb62012-08-12 19:27:14 +02003549 ironlake_fdi_pll_disable(intel_crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +01003550
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003551 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003552 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003553
3554 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003555 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003556 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003557}
3558
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003559static void haswell_crtc_disable(struct drm_crtc *crtc)
3560{
3561 struct drm_device *dev = crtc->dev;
3562 struct drm_i915_private *dev_priv = dev->dev_private;
3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564 struct intel_encoder *encoder;
3565 int pipe = intel_crtc->pipe;
3566 int plane = intel_crtc->plane;
Paulo Zanoniad80a812012-10-24 16:06:19 -02003567 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanoni83616632012-10-23 18:29:54 -02003568 bool is_pch_port;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003569
3570 if (!intel_crtc->active)
3571 return;
3572
Paulo Zanoni83616632012-10-23 18:29:54 -02003573 is_pch_port = haswell_crtc_driving_pch(crtc);
3574
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003575 for_each_encoder_on_crtc(dev, crtc, encoder)
3576 encoder->disable(encoder);
3577
3578 intel_crtc_wait_for_pending_flips(crtc);
3579 drm_vblank_off(dev, pipe);
3580 intel_crtc_update_cursor(crtc, false);
3581
3582 intel_disable_plane(dev_priv, plane, pipe);
3583
3584 if (dev_priv->cfb_plane == plane)
3585 intel_disable_fbc(dev);
3586
3587 intel_disable_pipe(dev_priv, pipe);
3588
Paulo Zanoniad80a812012-10-24 16:06:19 -02003589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003590
3591 /* Disable PF */
3592 I915_WRITE(PF_CTL(pipe), 0);
3593 I915_WRITE(PF_WIN_SZ(pipe), 0);
3594
Paulo Zanoni1f544382012-10-24 11:32:00 -02003595 intel_ddi_disable_pipe_clock(intel_crtc);
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003596
3597 for_each_encoder_on_crtc(dev, crtc, encoder)
3598 if (encoder->post_disable)
3599 encoder->post_disable(encoder);
3600
Paulo Zanoni83616632012-10-23 18:29:54 -02003601 if (is_pch_port) {
Paulo Zanoniab4d9662012-10-31 18:12:55 -02003602 lpt_disable_pch_transcoder(dev_priv);
Paulo Zanoni1ad960f2012-11-01 21:05:05 -02003603 intel_ddi_fdi_disable(crtc);
Paulo Zanoni83616632012-10-23 18:29:54 -02003604 }
Paulo Zanoni4f771f12012-10-23 18:29:51 -02003605
3606 intel_crtc->active = false;
3607 intel_update_watermarks(dev);
3608
3609 mutex_lock(&dev->struct_mutex);
3610 intel_update_fbc(dev);
3611 mutex_unlock(&dev->struct_mutex);
3612}
3613
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003614static void ironlake_crtc_off(struct drm_crtc *crtc)
3615{
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 intel_put_pch_pll(intel_crtc);
3618}
3619
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003620static void haswell_crtc_off(struct drm_crtc *crtc)
3621{
Paulo Zanonia5c961d2012-10-24 15:59:34 -02003622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623
3624 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3625 * start using it. */
3626 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3627
Paulo Zanoni6441ab52012-10-05 12:05:58 -03003628 intel_ddi_put_crtc_pll(crtc);
3629}
3630
Daniel Vetter02e792f2009-09-15 22:57:34 +02003631static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3632{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003633 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003634 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003635 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003636
Chris Wilson23f09ce2010-08-12 13:53:37 +01003637 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003638 dev_priv->mm.interruptible = false;
3639 (void) intel_overlay_switch_off(intel_crtc->overlay);
3640 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003641 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003642 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003643
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003644 /* Let userspace switch the overlay on again. In most cases userspace
3645 * has to recompute where to put it anyway.
3646 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003647}
3648
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003649static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003650{
3651 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003654 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08003655 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003656 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003657
Daniel Vetter08a48462012-07-02 11:43:47 +02003658 WARN_ON(!crtc->enabled);
3659
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003660 if (intel_crtc->active)
3661 return;
3662
3663 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003664 intel_update_watermarks(dev);
3665
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003666 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08003667 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003668 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003669
3670 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003671 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003672
3673 /* Give the overlay scaler a chance to enable if it's on this pipe */
3674 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01003675 intel_crtc_update_cursor(crtc, true);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003676
Daniel Vetterfa5c73b2012-07-01 23:24:36 +02003677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 encoder->enable(encoder);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003679}
3680
3681static void i9xx_crtc_disable(struct drm_crtc *crtc)
3682{
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003686 struct intel_encoder *encoder;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003687 int pipe = intel_crtc->pipe;
3688 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003689
Daniel Vetteref9c3ae2012-06-29 22:40:09 +02003690
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003691 if (!intel_crtc->active)
3692 return;
3693
Daniel Vetterea9d7582012-07-10 10:42:52 +02003694 for_each_encoder_on_crtc(dev, crtc, encoder)
3695 encoder->disable(encoder);
3696
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003697 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003698 intel_crtc_wait_for_pending_flips(crtc);
3699 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003700 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01003701 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003702
Chris Wilson973d04f2011-07-08 12:22:37 +01003703 if (dev_priv->cfb_plane == plane)
3704 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003705
Jesse Barnesb24e7172011-01-04 15:09:30 -08003706 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003707 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003708 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003709
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003710 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003711 intel_update_fbc(dev);
3712 intel_update_watermarks(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003713}
3714
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003715static void i9xx_crtc_off(struct drm_crtc *crtc)
3716{
3717}
3718
Daniel Vetter976f8a22012-07-08 22:34:21 +02003719static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3720 bool enabled)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003721{
3722 struct drm_device *dev = crtc->dev;
3723 struct drm_i915_master_private *master_priv;
3724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3725 int pipe = intel_crtc->pipe;
Jesse Barnes79e53942008-11-07 14:24:08 -08003726
3727 if (!dev->primary->master)
3728 return;
3729
3730 master_priv = dev->primary->master->driver_priv;
3731 if (!master_priv->sarea_priv)
3732 return;
3733
Jesse Barnes79e53942008-11-07 14:24:08 -08003734 switch (pipe) {
3735 case 0:
3736 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3737 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3738 break;
3739 case 1:
3740 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3741 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3742 break;
3743 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003744 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003745 break;
3746 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003747}
3748
Daniel Vetter976f8a22012-07-08 22:34:21 +02003749/**
3750 * Sets the power management mode of the pipe and plane.
3751 */
3752void intel_crtc_update_dpms(struct drm_crtc *crtc)
Chris Wilsoncdd59982010-09-08 16:30:16 +01003753{
Chris Wilsoncdd59982010-09-08 16:30:16 +01003754 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003755 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter976f8a22012-07-08 22:34:21 +02003756 struct intel_encoder *intel_encoder;
3757 bool enable = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003758
Daniel Vetter976f8a22012-07-08 22:34:21 +02003759 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3760 enable |= intel_encoder->connectors_active;
3761
3762 if (enable)
3763 dev_priv->display.crtc_enable(crtc);
3764 else
3765 dev_priv->display.crtc_disable(crtc);
3766
3767 intel_crtc_update_sarea(crtc, enable);
3768}
3769
3770static void intel_crtc_noop(struct drm_crtc *crtc)
3771{
3772}
3773
3774static void intel_crtc_disable(struct drm_crtc *crtc)
3775{
3776 struct drm_device *dev = crtc->dev;
3777 struct drm_connector *connector;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779
3780 /* crtc should still be enabled when we disable it. */
3781 WARN_ON(!crtc->enabled);
3782
3783 dev_priv->display.crtc_disable(crtc);
3784 intel_crtc_update_sarea(crtc, false);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003785 dev_priv->display.off(crtc);
3786
Chris Wilson931872f2012-01-16 23:01:13 +00003787 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3788 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003789
3790 if (crtc->fb) {
3791 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003792 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003793 mutex_unlock(&dev->struct_mutex);
Daniel Vetter976f8a22012-07-08 22:34:21 +02003794 crtc->fb = NULL;
3795 }
3796
3797 /* Update computed state. */
3798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3799 if (!connector->encoder || !connector->encoder->crtc)
3800 continue;
3801
3802 if (connector->encoder->crtc != crtc)
3803 continue;
3804
3805 connector->dpms = DRM_MODE_DPMS_OFF;
3806 to_intel_encoder(connector->encoder)->connectors_active = false;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003807 }
3808}
3809
Daniel Vettera261b242012-07-26 19:21:47 +02003810void intel_modeset_disable(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003811{
Daniel Vettera261b242012-07-26 19:21:47 +02003812 struct drm_crtc *crtc;
3813
3814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3815 if (crtc->enabled)
3816 intel_crtc_disable(crtc);
3817 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003818}
3819
Daniel Vetter1f703852012-07-11 16:51:39 +02003820void intel_encoder_noop(struct drm_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08003821{
Jesse Barnes79e53942008-11-07 14:24:08 -08003822}
3823
Chris Wilsonea5b2132010-08-04 13:50:23 +01003824void intel_encoder_destroy(struct drm_encoder *encoder)
3825{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003826 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003827
Chris Wilsonea5b2132010-08-04 13:50:23 +01003828 drm_encoder_cleanup(encoder);
3829 kfree(intel_encoder);
3830}
3831
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003832/* Simple dpms helper for encodres with just one connector, no cloning and only
3833 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3834 * state of the entire output pipe. */
3835void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3836{
3837 if (mode == DRM_MODE_DPMS_ON) {
3838 encoder->connectors_active = true;
3839
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003840 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003841 } else {
3842 encoder->connectors_active = false;
3843
Daniel Vetterb2cabb02012-07-01 22:42:24 +02003844 intel_crtc_update_dpms(encoder->base.crtc);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003845 }
3846}
3847
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003848/* Cross check the actual hw state with our own modeset state tracking (and it's
3849 * internal consistency). */
Daniel Vetterb9805142012-08-31 17:37:33 +02003850static void intel_connector_check_state(struct intel_connector *connector)
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003851{
3852 if (connector->get_hw_state(connector)) {
3853 struct intel_encoder *encoder = connector->encoder;
3854 struct drm_crtc *crtc;
3855 bool encoder_enabled;
3856 enum pipe pipe;
3857
3858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3859 connector->base.base.id,
3860 drm_get_connector_name(&connector->base));
3861
3862 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3863 "wrong connector dpms state\n");
3864 WARN(connector->base.encoder != &encoder->base,
3865 "active connector not linked to encoder\n");
3866 WARN(!encoder->connectors_active,
3867 "encoder->connectors_active not set\n");
3868
3869 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3870 WARN(!encoder_enabled, "encoder not enabled\n");
3871 if (WARN_ON(!encoder->base.crtc))
3872 return;
3873
3874 crtc = encoder->base.crtc;
3875
3876 WARN(!crtc->enabled, "crtc not enabled\n");
3877 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3878 WARN(pipe != to_intel_crtc(crtc)->pipe,
3879 "encoder active on the wrong pipe\n");
3880 }
3881}
3882
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003883/* Even simpler default implementation, if there's really no special case to
3884 * consider. */
3885void intel_connector_dpms(struct drm_connector *connector, int mode)
3886{
3887 struct intel_encoder *encoder = intel_attached_encoder(connector);
3888
3889 /* All the simple cases only support two dpms states. */
3890 if (mode != DRM_MODE_DPMS_ON)
3891 mode = DRM_MODE_DPMS_OFF;
3892
3893 if (mode == connector->dpms)
3894 return;
3895
3896 connector->dpms = mode;
3897
3898 /* Only need to change hw state when actually enabled */
3899 if (encoder->base.crtc)
3900 intel_encoder_dpms(encoder, mode);
3901 else
Daniel Vetter8af6cf82012-07-10 09:50:11 +02003902 WARN_ON(encoder->connectors_active != false);
Daniel Vetter0a91ca22012-07-02 21:54:27 +02003903
Daniel Vetterb9805142012-08-31 17:37:33 +02003904 intel_modeset_check_state(connector->dev);
Daniel Vetter5ab432e2012-06-30 08:59:56 +02003905}
3906
Daniel Vetterf0947c32012-07-02 13:10:34 +02003907/* Simple connector->get_hw_state implementation for encoders that support only
3908 * one connector and no cloning and hence the encoder state determines the state
3909 * of the connector. */
3910bool intel_connector_get_hw_state(struct intel_connector *connector)
3911{
Daniel Vetter24929352012-07-02 20:28:59 +02003912 enum pipe pipe = 0;
Daniel Vetterf0947c32012-07-02 13:10:34 +02003913 struct intel_encoder *encoder = connector->encoder;
3914
3915 return encoder->get_hw_state(encoder, &pipe);
3916}
3917
Jesse Barnes79e53942008-11-07 14:24:08 -08003918static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
Daniel Vetter35313cd2012-07-20 10:30:45 +02003919 const struct drm_display_mode *mode,
Jesse Barnes79e53942008-11-07 14:24:08 -08003920 struct drm_display_mode *adjusted_mode)
3921{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003922 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003923
Eric Anholtbad720f2009-10-22 16:11:14 -07003924 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003925 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003926 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3927 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003928 }
Chris Wilson89749352010-09-12 18:25:19 +01003929
Daniel Vetterf9bef082012-04-15 19:53:19 +02003930 /* All interlaced capable intel hw wants timings in frames. Note though
3931 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3932 * timings, so we need to be careful not to clobber these.*/
3933 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3934 drm_mode_set_crtcinfo(adjusted_mode, 0);
Chris Wilson89749352010-09-12 18:25:19 +01003935
Chris Wilson44f46b422012-06-21 13:19:59 +03003936 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3937 * with a hsync front porch of 0.
3938 */
3939 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3940 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3941 return false;
3942
Jesse Barnes79e53942008-11-07 14:24:08 -08003943 return true;
3944}
3945
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07003946static int valleyview_get_display_clock_speed(struct drm_device *dev)
3947{
3948 return 400000; /* FIXME */
3949}
3950
Jesse Barnese70236a2009-09-21 10:42:27 -07003951static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003952{
Jesse Barnese70236a2009-09-21 10:42:27 -07003953 return 400000;
3954}
Jesse Barnes79e53942008-11-07 14:24:08 -08003955
Jesse Barnese70236a2009-09-21 10:42:27 -07003956static int i915_get_display_clock_speed(struct drm_device *dev)
3957{
3958 return 333000;
3959}
Jesse Barnes79e53942008-11-07 14:24:08 -08003960
Jesse Barnese70236a2009-09-21 10:42:27 -07003961static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3962{
3963 return 200000;
3964}
Jesse Barnes79e53942008-11-07 14:24:08 -08003965
Jesse Barnese70236a2009-09-21 10:42:27 -07003966static int i915gm_get_display_clock_speed(struct drm_device *dev)
3967{
3968 u16 gcfgc = 0;
3969
3970 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3971
3972 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003973 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003974 else {
3975 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3976 case GC_DISPLAY_CLOCK_333_MHZ:
3977 return 333000;
3978 default:
3979 case GC_DISPLAY_CLOCK_190_200_MHZ:
3980 return 190000;
3981 }
3982 }
3983}
Jesse Barnes79e53942008-11-07 14:24:08 -08003984
Jesse Barnese70236a2009-09-21 10:42:27 -07003985static int i865_get_display_clock_speed(struct drm_device *dev)
3986{
3987 return 266000;
3988}
3989
3990static int i855_get_display_clock_speed(struct drm_device *dev)
3991{
3992 u16 hpllcc = 0;
3993 /* Assume that the hardware is in the high speed state. This
3994 * should be the default.
3995 */
3996 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3997 case GC_CLOCK_133_200:
3998 case GC_CLOCK_100_200:
3999 return 200000;
4000 case GC_CLOCK_166_250:
4001 return 250000;
4002 case GC_CLOCK_100_133:
4003 return 133000;
4004 }
4005
4006 /* Shouldn't happen */
4007 return 0;
4008}
4009
4010static int i830_get_display_clock_speed(struct drm_device *dev)
4011{
4012 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08004013}
4014
Zhenyu Wang2c072452009-06-05 15:38:42 +08004015struct fdi_m_n {
4016 u32 tu;
4017 u32 gmch_m;
4018 u32 gmch_n;
4019 u32 link_m;
4020 u32 link_n;
4021};
4022
4023static void
4024fdi_reduce_ratio(u32 *num, u32 *den)
4025{
4026 while (*num > 0xffffff || *den > 0xffffff) {
4027 *num >>= 1;
4028 *den >>= 1;
4029 }
4030}
4031
Zhenyu Wang2c072452009-06-05 15:38:42 +08004032static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05004033ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4034 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08004035{
Zhenyu Wang2c072452009-06-05 15:38:42 +08004036 m_n->tu = 64; /* default size */
4037
Chris Wilson22ed1112010-12-04 01:01:29 +00004038 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4039 m_n->gmch_m = bits_per_pixel * pixel_clock;
4040 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004041 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4042
Chris Wilson22ed1112010-12-04 01:01:29 +00004043 m_n->link_m = pixel_clock;
4044 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004045 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4046}
4047
Chris Wilsona7615032011-01-12 17:04:08 +00004048static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4049{
Keith Packard72bbe582011-09-26 16:09:45 -07004050 if (i915_panel_use_ssc >= 0)
4051 return i915_panel_use_ssc != 0;
4052 return dev_priv->lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07004053 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004054}
4055
Jesse Barnes5a354202011-06-24 12:19:22 -07004056/**
4057 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4058 * @crtc: CRTC structure
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004059 * @mode: requested mode
Jesse Barnes5a354202011-06-24 12:19:22 -07004060 *
4061 * A pipe may be connected to one or more outputs. Based on the depth of the
4062 * attached framebuffer, choose a good color depth to use on the pipe.
4063 *
4064 * If possible, match the pipe depth to the fb depth. In some cases, this
4065 * isn't ideal, because the connected output supports a lesser or restricted
4066 * set of depths. Resolve that here:
4067 * LVDS typically supports only 6bpc, so clamp down in that case
4068 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4069 * Displays may support a restricted set as well, check EDID and clamp as
4070 * appropriate.
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004071 * DP may want to dither down to 6bpc to fit larger modes
Jesse Barnes5a354202011-06-24 12:19:22 -07004072 *
4073 * RETURNS:
4074 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4075 * true if they don't match).
4076 */
4077static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +02004078 struct drm_framebuffer *fb,
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004079 unsigned int *pipe_bpp,
4080 struct drm_display_mode *mode)
Jesse Barnes5a354202011-06-24 12:19:22 -07004081{
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes5a354202011-06-24 12:19:22 -07004084 struct drm_connector *connector;
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004085 struct intel_encoder *intel_encoder;
Jesse Barnes5a354202011-06-24 12:19:22 -07004086 unsigned int display_bpc = UINT_MAX, bpc;
4087
4088 /* Walk the encoders & connectors on this crtc, get min bpc */
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004089 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
Jesse Barnes5a354202011-06-24 12:19:22 -07004090
4091 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4092 unsigned int lvds_bpc;
4093
4094 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4095 LVDS_A3_POWER_UP)
4096 lvds_bpc = 8;
4097 else
4098 lvds_bpc = 6;
4099
4100 if (lvds_bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04004101 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07004102 display_bpc = lvds_bpc;
4103 }
4104 continue;
4105 }
4106
Jesse Barnes5a354202011-06-24 12:19:22 -07004107 /* Not one of the known troublemakers, check the EDID */
4108 list_for_each_entry(connector, &dev->mode_config.connector_list,
4109 head) {
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004110 if (connector->encoder != &intel_encoder->base)
Jesse Barnes5a354202011-06-24 12:19:22 -07004111 continue;
4112
Jesse Barnes62ac41a2011-07-28 12:55:14 -07004113 /* Don't use an invalid EDID bpc value */
4114 if (connector->display_info.bpc &&
4115 connector->display_info.bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04004116 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07004117 display_bpc = connector->display_info.bpc;
4118 }
4119 }
4120
Jani Nikula2f4f6492012-11-12 14:33:44 +02004121 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4122 /* Use VBT settings if we have an eDP panel */
4123 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4124
Jani Nikula9a30a612012-11-12 14:33:45 +02004125 if (edp_bpc && edp_bpc < display_bpc) {
Jani Nikula2f4f6492012-11-12 14:33:44 +02004126 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4127 display_bpc = edp_bpc;
4128 }
4129 continue;
4130 }
4131
Jesse Barnes5a354202011-06-24 12:19:22 -07004132 /*
4133 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4134 * through, clamp it down. (Note: >12bpc will be caught below.)
4135 */
4136 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4137 if (display_bpc > 8 && display_bpc < 12) {
Adam Jackson82820492011-10-10 16:33:34 -04004138 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07004139 display_bpc = 12;
4140 } else {
Adam Jackson82820492011-10-10 16:33:34 -04004141 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07004142 display_bpc = 8;
4143 }
4144 }
4145 }
4146
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004147 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4148 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4149 display_bpc = 6;
4150 }
4151
Jesse Barnes5a354202011-06-24 12:19:22 -07004152 /*
4153 * We could just drive the pipe at the highest bpc all the time and
4154 * enable dithering as needed, but that costs bandwidth. So choose
4155 * the minimum value that expresses the full color range of the fb but
4156 * also stays within the max display bpc discovered above.
4157 */
4158
Daniel Vetter94352cf2012-07-05 22:51:56 +02004159 switch (fb->depth) {
Jesse Barnes5a354202011-06-24 12:19:22 -07004160 case 8:
4161 bpc = 8; /* since we go through a colormap */
4162 break;
4163 case 15:
4164 case 16:
4165 bpc = 6; /* min is 18bpp */
4166 break;
4167 case 24:
Keith Packard578393c2011-09-05 11:53:21 -07004168 bpc = 8;
Jesse Barnes5a354202011-06-24 12:19:22 -07004169 break;
4170 case 30:
Keith Packard578393c2011-09-05 11:53:21 -07004171 bpc = 10;
Jesse Barnes5a354202011-06-24 12:19:22 -07004172 break;
4173 case 48:
Keith Packard578393c2011-09-05 11:53:21 -07004174 bpc = 12;
Jesse Barnes5a354202011-06-24 12:19:22 -07004175 break;
4176 default:
4177 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4178 bpc = min((unsigned int)8, display_bpc);
4179 break;
4180 }
4181
Keith Packard578393c2011-09-05 11:53:21 -07004182 display_bpc = min(display_bpc, bpc);
4183
Adam Jackson82820492011-10-10 16:33:34 -04004184 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4185 bpc, display_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07004186
Keith Packard578393c2011-09-05 11:53:21 -07004187 *pipe_bpp = display_bpc * 3;
Jesse Barnes5a354202011-06-24 12:19:22 -07004188
4189 return display_bpc != bpc;
4190}
4191
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004192static int vlv_get_refclk(struct drm_crtc *crtc)
4193{
4194 struct drm_device *dev = crtc->dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 int refclk = 27000; /* for DP & HDMI */
4197
4198 return 100000; /* only one validated so far */
4199
4200 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4201 refclk = 96000;
4202 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4203 if (intel_panel_use_ssc(dev_priv))
4204 refclk = 100000;
4205 else
4206 refclk = 96000;
4207 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4208 refclk = 100000;
4209 }
4210
4211 return refclk;
4212}
4213
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004214static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4215{
4216 struct drm_device *dev = crtc->dev;
4217 struct drm_i915_private *dev_priv = dev->dev_private;
4218 int refclk;
4219
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004220 if (IS_VALLEYVIEW(dev)) {
4221 refclk = vlv_get_refclk(crtc);
4222 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004223 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4224 refclk = dev_priv->lvds_ssc_freq * 1000;
4225 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4226 refclk / 1000);
4227 } else if (!IS_GEN2(dev)) {
4228 refclk = 96000;
4229 } else {
4230 refclk = 48000;
4231 }
4232
4233 return refclk;
4234}
4235
4236static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4237 intel_clock_t *clock)
4238{
4239 /* SDVO TV has fixed PLL values depend on its clock range,
4240 this mirrors vbios setting. */
4241 if (adjusted_mode->clock >= 100000
4242 && adjusted_mode->clock < 140500) {
4243 clock->p1 = 2;
4244 clock->p2 = 10;
4245 clock->n = 3;
4246 clock->m1 = 16;
4247 clock->m2 = 8;
4248 } else if (adjusted_mode->clock >= 140500
4249 && adjusted_mode->clock <= 200000) {
4250 clock->p1 = 1;
4251 clock->p2 = 10;
4252 clock->n = 6;
4253 clock->m1 = 12;
4254 clock->m2 = 8;
4255 }
4256}
4257
Jesse Barnesa7516a02011-12-15 12:30:37 -08004258static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4259 intel_clock_t *clock,
4260 intel_clock_t *reduced_clock)
4261{
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 int pipe = intel_crtc->pipe;
4266 u32 fp, fp2 = 0;
4267
4268 if (IS_PINEVIEW(dev)) {
4269 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4270 if (reduced_clock)
4271 fp2 = (1 << reduced_clock->n) << 16 |
4272 reduced_clock->m1 << 8 | reduced_clock->m2;
4273 } else {
4274 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4275 if (reduced_clock)
4276 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4277 reduced_clock->m2;
4278 }
4279
4280 I915_WRITE(FP0(pipe), fp);
4281
4282 intel_crtc->lowfreq_avail = false;
4283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4284 reduced_clock && i915_powersave) {
4285 I915_WRITE(FP1(pipe), fp2);
4286 intel_crtc->lowfreq_avail = true;
4287 } else {
4288 I915_WRITE(FP1(pipe), fp);
4289 }
4290}
4291
Daniel Vetter93e537a2012-03-28 23:11:26 +02004292static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4293 struct drm_display_mode *adjusted_mode)
4294{
4295 struct drm_device *dev = crtc->dev;
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4298 int pipe = intel_crtc->pipe;
Chris Wilson284d5df2012-04-14 17:41:59 +01004299 u32 temp;
Daniel Vetter93e537a2012-03-28 23:11:26 +02004300
4301 temp = I915_READ(LVDS);
4302 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4303 if (pipe == 1) {
4304 temp |= LVDS_PIPEB_SELECT;
4305 } else {
4306 temp &= ~LVDS_PIPEB_SELECT;
4307 }
4308 /* set the corresponsding LVDS_BORDER bit */
4309 temp |= dev_priv->lvds_border_bits;
4310 /* Set the B0-B3 data pairs corresponding to whether we're going to
4311 * set the DPLLs for dual-channel mode or not.
4312 */
4313 if (clock->p2 == 7)
4314 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4315 else
4316 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4317
4318 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4319 * appropriately here, but we need to look more thoroughly into how
4320 * panels behave in the two modes.
4321 */
4322 /* set the dithering flag on LVDS as needed */
4323 if (INTEL_INFO(dev)->gen >= 4) {
4324 if (dev_priv->lvds_dither)
4325 temp |= LVDS_ENABLE_DITHER;
4326 else
4327 temp &= ~LVDS_ENABLE_DITHER;
4328 }
Chris Wilson284d5df2012-04-14 17:41:59 +01004329 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
Daniel Vetter93e537a2012-03-28 23:11:26 +02004330 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01004331 temp |= LVDS_HSYNC_POLARITY;
Daniel Vetter93e537a2012-03-28 23:11:26 +02004332 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01004333 temp |= LVDS_VSYNC_POLARITY;
Daniel Vetter93e537a2012-03-28 23:11:26 +02004334 I915_WRITE(LVDS, temp);
4335}
4336
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004337static void vlv_update_pll(struct drm_crtc *crtc,
4338 struct drm_display_mode *mode,
4339 struct drm_display_mode *adjusted_mode,
4340 intel_clock_t *clock, intel_clock_t *reduced_clock,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304341 int num_connectors)
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004342{
4343 struct drm_device *dev = crtc->dev;
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4346 int pipe = intel_crtc->pipe;
4347 u32 dpll, mdiv, pdiv;
4348 u32 bestn, bestm1, bestm2, bestp1, bestp2;
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304349 bool is_sdvo;
4350 u32 temp;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004351
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304352 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4353 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4354
4355 dpll = DPLL_VGA_MODE_DIS;
4356 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4357 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4358 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4359
4360 I915_WRITE(DPLL(pipe), dpll);
4361 POSTING_READ(DPLL(pipe));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004362
4363 bestn = clock->n;
4364 bestm1 = clock->m1;
4365 bestm2 = clock->m2;
4366 bestp1 = clock->p1;
4367 bestp2 = clock->p2;
4368
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304369 /*
4370 * In Valleyview PLL and program lane counter registers are exposed
4371 * through DPIO interface
4372 */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004373 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4374 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4375 mdiv |= ((bestn << DPIO_N_SHIFT));
4376 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4377 mdiv |= (1 << DPIO_K_SHIFT);
4378 mdiv |= DPIO_ENABLE_CALIBRATION;
4379 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4380
4381 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4382
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304383 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004384 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304385 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4386 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004387 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4388
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304389 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004390
4391 dpll |= DPLL_VCO_ENABLE;
4392 I915_WRITE(DPLL(pipe), dpll);
4393 POSTING_READ(DPLL(pipe));
4394 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4395 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4396
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304397 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004398
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4400 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4401
4402 I915_WRITE(DPLL(pipe), dpll);
4403
4404 /* Wait for the clocks to stabilize. */
4405 POSTING_READ(DPLL(pipe));
4406 udelay(150);
4407
4408 temp = 0;
4409 if (is_sdvo) {
4410 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004411 if (temp > 1)
4412 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4413 else
4414 temp = 0;
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004415 }
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304416 I915_WRITE(DPLL_MD(pipe), temp);
4417 POSTING_READ(DPLL_MD(pipe));
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004418
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304419 /* Now program lane control registers */
4420 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4421 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4422 {
4423 temp = 0x1000C4;
4424 if(pipe == 1)
4425 temp |= (1 << 21);
4426 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4427 }
4428 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4429 {
4430 temp = 0x1000C4;
4431 if(pipe == 1)
4432 temp |= (1 << 21);
4433 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4434 }
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004435}
4436
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004437static void i9xx_update_pll(struct drm_crtc *crtc,
4438 struct drm_display_mode *mode,
4439 struct drm_display_mode *adjusted_mode,
4440 intel_clock_t *clock, intel_clock_t *reduced_clock,
4441 int num_connectors)
4442{
4443 struct drm_device *dev = crtc->dev;
4444 struct drm_i915_private *dev_priv = dev->dev_private;
4445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4446 int pipe = intel_crtc->pipe;
4447 u32 dpll;
4448 bool is_sdvo;
4449
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304450 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4451
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004452 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4453 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4454
4455 dpll = DPLL_VGA_MODE_DIS;
4456
4457 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4458 dpll |= DPLLB_MODE_LVDS;
4459 else
4460 dpll |= DPLLB_MODE_DAC_SERIAL;
4461 if (is_sdvo) {
4462 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4463 if (pixel_multiplier > 1) {
4464 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4465 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4466 }
4467 dpll |= DPLL_DVO_HIGH_SPEED;
4468 }
4469 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4470 dpll |= DPLL_DVO_HIGH_SPEED;
4471
4472 /* compute bitmask from p1 value */
4473 if (IS_PINEVIEW(dev))
4474 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4475 else {
4476 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4477 if (IS_G4X(dev) && reduced_clock)
4478 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4479 }
4480 switch (clock->p2) {
4481 case 5:
4482 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4483 break;
4484 case 7:
4485 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4486 break;
4487 case 10:
4488 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4489 break;
4490 case 14:
4491 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4492 break;
4493 }
4494 if (INTEL_INFO(dev)->gen >= 4)
4495 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4496
4497 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4498 dpll |= PLL_REF_INPUT_TVCLKINBC;
4499 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4500 /* XXX: just matching BIOS for now */
4501 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4502 dpll |= 3;
4503 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4504 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4505 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4506 else
4507 dpll |= PLL_REF_INPUT_DREFCLK;
4508
4509 dpll |= DPLL_VCO_ENABLE;
4510 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4511 POSTING_READ(DPLL(pipe));
4512 udelay(150);
4513
4514 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4515 * This is an exception to the general rule that mode_set doesn't turn
4516 * things on.
4517 */
4518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4519 intel_update_lvds(crtc, clock, adjusted_mode);
4520
4521 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4522 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4523
4524 I915_WRITE(DPLL(pipe), dpll);
4525
4526 /* Wait for the clocks to stabilize. */
4527 POSTING_READ(DPLL(pipe));
4528 udelay(150);
4529
4530 if (INTEL_INFO(dev)->gen >= 4) {
4531 u32 temp = 0;
4532 if (is_sdvo) {
4533 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4534 if (temp > 1)
4535 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4536 else
4537 temp = 0;
4538 }
4539 I915_WRITE(DPLL_MD(pipe), temp);
4540 } else {
4541 /* The pixel multiplier can only be updated once the
4542 * DPLL is enabled and the clocks are stable.
4543 *
4544 * So write it again.
4545 */
4546 I915_WRITE(DPLL(pipe), dpll);
4547 }
4548}
4549
4550static void i8xx_update_pll(struct drm_crtc *crtc,
4551 struct drm_display_mode *adjusted_mode,
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304552 intel_clock_t *clock, intel_clock_t *reduced_clock,
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004553 int num_connectors)
4554{
4555 struct drm_device *dev = crtc->dev;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4558 int pipe = intel_crtc->pipe;
4559 u32 dpll;
4560
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304561 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4562
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004563 dpll = DPLL_VGA_MODE_DIS;
4564
4565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4566 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4567 } else {
4568 if (clock->p1 == 2)
4569 dpll |= PLL_P1_DIVIDE_BY_TWO;
4570 else
4571 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4572 if (clock->p2 == 4)
4573 dpll |= PLL_P2_DIVIDE_BY_4;
4574 }
4575
4576 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4577 /* XXX: just matching BIOS for now */
4578 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4579 dpll |= 3;
4580 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4581 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4582 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4583 else
4584 dpll |= PLL_REF_INPUT_DREFCLK;
4585
4586 dpll |= DPLL_VCO_ENABLE;
4587 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4588 POSTING_READ(DPLL(pipe));
4589 udelay(150);
4590
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004591 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4592 * This is an exception to the general rule that mode_set doesn't turn
4593 * things on.
4594 */
4595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4596 intel_update_lvds(crtc, clock, adjusted_mode);
4597
Daniel Vetter5b5896e2012-09-11 12:37:55 +02004598 I915_WRITE(DPLL(pipe), dpll);
4599
4600 /* Wait for the clocks to stabilize. */
4601 POSTING_READ(DPLL(pipe));
4602 udelay(150);
4603
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004604 /* The pixel multiplier can only be updated once the
4605 * DPLL is enabled and the clocks are stable.
4606 *
4607 * So write it again.
4608 */
4609 I915_WRITE(DPLL(pipe), dpll);
4610}
4611
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004612static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4613 struct drm_display_mode *mode,
4614 struct drm_display_mode *adjusted_mode)
4615{
4616 struct drm_device *dev = intel_crtc->base.dev;
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618 enum pipe pipe = intel_crtc->pipe;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004619 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004620 uint32_t vsyncshift;
4621
4622 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4623 /* the chip adds 2 halflines automatically */
4624 adjusted_mode->crtc_vtotal -= 1;
4625 adjusted_mode->crtc_vblank_end -= 1;
4626 vsyncshift = adjusted_mode->crtc_hsync_start
4627 - adjusted_mode->crtc_htotal / 2;
4628 } else {
4629 vsyncshift = 0;
4630 }
4631
4632 if (INTEL_INFO(dev)->gen > 3)
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004633 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004634
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004635 I915_WRITE(HTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004636 (adjusted_mode->crtc_hdisplay - 1) |
4637 ((adjusted_mode->crtc_htotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004638 I915_WRITE(HBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004639 (adjusted_mode->crtc_hblank_start - 1) |
4640 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004641 I915_WRITE(HSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004642 (adjusted_mode->crtc_hsync_start - 1) |
4643 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4644
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004645 I915_WRITE(VTOTAL(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004646 (adjusted_mode->crtc_vdisplay - 1) |
4647 ((adjusted_mode->crtc_vtotal - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004648 I915_WRITE(VBLANK(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004649 (adjusted_mode->crtc_vblank_start - 1) |
4650 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02004651 I915_WRITE(VSYNC(cpu_transcoder),
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004652 (adjusted_mode->crtc_vsync_start - 1) |
4653 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4654
Paulo Zanonib5e508d2012-10-24 11:34:43 -02004655 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4656 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4657 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4658 * bits. */
4659 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4660 (pipe == PIPE_B || pipe == PIPE_C))
4661 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4662
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004663 /* pipesrc controls the size that is scaled from, which should
4664 * always be the user's requested size.
4665 */
4666 I915_WRITE(PIPESRC(pipe),
4667 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4668}
4669
Eric Anholtf564048e2011-03-30 13:01:02 -07004670static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4671 struct drm_display_mode *mode,
4672 struct drm_display_mode *adjusted_mode,
4673 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02004674 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004675{
4676 struct drm_device *dev = crtc->dev;
4677 struct drm_i915_private *dev_priv = dev->dev_private;
4678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4679 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004680 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004681 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004682 intel_clock_t clock, reduced_clock;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004683 u32 dspcntr, pipeconf;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004684 bool ok, has_reduced_clock = false, is_sdvo = false;
4685 bool is_lvds = false, is_tv = false, is_dp = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01004686 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004687 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004688 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004689
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004690 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004691 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004692 case INTEL_OUTPUT_LVDS:
4693 is_lvds = true;
4694 break;
4695 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004696 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004697 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004698 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004699 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004700 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004701 case INTEL_OUTPUT_TVOUT:
4702 is_tv = true;
4703 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004704 case INTEL_OUTPUT_DISPLAYPORT:
4705 is_dp = true;
4706 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004707 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004708
Eric Anholtc751ce42010-03-25 11:48:48 -07004709 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004710 }
4711
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004712 refclk = i9xx_get_refclk(crtc, num_connectors);
Jesse Barnes79e53942008-11-07 14:24:08 -08004713
Ma Lingd4906092009-03-18 20:13:27 +08004714 /*
4715 * Returns a set of divisors for the desired target clock with the given
4716 * refclk, or FALSE. The returned values represent the clock equation:
4717 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4718 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004719 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08004720 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4721 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004722 if (!ok) {
4723 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004724 return -EINVAL;
4725 }
4726
4727 /* Ensure that the cursor is valid for the new mode before changing... */
4728 intel_crtc_update_cursor(crtc, true);
4729
4730 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004731 /*
4732 * Ensure we match the reduced clock's P to the target clock.
4733 * If the clocks don't match, we can't switch the display clock
4734 * by using the FP0/FP1. In such case we will disable the LVDS
4735 * downclock feature.
4736 */
Eric Anholtf564048e2011-03-30 13:01:02 -07004737 has_reduced_clock = limit->find_pll(limit, crtc,
4738 dev_priv->lvds_downclock,
4739 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08004740 &clock,
Eric Anholtf564048e2011-03-30 13:01:02 -07004741 &reduced_clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004742 }
4743
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004744 if (is_sdvo && is_tv)
4745 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004746
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004747 if (IS_GEN2(dev))
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304748 i8xx_update_pll(crtc, adjusted_mode, &clock,
4749 has_reduced_clock ? &reduced_clock : NULL,
4750 num_connectors);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004751 else if (IS_VALLEYVIEW(dev))
Vijay Purushothaman2a8f64c2012-09-27 19:13:06 +05304752 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4753 has_reduced_clock ? &reduced_clock : NULL,
4754 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004755 else
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004756 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4757 has_reduced_clock ? &reduced_clock : NULL,
4758 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004759
4760 /* setup pipeconf */
4761 pipeconf = I915_READ(PIPECONF(pipe));
4762
4763 /* Set up the display plane register */
4764 dspcntr = DISPPLANE_GAMMA_ENABLE;
4765
Eric Anholt929c77f2011-03-30 13:01:04 -07004766 if (pipe == 0)
4767 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4768 else
4769 dspcntr |= DISPPLANE_SEL_PIPE_B;
Eric Anholtf564048e2011-03-30 13:01:02 -07004770
4771 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4772 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4773 * core speed.
4774 *
4775 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4776 * pipe == 0 check?
4777 */
4778 if (mode->clock >
4779 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4780 pipeconf |= PIPECONF_DOUBLE_WIDE;
4781 else
4782 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4783 }
4784
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004785 /* default to 8bpc */
4786 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4787 if (is_dp) {
Jani Nikula0c96c652012-09-26 18:43:10 +03004788 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004789 pipeconf |= PIPECONF_BPP_6 |
4790 PIPECONF_DITHER_EN |
4791 PIPECONF_DITHER_TYPE_SP;
4792 }
4793 }
4794
Gajanan Bhat19c03922012-09-27 19:13:07 +05304795 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4796 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4797 pipeconf |= PIPECONF_BPP_6 |
4798 PIPECONF_ENABLE |
4799 I965_PIPECONF_ACTIVE;
4800 }
4801 }
4802
Eric Anholtf564048e2011-03-30 13:01:02 -07004803 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4804 drm_mode_debug_printmodeline(mode);
4805
Jesse Barnesa7516a02011-12-15 12:30:37 -08004806 if (HAS_PIPE_CXSR(dev)) {
4807 if (intel_crtc->lowfreq_avail) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004808 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4809 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004810 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07004811 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4812 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4813 }
4814 }
4815
Keith Packard617cf882012-02-08 13:53:38 -08004816 pipeconf &= ~PIPECONF_INTERLACE_MASK;
Daniel Vetterdbb02572012-01-28 14:49:23 +01004817 if (!IS_GEN2(dev) &&
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004818 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Eric Anholtf564048e2011-03-30 13:01:02 -07004819 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004820 else
Keith Packard617cf882012-02-08 13:53:38 -08004821 pipeconf |= PIPECONF_PROGRESSIVE;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004822
Paulo Zanonib0e77b92012-10-01 18:10:53 -03004823 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
Eric Anholtf564048e2011-03-30 13:01:02 -07004824
4825 /* pipesrc and dspsize control the size that is scaled from,
4826 * which should always be the user's requested size.
4827 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004828 I915_WRITE(DSPSIZE(plane),
4829 ((mode->vdisplay - 1) << 16) |
4830 (mode->hdisplay - 1));
4831 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07004832
Eric Anholtf564048e2011-03-30 13:01:02 -07004833 I915_WRITE(PIPECONF(pipe), pipeconf);
4834 POSTING_READ(PIPECONF(pipe));
Eric Anholt929c77f2011-03-30 13:01:04 -07004835 intel_enable_pipe(dev_priv, pipe, false);
Eric Anholtf564048e2011-03-30 13:01:02 -07004836
4837 intel_wait_for_vblank(dev, pipe);
4838
Eric Anholtf564048e2011-03-30 13:01:02 -07004839 I915_WRITE(DSPCNTR(plane), dspcntr);
4840 POSTING_READ(DSPCNTR(plane));
4841
Daniel Vetter94352cf2012-07-05 22:51:56 +02004842 ret = intel_pipe_set_base(crtc, x, y, fb);
Eric Anholtf564048e2011-03-30 13:01:02 -07004843
4844 intel_update_watermarks(dev);
4845
Eric Anholtf564048e2011-03-30 13:01:02 -07004846 return ret;
4847}
4848
Paulo Zanonidde86e22012-12-01 12:04:25 -02004849static void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07004850{
4851 struct drm_i915_private *dev_priv = dev->dev_private;
4852 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004853 struct intel_encoder *encoder;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004854 u32 temp;
4855 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07004856 bool has_cpu_edp = false;
4857 bool has_pch_edp = false;
4858 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07004859 bool has_ck505 = false;
4860 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004861
4862 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07004863 list_for_each_entry(encoder, &mode_config->encoder_list,
4864 base.head) {
4865 switch (encoder->type) {
4866 case INTEL_OUTPUT_LVDS:
4867 has_panel = true;
4868 has_lvds = true;
4869 break;
4870 case INTEL_OUTPUT_EDP:
4871 has_panel = true;
4872 if (intel_encoder_is_pch_edp(&encoder->base))
4873 has_pch_edp = true;
4874 else
4875 has_cpu_edp = true;
4876 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004877 }
4878 }
4879
Keith Packard99eb6a02011-09-26 14:29:12 -07004880 if (HAS_PCH_IBX(dev)) {
4881 has_ck505 = dev_priv->display_clock_mode;
4882 can_ssc = has_ck505;
4883 } else {
4884 has_ck505 = false;
4885 can_ssc = true;
4886 }
4887
4888 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4889 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4890 has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07004891
4892 /* Ironlake: try to setup display ref clock before DPLL
4893 * enabling. This is only under driver's control after
4894 * PCH B stepping, previous chipset stepping should be
4895 * ignoring this setting.
4896 */
4897 temp = I915_READ(PCH_DREF_CONTROL);
4898 /* Always enable nonspread source */
4899 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004900
Keith Packard99eb6a02011-09-26 14:29:12 -07004901 if (has_ck505)
4902 temp |= DREF_NONSPREAD_CK505_ENABLE;
4903 else
4904 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004905
Keith Packard199e5d72011-09-22 12:01:57 -07004906 if (has_panel) {
4907 temp &= ~DREF_SSC_SOURCE_MASK;
4908 temp |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004909
Keith Packard199e5d72011-09-22 12:01:57 -07004910 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07004911 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004912 DRM_DEBUG_KMS("Using SSC on panel\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07004913 temp |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02004914 } else
4915 temp &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004916
4917 /* Get SSC going before enabling the outputs */
4918 I915_WRITE(PCH_DREF_CONTROL, temp);
4919 POSTING_READ(PCH_DREF_CONTROL);
4920 udelay(200);
4921
Jesse Barnes13d83a62011-08-03 12:59:20 -07004922 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4923
4924 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07004925 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07004926 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004927 DRM_DEBUG_KMS("Using SSC on eDP\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07004928 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004929 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07004930 else
4931 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004932 } else
4933 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4934
4935 I915_WRITE(PCH_DREF_CONTROL, temp);
4936 POSTING_READ(PCH_DREF_CONTROL);
4937 udelay(200);
4938 } else {
4939 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4940
4941 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4942
4943 /* Turn off CPU output */
4944 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4945
4946 I915_WRITE(PCH_DREF_CONTROL, temp);
4947 POSTING_READ(PCH_DREF_CONTROL);
4948 udelay(200);
4949
4950 /* Turn off the SSC source */
4951 temp &= ~DREF_SSC_SOURCE_MASK;
4952 temp |= DREF_SSC_SOURCE_DISABLE;
4953
4954 /* Turn off SSC1 */
4955 temp &= ~ DREF_SSC1_ENABLE;
4956
Jesse Barnes13d83a62011-08-03 12:59:20 -07004957 I915_WRITE(PCH_DREF_CONTROL, temp);
4958 POSTING_READ(PCH_DREF_CONTROL);
4959 udelay(200);
4960 }
4961}
4962
Paulo Zanonidde86e22012-12-01 12:04:25 -02004963/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4964static void lpt_init_pch_refclk(struct drm_device *dev)
4965{
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 struct drm_mode_config *mode_config = &dev->mode_config;
4968 struct intel_encoder *encoder;
4969 bool has_vga = false;
4970 bool is_sdv = false;
4971 u32 tmp;
4972
4973 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4974 switch (encoder->type) {
4975 case INTEL_OUTPUT_ANALOG:
4976 has_vga = true;
4977 break;
4978 }
4979 }
4980
4981 if (!has_vga)
4982 return;
4983
4984 /* XXX: Rip out SDV support once Haswell ships for real. */
4985 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4986 is_sdv = true;
4987
4988 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4989 tmp &= ~SBI_SSCCTL_DISABLE;
4990 tmp |= SBI_SSCCTL_PATHALT;
4991 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4992
4993 udelay(24);
4994
4995 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4996 tmp &= ~SBI_SSCCTL_PATHALT;
4997 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4998
4999 if (!is_sdv) {
5000 tmp = I915_READ(SOUTH_CHICKEN2);
5001 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5002 I915_WRITE(SOUTH_CHICKEN2, tmp);
5003
5004 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5005 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5006 DRM_ERROR("FDI mPHY reset assert timeout\n");
5007
5008 tmp = I915_READ(SOUTH_CHICKEN2);
5009 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5010 I915_WRITE(SOUTH_CHICKEN2, tmp);
5011
5012 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5013 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5014 100))
5015 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5016 }
5017
5018 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5019 tmp &= ~(0xFF << 24);
5020 tmp |= (0x12 << 24);
5021 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5022
5023 if (!is_sdv) {
5024 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5025 tmp &= ~(0x3 << 6);
5026 tmp |= (1 << 6) | (1 << 0);
5027 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5028 }
5029
5030 if (is_sdv) {
5031 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5032 tmp |= 0x7FFF;
5033 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5034 }
5035
5036 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5037 tmp |= (1 << 11);
5038 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5039
5040 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5041 tmp |= (1 << 11);
5042 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5043
5044 if (is_sdv) {
5045 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5046 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5047 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5048
5049 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5050 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5051 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5052
5053 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5054 tmp |= (0x3F << 8);
5055 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5056
5057 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5058 tmp |= (0x3F << 8);
5059 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5060 }
5061
5062 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5063 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5064 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5065
5066 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5067 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5068 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5069
5070 if (!is_sdv) {
5071 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5072 tmp &= ~(7 << 13);
5073 tmp |= (5 << 13);
5074 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5075
5076 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5077 tmp &= ~(7 << 13);
5078 tmp |= (5 << 13);
5079 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5080 }
5081
5082 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5083 tmp &= ~0xFF;
5084 tmp |= 0x1C;
5085 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5086
5087 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5088 tmp &= ~0xFF;
5089 tmp |= 0x1C;
5090 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5091
5092 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5093 tmp &= ~(0xFF << 16);
5094 tmp |= (0x1C << 16);
5095 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5096
5097 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5098 tmp &= ~(0xFF << 16);
5099 tmp |= (0x1C << 16);
5100 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5101
5102 if (!is_sdv) {
5103 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5104 tmp |= (1 << 27);
5105 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5106
5107 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5108 tmp |= (1 << 27);
5109 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5110
5111 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5112 tmp &= ~(0xF << 28);
5113 tmp |= (4 << 28);
5114 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5115
5116 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5117 tmp &= ~(0xF << 28);
5118 tmp |= (4 << 28);
5119 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5120 }
5121
5122 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5123 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5124 tmp |= SBI_DBUFF0_ENABLE;
5125 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5126}
5127
5128/*
5129 * Initialize reference clocks when the driver loads
5130 */
5131void intel_init_pch_refclk(struct drm_device *dev)
5132{
5133 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5134 ironlake_init_pch_refclk(dev);
5135 else if (HAS_PCH_LPT(dev))
5136 lpt_init_pch_refclk(dev);
5137}
5138
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005139static int ironlake_get_refclk(struct drm_crtc *crtc)
5140{
5141 struct drm_device *dev = crtc->dev;
5142 struct drm_i915_private *dev_priv = dev->dev_private;
5143 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005144 struct intel_encoder *edp_encoder = NULL;
5145 int num_connectors = 0;
5146 bool is_lvds = false;
5147
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02005148 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005149 switch (encoder->type) {
5150 case INTEL_OUTPUT_LVDS:
5151 is_lvds = true;
5152 break;
5153 case INTEL_OUTPUT_EDP:
5154 edp_encoder = encoder;
5155 break;
5156 }
5157 num_connectors++;
5158 }
5159
5160 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5161 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5162 dev_priv->lvds_ssc_freq);
5163 return dev_priv->lvds_ssc_freq * 1000;
5164 }
5165
5166 return 120000;
5167}
5168
Paulo Zanonic8203562012-09-12 10:06:29 -03005169static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5170 struct drm_display_mode *adjusted_mode,
5171 bool dither)
5172{
5173 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5175 int pipe = intel_crtc->pipe;
5176 uint32_t val;
5177
5178 val = I915_READ(PIPECONF(pipe));
5179
5180 val &= ~PIPE_BPC_MASK;
5181 switch (intel_crtc->bpp) {
5182 case 18:
5183 val |= PIPE_6BPC;
5184 break;
5185 case 24:
5186 val |= PIPE_8BPC;
5187 break;
5188 case 30:
5189 val |= PIPE_10BPC;
5190 break;
5191 case 36:
5192 val |= PIPE_12BPC;
5193 break;
5194 default:
Paulo Zanonicc769b62012-09-20 18:36:03 -03005195 /* Case prevented by intel_choose_pipe_bpp_dither. */
5196 BUG();
Paulo Zanonic8203562012-09-12 10:06:29 -03005197 }
5198
5199 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5200 if (dither)
5201 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5202
5203 val &= ~PIPECONF_INTERLACE_MASK;
5204 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5205 val |= PIPECONF_INTERLACED_ILK;
5206 else
5207 val |= PIPECONF_PROGRESSIVE;
5208
5209 I915_WRITE(PIPECONF(pipe), val);
5210 POSTING_READ(PIPECONF(pipe));
5211}
5212
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005213static void haswell_set_pipeconf(struct drm_crtc *crtc,
5214 struct drm_display_mode *adjusted_mode,
5215 bool dither)
5216{
5217 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005219 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005220 uint32_t val;
5221
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005222 val = I915_READ(PIPECONF(cpu_transcoder));
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005223
5224 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5225 if (dither)
5226 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5227
5228 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5229 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5230 val |= PIPECONF_INTERLACED_ILK;
5231 else
5232 val |= PIPECONF_PROGRESSIVE;
5233
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005234 I915_WRITE(PIPECONF(cpu_transcoder), val);
5235 POSTING_READ(PIPECONF(cpu_transcoder));
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005236}
5237
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005238static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5239 struct drm_display_mode *adjusted_mode,
5240 intel_clock_t *clock,
5241 bool *has_reduced_clock,
5242 intel_clock_t *reduced_clock)
5243{
5244 struct drm_device *dev = crtc->dev;
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 struct intel_encoder *intel_encoder;
5247 int refclk;
5248 const intel_limit_t *limit;
5249 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5250
5251 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5252 switch (intel_encoder->type) {
5253 case INTEL_OUTPUT_LVDS:
5254 is_lvds = true;
5255 break;
5256 case INTEL_OUTPUT_SDVO:
5257 case INTEL_OUTPUT_HDMI:
5258 is_sdvo = true;
5259 if (intel_encoder->needs_tv_clock)
5260 is_tv = true;
5261 break;
5262 case INTEL_OUTPUT_TVOUT:
5263 is_tv = true;
5264 break;
5265 }
5266 }
5267
5268 refclk = ironlake_get_refclk(crtc);
5269
5270 /*
5271 * Returns a set of divisors for the desired target clock with the given
5272 * refclk, or FALSE. The returned values represent the clock equation:
5273 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5274 */
5275 limit = intel_limit(crtc, refclk);
5276 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5277 clock);
5278 if (!ret)
5279 return false;
5280
5281 if (is_lvds && dev_priv->lvds_downclock_avail) {
5282 /*
5283 * Ensure we match the reduced clock's P to the target clock.
5284 * If the clocks don't match, we can't switch the display clock
5285 * by using the FP0/FP1. In such case we will disable the LVDS
5286 * downclock feature.
5287 */
5288 *has_reduced_clock = limit->find_pll(limit, crtc,
5289 dev_priv->lvds_downclock,
5290 refclk,
5291 clock,
5292 reduced_clock);
5293 }
5294
5295 if (is_sdvo && is_tv)
5296 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5297
5298 return true;
5299}
5300
Daniel Vetter01a415f2012-10-27 15:58:40 +02005301static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5302{
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 uint32_t temp;
5305
5306 temp = I915_READ(SOUTH_CHICKEN1);
5307 if (temp & FDI_BC_BIFURCATION_SELECT)
5308 return;
5309
5310 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5311 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5312
5313 temp |= FDI_BC_BIFURCATION_SELECT;
5314 DRM_DEBUG_KMS("enabling fdi C rx\n");
5315 I915_WRITE(SOUTH_CHICKEN1, temp);
5316 POSTING_READ(SOUTH_CHICKEN1);
5317}
5318
5319static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5320{
5321 struct drm_device *dev = intel_crtc->base.dev;
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 struct intel_crtc *pipe_B_crtc =
5324 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5325
5326 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5327 intel_crtc->pipe, intel_crtc->fdi_lanes);
5328 if (intel_crtc->fdi_lanes > 4) {
5329 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5330 intel_crtc->pipe, intel_crtc->fdi_lanes);
5331 /* Clamp lanes to avoid programming the hw with bogus values. */
5332 intel_crtc->fdi_lanes = 4;
5333
5334 return false;
5335 }
5336
5337 if (dev_priv->num_pipe == 2)
5338 return true;
5339
5340 switch (intel_crtc->pipe) {
5341 case PIPE_A:
5342 return true;
5343 case PIPE_B:
5344 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5345 intel_crtc->fdi_lanes > 2) {
5346 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5347 intel_crtc->pipe, intel_crtc->fdi_lanes);
5348 /* Clamp lanes to avoid programming the hw with bogus values. */
5349 intel_crtc->fdi_lanes = 2;
5350
5351 return false;
5352 }
5353
5354 if (intel_crtc->fdi_lanes > 2)
5355 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5356 else
5357 cpt_enable_fdi_bc_bifurcation(dev);
5358
5359 return true;
5360 case PIPE_C:
5361 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5362 if (intel_crtc->fdi_lanes > 2) {
5363 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5364 intel_crtc->pipe, intel_crtc->fdi_lanes);
5365 /* Clamp lanes to avoid programming the hw with bogus values. */
5366 intel_crtc->fdi_lanes = 2;
5367
5368 return false;
5369 }
5370 } else {
5371 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5372 return false;
5373 }
5374
5375 cpt_enable_fdi_bc_bifurcation(dev);
5376
5377 return true;
5378 default:
5379 BUG();
5380 }
5381}
5382
Paulo Zanonid4b19312012-11-29 11:29:32 -02005383int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5384{
5385 /*
5386 * Account for spread spectrum to avoid
5387 * oversubscribing the link. Max center spread
5388 * is 2.5%; use 5% for safety's sake.
5389 */
5390 u32 bps = target_clock * bpp * 21 / 20;
5391 return bps / (link_bw * 8) + 1;
5392}
5393
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005394static void ironlake_set_m_n(struct drm_crtc *crtc,
5395 struct drm_display_mode *mode,
5396 struct drm_display_mode *adjusted_mode)
Jesse Barnes79e53942008-11-07 14:24:08 -08005397{
5398 struct drm_device *dev = crtc->dev;
5399 struct drm_i915_private *dev_priv = dev->dev_private;
5400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanoniafe2fcf2012-10-23 18:30:01 -02005401 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005402 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005403 struct fdi_m_n m_n = {0};
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005404 int target_clock, pixel_multiplier, lane, link_bw;
5405 bool is_dp = false, is_cpu_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005406
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005407 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5408 switch (intel_encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005409 case INTEL_OUTPUT_DISPLAYPORT:
5410 is_dp = true;
5411 break;
5412 case INTEL_OUTPUT_EDP:
Jesse Barnese3aef172012-04-10 11:58:03 -07005413 is_dp = true;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005414 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
Jesse Barnese3aef172012-04-10 11:58:03 -07005415 is_cpu_edp = true;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005416 edp_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005417 break;
5418 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005419 }
5420
Zhenyu Wang2c072452009-06-05 15:38:42 +08005421 /* FDI link */
Eric Anholt8febb292011-03-30 13:01:07 -07005422 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5423 lane = 0;
5424 /* CPU eDP doesn't require FDI link, so just set DP M/N
5425 according to current link config */
Jesse Barnese3aef172012-04-10 11:58:03 -07005426 if (is_cpu_edp) {
Jesse Barnese3aef172012-04-10 11:58:03 -07005427 intel_edp_link_config(edp_encoder, &lane, &link_bw);
Eric Anholt8febb292011-03-30 13:01:07 -07005428 } else {
Eric Anholt8febb292011-03-30 13:01:07 -07005429 /* FDI is a binary signal running at ~2.7GHz, encoding
5430 * each output octet as 10 bits. The actual frequency
5431 * is stored as a divider into a 100MHz clock, and the
5432 * mode pixel clock is stored in units of 1KHz.
5433 * Hence the bw of each lane in terms of the mode signal
5434 * is:
5435 */
5436 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005437 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08005438
Daniel Vetter94bf2ce2012-06-04 18:39:19 +02005439 /* [e]DP over FDI requires target mode clock instead of link clock. */
5440 if (edp_encoder)
5441 target_clock = intel_edp_target_clock(edp_encoder, mode);
5442 else if (is_dp)
5443 target_clock = mode->clock;
5444 else
5445 target_clock = adjusted_mode->clock;
5446
Paulo Zanonid4b19312012-11-29 11:29:32 -02005447 if (!lane)
5448 lane = ironlake_get_lanes_required(target_clock, link_bw,
5449 intel_crtc->bpp);
Eric Anholt8febb292011-03-30 13:01:07 -07005450
5451 intel_crtc->fdi_lanes = lane;
5452
5453 if (pixel_multiplier > 1)
5454 link_bw *= pixel_multiplier;
Jesse Barnes5a354202011-06-24 12:19:22 -07005455 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5456 &m_n);
Eric Anholt8febb292011-03-30 13:01:07 -07005457
Paulo Zanoniafe2fcf2012-10-23 18:30:01 -02005458 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5459 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5460 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5461 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005462}
5463
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005464static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5465 struct drm_display_mode *adjusted_mode,
5466 intel_clock_t *clock, u32 fp)
5467{
5468 struct drm_crtc *crtc = &intel_crtc->base;
5469 struct drm_device *dev = crtc->dev;
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 struct intel_encoder *intel_encoder;
5472 uint32_t dpll;
5473 int factor, pixel_multiplier, num_connectors = 0;
5474 bool is_lvds = false, is_sdvo = false, is_tv = false;
5475 bool is_dp = false, is_cpu_edp = false;
5476
5477 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5478 switch (intel_encoder->type) {
5479 case INTEL_OUTPUT_LVDS:
5480 is_lvds = true;
5481 break;
5482 case INTEL_OUTPUT_SDVO:
5483 case INTEL_OUTPUT_HDMI:
5484 is_sdvo = true;
5485 if (intel_encoder->needs_tv_clock)
5486 is_tv = true;
5487 break;
5488 case INTEL_OUTPUT_TVOUT:
5489 is_tv = true;
5490 break;
5491 case INTEL_OUTPUT_DISPLAYPORT:
5492 is_dp = true;
5493 break;
5494 case INTEL_OUTPUT_EDP:
5495 is_dp = true;
5496 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5497 is_cpu_edp = true;
5498 break;
5499 }
5500
5501 num_connectors++;
5502 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005503
Chris Wilsonc1858122010-12-03 21:35:48 +00005504 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07005505 factor = 21;
5506 if (is_lvds) {
5507 if ((intel_panel_use_ssc(dev_priv) &&
5508 dev_priv->lvds_ssc_freq == 100) ||
5509 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5510 factor = 25;
5511 } else if (is_sdvo && is_tv)
5512 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00005513
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005514 if (clock->m < factor * clock->n)
Eric Anholt8febb292011-03-30 13:01:07 -07005515 fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00005516
Chris Wilson5eddb702010-09-11 13:48:45 +01005517 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005518
Eric Anholta07d6782011-03-30 13:01:08 -07005519 if (is_lvds)
5520 dpll |= DPLLB_MODE_LVDS;
5521 else
5522 dpll |= DPLLB_MODE_DAC_SERIAL;
5523 if (is_sdvo) {
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005524 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
Eric Anholta07d6782011-03-30 13:01:08 -07005525 if (pixel_multiplier > 1) {
5526 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08005527 }
Eric Anholta07d6782011-03-30 13:01:08 -07005528 dpll |= DPLL_DVO_HIGH_SPEED;
5529 }
Jesse Barnese3aef172012-04-10 11:58:03 -07005530 if (is_dp && !is_cpu_edp)
Eric Anholta07d6782011-03-30 13:01:08 -07005531 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08005532
Eric Anholta07d6782011-03-30 13:01:08 -07005533 /* compute bitmask from p1 value */
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005534 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07005535 /* also FPA1 */
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005536 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
Eric Anholta07d6782011-03-30 13:01:08 -07005537
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005538 switch (clock->p2) {
Eric Anholta07d6782011-03-30 13:01:08 -07005539 case 5:
5540 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5541 break;
5542 case 7:
5543 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5544 break;
5545 case 10:
5546 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5547 break;
5548 case 14:
5549 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5550 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005551 }
5552
5553 if (is_sdvo && is_tv)
5554 dpll |= PLL_REF_INPUT_TVCLKINBC;
5555 else if (is_tv)
5556 /* XXX: just matching BIOS for now */
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005557 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
Jesse Barnes79e53942008-11-07 14:24:08 -08005558 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00005559 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005560 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
Jesse Barnes79e53942008-11-07 14:24:08 -08005561 else
5562 dpll |= PLL_REF_INPUT_DREFCLK;
5563
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005564 return dpll;
5565}
5566
Jesse Barnes79e53942008-11-07 14:24:08 -08005567static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5568 struct drm_display_mode *mode,
5569 struct drm_display_mode *adjusted_mode,
5570 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005571 struct drm_framebuffer *fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005572{
5573 struct drm_device *dev = crtc->dev;
5574 struct drm_i915_private *dev_priv = dev->dev_private;
5575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5576 int pipe = intel_crtc->pipe;
5577 int plane = intel_crtc->plane;
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005578 int num_connectors = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005579 intel_clock_t clock, reduced_clock;
Paulo Zanonia1f9e772012-09-12 10:06:32 -03005580 u32 dpll, fp = 0, fp2 = 0;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03005581 bool ok, has_reduced_clock = false;
5582 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005583 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005584 u32 temp;
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005585 int ret;
Daniel Vetter01a415f2012-10-27 15:58:40 +02005586 bool dither, fdi_config_ok;
Jesse Barnes79e53942008-11-07 14:24:08 -08005587
5588 for_each_encoder_on_crtc(dev, crtc, encoder) {
5589 switch (encoder->type) {
5590 case INTEL_OUTPUT_LVDS:
5591 is_lvds = true;
5592 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005593 case INTEL_OUTPUT_DISPLAYPORT:
5594 is_dp = true;
5595 break;
5596 case INTEL_OUTPUT_EDP:
5597 is_dp = true;
Paulo Zanonie2f12b02012-09-20 18:36:06 -03005598 if (!intel_encoder_is_pch_edp(&encoder->base))
Jesse Barnes79e53942008-11-07 14:24:08 -08005599 is_cpu_edp = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005600 break;
5601 }
5602
5603 num_connectors++;
5604 }
5605
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005606 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5607 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5608
Paulo Zanoni6591c6e2012-09-12 10:06:34 -03005609 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5610 &has_reduced_clock, &reduced_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005611 if (!ok) {
5612 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5613 return -EINVAL;
5614 }
5615
5616 /* Ensure that the cursor is valid for the new mode before changing... */
5617 intel_crtc_update_cursor(crtc, true);
5618
Jesse Barnes79e53942008-11-07 14:24:08 -08005619 /* determine panel color depth */
Jani Nikulac8241962012-11-02 10:19:55 +02005620 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5621 adjusted_mode);
Paulo Zanonic8203562012-09-12 10:06:29 -03005622 if (is_lvds && dev_priv->lvds_dither)
5623 dither = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005624
Jesse Barnes79e53942008-11-07 14:24:08 -08005625 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5626 if (has_reduced_clock)
5627 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5628 reduced_clock.m2;
5629
Paulo Zanonide13a2e2012-09-20 18:36:05 -03005630 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005631
Jesse Barnesf7cb34d2011-10-12 10:49:14 -07005632 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005633 drm_mode_debug_printmodeline(mode);
5634
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005635 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5636 if (!is_cpu_edp) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005637 struct intel_pch_pll *pll;
Chris Wilson5eddb702010-09-11 13:48:45 +01005638
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005639 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5640 if (pll == NULL) {
5641 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5642 pipe);
Jesse Barnes4b645f12011-10-12 09:51:31 -07005643 return -EINVAL;
5644 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005645 } else
5646 intel_put_pch_pll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005647
5648 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5649 * This is an exception to the general rule that mode_set doesn't turn
5650 * things on.
5651 */
5652 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07005653 temp = I915_READ(PCH_LVDS);
Chris Wilson5eddb702010-09-11 13:48:45 +01005654 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Jesse Barnes7885d202012-01-12 14:51:17 -08005655 if (HAS_PCH_CPT(dev)) {
5656 temp &= ~PORT_TRANS_SEL_MASK;
Jesse Barnes4b645f12011-10-12 09:51:31 -07005657 temp |= PORT_TRANS_SEL_CPT(pipe);
Jesse Barnes7885d202012-01-12 14:51:17 -08005658 } else {
5659 if (pipe == 1)
5660 temp |= LVDS_PIPEB_SELECT;
5661 else
5662 temp &= ~LVDS_PIPEB_SELECT;
5663 }
Jesse Barnes4b645f12011-10-12 09:51:31 -07005664
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08005665 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01005666 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08005667 /* Set the B0-B3 data pairs corresponding to whether we're going to
5668 * set the DPLLs for dual-channel mode or not.
5669 */
5670 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01005671 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08005672 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005673 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08005674
5675 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5676 * appropriately here, but we need to look more thoroughly into how
5677 * panels behave in the two modes.
5678 */
Chris Wilson284d5df2012-04-14 17:41:59 +01005679 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
Bryan Freedaa9b5002011-01-12 13:43:19 -08005680 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01005681 temp |= LVDS_HSYNC_POLARITY;
Bryan Freedaa9b5002011-01-12 13:43:19 -08005682 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01005683 temp |= LVDS_VSYNC_POLARITY;
Eric Anholtfae14982011-03-30 13:01:09 -07005684 I915_WRITE(PCH_LVDS, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005685 }
Jesse Barnes434ed092010-09-07 14:48:06 -07005686
Jesse Barnese3aef172012-04-10 11:58:03 -07005687 if (is_dp && !is_cpu_edp) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005688 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholt8febb292011-03-30 13:01:07 -07005689 } else {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005690 /* For non-DP output, clear any trans DP clock recovery setting.*/
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005691 I915_WRITE(TRANSDATA_M1(pipe), 0);
5692 I915_WRITE(TRANSDATA_N1(pipe), 0);
5693 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5694 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08005695 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005696
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005697 if (intel_crtc->pch_pll) {
5698 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01005699
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005700 /* Wait for the clocks to stabilize. */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005701 POSTING_READ(intel_crtc->pch_pll->pll_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005702 udelay(150);
5703
Eric Anholt8febb292011-03-30 13:01:07 -07005704 /* The pixel multiplier can only be updated once the
5705 * DPLL is enabled and the clocks are stable.
5706 *
5707 * So write it again.
5708 */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005709 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Jesse Barnes79e53942008-11-07 14:24:08 -08005710 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005711
Chris Wilson5eddb702010-09-11 13:48:45 +01005712 intel_crtc->lowfreq_avail = false;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005713 if (intel_crtc->pch_pll) {
Jesse Barnes4b645f12011-10-12 09:51:31 -07005714 if (is_lvds && has_reduced_clock && i915_powersave) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005715 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
Jesse Barnes4b645f12011-10-12 09:51:31 -07005716 intel_crtc->lowfreq_avail = true;
Jesse Barnes4b645f12011-10-12 09:51:31 -07005717 } else {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01005718 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07005719 }
5720 }
5721
Paulo Zanonib0e77b92012-10-01 18:10:53 -03005722 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
Krzysztof Halasa734b4152010-05-25 18:41:46 +02005723
Daniel Vetter01a415f2012-10-27 15:58:40 +02005724 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5725 * ironlake_check_fdi_lanes. */
Paulo Zanonif48d8f22012-09-20 18:36:04 -03005726 ironlake_set_m_n(crtc, mode, adjusted_mode);
Chris Wilson5eddb702010-09-11 13:48:45 +01005727
Daniel Vetter01a415f2012-10-27 15:58:40 +02005728 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005729
Jesse Barnese3aef172012-04-10 11:58:03 -07005730 if (is_cpu_edp)
Eric Anholt8febb292011-03-30 13:01:07 -07005731 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005732
Paulo Zanonic8203562012-09-12 10:06:29 -03005733 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
Jesse Barnes79e53942008-11-07 14:24:08 -08005734
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005735 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005736
Paulo Zanonia1f9e772012-09-12 10:06:32 -03005737 /* Set up the display plane register */
5738 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08005739 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08005740
Daniel Vetter94352cf2012-07-05 22:51:56 +02005741 ret = intel_pipe_set_base(crtc, x, y, fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08005742
5743 intel_update_watermarks(dev);
5744
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03005745 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5746
Daniel Vetter01a415f2012-10-27 15:58:40 +02005747 return fdi_config_ok ? ret : -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005748}
5749
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005750static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5751 struct drm_display_mode *mode,
5752 struct drm_display_mode *adjusted_mode,
5753 int x, int y,
5754 struct drm_framebuffer *fb)
5755{
5756 struct drm_device *dev = crtc->dev;
5757 struct drm_i915_private *dev_priv = dev->dev_private;
5758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5759 int pipe = intel_crtc->pipe;
5760 int plane = intel_crtc->plane;
5761 int num_connectors = 0;
5762 intel_clock_t clock, reduced_clock;
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005763 u32 dpll = 0, fp = 0, fp2 = 0;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005764 bool ok, has_reduced_clock = false;
5765 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5766 struct intel_encoder *encoder;
5767 u32 temp;
5768 int ret;
5769 bool dither;
5770
5771 for_each_encoder_on_crtc(dev, crtc, encoder) {
5772 switch (encoder->type) {
5773 case INTEL_OUTPUT_LVDS:
5774 is_lvds = true;
5775 break;
5776 case INTEL_OUTPUT_DISPLAYPORT:
5777 is_dp = true;
5778 break;
5779 case INTEL_OUTPUT_EDP:
5780 is_dp = true;
5781 if (!intel_encoder_is_pch_edp(&encoder->base))
5782 is_cpu_edp = true;
5783 break;
5784 }
5785
5786 num_connectors++;
5787 }
5788
Paulo Zanonia5c961d2012-10-24 15:59:34 -02005789 if (is_cpu_edp)
5790 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5791 else
5792 intel_crtc->cpu_transcoder = pipe;
5793
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005794 /* We are not sure yet this won't happen. */
5795 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5796 INTEL_PCH_TYPE(dev));
5797
5798 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5799 num_connectors, pipe_name(pipe));
5800
Paulo Zanoni702e7a52012-10-23 18:29:59 -02005801 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
Paulo Zanoni1ce42922012-10-05 12:06:01 -03005802 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5803
5804 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5805
Paulo Zanoni6441ab52012-10-05 12:05:58 -03005806 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5807 return -EINVAL;
5808
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005809 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5810 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5811 &has_reduced_clock,
5812 &reduced_clock);
5813 if (!ok) {
5814 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5815 return -EINVAL;
5816 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005817 }
5818
5819 /* Ensure that the cursor is valid for the new mode before changing... */
5820 intel_crtc_update_cursor(crtc, true);
5821
5822 /* determine panel color depth */
Jani Nikulac8241962012-11-02 10:19:55 +02005823 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5824 adjusted_mode);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005825 if (is_lvds && dev_priv->lvds_dither)
5826 dither = true;
5827
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005828 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5829 drm_mode_debug_printmodeline(mode);
5830
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005831 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5832 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5833 if (has_reduced_clock)
5834 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5835 reduced_clock.m2;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005836
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005837 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5838 fp);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005839
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005840 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5841 * own on pre-Haswell/LPT generation */
5842 if (!is_cpu_edp) {
5843 struct intel_pch_pll *pll;
5844
5845 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5846 if (pll == NULL) {
5847 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5848 pipe);
5849 return -EINVAL;
5850 }
5851 } else
5852 intel_put_pch_pll(intel_crtc);
5853
5854 /* The LVDS pin pair needs to be on before the DPLLs are
5855 * enabled. This is an exception to the general rule that
5856 * mode_set doesn't turn things on.
5857 */
5858 if (is_lvds) {
5859 temp = I915_READ(PCH_LVDS);
5860 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5861 if (HAS_PCH_CPT(dev)) {
5862 temp &= ~PORT_TRANS_SEL_MASK;
5863 temp |= PORT_TRANS_SEL_CPT(pipe);
5864 } else {
5865 if (pipe == 1)
5866 temp |= LVDS_PIPEB_SELECT;
5867 else
5868 temp &= ~LVDS_PIPEB_SELECT;
5869 }
5870
5871 /* set the corresponsding LVDS_BORDER bit */
5872 temp |= dev_priv->lvds_border_bits;
5873 /* Set the B0-B3 data pairs corresponding to whether
5874 * we're going to set the DPLLs for dual-channel mode or
5875 * not.
5876 */
5877 if (clock.p2 == 7)
5878 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005879 else
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005880 temp &= ~(LVDS_B0B3_POWER_UP |
5881 LVDS_CLKB_POWER_UP);
5882
5883 /* It would be nice to set 24 vs 18-bit mode
5884 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5885 * look more thoroughly into how panels behave in the
5886 * two modes.
5887 */
5888 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5889 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5890 temp |= LVDS_HSYNC_POLARITY;
5891 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5892 temp |= LVDS_VSYNC_POLARITY;
5893 I915_WRITE(PCH_LVDS, temp);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005894 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005895 }
5896
5897 if (is_dp && !is_cpu_edp) {
5898 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5899 } else {
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005900 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5901 /* For non-DP output, clear any trans DP clock recovery
5902 * setting.*/
5903 I915_WRITE(TRANSDATA_M1(pipe), 0);
5904 I915_WRITE(TRANSDATA_N1(pipe), 0);
5905 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5906 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5907 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005908 }
5909
5910 intel_crtc->lowfreq_avail = false;
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005911 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5912 if (intel_crtc->pch_pll) {
5913 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5914
5915 /* Wait for the clocks to stabilize. */
5916 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5917 udelay(150);
5918
5919 /* The pixel multiplier can only be updated once the
5920 * DPLL is enabled and the clocks are stable.
5921 *
5922 * So write it again.
5923 */
5924 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5925 }
5926
5927 if (intel_crtc->pch_pll) {
5928 if (is_lvds && has_reduced_clock && i915_powersave) {
5929 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5930 intel_crtc->lowfreq_avail = true;
5931 } else {
5932 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5933 }
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005934 }
5935 }
5936
5937 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5938
Paulo Zanoni1eb8dfe2012-10-18 12:42:10 -03005939 if (!is_dp || is_cpu_edp)
5940 ironlake_set_m_n(crtc, mode, adjusted_mode);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005941
Paulo Zanoni5dc52982012-10-05 12:05:56 -03005942 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5943 if (is_cpu_edp)
5944 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005945
Paulo Zanoniee2b0b32012-10-05 12:05:57 -03005946 haswell_set_pipeconf(crtc, adjusted_mode, dither);
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005947
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03005948 /* Set up the display plane register */
5949 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5950 POSTING_READ(DSPCNTR(plane));
5951
5952 ret = intel_pipe_set_base(crtc, x, y, fb);
5953
5954 intel_update_watermarks(dev);
5955
5956 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5957
Jesse Barnes79e53942008-11-07 14:24:08 -08005958 return ret;
5959}
5960
Eric Anholtf564048e2011-03-30 13:01:02 -07005961static int intel_crtc_mode_set(struct drm_crtc *crtc,
5962 struct drm_display_mode *mode,
5963 struct drm_display_mode *adjusted_mode,
5964 int x, int y,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005965 struct drm_framebuffer *fb)
Eric Anholtf564048e2011-03-30 13:01:02 -07005966{
5967 struct drm_device *dev = crtc->dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9256aa12012-10-31 19:26:13 +01005969 struct drm_encoder_helper_funcs *encoder_funcs;
5970 struct intel_encoder *encoder;
Eric Anholt0b701d22011-03-30 13:01:03 -07005971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5972 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07005973 int ret;
5974
Eric Anholt0b701d22011-03-30 13:01:03 -07005975 drm_vblank_pre_modeset(dev, pipe);
5976
Eric Anholtf564048e2011-03-30 13:01:02 -07005977 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
Daniel Vetter94352cf2012-07-05 22:51:56 +02005978 x, y, fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08005979 drm_vblank_post_modeset(dev, pipe);
5980
Daniel Vetter9256aa12012-10-31 19:26:13 +01005981 if (ret != 0)
5982 return ret;
5983
5984 for_each_encoder_on_crtc(dev, crtc, encoder) {
5985 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5986 encoder->base.base.id,
5987 drm_get_encoder_name(&encoder->base),
5988 mode->base.id, mode->name);
5989 encoder_funcs = encoder->base.helper_private;
5990 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5991 }
5992
5993 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005994}
5995
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005996static bool intel_eld_uptodate(struct drm_connector *connector,
5997 int reg_eldv, uint32_t bits_eldv,
5998 int reg_elda, uint32_t bits_elda,
5999 int reg_edid)
6000{
6001 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6002 uint8_t *eld = connector->eld;
6003 uint32_t i;
6004
6005 i = I915_READ(reg_eldv);
6006 i &= bits_eldv;
6007
6008 if (!eld[0])
6009 return !i;
6010
6011 if (!i)
6012 return false;
6013
6014 i = I915_READ(reg_elda);
6015 i &= ~bits_elda;
6016 I915_WRITE(reg_elda, i);
6017
6018 for (i = 0; i < eld[2]; i++)
6019 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6020 return false;
6021
6022 return true;
6023}
6024
Wu Fengguange0dac652011-09-05 14:25:34 +08006025static void g4x_write_eld(struct drm_connector *connector,
6026 struct drm_crtc *crtc)
6027{
6028 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6029 uint8_t *eld = connector->eld;
6030 uint32_t eldv;
6031 uint32_t len;
6032 uint32_t i;
6033
6034 i = I915_READ(G4X_AUD_VID_DID);
6035
6036 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6037 eldv = G4X_ELDV_DEVCL_DEVBLC;
6038 else
6039 eldv = G4X_ELDV_DEVCTG;
6040
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006041 if (intel_eld_uptodate(connector,
6042 G4X_AUD_CNTL_ST, eldv,
6043 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6044 G4X_HDMIW_HDMIEDID))
6045 return;
6046
Wu Fengguange0dac652011-09-05 14:25:34 +08006047 i = I915_READ(G4X_AUD_CNTL_ST);
6048 i &= ~(eldv | G4X_ELD_ADDR);
6049 len = (i >> 9) & 0x1f; /* ELD buffer size */
6050 I915_WRITE(G4X_AUD_CNTL_ST, i);
6051
6052 if (!eld[0])
6053 return;
6054
6055 len = min_t(uint8_t, eld[2], len);
6056 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6057 for (i = 0; i < len; i++)
6058 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6059
6060 i = I915_READ(G4X_AUD_CNTL_ST);
6061 i |= eldv;
6062 I915_WRITE(G4X_AUD_CNTL_ST, i);
6063}
6064
Wang Xingchao83358c852012-08-16 22:43:37 +08006065static void haswell_write_eld(struct drm_connector *connector,
6066 struct drm_crtc *crtc)
6067{
6068 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6069 uint8_t *eld = connector->eld;
6070 struct drm_device *dev = crtc->dev;
6071 uint32_t eldv;
6072 uint32_t i;
6073 int len;
6074 int pipe = to_intel_crtc(crtc)->pipe;
6075 int tmp;
6076
6077 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6078 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6079 int aud_config = HSW_AUD_CFG(pipe);
6080 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6081
6082
6083 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6084
6085 /* Audio output enable */
6086 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6087 tmp = I915_READ(aud_cntrl_st2);
6088 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6089 I915_WRITE(aud_cntrl_st2, tmp);
6090
6091 /* Wait for 1 vertical blank */
6092 intel_wait_for_vblank(dev, pipe);
6093
6094 /* Set ELD valid state */
6095 tmp = I915_READ(aud_cntrl_st2);
6096 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6097 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6098 I915_WRITE(aud_cntrl_st2, tmp);
6099 tmp = I915_READ(aud_cntrl_st2);
6100 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6101
6102 /* Enable HDMI mode */
6103 tmp = I915_READ(aud_config);
6104 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6105 /* clear N_programing_enable and N_value_index */
6106 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6107 I915_WRITE(aud_config, tmp);
6108
6109 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6110
6111 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6112
6113 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6114 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6115 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6116 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6117 } else
6118 I915_WRITE(aud_config, 0);
6119
6120 if (intel_eld_uptodate(connector,
6121 aud_cntrl_st2, eldv,
6122 aud_cntl_st, IBX_ELD_ADDRESS,
6123 hdmiw_hdmiedid))
6124 return;
6125
6126 i = I915_READ(aud_cntrl_st2);
6127 i &= ~eldv;
6128 I915_WRITE(aud_cntrl_st2, i);
6129
6130 if (!eld[0])
6131 return;
6132
6133 i = I915_READ(aud_cntl_st);
6134 i &= ~IBX_ELD_ADDRESS;
6135 I915_WRITE(aud_cntl_st, i);
6136 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6137 DRM_DEBUG_DRIVER("port num:%d\n", i);
6138
6139 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6140 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6141 for (i = 0; i < len; i++)
6142 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6143
6144 i = I915_READ(aud_cntrl_st2);
6145 i |= eldv;
6146 I915_WRITE(aud_cntrl_st2, i);
6147
6148}
6149
Wu Fengguange0dac652011-09-05 14:25:34 +08006150static void ironlake_write_eld(struct drm_connector *connector,
6151 struct drm_crtc *crtc)
6152{
6153 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6154 uint8_t *eld = connector->eld;
6155 uint32_t eldv;
6156 uint32_t i;
6157 int len;
6158 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06006159 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08006160 int aud_cntl_st;
6161 int aud_cntrl_st2;
Wang Xingchao9b138a82012-08-09 16:52:18 +08006162 int pipe = to_intel_crtc(crtc)->pipe;
Wu Fengguange0dac652011-09-05 14:25:34 +08006163
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08006164 if (HAS_PCH_IBX(connector->dev)) {
Wang Xingchao9b138a82012-08-09 16:52:18 +08006165 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6166 aud_config = IBX_AUD_CFG(pipe);
6167 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006168 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006169 } else {
Wang Xingchao9b138a82012-08-09 16:52:18 +08006170 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6171 aud_config = CPT_AUD_CFG(pipe);
6172 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006173 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006174 }
6175
Wang Xingchao9b138a82012-08-09 16:52:18 +08006176 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
Wu Fengguange0dac652011-09-05 14:25:34 +08006177
6178 i = I915_READ(aud_cntl_st);
Wang Xingchao9b138a82012-08-09 16:52:18 +08006179 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
Wu Fengguange0dac652011-09-05 14:25:34 +08006180 if (!i) {
6181 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6182 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006183 eldv = IBX_ELD_VALIDB;
6184 eldv |= IBX_ELD_VALIDB << 4;
6185 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08006186 } else {
6187 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006188 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08006189 }
6190
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6192 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6193 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06006194 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6195 } else
6196 I915_WRITE(aud_config, 0);
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006197
6198 if (intel_eld_uptodate(connector,
6199 aud_cntrl_st2, eldv,
6200 aud_cntl_st, IBX_ELD_ADDRESS,
6201 hdmiw_hdmiedid))
6202 return;
6203
Wu Fengguange0dac652011-09-05 14:25:34 +08006204 i = I915_READ(aud_cntrl_st2);
6205 i &= ~eldv;
6206 I915_WRITE(aud_cntrl_st2, i);
6207
6208 if (!eld[0])
6209 return;
6210
Wu Fengguange0dac652011-09-05 14:25:34 +08006211 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08006212 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08006213 I915_WRITE(aud_cntl_st, i);
6214
6215 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6216 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6217 for (i = 0; i < len; i++)
6218 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6219
6220 i = I915_READ(aud_cntrl_st2);
6221 i |= eldv;
6222 I915_WRITE(aud_cntrl_st2, i);
6223}
6224
6225void intel_write_eld(struct drm_encoder *encoder,
6226 struct drm_display_mode *mode)
6227{
6228 struct drm_crtc *crtc = encoder->crtc;
6229 struct drm_connector *connector;
6230 struct drm_device *dev = encoder->dev;
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232
6233 connector = drm_select_eld(encoder, mode);
6234 if (!connector)
6235 return;
6236
6237 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6238 connector->base.id,
6239 drm_get_connector_name(connector),
6240 connector->encoder->base.id,
6241 drm_get_encoder_name(connector->encoder));
6242
6243 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6244
6245 if (dev_priv->display.write_eld)
6246 dev_priv->display.write_eld(connector, crtc);
6247}
6248
Jesse Barnes79e53942008-11-07 14:24:08 -08006249/** Loads the palette/gamma unit for the CRTC with the prepared values */
6250void intel_crtc_load_lut(struct drm_crtc *crtc)
6251{
6252 struct drm_device *dev = crtc->dev;
6253 struct drm_i915_private *dev_priv = dev->dev_private;
6254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006255 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006256 int i;
6257
6258 /* The clocks have to be on to load the palette. */
Alban Browaeysaed3f092012-02-24 17:12:45 +00006259 if (!crtc->enabled || !intel_crtc->active)
Jesse Barnes79e53942008-11-07 14:24:08 -08006260 return;
6261
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006262 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07006263 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006264 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08006265
Jesse Barnes79e53942008-11-07 14:24:08 -08006266 for (i = 0; i < 256; i++) {
6267 I915_WRITE(palreg + 4 * i,
6268 (intel_crtc->lut_r[i] << 16) |
6269 (intel_crtc->lut_g[i] << 8) |
6270 intel_crtc->lut_b[i]);
6271 }
6272}
6273
Chris Wilson560b85b2010-08-07 11:01:38 +01006274static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6275{
6276 struct drm_device *dev = crtc->dev;
6277 struct drm_i915_private *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279 bool visible = base != 0;
6280 u32 cntl;
6281
6282 if (intel_crtc->cursor_visible == visible)
6283 return;
6284
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006285 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01006286 if (visible) {
6287 /* On these chipsets we can only modify the base whilst
6288 * the cursor is disabled.
6289 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006290 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006291
6292 cntl &= ~(CURSOR_FORMAT_MASK);
6293 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6294 cntl |= CURSOR_ENABLE |
6295 CURSOR_GAMMA_ENABLE |
6296 CURSOR_FORMAT_ARGB;
6297 } else
6298 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006299 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006300
6301 intel_crtc->cursor_visible = visible;
6302}
6303
6304static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6305{
6306 struct drm_device *dev = crtc->dev;
6307 struct drm_i915_private *dev_priv = dev->dev_private;
6308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6309 int pipe = intel_crtc->pipe;
6310 bool visible = base != 0;
6311
6312 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08006313 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01006314 if (base) {
6315 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6316 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6317 cntl |= pipe << 28; /* Connect to correct pipe */
6318 } else {
6319 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6320 cntl |= CURSOR_MODE_DISABLE;
6321 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006322 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006323
6324 intel_crtc->cursor_visible = visible;
6325 }
6326 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006327 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006328}
6329
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006330static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6331{
6332 struct drm_device *dev = crtc->dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6335 int pipe = intel_crtc->pipe;
6336 bool visible = base != 0;
6337
6338 if (intel_crtc->cursor_visible != visible) {
6339 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6340 if (base) {
6341 cntl &= ~CURSOR_MODE;
6342 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6343 } else {
6344 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6345 cntl |= CURSOR_MODE_DISABLE;
6346 }
6347 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6348
6349 intel_crtc->cursor_visible = visible;
6350 }
6351 /* and commit changes on next vblank */
6352 I915_WRITE(CURBASE_IVB(pipe), base);
6353}
6354
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006355/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01006356static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6357 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006358{
6359 struct drm_device *dev = crtc->dev;
6360 struct drm_i915_private *dev_priv = dev->dev_private;
6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362 int pipe = intel_crtc->pipe;
6363 int x = intel_crtc->cursor_x;
6364 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01006365 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006366 bool visible;
6367
6368 pos = 0;
6369
Chris Wilson6b383a72010-09-13 13:54:26 +01006370 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006371 base = intel_crtc->cursor_addr;
6372 if (x > (int) crtc->fb->width)
6373 base = 0;
6374
6375 if (y > (int) crtc->fb->height)
6376 base = 0;
6377 } else
6378 base = 0;
6379
6380 if (x < 0) {
6381 if (x + intel_crtc->cursor_width < 0)
6382 base = 0;
6383
6384 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6385 x = -x;
6386 }
6387 pos |= x << CURSOR_X_SHIFT;
6388
6389 if (y < 0) {
6390 if (y + intel_crtc->cursor_height < 0)
6391 base = 0;
6392
6393 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6394 y = -y;
6395 }
6396 pos |= y << CURSOR_Y_SHIFT;
6397
6398 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01006399 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006400 return;
6401
Eugeni Dodonov0cd83aa2012-04-13 17:08:48 -03006402 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006403 I915_WRITE(CURPOS_IVB(pipe), pos);
6404 ivb_update_cursor(crtc, base);
6405 } else {
6406 I915_WRITE(CURPOS(pipe), pos);
6407 if (IS_845G(dev) || IS_I865G(dev))
6408 i845_update_cursor(crtc, base);
6409 else
6410 i9xx_update_cursor(crtc, base);
6411 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006412}
6413
Jesse Barnes79e53942008-11-07 14:24:08 -08006414static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00006415 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006416 uint32_t handle,
6417 uint32_t width, uint32_t height)
6418{
6419 struct drm_device *dev = crtc->dev;
6420 struct drm_i915_private *dev_priv = dev->dev_private;
6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00006422 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006423 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006424 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006425
Jesse Barnes79e53942008-11-07 14:24:08 -08006426 /* if we want to turn off the cursor ignore width and height */
6427 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006428 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006429 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00006430 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10006431 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006432 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08006433 }
6434
6435 /* Currently we only support 64x64 cursors */
6436 if (width != 64 || height != 64) {
6437 DRM_ERROR("we currently only support 64x64 cursors\n");
6438 return -EINVAL;
6439 }
6440
Chris Wilson05394f32010-11-08 19:18:58 +00006441 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00006442 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08006443 return -ENOENT;
6444
Chris Wilson05394f32010-11-08 19:18:58 +00006445 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006446 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10006447 ret = -ENOMEM;
6448 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08006449 }
6450
Dave Airlie71acb5e2008-12-30 20:31:46 +10006451 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006452 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006453 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00006454 if (obj->tiling_mode) {
6455 DRM_ERROR("cursor cannot be tiled\n");
6456 ret = -EINVAL;
6457 goto fail_locked;
6458 }
6459
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006460 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01006461 if (ret) {
6462 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006463 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006464 }
6465
Chris Wilsond9e86c02010-11-10 16:40:20 +00006466 ret = i915_gem_object_put_fence(obj);
6467 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006468 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00006469 goto fail_unpin;
6470 }
6471
Chris Wilson05394f32010-11-08 19:18:58 +00006472 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006473 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006474 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00006475 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006476 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6477 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10006478 if (ret) {
6479 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006480 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006481 }
Chris Wilson05394f32010-11-08 19:18:58 +00006482 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006483 }
6484
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006485 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04006486 I915_WRITE(CURSIZE, (height << 12) | width);
6487
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006488 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006489 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006490 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00006491 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10006492 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6493 } else
6494 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00006495 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006496 }
Jesse Barnes80824002009-09-10 15:28:06 -07006497
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006498 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006499
6500 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00006501 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006502 intel_crtc->cursor_width = width;
6503 intel_crtc->cursor_height = height;
6504
Chris Wilson6b383a72010-09-13 13:54:26 +01006505 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006506
Jesse Barnes79e53942008-11-07 14:24:08 -08006507 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006508fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00006509 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006510fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10006511 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00006512fail:
Chris Wilson05394f32010-11-08 19:18:58 +00006513 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10006514 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006515}
6516
6517static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6518{
Jesse Barnes79e53942008-11-07 14:24:08 -08006519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006520
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006521 intel_crtc->cursor_x = x;
6522 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07006523
Chris Wilson6b383a72010-09-13 13:54:26 +01006524 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08006525
6526 return 0;
6527}
6528
6529/** Sets the color ramps on behalf of RandR */
6530void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6531 u16 blue, int regno)
6532{
6533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6534
6535 intel_crtc->lut_r[regno] = red >> 8;
6536 intel_crtc->lut_g[regno] = green >> 8;
6537 intel_crtc->lut_b[regno] = blue >> 8;
6538}
6539
Dave Airlieb8c00ac2009-10-06 13:54:01 +10006540void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6541 u16 *blue, int regno)
6542{
6543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6544
6545 *red = intel_crtc->lut_r[regno] << 8;
6546 *green = intel_crtc->lut_g[regno] << 8;
6547 *blue = intel_crtc->lut_b[regno] << 8;
6548}
6549
Jesse Barnes79e53942008-11-07 14:24:08 -08006550static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01006551 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08006552{
James Simmons72034252010-08-03 01:33:19 +01006553 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08006554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006555
James Simmons72034252010-08-03 01:33:19 +01006556 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006557 intel_crtc->lut_r[i] = red[i] >> 8;
6558 intel_crtc->lut_g[i] = green[i] >> 8;
6559 intel_crtc->lut_b[i] = blue[i] >> 8;
6560 }
6561
6562 intel_crtc_load_lut(crtc);
6563}
6564
6565/**
6566 * Get a pipe with a simple mode set on it for doing load-based monitor
6567 * detection.
6568 *
6569 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07006570 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08006571 *
Eric Anholtc751ce42010-03-25 11:48:48 -07006572 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08006573 * configured for it. In the future, it could choose to temporarily disable
6574 * some outputs to free up a pipe for its use.
6575 *
6576 * \return crtc, or NULL if no pipes are available.
6577 */
6578
6579/* VESA 640x480x72Hz mode to set on the pipe */
6580static struct drm_display_mode load_detect_mode = {
6581 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6582 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6583};
6584
Chris Wilsond2dff872011-04-19 08:36:26 +01006585static struct drm_framebuffer *
6586intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006587 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01006588 struct drm_i915_gem_object *obj)
6589{
6590 struct intel_framebuffer *intel_fb;
6591 int ret;
6592
6593 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6594 if (!intel_fb) {
6595 drm_gem_object_unreference_unlocked(&obj->base);
6596 return ERR_PTR(-ENOMEM);
6597 }
6598
6599 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6600 if (ret) {
6601 drm_gem_object_unreference_unlocked(&obj->base);
6602 kfree(intel_fb);
6603 return ERR_PTR(ret);
6604 }
6605
6606 return &intel_fb->base;
6607}
6608
6609static u32
6610intel_framebuffer_pitch_for_width(int width, int bpp)
6611{
6612 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6613 return ALIGN(pitch, 64);
6614}
6615
6616static u32
6617intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6618{
6619 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6620 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6621}
6622
6623static struct drm_framebuffer *
6624intel_framebuffer_create_for_mode(struct drm_device *dev,
6625 struct drm_display_mode *mode,
6626 int depth, int bpp)
6627{
6628 struct drm_i915_gem_object *obj;
Chris Wilson0fed39b2012-11-05 22:25:07 +00006629 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
Chris Wilsond2dff872011-04-19 08:36:26 +01006630
6631 obj = i915_gem_alloc_object(dev,
6632 intel_framebuffer_size_for_mode(mode, bpp));
6633 if (obj == NULL)
6634 return ERR_PTR(-ENOMEM);
6635
6636 mode_cmd.width = mode->hdisplay;
6637 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006638 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6639 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00006640 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01006641
6642 return intel_framebuffer_create(dev, &mode_cmd, obj);
6643}
6644
6645static struct drm_framebuffer *
6646mode_fits_in_fbdev(struct drm_device *dev,
6647 struct drm_display_mode *mode)
6648{
6649 struct drm_i915_private *dev_priv = dev->dev_private;
6650 struct drm_i915_gem_object *obj;
6651 struct drm_framebuffer *fb;
6652
6653 if (dev_priv->fbdev == NULL)
6654 return NULL;
6655
6656 obj = dev_priv->fbdev->ifb.obj;
6657 if (obj == NULL)
6658 return NULL;
6659
6660 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006661 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6662 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01006663 return NULL;
6664
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006665 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01006666 return NULL;
6667
6668 return fb;
6669}
6670
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006671bool intel_get_load_detect_pipe(struct drm_connector *connector,
Chris Wilson71731882011-04-19 23:10:58 +01006672 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01006673 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006674{
6675 struct intel_crtc *intel_crtc;
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006676 struct intel_encoder *intel_encoder =
6677 intel_attached_encoder(connector);
Jesse Barnes79e53942008-11-07 14:24:08 -08006678 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006679 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006680 struct drm_crtc *crtc = NULL;
6681 struct drm_device *dev = encoder->dev;
Daniel Vetter94352cf2012-07-05 22:51:56 +02006682 struct drm_framebuffer *fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006683 int i = -1;
6684
Chris Wilsond2dff872011-04-19 08:36:26 +01006685 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6686 connector->base.id, drm_get_connector_name(connector),
6687 encoder->base.id, drm_get_encoder_name(encoder));
6688
Jesse Barnes79e53942008-11-07 14:24:08 -08006689 /*
6690 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01006691 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006692 * - if the connector already has an assigned crtc, use it (but make
6693 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01006694 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006695 * - try to find the first unused crtc that can drive this connector,
6696 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08006697 */
6698
6699 /* See if we already have a CRTC for this connector */
6700 if (encoder->crtc) {
6701 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01006702
Daniel Vetter24218aa2012-08-12 19:27:11 +02006703 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006704 old->load_detect_temp = false;
6705
6706 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006707 if (connector->dpms != DRM_MODE_DPMS_ON)
6708 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01006709
Chris Wilson71731882011-04-19 23:10:58 +01006710 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006711 }
6712
6713 /* Find an unused one (if possible) */
6714 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6715 i++;
6716 if (!(encoder->possible_crtcs & (1 << i)))
6717 continue;
6718 if (!possible_crtc->enabled) {
6719 crtc = possible_crtc;
6720 break;
6721 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006722 }
6723
6724 /*
6725 * If we didn't find an unused CRTC, don't use any.
6726 */
6727 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01006728 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6729 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006730 }
6731
Daniel Vetterfc303102012-07-09 10:40:58 +02006732 intel_encoder->new_crtc = to_intel_crtc(crtc);
6733 to_intel_connector(connector)->new_encoder = intel_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006734
6735 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02006736 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01006737 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01006738 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006739
Chris Wilson64927112011-04-20 07:25:26 +01006740 if (!mode)
6741 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08006742
Chris Wilsond2dff872011-04-19 08:36:26 +01006743 /* We need a framebuffer large enough to accommodate all accesses
6744 * that the plane may generate whilst we perform load detection.
6745 * We can not rely on the fbcon either being present (we get called
6746 * during its initialisation to detect all boot displays, or it may
6747 * not even exist) or that it is large enough to satisfy the
6748 * requested mode.
6749 */
Daniel Vetter94352cf2012-07-05 22:51:56 +02006750 fb = mode_fits_in_fbdev(dev, mode);
6751 if (fb == NULL) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006752 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006753 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6754 old->release_fb = fb;
Chris Wilsond2dff872011-04-19 08:36:26 +01006755 } else
6756 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
Daniel Vetter94352cf2012-07-05 22:51:56 +02006757 if (IS_ERR(fb)) {
Chris Wilsond2dff872011-04-19 08:36:26 +01006758 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Chris Wilson0e8b3d32012-11-05 22:25:08 +00006759 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006760 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006761
Daniel Vetter94352cf2012-07-05 22:51:56 +02006762 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01006763 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01006764 if (old->release_fb)
6765 old->release_fb->funcs->destroy(old->release_fb);
Chris Wilson0e8b3d32012-11-05 22:25:08 +00006766 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006767 }
Chris Wilson71731882011-04-19 23:10:58 +01006768
Jesse Barnes79e53942008-11-07 14:24:08 -08006769 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006770 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson71731882011-04-19 23:10:58 +01006771 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006772}
6773
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006774void intel_release_load_detect_pipe(struct drm_connector *connector,
Chris Wilson8261b192011-04-19 23:18:09 +01006775 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006776{
Daniel Vetterd2434ab2012-08-12 21:20:10 +02006777 struct intel_encoder *intel_encoder =
6778 intel_attached_encoder(connector);
Chris Wilson4ef69c72010-09-09 15:14:28 +01006779 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006780
Chris Wilsond2dff872011-04-19 08:36:26 +01006781 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6782 connector->base.id, drm_get_connector_name(connector),
6783 encoder->base.id, drm_get_encoder_name(encoder));
6784
Chris Wilson8261b192011-04-19 23:18:09 +01006785 if (old->load_detect_temp) {
Daniel Vetterfc303102012-07-09 10:40:58 +02006786 struct drm_crtc *crtc = encoder->crtc;
6787
6788 to_intel_connector(connector)->new_encoder = NULL;
6789 intel_encoder->new_crtc = NULL;
6790 intel_set_mode(crtc, NULL, 0, 0, NULL);
Chris Wilsond2dff872011-04-19 08:36:26 +01006791
6792 if (old->release_fb)
6793 old->release_fb->funcs->destroy(old->release_fb);
6794
Chris Wilson0622a532011-04-21 09:32:11 +01006795 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08006796 }
6797
Eric Anholtc751ce42010-03-25 11:48:48 -07006798 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02006799 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6800 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08006801}
6802
6803/* Returns the clock of the currently programmed mode of the given pipe. */
6804static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6805{
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6808 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08006809 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006810 u32 fp;
6811 intel_clock_t clock;
6812
6813 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01006814 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006815 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01006816 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006817
6818 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006819 if (IS_PINEVIEW(dev)) {
6820 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6821 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08006822 } else {
6823 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6824 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6825 }
6826
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006827 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006828 if (IS_PINEVIEW(dev))
6829 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6830 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08006831 else
6832 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08006833 DPLL_FPA01_P1_POST_DIV_SHIFT);
6834
6835 switch (dpll & DPLL_MODE_MASK) {
6836 case DPLLB_MODE_DAC_SERIAL:
6837 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6838 5 : 10;
6839 break;
6840 case DPLLB_MODE_LVDS:
6841 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6842 7 : 14;
6843 break;
6844 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08006845 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08006846 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6847 return 0;
6848 }
6849
6850 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08006851 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006852 } else {
6853 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6854
6855 if (is_lvds) {
6856 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6857 DPLL_FPA01_P1_POST_DIV_SHIFT);
6858 clock.p2 = 14;
6859
6860 if ((dpll & PLL_REF_INPUT_MASK) ==
6861 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6862 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08006863 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006864 } else
Shaohua Li21778322009-02-23 15:19:16 +08006865 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006866 } else {
6867 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6868 clock.p1 = 2;
6869 else {
6870 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6871 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6872 }
6873 if (dpll & PLL_P2_DIVIDE_BY_4)
6874 clock.p2 = 4;
6875 else
6876 clock.p2 = 2;
6877
Shaohua Li21778322009-02-23 15:19:16 +08006878 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006879 }
6880 }
6881
6882 /* XXX: It would be nice to validate the clocks, but we can't reuse
6883 * i830PllIsValid() because it relies on the xf86_config connector
6884 * configuration being accurate, which it isn't necessarily.
6885 */
6886
6887 return clock.dot;
6888}
6889
6890/** Returns the currently programmed mode of the given pipe. */
6891struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6892 struct drm_crtc *crtc)
6893{
Jesse Barnes548f2452011-02-17 10:40:53 -08006894 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006896 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006897 struct drm_display_mode *mode;
Paulo Zanonife2b8f92012-10-23 18:30:02 -02006898 int htot = I915_READ(HTOTAL(cpu_transcoder));
6899 int hsync = I915_READ(HSYNC(cpu_transcoder));
6900 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6901 int vsync = I915_READ(VSYNC(cpu_transcoder));
Jesse Barnes79e53942008-11-07 14:24:08 -08006902
6903 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6904 if (!mode)
6905 return NULL;
6906
6907 mode->clock = intel_crtc_clock_get(dev, crtc);
6908 mode->hdisplay = (htot & 0xffff) + 1;
6909 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6910 mode->hsync_start = (hsync & 0xffff) + 1;
6911 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6912 mode->vdisplay = (vtot & 0xffff) + 1;
6913 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6914 mode->vsync_start = (vsync & 0xffff) + 1;
6915 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6916
6917 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08006918
6919 return mode;
6920}
6921
Daniel Vetter3dec0092010-08-20 21:40:52 +02006922static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07006923{
6924 struct drm_device *dev = crtc->dev;
6925 drm_i915_private_t *dev_priv = dev->dev_private;
6926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6927 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006928 int dpll_reg = DPLL(pipe);
6929 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07006930
Eric Anholtbad720f2009-10-22 16:11:14 -07006931 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006932 return;
6933
6934 if (!dev_priv->lvds_downclock_avail)
6935 return;
6936
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006937 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006938 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006939 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006940
Sean Paul8ac5a6d2012-02-13 13:14:51 -05006941 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006942
6943 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6944 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006945 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006946
Jesse Barnes652c3932009-08-17 13:31:43 -07006947 dpll = I915_READ(dpll_reg);
6948 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08006949 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006950 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006951}
6952
6953static void intel_decrease_pllclock(struct drm_crtc *crtc)
6954{
6955 struct drm_device *dev = crtc->dev;
6956 drm_i915_private_t *dev_priv = dev->dev_private;
6957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07006958
Eric Anholtbad720f2009-10-22 16:11:14 -07006959 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006960 return;
6961
6962 if (!dev_priv->lvds_downclock_avail)
6963 return;
6964
6965 /*
6966 * Since this is called by a timer, we should never get here in
6967 * the manual case.
6968 */
6969 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01006970 int pipe = intel_crtc->pipe;
6971 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02006972 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01006973
Zhao Yakui44d98a62009-10-09 11:39:40 +08006974 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006975
Sean Paul8ac5a6d2012-02-13 13:14:51 -05006976 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006977
Chris Wilson074b5e12012-05-02 12:07:06 +01006978 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006979 dpll |= DISPLAY_RATE_SELECT_FPA1;
6980 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006981 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07006982 dpll = I915_READ(dpll_reg);
6983 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08006984 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006985 }
6986
6987}
6988
Chris Wilsonf047e392012-07-21 12:31:41 +01006989void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07006990{
Chris Wilsonf047e392012-07-21 12:31:41 +01006991 i915_update_gfx_val(dev->dev_private);
6992}
6993
6994void intel_mark_idle(struct drm_device *dev)
6995{
Chris Wilsonf047e392012-07-21 12:31:41 +01006996}
6997
6998void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6999{
7000 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07007001 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07007002
7003 if (!i915_powersave)
7004 return;
7005
Jesse Barnes652c3932009-08-17 13:31:43 -07007006 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07007007 if (!crtc->fb)
7008 continue;
7009
Chris Wilsonf047e392012-07-21 12:31:41 +01007010 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7011 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007012 }
Jesse Barnes652c3932009-08-17 13:31:43 -07007013}
7014
Chris Wilsonf047e392012-07-21 12:31:41 +01007015void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07007016{
Chris Wilsonf047e392012-07-21 12:31:41 +01007017 struct drm_device *dev = obj->base.dev;
7018 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07007019
Chris Wilsonf047e392012-07-21 12:31:41 +01007020 if (!i915_powersave)
Chris Wilsonacb87df2012-05-03 15:47:57 +01007021 return;
7022
Jesse Barnes652c3932009-08-17 13:31:43 -07007023 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7024 if (!crtc->fb)
7025 continue;
7026
Chris Wilsonf047e392012-07-21 12:31:41 +01007027 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7028 intel_decrease_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007029 }
7030}
7031
Jesse Barnes79e53942008-11-07 14:24:08 -08007032static void intel_crtc_destroy(struct drm_crtc *crtc)
7033{
7034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02007035 struct drm_device *dev = crtc->dev;
7036 struct intel_unpin_work *work;
7037 unsigned long flags;
7038
7039 spin_lock_irqsave(&dev->event_lock, flags);
7040 work = intel_crtc->unpin_work;
7041 intel_crtc->unpin_work = NULL;
7042 spin_unlock_irqrestore(&dev->event_lock, flags);
7043
7044 if (work) {
7045 cancel_work_sync(&work->work);
7046 kfree(work);
7047 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007048
7049 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02007050
Jesse Barnes79e53942008-11-07 14:24:08 -08007051 kfree(intel_crtc);
7052}
7053
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007054static void intel_unpin_work_fn(struct work_struct *__work)
7055{
7056 struct intel_unpin_work *work =
7057 container_of(__work, struct intel_unpin_work, work);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007058 struct drm_device *dev = work->crtc->dev;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007059
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007060 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01007061 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00007062 drm_gem_object_unreference(&work->pending_flip_obj->base);
7063 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00007064
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007065 intel_update_fbc(dev);
7066 mutex_unlock(&dev->struct_mutex);
7067
7068 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7069 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7070
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007071 kfree(work);
7072}
7073
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007074static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01007075 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007076{
7077 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00007080 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007081 unsigned long flags;
7082
7083 /* Ignore early vblank irqs */
7084 if (intel_crtc == NULL)
7085 return;
7086
7087 spin_lock_irqsave(&dev->event_lock, flags);
7088 work = intel_crtc->unpin_work;
Chris Wilsone7d841c2012-12-03 11:36:30 +00007089
7090 /* Ensure we don't miss a work->pending update ... */
7091 smp_rmb();
7092
7093 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007094 spin_unlock_irqrestore(&dev->event_lock, flags);
7095 return;
7096 }
7097
Chris Wilsone7d841c2012-12-03 11:36:30 +00007098 /* and that the unpin work is consistent wrt ->pending. */
7099 smp_rmb();
7100
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007101 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007102
Rob Clark45a066e2012-10-08 14:50:40 -05007103 if (work->event)
7104 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007105
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007106 drm_vblank_put(dev, intel_crtc->pipe);
7107
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007108 spin_unlock_irqrestore(&dev->event_lock, flags);
7109
Chris Wilson05394f32010-11-08 19:18:58 +00007110 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00007111
Chris Wilsone59f2ba2010-10-07 17:28:15 +01007112 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00007113 &obj->pending_flip.counter);
Chris Wilson5bb61642012-09-27 21:25:58 +01007114 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007115
7116 queue_work(dev_priv->wq, &work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07007117
7118 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007119}
7120
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007121void intel_finish_page_flip(struct drm_device *dev, int pipe)
7122{
7123 drm_i915_private_t *dev_priv = dev->dev_private;
7124 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7125
Mario Kleiner49b14a52010-12-09 07:00:07 +01007126 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007127}
7128
7129void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7130{
7131 drm_i915_private_t *dev_priv = dev->dev_private;
7132 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7133
Mario Kleiner49b14a52010-12-09 07:00:07 +01007134 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007135}
7136
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007137void intel_prepare_page_flip(struct drm_device *dev, int plane)
7138{
7139 drm_i915_private_t *dev_priv = dev->dev_private;
7140 struct intel_crtc *intel_crtc =
7141 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7142 unsigned long flags;
7143
Chris Wilsone7d841c2012-12-03 11:36:30 +00007144 /* NB: An MMIO update of the plane base pointer will also
7145 * generate a page-flip completion irq, i.e. every modeset
7146 * is also accompanied by a spurious intel_prepare_page_flip().
7147 */
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007148 spin_lock_irqsave(&dev->event_lock, flags);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007149 if (intel_crtc->unpin_work)
7150 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007151 spin_unlock_irqrestore(&dev->event_lock, flags);
7152}
7153
Chris Wilsone7d841c2012-12-03 11:36:30 +00007154inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7155{
7156 /* Ensure that the work item is consistent when activating it ... */
7157 smp_wmb();
7158 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7159 /* and that it is marked active as soon as the irq could fire. */
7160 smp_wmb();
7161}
7162
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007163static int intel_gen2_queue_flip(struct drm_device *dev,
7164 struct drm_crtc *crtc,
7165 struct drm_framebuffer *fb,
7166 struct drm_i915_gem_object *obj)
7167{
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007170 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007171 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007172 int ret;
7173
Daniel Vetter6d90c952012-04-26 23:28:05 +02007174 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007175 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007176 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007177
Daniel Vetter6d90c952012-04-26 23:28:05 +02007178 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007179 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007180 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007181
7182 /* Can't queue multiple flips, so wait for the previous
7183 * one to finish before executing the next.
7184 */
7185 if (intel_crtc->plane)
7186 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7187 else
7188 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007189 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7190 intel_ring_emit(ring, MI_NOOP);
7191 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7192 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7193 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02007194 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007195 intel_ring_emit(ring, 0); /* aux display base address, unused */
Chris Wilsone7d841c2012-12-03 11:36:30 +00007196
7197 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007198 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007199 return 0;
7200
7201err_unpin:
7202 intel_unpin_fb_obj(obj);
7203err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007204 return ret;
7205}
7206
7207static int intel_gen3_queue_flip(struct drm_device *dev,
7208 struct drm_crtc *crtc,
7209 struct drm_framebuffer *fb,
7210 struct drm_i915_gem_object *obj)
7211{
7212 struct drm_i915_private *dev_priv = dev->dev_private;
7213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007214 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007215 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007216 int ret;
7217
Daniel Vetter6d90c952012-04-26 23:28:05 +02007218 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007219 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007220 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007221
Daniel Vetter6d90c952012-04-26 23:28:05 +02007222 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007223 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007224 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007225
7226 if (intel_crtc->plane)
7227 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7228 else
7229 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007230 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7231 intel_ring_emit(ring, MI_NOOP);
7232 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7233 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7234 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02007235 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007236 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007237
Chris Wilsone7d841c2012-12-03 11:36:30 +00007238 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007239 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007240 return 0;
7241
7242err_unpin:
7243 intel_unpin_fb_obj(obj);
7244err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007245 return ret;
7246}
7247
7248static int intel_gen4_queue_flip(struct drm_device *dev,
7249 struct drm_crtc *crtc,
7250 struct drm_framebuffer *fb,
7251 struct drm_i915_gem_object *obj)
7252{
7253 struct drm_i915_private *dev_priv = dev->dev_private;
7254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7255 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007256 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007257 int ret;
7258
Daniel Vetter6d90c952012-04-26 23:28:05 +02007259 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007260 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007261 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007262
Daniel Vetter6d90c952012-04-26 23:28:05 +02007263 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007264 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007265 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007266
7267 /* i965+ uses the linear or tiled offsets from the
7268 * Display Registers (which do not change across a page-flip)
7269 * so we need only reprogram the base address.
7270 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02007271 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7272 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7273 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02007274 intel_ring_emit(ring,
7275 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7276 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007277
7278 /* XXX Enabling the panel-fitter across page-flip is so far
7279 * untested on non-native modes, so ignore it for now.
7280 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7281 */
7282 pf = 0;
7283 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007284 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007285
7286 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007287 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007288 return 0;
7289
7290err_unpin:
7291 intel_unpin_fb_obj(obj);
7292err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007293 return ret;
7294}
7295
7296static int intel_gen6_queue_flip(struct drm_device *dev,
7297 struct drm_crtc *crtc,
7298 struct drm_framebuffer *fb,
7299 struct drm_i915_gem_object *obj)
7300{
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007303 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007304 uint32_t pf, pipesrc;
7305 int ret;
7306
Daniel Vetter6d90c952012-04-26 23:28:05 +02007307 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007308 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007309 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007310
Daniel Vetter6d90c952012-04-26 23:28:05 +02007311 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007312 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007313 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007314
Daniel Vetter6d90c952012-04-26 23:28:05 +02007315 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7316 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7317 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Daniel Vetterc2c75132012-07-05 12:17:30 +02007318 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007319
Chris Wilson99d9acd2012-04-17 20:37:00 +01007320 /* Contrary to the suggestions in the documentation,
7321 * "Enable Panel Fitter" does not seem to be required when page
7322 * flipping with a non-native mode, and worse causes a normal
7323 * modeset to fail.
7324 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7325 */
7326 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007327 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02007328 intel_ring_emit(ring, pf | pipesrc);
Chris Wilsone7d841c2012-12-03 11:36:30 +00007329
7330 intel_mark_page_flip_active(intel_crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02007331 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007332 return 0;
7333
7334err_unpin:
7335 intel_unpin_fb_obj(obj);
7336err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007337 return ret;
7338}
7339
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007340/*
7341 * On gen7 we currently use the blit ring because (in early silicon at least)
7342 * the render ring doesn't give us interrpts for page flip completion, which
7343 * means clients will hang after the first flip is queued. Fortunately the
7344 * blit ring generates interrupts properly, so use it instead.
7345 */
7346static int intel_gen7_queue_flip(struct drm_device *dev,
7347 struct drm_crtc *crtc,
7348 struct drm_framebuffer *fb,
7349 struct drm_i915_gem_object *obj)
7350{
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7353 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007354 uint32_t plane_bit = 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007355 int ret;
7356
7357 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7358 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007359 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007360
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007361 switch(intel_crtc->plane) {
7362 case PLANE_A:
7363 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7364 break;
7365 case PLANE_B:
7366 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7367 break;
7368 case PLANE_C:
7369 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7370 break;
7371 default:
7372 WARN_ONCE(1, "unknown plane in flip command\n");
7373 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03007374 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007375 }
7376
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007377 ret = intel_ring_begin(ring, 4);
7378 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01007379 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007380
Daniel Vettercb05d8d2012-05-23 14:02:00 +02007381 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007382 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Daniel Vetterc2c75132012-07-05 12:17:30 +02007383 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007384 intel_ring_emit(ring, (MI_NOOP));
Chris Wilsone7d841c2012-12-03 11:36:30 +00007385
7386 intel_mark_page_flip_active(intel_crtc);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007387 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01007388 return 0;
7389
7390err_unpin:
7391 intel_unpin_fb_obj(obj);
7392err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007393 return ret;
7394}
7395
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007396static int intel_default_queue_flip(struct drm_device *dev,
7397 struct drm_crtc *crtc,
7398 struct drm_framebuffer *fb,
7399 struct drm_i915_gem_object *obj)
7400{
7401 return -ENODEV;
7402}
7403
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007404static int intel_crtc_page_flip(struct drm_crtc *crtc,
7405 struct drm_framebuffer *fb,
7406 struct drm_pending_vblank_event *event)
7407{
7408 struct drm_device *dev = crtc->dev;
7409 struct drm_i915_private *dev_priv = dev->dev_private;
7410 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00007411 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7413 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007414 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01007415 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007416
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03007417 /* Can't change pixel format via MI display flips. */
7418 if (fb->pixel_format != crtc->fb->pixel_format)
7419 return -EINVAL;
7420
7421 /*
7422 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7423 * Note that pitch changes could also affect these register.
7424 */
7425 if (INTEL_INFO(dev)->gen > 3 &&
7426 (fb->offsets[0] != crtc->fb->offsets[0] ||
7427 fb->pitches[0] != crtc->fb->pitches[0]))
7428 return -EINVAL;
7429
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007430 work = kzalloc(sizeof *work, GFP_KERNEL);
7431 if (work == NULL)
7432 return -ENOMEM;
7433
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007434 work->event = event;
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007435 work->crtc = crtc;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007436 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08007437 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007438 INIT_WORK(&work->work, intel_unpin_work_fn);
7439
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007440 ret = drm_vblank_get(dev, intel_crtc->pipe);
7441 if (ret)
7442 goto free_work;
7443
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007444 /* We borrow the event spin lock for protecting unpin_work */
7445 spin_lock_irqsave(&dev->event_lock, flags);
7446 if (intel_crtc->unpin_work) {
7447 spin_unlock_irqrestore(&dev->event_lock, flags);
7448 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007449 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01007450
7451 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007452 return -EBUSY;
7453 }
7454 intel_crtc->unpin_work = work;
7455 spin_unlock_irqrestore(&dev->event_lock, flags);
7456
7457 intel_fb = to_intel_framebuffer(fb);
7458 obj = intel_fb->obj;
7459
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007460 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7461 flush_workqueue(dev_priv->wq);
7462
Chris Wilson79158102012-05-23 11:13:58 +01007463 ret = i915_mutex_lock_interruptible(dev);
7464 if (ret)
7465 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007466
Jesse Barnes75dfca82010-02-10 15:09:44 -08007467 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00007468 drm_gem_object_reference(&work->old_fb_obj->base);
7469 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007470
7471 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01007472
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007473 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007474
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01007475 work->enable_stall_check = true;
7476
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007477 /* Block clients from rendering to the new back buffer until
7478 * the flip occurs and the object is no longer visible.
7479 */
Chris Wilson05394f32010-11-08 19:18:58 +00007480 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007481 atomic_inc(&intel_crtc->unpin_work_count);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007482
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007483 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7484 if (ret)
7485 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007486
Chris Wilson7782de32011-07-08 12:22:41 +01007487 intel_disable_fbc(dev);
Chris Wilsonf047e392012-07-21 12:31:41 +01007488 intel_mark_fb_busy(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007489 mutex_unlock(&dev->struct_mutex);
7490
Jesse Barnese5510fa2010-07-01 16:48:37 -07007491 trace_i915_flip_request(intel_crtc->plane, obj);
7492
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007493 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01007494
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007495cleanup_pending:
Chris Wilsonb4a98e52012-11-01 09:26:26 +00007496 atomic_dec(&intel_crtc->unpin_work_count);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007497 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilson05394f32010-11-08 19:18:58 +00007498 drm_gem_object_unreference(&work->old_fb_obj->base);
7499 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01007500 mutex_unlock(&dev->struct_mutex);
7501
Chris Wilson79158102012-05-23 11:13:58 +01007502cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01007503 spin_lock_irqsave(&dev->event_lock, flags);
7504 intel_crtc->unpin_work = NULL;
7505 spin_unlock_irqrestore(&dev->event_lock, flags);
7506
Jesse Barnes7317c75e62011-08-29 09:45:28 -07007507 drm_vblank_put(dev, intel_crtc->pipe);
7508free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01007509 kfree(work);
7510
7511 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007512}
7513
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007514static struct drm_crtc_helper_funcs intel_helper_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007515 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7516 .load_lut = intel_crtc_load_lut,
Daniel Vetter976f8a22012-07-08 22:34:21 +02007517 .disable = intel_crtc_noop,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007518};
7519
Daniel Vetter6ed0f792012-07-08 19:41:43 +02007520bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7521{
7522 struct intel_encoder *other_encoder;
7523 struct drm_crtc *crtc = &encoder->new_crtc->base;
7524
7525 if (WARN_ON(!crtc))
7526 return false;
7527
7528 list_for_each_entry(other_encoder,
7529 &crtc->dev->mode_config.encoder_list,
7530 base.head) {
7531
7532 if (&other_encoder->new_crtc->base != crtc ||
7533 encoder == other_encoder)
7534 continue;
7535 else
7536 return true;
7537 }
7538
7539 return false;
7540}
7541
Daniel Vetter50f56112012-07-02 09:35:43 +02007542static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7543 struct drm_crtc *crtc)
7544{
7545 struct drm_device *dev;
7546 struct drm_crtc *tmp;
7547 int crtc_mask = 1;
7548
7549 WARN(!crtc, "checking null crtc?\n");
7550
7551 dev = crtc->dev;
7552
7553 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7554 if (tmp == crtc)
7555 break;
7556 crtc_mask <<= 1;
7557 }
7558
7559 if (encoder->possible_crtcs & crtc_mask)
7560 return true;
7561 return false;
7562}
7563
Daniel Vetter9a935852012-07-05 22:34:27 +02007564/**
7565 * intel_modeset_update_staged_output_state
7566 *
7567 * Updates the staged output configuration state, e.g. after we've read out the
7568 * current hw state.
7569 */
7570static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7571{
7572 struct intel_encoder *encoder;
7573 struct intel_connector *connector;
7574
7575 list_for_each_entry(connector, &dev->mode_config.connector_list,
7576 base.head) {
7577 connector->new_encoder =
7578 to_intel_encoder(connector->base.encoder);
7579 }
7580
7581 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7582 base.head) {
7583 encoder->new_crtc =
7584 to_intel_crtc(encoder->base.crtc);
7585 }
7586}
7587
7588/**
7589 * intel_modeset_commit_output_state
7590 *
7591 * This function copies the stage display pipe configuration to the real one.
7592 */
7593static void intel_modeset_commit_output_state(struct drm_device *dev)
7594{
7595 struct intel_encoder *encoder;
7596 struct intel_connector *connector;
7597
7598 list_for_each_entry(connector, &dev->mode_config.connector_list,
7599 base.head) {
7600 connector->base.encoder = &connector->new_encoder->base;
7601 }
7602
7603 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7604 base.head) {
7605 encoder->base.crtc = &encoder->new_crtc->base;
7606 }
7607}
7608
Daniel Vetter7758a112012-07-08 19:40:39 +02007609static struct drm_display_mode *
7610intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7611 struct drm_display_mode *mode)
7612{
7613 struct drm_device *dev = crtc->dev;
7614 struct drm_display_mode *adjusted_mode;
7615 struct drm_encoder_helper_funcs *encoder_funcs;
7616 struct intel_encoder *encoder;
7617
7618 adjusted_mode = drm_mode_duplicate(dev, mode);
7619 if (!adjusted_mode)
7620 return ERR_PTR(-ENOMEM);
7621
7622 /* Pass our mode to the connectors and the CRTC to give them a chance to
7623 * adjust it according to limitations or connector properties, and also
7624 * a chance to reject the mode entirely.
7625 */
7626 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7627 base.head) {
7628
7629 if (&encoder->new_crtc->base != crtc)
7630 continue;
7631 encoder_funcs = encoder->base.helper_private;
7632 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7633 adjusted_mode))) {
7634 DRM_DEBUG_KMS("Encoder fixup failed\n");
7635 goto fail;
7636 }
7637 }
7638
7639 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7640 DRM_DEBUG_KMS("CRTC fixup failed\n");
7641 goto fail;
7642 }
7643 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7644
7645 return adjusted_mode;
7646fail:
7647 drm_mode_destroy(dev, adjusted_mode);
7648 return ERR_PTR(-EINVAL);
7649}
7650
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007651/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7652 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7653static void
7654intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7655 unsigned *prepare_pipes, unsigned *disable_pipes)
7656{
7657 struct intel_crtc *intel_crtc;
7658 struct drm_device *dev = crtc->dev;
7659 struct intel_encoder *encoder;
7660 struct intel_connector *connector;
7661 struct drm_crtc *tmp_crtc;
7662
7663 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7664
7665 /* Check which crtcs have changed outputs connected to them, these need
7666 * to be part of the prepare_pipes mask. We don't (yet) support global
7667 * modeset across multiple crtcs, so modeset_pipes will only have one
7668 * bit set at most. */
7669 list_for_each_entry(connector, &dev->mode_config.connector_list,
7670 base.head) {
7671 if (connector->base.encoder == &connector->new_encoder->base)
7672 continue;
7673
7674 if (connector->base.encoder) {
7675 tmp_crtc = connector->base.encoder->crtc;
7676
7677 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7678 }
7679
7680 if (connector->new_encoder)
7681 *prepare_pipes |=
7682 1 << connector->new_encoder->new_crtc->pipe;
7683 }
7684
7685 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7686 base.head) {
7687 if (encoder->base.crtc == &encoder->new_crtc->base)
7688 continue;
7689
7690 if (encoder->base.crtc) {
7691 tmp_crtc = encoder->base.crtc;
7692
7693 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7694 }
7695
7696 if (encoder->new_crtc)
7697 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7698 }
7699
7700 /* Check for any pipes that will be fully disabled ... */
7701 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7702 base.head) {
7703 bool used = false;
7704
7705 /* Don't try to disable disabled crtcs. */
7706 if (!intel_crtc->base.enabled)
7707 continue;
7708
7709 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7710 base.head) {
7711 if (encoder->new_crtc == intel_crtc)
7712 used = true;
7713 }
7714
7715 if (!used)
7716 *disable_pipes |= 1 << intel_crtc->pipe;
7717 }
7718
7719
7720 /* set_mode is also used to update properties on life display pipes. */
7721 intel_crtc = to_intel_crtc(crtc);
7722 if (crtc->enabled)
7723 *prepare_pipes |= 1 << intel_crtc->pipe;
7724
7725 /* We only support modeset on one single crtc, hence we need to do that
7726 * only for the passed in crtc iff we change anything else than just
7727 * disable crtcs.
7728 *
7729 * This is actually not true, to be fully compatible with the old crtc
7730 * helper we automatically disable _any_ output (i.e. doesn't need to be
7731 * connected to the crtc we're modesetting on) if it's disconnected.
7732 * Which is a rather nutty api (since changed the output configuration
7733 * without userspace's explicit request can lead to confusion), but
7734 * alas. Hence we currently need to modeset on all pipes we prepare. */
7735 if (*prepare_pipes)
7736 *modeset_pipes = *prepare_pipes;
7737
7738 /* ... and mask these out. */
7739 *modeset_pipes &= ~(*disable_pipes);
7740 *prepare_pipes &= ~(*disable_pipes);
7741}
7742
Daniel Vetterea9d7582012-07-10 10:42:52 +02007743static bool intel_crtc_in_use(struct drm_crtc *crtc)
7744{
7745 struct drm_encoder *encoder;
7746 struct drm_device *dev = crtc->dev;
7747
7748 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7749 if (encoder->crtc == crtc)
7750 return true;
7751
7752 return false;
7753}
7754
7755static void
7756intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7757{
7758 struct intel_encoder *intel_encoder;
7759 struct intel_crtc *intel_crtc;
7760 struct drm_connector *connector;
7761
7762 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7763 base.head) {
7764 if (!intel_encoder->base.crtc)
7765 continue;
7766
7767 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7768
7769 if (prepare_pipes & (1 << intel_crtc->pipe))
7770 intel_encoder->connectors_active = false;
7771 }
7772
7773 intel_modeset_commit_output_state(dev);
7774
7775 /* Update computed state. */
7776 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7777 base.head) {
7778 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7779 }
7780
7781 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7782 if (!connector->encoder || !connector->encoder->crtc)
7783 continue;
7784
7785 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7786
7787 if (prepare_pipes & (1 << intel_crtc->pipe)) {
Daniel Vetter68d34722012-09-06 22:08:35 +02007788 struct drm_property *dpms_property =
7789 dev->mode_config.dpms_property;
7790
Daniel Vetterea9d7582012-07-10 10:42:52 +02007791 connector->dpms = DRM_MODE_DPMS_ON;
Rob Clark662595d2012-10-11 20:36:04 -05007792 drm_object_property_set_value(&connector->base,
Daniel Vetter68d34722012-09-06 22:08:35 +02007793 dpms_property,
7794 DRM_MODE_DPMS_ON);
Daniel Vetterea9d7582012-07-10 10:42:52 +02007795
7796 intel_encoder = to_intel_encoder(connector->encoder);
7797 intel_encoder->connectors_active = true;
7798 }
7799 }
7800
7801}
7802
Daniel Vetter25c5b262012-07-08 22:08:04 +02007803#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7804 list_for_each_entry((intel_crtc), \
7805 &(dev)->mode_config.crtc_list, \
7806 base.head) \
7807 if (mask & (1 <<(intel_crtc)->pipe)) \
7808
Daniel Vetterb9805142012-08-31 17:37:33 +02007809void
Daniel Vetter8af6cf82012-07-10 09:50:11 +02007810intel_modeset_check_state(struct drm_device *dev)
7811{
7812 struct intel_crtc *crtc;
7813 struct intel_encoder *encoder;
7814 struct intel_connector *connector;
7815
7816 list_for_each_entry(connector, &dev->mode_config.connector_list,
7817 base.head) {
7818 /* This also checks the encoder/connector hw state with the
7819 * ->get_hw_state callbacks. */
7820 intel_connector_check_state(connector);
7821
7822 WARN(&connector->new_encoder->base != connector->base.encoder,
7823 "connector's staged encoder doesn't match current encoder\n");
7824 }
7825
7826 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7827 base.head) {
7828 bool enabled = false;
7829 bool active = false;
7830 enum pipe pipe, tracked_pipe;
7831
7832 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7833 encoder->base.base.id,
7834 drm_get_encoder_name(&encoder->base));
7835
7836 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7837 "encoder's stage crtc doesn't match current crtc\n");
7838 WARN(encoder->connectors_active && !encoder->base.crtc,
7839 "encoder's active_connectors set, but no crtc\n");
7840
7841 list_for_each_entry(connector, &dev->mode_config.connector_list,
7842 base.head) {
7843 if (connector->base.encoder != &encoder->base)
7844 continue;
7845 enabled = true;
7846 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7847 active = true;
7848 }
7849 WARN(!!encoder->base.crtc != enabled,
7850 "encoder's enabled state mismatch "
7851 "(expected %i, found %i)\n",
7852 !!encoder->base.crtc, enabled);
7853 WARN(active && !encoder->base.crtc,
7854 "active encoder with no crtc\n");
7855
7856 WARN(encoder->connectors_active != active,
7857 "encoder's computed active state doesn't match tracked active state "
7858 "(expected %i, found %i)\n", active, encoder->connectors_active);
7859
7860 active = encoder->get_hw_state(encoder, &pipe);
7861 WARN(active != encoder->connectors_active,
7862 "encoder's hw state doesn't match sw tracking "
7863 "(expected %i, found %i)\n",
7864 encoder->connectors_active, active);
7865
7866 if (!encoder->base.crtc)
7867 continue;
7868
7869 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7870 WARN(active && pipe != tracked_pipe,
7871 "active encoder's pipe doesn't match"
7872 "(expected %i, found %i)\n",
7873 tracked_pipe, pipe);
7874
7875 }
7876
7877 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7878 base.head) {
7879 bool enabled = false;
7880 bool active = false;
7881
7882 DRM_DEBUG_KMS("[CRTC:%d]\n",
7883 crtc->base.base.id);
7884
7885 WARN(crtc->active && !crtc->base.enabled,
7886 "active crtc, but not enabled in sw tracking\n");
7887
7888 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7889 base.head) {
7890 if (encoder->base.crtc != &crtc->base)
7891 continue;
7892 enabled = true;
7893 if (encoder->connectors_active)
7894 active = true;
7895 }
7896 WARN(active != crtc->active,
7897 "crtc's computed active state doesn't match tracked active state "
7898 "(expected %i, found %i)\n", active, crtc->active);
7899 WARN(enabled != crtc->base.enabled,
7900 "crtc's computed enabled state doesn't match tracked enabled state "
7901 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7902
7903 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7904 }
7905}
7906
Daniel Vettera6778b32012-07-02 09:56:42 +02007907bool intel_set_mode(struct drm_crtc *crtc,
7908 struct drm_display_mode *mode,
Daniel Vetter94352cf2012-07-05 22:51:56 +02007909 int x, int y, struct drm_framebuffer *fb)
Daniel Vettera6778b32012-07-02 09:56:42 +02007910{
7911 struct drm_device *dev = crtc->dev;
Daniel Vetterdbf2b54e2012-07-02 11:18:29 +02007912 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vettera6778b32012-07-02 09:56:42 +02007913 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
Daniel Vetter25c5b262012-07-08 22:08:04 +02007914 struct intel_crtc *intel_crtc;
7915 unsigned disable_pipes, prepare_pipes, modeset_pipes;
Daniel Vettera6778b32012-07-02 09:56:42 +02007916 bool ret = true;
7917
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007918 intel_modeset_affected_pipes(crtc, &modeset_pipes,
Daniel Vetter25c5b262012-07-08 22:08:04 +02007919 &prepare_pipes, &disable_pipes);
7920
7921 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7922 modeset_pipes, prepare_pipes, disable_pipes);
Daniel Vettere2e1ed42012-07-08 21:14:38 +02007923
Daniel Vetter976f8a22012-07-08 22:34:21 +02007924 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7925 intel_crtc_disable(&intel_crtc->base);
7926
Daniel Vettera6778b32012-07-02 09:56:42 +02007927 saved_hwmode = crtc->hwmode;
7928 saved_mode = crtc->mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02007929
Daniel Vetter25c5b262012-07-08 22:08:04 +02007930 /* Hack: Because we don't (yet) support global modeset on multiple
7931 * crtcs, we don't keep track of the new mode for more than one crtc.
7932 * Hence simply check whether any bit is set in modeset_pipes in all the
7933 * pieces of code that are not yet converted to deal with mutliple crtcs
7934 * changing their mode at the same time. */
7935 adjusted_mode = NULL;
7936 if (modeset_pipes) {
7937 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7938 if (IS_ERR(adjusted_mode)) {
7939 return false;
7940 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007941 }
7942
Daniel Vetterea9d7582012-07-10 10:42:52 +02007943 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7944 if (intel_crtc->base.enabled)
7945 dev_priv->display.crtc_disable(&intel_crtc->base);
7946 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007947
Daniel Vetter6c4c86f2012-09-10 21:58:30 +02007948 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7949 * to set it here already despite that we pass it down the callchain.
7950 */
7951 if (modeset_pipes)
Daniel Vetter25c5b262012-07-08 22:08:04 +02007952 crtc->mode = *mode;
Daniel Vetter7758a112012-07-08 19:40:39 +02007953
Daniel Vetterea9d7582012-07-10 10:42:52 +02007954 /* Only after disabling all output pipelines that will be changed can we
7955 * update the the output configuration. */
7956 intel_modeset_update_state(dev, prepare_pipes);
7957
Daniel Vetter47fab732012-10-26 10:58:18 +02007958 if (dev_priv->display.modeset_global_resources)
7959 dev_priv->display.modeset_global_resources(dev);
7960
Daniel Vettera6778b32012-07-02 09:56:42 +02007961 /* Set up the DPLL and any encoders state that needs to adjust or depend
7962 * on the DPLL.
7963 */
Daniel Vetter25c5b262012-07-08 22:08:04 +02007964 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7965 ret = !intel_crtc_mode_set(&intel_crtc->base,
7966 mode, adjusted_mode,
7967 x, y, fb);
7968 if (!ret)
7969 goto done;
Daniel Vettera6778b32012-07-02 09:56:42 +02007970 }
7971
7972 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
Daniel Vetter25c5b262012-07-08 22:08:04 +02007973 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7974 dev_priv->display.crtc_enable(&intel_crtc->base);
Daniel Vettera6778b32012-07-02 09:56:42 +02007975
Daniel Vetter25c5b262012-07-08 22:08:04 +02007976 if (modeset_pipes) {
7977 /* Store real post-adjustment hardware mode. */
7978 crtc->hwmode = *adjusted_mode;
Daniel Vettera6778b32012-07-02 09:56:42 +02007979
Daniel Vetter25c5b262012-07-08 22:08:04 +02007980 /* Calculate and store various constants which
7981 * are later needed by vblank and swap-completion
7982 * timestamping. They are derived from true hwmode.
7983 */
7984 drm_calc_timestamping_constants(crtc);
7985 }
Daniel Vettera6778b32012-07-02 09:56:42 +02007986
7987 /* FIXME: add subpixel order */
7988done:
7989 drm_mode_destroy(dev, adjusted_mode);
Daniel Vetter25c5b262012-07-08 22:08:04 +02007990 if (!ret && crtc->enabled) {
Daniel Vettera6778b32012-07-02 09:56:42 +02007991 crtc->hwmode = saved_hwmode;
7992 crtc->mode = saved_mode;
Daniel Vetter8af6cf82012-07-10 09:50:11 +02007993 } else {
7994 intel_modeset_check_state(dev);
Daniel Vettera6778b32012-07-02 09:56:42 +02007995 }
7996
7997 return ret;
7998}
7999
Daniel Vetter25c5b262012-07-08 22:08:04 +02008000#undef for_each_intel_crtc_masked
8001
Daniel Vetterd9e55602012-07-04 22:16:09 +02008002static void intel_set_config_free(struct intel_set_config *config)
8003{
8004 if (!config)
8005 return;
8006
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008007 kfree(config->save_connector_encoders);
8008 kfree(config->save_encoder_crtcs);
Daniel Vetterd9e55602012-07-04 22:16:09 +02008009 kfree(config);
8010}
8011
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008012static int intel_set_config_save_state(struct drm_device *dev,
8013 struct intel_set_config *config)
8014{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008015 struct drm_encoder *encoder;
8016 struct drm_connector *connector;
8017 int count;
8018
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008019 config->save_encoder_crtcs =
8020 kcalloc(dev->mode_config.num_encoder,
8021 sizeof(struct drm_crtc *), GFP_KERNEL);
8022 if (!config->save_encoder_crtcs)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008023 return -ENOMEM;
8024
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008025 config->save_connector_encoders =
8026 kcalloc(dev->mode_config.num_connector,
8027 sizeof(struct drm_encoder *), GFP_KERNEL);
8028 if (!config->save_connector_encoders)
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008029 return -ENOMEM;
8030
8031 /* Copy data. Note that driver private data is not affected.
8032 * Should anything bad happen only the expected state is
8033 * restored, not the drivers personal bookkeeping.
8034 */
8035 count = 0;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008036 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008037 config->save_encoder_crtcs[count++] = encoder->crtc;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008038 }
8039
8040 count = 0;
8041 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
Daniel Vetter1aa4b622012-07-05 16:20:48 +02008042 config->save_connector_encoders[count++] = connector->encoder;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008043 }
8044
8045 return 0;
8046}
8047
8048static void intel_set_config_restore_state(struct drm_device *dev,
8049 struct intel_set_config *config)
8050{
Daniel Vetter9a935852012-07-05 22:34:27 +02008051 struct intel_encoder *encoder;
8052 struct intel_connector *connector;
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008053 int count;
8054
8055 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008056 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8057 encoder->new_crtc =
8058 to_intel_crtc(config->save_encoder_crtcs[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008059 }
8060
8061 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008062 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8063 connector->new_encoder =
8064 to_intel_encoder(config->save_connector_encoders[count++]);
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008065 }
8066}
8067
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008068static void
8069intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8070 struct intel_set_config *config)
8071{
8072
8073 /* We should be able to check here if the fb has the same properties
8074 * and then just flip_or_move it */
8075 if (set->crtc->fb != set->fb) {
8076 /* If we have no fb then treat it as a full mode set */
8077 if (set->crtc->fb == NULL) {
8078 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8079 config->mode_changed = true;
8080 } else if (set->fb == NULL) {
8081 config->mode_changed = true;
8082 } else if (set->fb->depth != set->crtc->fb->depth) {
8083 config->mode_changed = true;
8084 } else if (set->fb->bits_per_pixel !=
8085 set->crtc->fb->bits_per_pixel) {
8086 config->mode_changed = true;
8087 } else
8088 config->fb_changed = true;
8089 }
8090
Daniel Vetter835c5872012-07-10 18:11:08 +02008091 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008092 config->fb_changed = true;
8093
8094 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8095 DRM_DEBUG_KMS("modes are different, full mode set\n");
8096 drm_mode_debug_printmodeline(&set->crtc->mode);
8097 drm_mode_debug_printmodeline(set->mode);
8098 config->mode_changed = true;
8099 }
8100}
8101
Daniel Vetter2e431052012-07-04 22:42:15 +02008102static int
Daniel Vetter9a935852012-07-05 22:34:27 +02008103intel_modeset_stage_output_state(struct drm_device *dev,
8104 struct drm_mode_set *set,
8105 struct intel_set_config *config)
Daniel Vetter50f56112012-07-02 09:35:43 +02008106{
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008107 struct drm_crtc *new_crtc;
Daniel Vetter9a935852012-07-05 22:34:27 +02008108 struct intel_connector *connector;
8109 struct intel_encoder *encoder;
Daniel Vetter2e431052012-07-04 22:42:15 +02008110 int count, ro;
Daniel Vetter50f56112012-07-02 09:35:43 +02008111
Daniel Vetter9a935852012-07-05 22:34:27 +02008112 /* The upper layers ensure that we either disabl a crtc or have a list
8113 * of connectors. For paranoia, double-check this. */
8114 WARN_ON(!set->fb && (set->num_connectors != 0));
8115 WARN_ON(set->fb && (set->num_connectors == 0));
8116
Daniel Vetter50f56112012-07-02 09:35:43 +02008117 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008118 list_for_each_entry(connector, &dev->mode_config.connector_list,
8119 base.head) {
8120 /* Otherwise traverse passed in connector list and get encoders
8121 * for them. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008122 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02008123 if (set->connectors[ro] == &connector->base) {
8124 connector->new_encoder = connector->encoder;
Daniel Vetter50f56112012-07-02 09:35:43 +02008125 break;
8126 }
8127 }
8128
Daniel Vetter9a935852012-07-05 22:34:27 +02008129 /* If we disable the crtc, disable all its connectors. Also, if
8130 * the connector is on the changing crtc but not on the new
8131 * connector list, disable it. */
8132 if ((!set->fb || ro == set->num_connectors) &&
8133 connector->base.encoder &&
8134 connector->base.encoder->crtc == set->crtc) {
8135 connector->new_encoder = NULL;
8136
8137 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8138 connector->base.base.id,
8139 drm_get_connector_name(&connector->base));
8140 }
8141
8142
8143 if (&connector->new_encoder->base != connector->base.encoder) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008144 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008145 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02008146 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008147 }
8148 /* connector->new_encoder is now updated for all connectors. */
8149
8150 /* Update crtc of enabled connectors. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008151 count = 0;
Daniel Vetter9a935852012-07-05 22:34:27 +02008152 list_for_each_entry(connector, &dev->mode_config.connector_list,
8153 base.head) {
8154 if (!connector->new_encoder)
Daniel Vetter50f56112012-07-02 09:35:43 +02008155 continue;
8156
Daniel Vetter9a935852012-07-05 22:34:27 +02008157 new_crtc = connector->new_encoder->base.crtc;
Daniel Vetter50f56112012-07-02 09:35:43 +02008158
8159 for (ro = 0; ro < set->num_connectors; ro++) {
Daniel Vetter9a935852012-07-05 22:34:27 +02008160 if (set->connectors[ro] == &connector->base)
Daniel Vetter50f56112012-07-02 09:35:43 +02008161 new_crtc = set->crtc;
8162 }
8163
8164 /* Make sure the new CRTC will work with the encoder */
Daniel Vetter9a935852012-07-05 22:34:27 +02008165 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8166 new_crtc)) {
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008167 return -EINVAL;
Daniel Vetter50f56112012-07-02 09:35:43 +02008168 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008169 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8170
8171 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8172 connector->base.base.id,
8173 drm_get_connector_name(&connector->base),
8174 new_crtc->base.id);
8175 }
8176
8177 /* Check for any encoders that needs to be disabled. */
8178 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8179 base.head) {
8180 list_for_each_entry(connector,
8181 &dev->mode_config.connector_list,
8182 base.head) {
8183 if (connector->new_encoder == encoder) {
8184 WARN_ON(!connector->new_encoder->new_crtc);
8185
8186 goto next_encoder;
8187 }
8188 }
8189 encoder->new_crtc = NULL;
8190next_encoder:
8191 /* Only now check for crtc changes so we don't miss encoders
8192 * that will be disabled. */
8193 if (&encoder->new_crtc->base != encoder->base.crtc) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008194 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008195 config->mode_changed = true;
Daniel Vetter50f56112012-07-02 09:35:43 +02008196 }
8197 }
Daniel Vetter9a935852012-07-05 22:34:27 +02008198 /* Now we've also updated encoder->new_crtc for all encoders. */
Daniel Vetter50f56112012-07-02 09:35:43 +02008199
Daniel Vetter2e431052012-07-04 22:42:15 +02008200 return 0;
8201}
8202
8203static int intel_crtc_set_config(struct drm_mode_set *set)
8204{
8205 struct drm_device *dev;
Daniel Vetter2e431052012-07-04 22:42:15 +02008206 struct drm_mode_set save_set;
8207 struct intel_set_config *config;
8208 int ret;
Daniel Vetter2e431052012-07-04 22:42:15 +02008209
Daniel Vetter8d3e3752012-07-05 16:09:09 +02008210 BUG_ON(!set);
8211 BUG_ON(!set->crtc);
8212 BUG_ON(!set->crtc->helper_private);
Daniel Vetter2e431052012-07-04 22:42:15 +02008213
8214 if (!set->mode)
8215 set->fb = NULL;
8216
Daniel Vetter431e50f2012-07-10 17:53:42 +02008217 /* The fb helper likes to play gross jokes with ->mode_set_config.
8218 * Unfortunately the crtc helper doesn't do much at all for this case,
8219 * so we have to cope with this madness until the fb helper is fixed up. */
8220 if (set->fb && set->num_connectors == 0)
8221 return 0;
8222
Daniel Vetter2e431052012-07-04 22:42:15 +02008223 if (set->fb) {
8224 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8225 set->crtc->base.id, set->fb->base.id,
8226 (int)set->num_connectors, set->x, set->y);
8227 } else {
8228 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
Daniel Vetter2e431052012-07-04 22:42:15 +02008229 }
8230
8231 dev = set->crtc->dev;
8232
8233 ret = -ENOMEM;
8234 config = kzalloc(sizeof(*config), GFP_KERNEL);
8235 if (!config)
8236 goto out_config;
8237
8238 ret = intel_set_config_save_state(dev, config);
8239 if (ret)
8240 goto out_config;
8241
8242 save_set.crtc = set->crtc;
8243 save_set.mode = &set->crtc->mode;
8244 save_set.x = set->crtc->x;
8245 save_set.y = set->crtc->y;
8246 save_set.fb = set->crtc->fb;
8247
8248 /* Compute whether we need a full modeset, only an fb base update or no
8249 * change at all. In the future we might also check whether only the
8250 * mode changed, e.g. for LVDS where we only change the panel fitter in
8251 * such cases. */
8252 intel_set_config_compute_mode_changes(set, config);
8253
Daniel Vetter9a935852012-07-05 22:34:27 +02008254 ret = intel_modeset_stage_output_state(dev, set, config);
Daniel Vetter2e431052012-07-04 22:42:15 +02008255 if (ret)
8256 goto fail;
8257
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008258 if (config->mode_changed) {
Daniel Vetter87f1faa2012-07-05 23:36:17 +02008259 if (set->mode) {
Daniel Vetter50f56112012-07-02 09:35:43 +02008260 DRM_DEBUG_KMS("attempting to set mode from"
8261 " userspace\n");
8262 drm_mode_debug_printmodeline(set->mode);
Daniel Vetter87f1faa2012-07-05 23:36:17 +02008263 }
8264
8265 if (!intel_set_mode(set->crtc, set->mode,
8266 set->x, set->y, set->fb)) {
8267 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8268 set->crtc->base.id);
8269 ret = -EINVAL;
8270 goto fail;
8271 }
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008272 } else if (config->fb_changed) {
Daniel Vetter4f660f42012-07-02 09:47:37 +02008273 ret = intel_pipe_set_base(set->crtc,
Daniel Vetter94352cf2012-07-05 22:51:56 +02008274 set->x, set->y, set->fb);
Daniel Vetter50f56112012-07-02 09:35:43 +02008275 }
8276
Daniel Vetterd9e55602012-07-04 22:16:09 +02008277 intel_set_config_free(config);
8278
Daniel Vetter50f56112012-07-02 09:35:43 +02008279 return 0;
8280
8281fail:
Daniel Vetter85f9eb72012-07-04 22:24:08 +02008282 intel_set_config_restore_state(dev, config);
Daniel Vetter50f56112012-07-02 09:35:43 +02008283
8284 /* Try to restore the config */
Daniel Vetter5e2b5842012-07-04 22:41:29 +02008285 if (config->mode_changed &&
Daniel Vettera6778b32012-07-02 09:56:42 +02008286 !intel_set_mode(save_set.crtc, save_set.mode,
8287 save_set.x, save_set.y, save_set.fb))
Daniel Vetter50f56112012-07-02 09:35:43 +02008288 DRM_ERROR("failed to restore config after modeset failure\n");
8289
Daniel Vetterd9e55602012-07-04 22:16:09 +02008290out_config:
8291 intel_set_config_free(config);
Daniel Vetter50f56112012-07-02 09:35:43 +02008292 return ret;
8293}
8294
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008295static const struct drm_crtc_funcs intel_crtc_funcs = {
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008296 .cursor_set = intel_crtc_cursor_set,
8297 .cursor_move = intel_crtc_cursor_move,
8298 .gamma_set = intel_crtc_gamma_set,
Daniel Vetter50f56112012-07-02 09:35:43 +02008299 .set_config = intel_crtc_set_config,
Chris Wilsonf6e5b162011-04-12 18:06:51 +01008300 .destroy = intel_crtc_destroy,
8301 .page_flip = intel_crtc_page_flip,
8302};
8303
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008304static void intel_cpu_pll_init(struct drm_device *dev)
8305{
8306 if (IS_HASWELL(dev))
8307 intel_ddi_pll_init(dev);
8308}
8309
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008310static void intel_pch_pll_init(struct drm_device *dev)
8311{
8312 drm_i915_private_t *dev_priv = dev->dev_private;
8313 int i;
8314
8315 if (dev_priv->num_pch_pll == 0) {
8316 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8317 return;
8318 }
8319
8320 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8321 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8322 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8323 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8324 }
8325}
8326
Hannes Ederb358d0a2008-12-18 21:18:47 +01008327static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08008328{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08008329 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08008330 struct intel_crtc *intel_crtc;
8331 int i;
8332
8333 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8334 if (intel_crtc == NULL)
8335 return;
8336
8337 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8338
8339 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08008340 for (i = 0; i < 256; i++) {
8341 intel_crtc->lut_r[i] = i;
8342 intel_crtc->lut_g[i] = i;
8343 intel_crtc->lut_b[i] = i;
8344 }
8345
Jesse Barnes80824002009-09-10 15:28:06 -07008346 /* Swap pipes & planes for FBC on pre-965 */
8347 intel_crtc->pipe = pipe;
8348 intel_crtc->plane = pipe;
Paulo Zanonia5c961d2012-10-24 15:59:34 -02008349 intel_crtc->cpu_transcoder = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01008350 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08008351 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01008352 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07008353 }
8354
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08008355 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8356 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8357 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8358 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8359
Jesse Barnes5a354202011-06-24 12:19:22 -07008360 intel_crtc->bpp = 24; /* default for pre-Ironlake */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07008361
Jesse Barnes79e53942008-11-07 14:24:08 -08008362 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -08008363}
8364
Carl Worth08d7b3d2009-04-29 14:43:54 -07008365int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00008366 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07008367{
Carl Worth08d7b3d2009-04-29 14:43:54 -07008368 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02008369 struct drm_mode_object *drmmode_obj;
8370 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008371
Daniel Vetter1cff8f62012-04-24 09:55:08 +02008372 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8373 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008374
Daniel Vetterc05422d2009-08-11 16:05:30 +02008375 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8376 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07008377
Daniel Vetterc05422d2009-08-11 16:05:30 +02008378 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07008379 DRM_ERROR("no such CRTC id\n");
8380 return -EINVAL;
8381 }
8382
Daniel Vetterc05422d2009-08-11 16:05:30 +02008383 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8384 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008385
Daniel Vetterc05422d2009-08-11 16:05:30 +02008386 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07008387}
8388
Daniel Vetter66a92782012-07-12 20:08:18 +02008389static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08008390{
Daniel Vetter66a92782012-07-12 20:08:18 +02008391 struct drm_device *dev = encoder->base.dev;
8392 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08008393 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08008394 int entry = 0;
8395
Daniel Vetter66a92782012-07-12 20:08:18 +02008396 list_for_each_entry(source_encoder,
8397 &dev->mode_config.encoder_list, base.head) {
8398
8399 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08008400 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +02008401
8402 /* Intel hw has only one MUX where enocoders could be cloned. */
8403 if (encoder->cloneable && source_encoder->cloneable)
8404 index_mask |= (1 << entry);
8405
Jesse Barnes79e53942008-11-07 14:24:08 -08008406 entry++;
8407 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01008408
Jesse Barnes79e53942008-11-07 14:24:08 -08008409 return index_mask;
8410}
8411
Chris Wilson4d302442010-12-14 19:21:29 +00008412static bool has_edp_a(struct drm_device *dev)
8413{
8414 struct drm_i915_private *dev_priv = dev->dev_private;
8415
8416 if (!IS_MOBILE(dev))
8417 return false;
8418
8419 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8420 return false;
8421
8422 if (IS_GEN5(dev) &&
8423 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8424 return false;
8425
8426 return true;
8427}
8428
Jesse Barnes79e53942008-11-07 14:24:08 -08008429static void intel_setup_outputs(struct drm_device *dev)
8430{
Eric Anholt725e30a2009-01-22 13:01:02 -08008431 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01008432 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008433 bool dpd_is_edp = false;
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00008434 bool has_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08008435
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00008436 has_lvds = intel_lvds_init(dev);
Chris Wilsonc5d1b512010-11-29 18:00:23 +00008437 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8438 /* disable the panel fitter on everything but LVDS */
8439 I915_WRITE(PFIT_CONTROL, 0);
8440 }
Jesse Barnes79e53942008-11-07 14:24:08 -08008441
Paulo Zanoni79935fc2012-11-20 13:27:40 -02008442 if (!(IS_HASWELL(dev) &&
8443 (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8444 intel_crt_init(dev);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008445
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -03008446 if (IS_HASWELL(dev)) {
8447 int found;
8448
8449 /* Haswell uses DDI functions to detect digital outputs */
8450 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8451 /* DDI A only supports eDP */
8452 if (found)
8453 intel_ddi_init(dev, PORT_A);
8454
8455 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8456 * register */
8457 found = I915_READ(SFUSE_STRAP);
8458
8459 if (found & SFUSE_STRAP_DDIB_DETECTED)
8460 intel_ddi_init(dev, PORT_B);
8461 if (found & SFUSE_STRAP_DDIC_DETECTED)
8462 intel_ddi_init(dev, PORT_C);
8463 if (found & SFUSE_STRAP_DDID_DETECTED)
8464 intel_ddi_init(dev, PORT_D);
8465 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008466 int found;
Daniel Vetter270b3042012-10-27 15:52:05 +02008467 dpd_is_edp = intel_dpd_is_edp(dev);
8468
8469 if (has_edp_a(dev))
8470 intel_dp_init(dev, DP_A, PORT_A);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04008471
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008472 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08008473 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +01008474 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008475 if (!found)
Daniel Vetter08d644a2012-07-12 20:19:59 +02008476 intel_hdmi_init(dev, HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08008477 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008478 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008479 }
8480
8481 if (I915_READ(HDMIC) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02008482 intel_hdmi_init(dev, HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008483
Jesse Barnesb708a1d2012-06-11 14:39:56 -04008484 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02008485 intel_hdmi_init(dev, HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08008486
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08008487 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008488 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08008489
Daniel Vetter270b3042012-10-27 15:52:05 +02008490 if (I915_READ(PCH_DP_D) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008491 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -07008492 } else if (IS_VALLEYVIEW(dev)) {
8493 int found;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08008494
Gajanan Bhat19c03922012-09-27 19:13:07 +05308495 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8496 if (I915_READ(DP_C) & DP_DETECTED)
8497 intel_dp_init(dev, DP_C, PORT_C);
8498
Jesse Barnes4a87d652012-06-15 11:55:16 -07008499 if (I915_READ(SDVOB) & PORT_DETECTED) {
8500 /* SDVOB multiplex with HDMIB */
8501 found = intel_sdvo_init(dev, SDVOB, true);
8502 if (!found)
Daniel Vetter08d644a2012-07-12 20:19:59 +02008503 intel_hdmi_init(dev, SDVOB, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07008504 if (!found && (I915_READ(DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008505 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07008506 }
8507
8508 if (I915_READ(SDVOC) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02008509 intel_hdmi_init(dev, SDVOC, PORT_C);
Jesse Barnes4a87d652012-06-15 11:55:16 -07008510
Zhenyu Wang103a1962009-11-27 11:44:36 +08008511 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08008512 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08008513
Eric Anholt725e30a2009-01-22 13:01:02 -08008514 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008515 DRM_DEBUG_KMS("probing SDVOB\n");
Daniel Vettereef4eac2012-03-23 23:43:35 +01008516 found = intel_sdvo_init(dev, SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008517 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8518 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Daniel Vetter08d644a2012-07-12 20:19:59 +02008519 intel_hdmi_init(dev, SDVOB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008520 }
Ma Ling27185ae2009-08-24 13:50:23 +08008521
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008522 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8523 DRM_DEBUG_KMS("probing DP_B\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008524 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008525 }
Eric Anholt725e30a2009-01-22 13:01:02 -08008526 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04008527
8528 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04008529
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008530 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8531 DRM_DEBUG_KMS("probing SDVOC\n");
Daniel Vettereef4eac2012-03-23 23:43:35 +01008532 found = intel_sdvo_init(dev, SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008533 }
Ma Ling27185ae2009-08-24 13:50:23 +08008534
8535 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8536
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008537 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8538 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Daniel Vetter08d644a2012-07-12 20:19:59 +02008539 intel_hdmi_init(dev, SDVOC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008540 }
8541 if (SUPPORTS_INTEGRATED_DP(dev)) {
8542 DRM_DEBUG_KMS("probing DP_C\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008543 intel_dp_init(dev, DP_C, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008544 }
Eric Anholt725e30a2009-01-22 13:01:02 -08008545 }
Ma Ling27185ae2009-08-24 13:50:23 +08008546
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008547 if (SUPPORTS_INTEGRATED_DP(dev) &&
8548 (I915_READ(DP_D) & DP_DETECTED)) {
8549 DRM_DEBUG_KMS("probing DP_D\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03008550 intel_dp_init(dev, DP_D, PORT_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08008551 }
Eric Anholtbad720f2009-10-22 16:11:14 -07008552 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08008553 intel_dvo_init(dev);
8554
Zhenyu Wang103a1962009-11-27 11:44:36 +08008555 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08008556 intel_tv_init(dev);
8557
Chris Wilson4ef69c72010-09-09 15:14:28 +01008558 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8559 encoder->base.possible_crtcs = encoder->crtc_mask;
8560 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +02008561 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08008562 }
Chris Wilson47356eb2011-01-11 17:06:04 +00008563
Paulo Zanonidde86e22012-12-01 12:04:25 -02008564 intel_init_pch_refclk(dev);
Daniel Vetter270b3042012-10-27 15:52:05 +02008565
8566 drm_helper_move_panel_connectors_to_head(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08008567}
8568
8569static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8570{
8571 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08008572
8573 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00008574 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08008575
8576 kfree(intel_fb);
8577}
8578
8579static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00008580 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08008581 unsigned int *handle)
8582{
8583 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00008584 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08008585
Chris Wilson05394f32010-11-08 19:18:58 +00008586 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08008587}
8588
8589static const struct drm_framebuffer_funcs intel_fb_funcs = {
8590 .destroy = intel_user_framebuffer_destroy,
8591 .create_handle = intel_user_framebuffer_create_handle,
8592};
8593
Dave Airlie38651672010-03-30 05:34:13 +00008594int intel_framebuffer_init(struct drm_device *dev,
8595 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008596 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00008597 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08008598{
Jesse Barnes79e53942008-11-07 14:24:08 -08008599 int ret;
8600
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008601 if (obj->tiling_mode == I915_TILING_Y) {
8602 DRM_DEBUG("hardware does not support tiling Y\n");
Chris Wilson57cd6502010-08-08 12:34:44 +01008603 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008604 }
Chris Wilson57cd6502010-08-08 12:34:44 +01008605
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008606 if (mode_cmd->pitches[0] & 63) {
8607 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8608 mode_cmd->pitches[0]);
Chris Wilson57cd6502010-08-08 12:34:44 +01008609 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008610 }
Chris Wilson57cd6502010-08-08 12:34:44 +01008611
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008612 /* FIXME <= Gen4 stride limits are bit unclear */
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008613 if (mode_cmd->pitches[0] > 32768) {
8614 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8615 mode_cmd->pitches[0]);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008616 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008617 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008618
8619 if (obj->tiling_mode != I915_TILING_NONE &&
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008620 mode_cmd->pitches[0] != obj->stride) {
8621 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8622 mode_cmd->pitches[0], obj->stride);
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008623 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008624 }
Ville Syrjälä5d7bd702012-10-31 17:50:18 +02008625
Ville Syrjälä57779d02012-10-31 17:50:14 +02008626 /* Reject formats not supported by any plane early. */
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008627 switch (mode_cmd->pixel_format) {
Ville Syrjälä57779d02012-10-31 17:50:14 +02008628 case DRM_FORMAT_C8:
Ville Syrjälä04b39242011-11-17 18:05:13 +02008629 case DRM_FORMAT_RGB565:
8630 case DRM_FORMAT_XRGB8888:
8631 case DRM_FORMAT_ARGB8888:
Ville Syrjälä57779d02012-10-31 17:50:14 +02008632 break;
8633 case DRM_FORMAT_XRGB1555:
8634 case DRM_FORMAT_ARGB1555:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008635 if (INTEL_INFO(dev)->gen > 3) {
8636 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
Ville Syrjälä57779d02012-10-31 17:50:14 +02008637 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008638 }
Ville Syrjälä57779d02012-10-31 17:50:14 +02008639 break;
8640 case DRM_FORMAT_XBGR8888:
8641 case DRM_FORMAT_ABGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +02008642 case DRM_FORMAT_XRGB2101010:
8643 case DRM_FORMAT_ARGB2101010:
Ville Syrjälä57779d02012-10-31 17:50:14 +02008644 case DRM_FORMAT_XBGR2101010:
8645 case DRM_FORMAT_ABGR2101010:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008646 if (INTEL_INFO(dev)->gen < 4) {
8647 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
Ville Syrjälä57779d02012-10-31 17:50:14 +02008648 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008649 }
Jesse Barnesb5626742011-06-24 12:19:27 -07008650 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +02008651 case DRM_FORMAT_YUYV:
8652 case DRM_FORMAT_UYVY:
8653 case DRM_FORMAT_YVYU:
8654 case DRM_FORMAT_VYUY:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008655 if (INTEL_INFO(dev)->gen < 5) {
8656 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
Ville Syrjälä57779d02012-10-31 17:50:14 +02008657 return -EINVAL;
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008658 }
Chris Wilson57cd6502010-08-08 12:34:44 +01008659 break;
8660 default:
Chris Wilsonc16ed4b2012-12-18 22:13:14 +00008661 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
Chris Wilson57cd6502010-08-08 12:34:44 +01008662 return -EINVAL;
8663 }
8664
Ville Syrjälä90f9a332012-10-31 17:50:19 +02008665 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8666 if (mode_cmd->offsets[0] != 0)
8667 return -EINVAL;
8668
Daniel Vetterc7d73f62012-12-13 23:38:38 +01008669 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8670 intel_fb->obj = obj;
8671
Jesse Barnes79e53942008-11-07 14:24:08 -08008672 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8673 if (ret) {
8674 DRM_ERROR("framebuffer init failed %d\n", ret);
8675 return ret;
8676 }
8677
Jesse Barnes79e53942008-11-07 14:24:08 -08008678 return 0;
8679}
8680
Jesse Barnes79e53942008-11-07 14:24:08 -08008681static struct drm_framebuffer *
8682intel_user_framebuffer_create(struct drm_device *dev,
8683 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008684 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -08008685{
Chris Wilson05394f32010-11-08 19:18:58 +00008686 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08008687
Jesse Barnes308e5bc2011-11-14 14:51:28 -08008688 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8689 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +00008690 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01008691 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08008692
Chris Wilsond2dff872011-04-19 08:36:26 +01008693 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08008694}
8695
Jesse Barnes79e53942008-11-07 14:24:08 -08008696static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08008697 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00008698 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08008699};
8700
Jesse Barnese70236a2009-09-21 10:42:27 -07008701/* Set up chip specific display functions */
8702static void intel_init_display(struct drm_device *dev)
8703{
8704 struct drm_i915_private *dev_priv = dev->dev_private;
8705
8706 /* We always want a DPMS function */
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03008707 if (IS_HASWELL(dev)) {
8708 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
Paulo Zanoni4f771f12012-10-23 18:29:51 -02008709 dev_priv->display.crtc_enable = haswell_crtc_enable;
8710 dev_priv->display.crtc_disable = haswell_crtc_disable;
Paulo Zanoni6441ab52012-10-05 12:05:58 -03008711 dev_priv->display.off = haswell_crtc_off;
Paulo Zanoni09b4ddf2012-10-05 12:05:55 -03008712 dev_priv->display.update_plane = ironlake_update_plane;
8713 } else if (HAS_PCH_SPLIT(dev)) {
Eric Anholtf564048e2011-03-30 13:01:02 -07008714 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02008715 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8716 dev_priv->display.crtc_disable = ironlake_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008717 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008718 dev_priv->display.update_plane = ironlake_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07008719 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07008720 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Daniel Vetter76e5a892012-06-29 22:39:33 +02008721 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8722 dev_priv->display.crtc_disable = i9xx_crtc_disable;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008723 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008724 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07008725 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008726
Jesse Barnese70236a2009-09-21 10:42:27 -07008727 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07008728 if (IS_VALLEYVIEW(dev))
8729 dev_priv->display.get_display_clock_speed =
8730 valleyview_get_display_clock_speed;
8731 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07008732 dev_priv->display.get_display_clock_speed =
8733 i945_get_display_clock_speed;
8734 else if (IS_I915G(dev))
8735 dev_priv->display.get_display_clock_speed =
8736 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008737 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008738 dev_priv->display.get_display_clock_speed =
8739 i9xx_misc_get_display_clock_speed;
8740 else if (IS_I915GM(dev))
8741 dev_priv->display.get_display_clock_speed =
8742 i915gm_get_display_clock_speed;
8743 else if (IS_I865G(dev))
8744 dev_priv->display.get_display_clock_speed =
8745 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02008746 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008747 dev_priv->display.get_display_clock_speed =
8748 i855_get_display_clock_speed;
8749 else /* 852, 830 */
8750 dev_priv->display.get_display_clock_speed =
8751 i830_get_display_clock_speed;
8752
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008753 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01008754 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07008755 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008756 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08008757 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07008758 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008759 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07008760 } else if (IS_IVYBRIDGE(dev)) {
8761 /* FIXME: detect B0+ stepping and use auto training */
8762 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08008763 dev_priv->display.write_eld = ironlake_write_eld;
Daniel Vetter01a415f2012-10-27 15:58:40 +02008764 dev_priv->display.modeset_global_resources =
8765 ivb_modeset_global_resources;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -03008766 } else if (IS_HASWELL(dev)) {
8767 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Wang Xingchao83358c852012-08-16 22:43:37 +08008768 dev_priv->display.write_eld = haswell_write_eld;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008769 } else
8770 dev_priv->display.update_wm = NULL;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008771 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08008772 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07008773 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008774
8775 /* Default just returns -ENODEV to indicate unsupported */
8776 dev_priv->display.queue_flip = intel_default_queue_flip;
8777
8778 switch (INTEL_INFO(dev)->gen) {
8779 case 2:
8780 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8781 break;
8782
8783 case 3:
8784 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8785 break;
8786
8787 case 4:
8788 case 5:
8789 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8790 break;
8791
8792 case 6:
8793 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8794 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008795 case 7:
8796 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8797 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008798 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008799}
8800
Jesse Barnesb690e962010-07-19 13:53:12 -07008801/*
8802 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8803 * resume, or other times. This quirk makes sure that's the case for
8804 * affected systems.
8805 */
Akshay Joshi0206e352011-08-16 15:34:10 -04008806static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07008807{
8808 struct drm_i915_private *dev_priv = dev->dev_private;
8809
8810 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008811 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07008812}
8813
Keith Packard435793d2011-07-12 14:56:22 -07008814/*
8815 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8816 */
8817static void quirk_ssc_force_disable(struct drm_device *dev)
8818{
8819 struct drm_i915_private *dev_priv = dev->dev_private;
8820 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008821 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -07008822}
8823
Carsten Emde4dca20e2012-03-15 15:56:26 +01008824/*
Carsten Emde5a15ab52012-03-15 15:56:27 +01008825 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8826 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +01008827 */
8828static void quirk_invert_brightness(struct drm_device *dev)
8829{
8830 struct drm_i915_private *dev_priv = dev->dev_private;
8831 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02008832 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07008833}
8834
8835struct intel_quirk {
8836 int device;
8837 int subsystem_vendor;
8838 int subsystem_device;
8839 void (*hook)(struct drm_device *dev);
8840};
8841
Egbert Eich5f85f1762012-10-14 15:46:38 +02008842/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8843struct intel_dmi_quirk {
8844 void (*hook)(struct drm_device *dev);
8845 const struct dmi_system_id (*dmi_id_list)[];
8846};
8847
8848static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8849{
8850 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8851 return 1;
8852}
8853
8854static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8855 {
8856 .dmi_id_list = &(const struct dmi_system_id[]) {
8857 {
8858 .callback = intel_dmi_reverse_brightness,
8859 .ident = "NCR Corporation",
8860 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8861 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8862 },
8863 },
8864 { } /* terminating entry */
8865 },
8866 .hook = quirk_invert_brightness,
8867 },
8868};
8869
Ben Widawskyc43b5632012-04-16 14:07:40 -07008870static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -07008871 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04008872 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07008873
Jesse Barnesb690e962010-07-19 13:53:12 -07008874 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8875 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8876
Jesse Barnesb690e962010-07-19 13:53:12 -07008877 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8878 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8879
Daniel Vetterccd0d362012-10-10 23:13:59 +02008880 /* 830/845 need to leave pipe A & dpll A up */
Jesse Barnesb690e962010-07-19 13:53:12 -07008881 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Daniel Vetterdcdaed62012-08-12 21:19:34 +02008882 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07008883
8884 /* Lenovo U160 cannot use SSC on LVDS */
8885 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02008886
8887 /* Sony Vaio Y cannot use SSC on LVDS */
8888 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +01008889
8890 /* Acer Aspire 5734Z must invert backlight brightness */
8891 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -07008892};
8893
8894static void intel_init_quirks(struct drm_device *dev)
8895{
8896 struct pci_dev *d = dev->pdev;
8897 int i;
8898
8899 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8900 struct intel_quirk *q = &intel_quirks[i];
8901
8902 if (d->device == q->device &&
8903 (d->subsystem_vendor == q->subsystem_vendor ||
8904 q->subsystem_vendor == PCI_ANY_ID) &&
8905 (d->subsystem_device == q->subsystem_device ||
8906 q->subsystem_device == PCI_ANY_ID))
8907 q->hook(dev);
8908 }
Egbert Eich5f85f1762012-10-14 15:46:38 +02008909 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8910 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8911 intel_dmi_quirks[i].hook(dev);
8912 }
Jesse Barnesb690e962010-07-19 13:53:12 -07008913}
8914
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008915/* Disable the VGA plane that we never use */
8916static void i915_disable_vga(struct drm_device *dev)
8917{
8918 struct drm_i915_private *dev_priv = dev->dev_private;
8919 u8 sr1;
8920 u32 vga_reg;
8921
8922 if (HAS_PCH_SPLIT(dev))
8923 vga_reg = CPU_VGACNTRL;
8924 else
8925 vga_reg = VGACNTRL;
8926
8927 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -07008928 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07008929 sr1 = inb(VGA_SR_DATA);
8930 outb(sr1 | 1<<5, VGA_SR_DATA);
8931 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8932 udelay(300);
8933
8934 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8935 POSTING_READ(vga_reg);
8936}
8937
Daniel Vetterf8175862012-04-10 15:50:11 +02008938void intel_modeset_init_hw(struct drm_device *dev)
8939{
Eugeni Dodonov0232e922012-07-06 15:42:36 -03008940 /* We attempt to init the necessary power wells early in the initialization
8941 * time, so the subsystems that expect power to be enabled can work.
8942 */
8943 intel_init_power_wells(dev);
8944
Eugeni Dodonova8f78b52012-06-28 15:55:35 -03008945 intel_prepare_ddi(dev);
8946
Daniel Vetterf8175862012-04-10 15:50:11 +02008947 intel_init_clock_gating(dev);
8948
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02008949 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02008950 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02008951 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +02008952}
8953
Jesse Barnes79e53942008-11-07 14:24:08 -08008954void intel_modeset_init(struct drm_device *dev)
8955{
Jesse Barnes652c3932009-08-17 13:31:43 -07008956 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08008957 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08008958
8959 drm_mode_config_init(dev);
8960
8961 dev->mode_config.min_width = 0;
8962 dev->mode_config.min_height = 0;
8963
Dave Airlie019d96c2011-09-29 16:20:42 +01008964 dev->mode_config.preferred_depth = 24;
8965 dev->mode_config.prefer_shadow = 1;
8966
Laurent Pincharte6ecefa2012-05-17 13:27:23 +02008967 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -08008968
Jesse Barnesb690e962010-07-19 13:53:12 -07008969 intel_init_quirks(dev);
8970
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03008971 intel_init_pm(dev);
8972
Jesse Barnese70236a2009-09-21 10:42:27 -07008973 intel_init_display(dev);
8974
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008975 if (IS_GEN2(dev)) {
8976 dev->mode_config.max_width = 2048;
8977 dev->mode_config.max_height = 2048;
8978 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07008979 dev->mode_config.max_width = 4096;
8980 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08008981 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008982 dev->mode_config.max_width = 8192;
8983 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08008984 }
Daniel Vetterdd2757f2012-06-07 15:55:57 +02008985 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
Jesse Barnes79e53942008-11-07 14:24:08 -08008986
Zhao Yakui28c97732009-10-09 11:39:41 +08008987 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10008988 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08008989
Dave Airliea3524f12010-06-06 18:59:41 +10008990 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08008991 intel_crtc_init(dev, i);
Jesse Barnes00c2064b2012-01-13 15:48:39 -08008992 ret = intel_plane_init(dev, i);
8993 if (ret)
8994 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
Jesse Barnes79e53942008-11-07 14:24:08 -08008995 }
8996
Paulo Zanoni79f689a2012-10-05 12:05:52 -03008997 intel_cpu_pll_init(dev);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01008998 intel_pch_pll_init(dev);
8999
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009000 /* Just disable it once at startup */
9001 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009002 intel_setup_outputs(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01009003}
Jesse Barnesd5bb0812011-01-05 12:01:26 -08009004
Daniel Vetter24929352012-07-02 20:28:59 +02009005static void
9006intel_connector_break_all_links(struct intel_connector *connector)
9007{
9008 connector->base.dpms = DRM_MODE_DPMS_OFF;
9009 connector->base.encoder = NULL;
9010 connector->encoder->connectors_active = false;
9011 connector->encoder->base.crtc = NULL;
9012}
9013
Daniel Vetter7fad7982012-07-04 17:51:47 +02009014static void intel_enable_pipe_a(struct drm_device *dev)
9015{
9016 struct intel_connector *connector;
9017 struct drm_connector *crt = NULL;
9018 struct intel_load_detect_pipe load_detect_temp;
9019
9020 /* We can't just switch on the pipe A, we need to set things up with a
9021 * proper mode and output configuration. As a gross hack, enable pipe A
9022 * by enabling the load detect pipe once. */
9023 list_for_each_entry(connector,
9024 &dev->mode_config.connector_list,
9025 base.head) {
9026 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9027 crt = &connector->base;
9028 break;
9029 }
9030 }
9031
9032 if (!crt)
9033 return;
9034
9035 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9036 intel_release_load_detect_pipe(crt, &load_detect_temp);
9037
9038
9039}
9040
Daniel Vetterfa555832012-10-10 23:14:00 +02009041static bool
9042intel_check_plane_mapping(struct intel_crtc *crtc)
9043{
9044 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
9045 u32 reg, val;
9046
9047 if (dev_priv->num_pipe == 1)
9048 return true;
9049
9050 reg = DSPCNTR(!crtc->plane);
9051 val = I915_READ(reg);
9052
9053 if ((val & DISPLAY_PLANE_ENABLE) &&
9054 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9055 return false;
9056
9057 return true;
9058}
9059
Daniel Vetter24929352012-07-02 20:28:59 +02009060static void intel_sanitize_crtc(struct intel_crtc *crtc)
9061{
9062 struct drm_device *dev = crtc->base.dev;
9063 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterfa555832012-10-10 23:14:00 +02009064 u32 reg;
Daniel Vetter24929352012-07-02 20:28:59 +02009065
Daniel Vetter24929352012-07-02 20:28:59 +02009066 /* Clear any frame start delays used for debugging left by the BIOS */
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009067 reg = PIPECONF(crtc->cpu_transcoder);
Daniel Vetter24929352012-07-02 20:28:59 +02009068 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9069
9070 /* We need to sanitize the plane -> pipe mapping first because this will
Daniel Vetterfa555832012-10-10 23:14:00 +02009071 * disable the crtc (and hence change the state) if it is wrong. Note
9072 * that gen4+ has a fixed plane -> pipe mapping. */
9073 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
Daniel Vetter24929352012-07-02 20:28:59 +02009074 struct intel_connector *connector;
9075 bool plane;
9076
Daniel Vetter24929352012-07-02 20:28:59 +02009077 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9078 crtc->base.base.id);
9079
9080 /* Pipe has the wrong plane attached and the plane is active.
9081 * Temporarily change the plane mapping and disable everything
9082 * ... */
9083 plane = crtc->plane;
9084 crtc->plane = !plane;
9085 dev_priv->display.crtc_disable(&crtc->base);
9086 crtc->plane = plane;
9087
9088 /* ... and break all links. */
9089 list_for_each_entry(connector, &dev->mode_config.connector_list,
9090 base.head) {
9091 if (connector->encoder->base.crtc != &crtc->base)
9092 continue;
9093
9094 intel_connector_break_all_links(connector);
9095 }
9096
9097 WARN_ON(crtc->active);
9098 crtc->base.enabled = false;
9099 }
Daniel Vetter24929352012-07-02 20:28:59 +02009100
Daniel Vetter7fad7982012-07-04 17:51:47 +02009101 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9102 crtc->pipe == PIPE_A && !crtc->active) {
9103 /* BIOS forgot to enable pipe A, this mostly happens after
9104 * resume. Force-enable the pipe to fix this, the update_dpms
9105 * call below we restore the pipe to the right state, but leave
9106 * the required bits on. */
9107 intel_enable_pipe_a(dev);
9108 }
9109
Daniel Vetter24929352012-07-02 20:28:59 +02009110 /* Adjust the state of the output pipe according to whether we
9111 * have active connectors/encoders. */
9112 intel_crtc_update_dpms(&crtc->base);
9113
9114 if (crtc->active != crtc->base.enabled) {
9115 struct intel_encoder *encoder;
9116
9117 /* This can happen either due to bugs in the get_hw_state
9118 * functions or because the pipe is force-enabled due to the
9119 * pipe A quirk. */
9120 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9121 crtc->base.base.id,
9122 crtc->base.enabled ? "enabled" : "disabled",
9123 crtc->active ? "enabled" : "disabled");
9124
9125 crtc->base.enabled = crtc->active;
9126
9127 /* Because we only establish the connector -> encoder ->
9128 * crtc links if something is active, this means the
9129 * crtc is now deactivated. Break the links. connector
9130 * -> encoder links are only establish when things are
9131 * actually up, hence no need to break them. */
9132 WARN_ON(crtc->active);
9133
9134 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9135 WARN_ON(encoder->connectors_active);
9136 encoder->base.crtc = NULL;
9137 }
9138 }
9139}
9140
9141static void intel_sanitize_encoder(struct intel_encoder *encoder)
9142{
9143 struct intel_connector *connector;
9144 struct drm_device *dev = encoder->base.dev;
9145
9146 /* We need to check both for a crtc link (meaning that the
9147 * encoder is active and trying to read from a pipe) and the
9148 * pipe itself being active. */
9149 bool has_active_crtc = encoder->base.crtc &&
9150 to_intel_crtc(encoder->base.crtc)->active;
9151
9152 if (encoder->connectors_active && !has_active_crtc) {
9153 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9154 encoder->base.base.id,
9155 drm_get_encoder_name(&encoder->base));
9156
9157 /* Connector is active, but has no active pipe. This is
9158 * fallout from our resume register restoring. Disable
9159 * the encoder manually again. */
9160 if (encoder->base.crtc) {
9161 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9162 encoder->base.base.id,
9163 drm_get_encoder_name(&encoder->base));
9164 encoder->disable(encoder);
9165 }
9166
9167 /* Inconsistent output/port/pipe state happens presumably due to
9168 * a bug in one of the get_hw_state functions. Or someplace else
9169 * in our code, like the register restore mess on resume. Clamp
9170 * things to off as a safer default. */
9171 list_for_each_entry(connector,
9172 &dev->mode_config.connector_list,
9173 base.head) {
9174 if (connector->encoder != encoder)
9175 continue;
9176
9177 intel_connector_break_all_links(connector);
9178 }
9179 }
9180 /* Enabled encoders without active connectors will be fixed in
9181 * the crtc fixup. */
9182}
9183
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009184static void i915_redisable_vga(struct drm_device *dev)
9185{
9186 struct drm_i915_private *dev_priv = dev->dev_private;
9187 u32 vga_reg;
9188
9189 if (HAS_PCH_SPLIT(dev))
9190 vga_reg = CPU_VGACNTRL;
9191 else
9192 vga_reg = VGACNTRL;
9193
9194 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9195 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9196 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9197 POSTING_READ(vga_reg);
9198 }
9199}
9200
Daniel Vetter24929352012-07-02 20:28:59 +02009201/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9202 * and i915 state tracking structures. */
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009203void intel_modeset_setup_hw_state(struct drm_device *dev,
9204 bool force_restore)
Daniel Vetter24929352012-07-02 20:28:59 +02009205{
9206 struct drm_i915_private *dev_priv = dev->dev_private;
9207 enum pipe pipe;
9208 u32 tmp;
9209 struct intel_crtc *crtc;
9210 struct intel_encoder *encoder;
9211 struct intel_connector *connector;
9212
Paulo Zanonie28d54c2012-10-24 16:09:25 -02009213 if (IS_HASWELL(dev)) {
9214 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9215
9216 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9217 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9218 case TRANS_DDI_EDP_INPUT_A_ON:
9219 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9220 pipe = PIPE_A;
9221 break;
9222 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9223 pipe = PIPE_B;
9224 break;
9225 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9226 pipe = PIPE_C;
9227 break;
9228 }
9229
9230 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9231 crtc->cpu_transcoder = TRANSCODER_EDP;
9232
9233 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9234 pipe_name(pipe));
9235 }
9236 }
9237
Daniel Vetter24929352012-07-02 20:28:59 +02009238 for_each_pipe(pipe) {
9239 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9240
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009241 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
Daniel Vetter24929352012-07-02 20:28:59 +02009242 if (tmp & PIPECONF_ENABLE)
9243 crtc->active = true;
9244 else
9245 crtc->active = false;
9246
9247 crtc->base.enabled = crtc->active;
9248
9249 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9250 crtc->base.base.id,
9251 crtc->active ? "enabled" : "disabled");
9252 }
9253
Paulo Zanoni6441ab52012-10-05 12:05:58 -03009254 if (IS_HASWELL(dev))
9255 intel_ddi_setup_hw_pll_state(dev);
9256
Daniel Vetter24929352012-07-02 20:28:59 +02009257 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9258 base.head) {
9259 pipe = 0;
9260
9261 if (encoder->get_hw_state(encoder, &pipe)) {
9262 encoder->base.crtc =
9263 dev_priv->pipe_to_crtc_mapping[pipe];
9264 } else {
9265 encoder->base.crtc = NULL;
9266 }
9267
9268 encoder->connectors_active = false;
9269 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9270 encoder->base.base.id,
9271 drm_get_encoder_name(&encoder->base),
9272 encoder->base.crtc ? "enabled" : "disabled",
9273 pipe);
9274 }
9275
9276 list_for_each_entry(connector, &dev->mode_config.connector_list,
9277 base.head) {
9278 if (connector->get_hw_state(connector)) {
9279 connector->base.dpms = DRM_MODE_DPMS_ON;
9280 connector->encoder->connectors_active = true;
9281 connector->base.encoder = &connector->encoder->base;
9282 } else {
9283 connector->base.dpms = DRM_MODE_DPMS_OFF;
9284 connector->base.encoder = NULL;
9285 }
9286 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9287 connector->base.base.id,
9288 drm_get_connector_name(&connector->base),
9289 connector->base.encoder ? "enabled" : "disabled");
9290 }
9291
9292 /* HW state is read out, now we need to sanitize this mess. */
9293 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9294 base.head) {
9295 intel_sanitize_encoder(encoder);
9296 }
9297
9298 for_each_pipe(pipe) {
9299 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9300 intel_sanitize_crtc(crtc);
9301 }
Daniel Vetter9a935852012-07-05 22:34:27 +02009302
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009303 if (force_restore) {
9304 for_each_pipe(pipe) {
9305 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9306 intel_set_mode(&crtc->base, &crtc->base.mode,
9307 crtc->base.x, crtc->base.y, crtc->base.fb);
9308 }
Krzysztof Mazur0fde9012012-12-19 11:03:41 +01009309
9310 i915_redisable_vga(dev);
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009311 } else {
9312 intel_modeset_update_staged_output_state(dev);
9313 }
Daniel Vetter8af6cf82012-07-10 09:50:11 +02009314
9315 intel_modeset_check_state(dev);
Daniel Vetter2e938892012-10-11 20:08:24 +02009316
9317 drm_mode_config_reset(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01009318}
9319
9320void intel_modeset_gem_init(struct drm_device *dev)
9321{
Chris Wilson1833b132012-05-09 11:56:28 +01009322 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02009323
9324 intel_setup_overlay(dev);
Daniel Vetter24929352012-07-02 20:28:59 +02009325
Daniel Vetter45e2b5f2012-11-23 18:16:34 +01009326 intel_modeset_setup_hw_state(dev, false);
Jesse Barnes79e53942008-11-07 14:24:08 -08009327}
9328
9329void intel_modeset_cleanup(struct drm_device *dev)
9330{
Jesse Barnes652c3932009-08-17 13:31:43 -07009331 struct drm_i915_private *dev_priv = dev->dev_private;
9332 struct drm_crtc *crtc;
9333 struct intel_crtc *intel_crtc;
9334
Keith Packardf87ea762010-10-03 19:36:26 -07009335 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07009336 mutex_lock(&dev->struct_mutex);
9337
Jesse Barnes723bfd72010-10-07 16:01:13 -07009338 intel_unregister_dsm_handler();
9339
9340
Jesse Barnes652c3932009-08-17 13:31:43 -07009341 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9342 /* Skip inactive CRTCs */
9343 if (!crtc->fb)
9344 continue;
9345
9346 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02009347 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07009348 }
9349
Chris Wilson973d04f2011-07-08 12:22:37 +01009350 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -07009351
Daniel Vetter8090c6b2012-06-24 16:42:32 +02009352 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00009353
Daniel Vetter930ebb42012-06-29 23:32:16 +02009354 ironlake_teardown_rc6(dev);
9355
Jesse Barnes57f350b2012-03-28 13:39:25 -07009356 if (IS_VALLEYVIEW(dev))
9357 vlv_init_dpio(dev);
9358
Kristian Høgsberg69341a52009-11-11 12:19:17 -05009359 mutex_unlock(&dev->struct_mutex);
9360
Daniel Vetter6c0d93502010-08-20 18:26:46 +02009361 /* Disable the irq before mode object teardown, for the irq might
9362 * enqueue unpin/hotplug work. */
9363 drm_irq_uninstall(dev);
9364 cancel_work_sync(&dev_priv->hotplug_work);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02009365 cancel_work_sync(&dev_priv->rps.work);
Daniel Vetter6c0d93502010-08-20 18:26:46 +02009366
Chris Wilson1630fe72011-07-08 12:22:42 +01009367 /* flush any delayed tasks or pending work */
9368 flush_scheduled_work();
9369
Jesse Barnes79e53942008-11-07 14:24:08 -08009370 drm_mode_config_cleanup(dev);
9371}
9372
Dave Airlie28d52042009-09-21 14:33:58 +10009373/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08009374 * Return which encoder is currently attached for connector.
9375 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01009376struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08009377{
Chris Wilsondf0e9242010-09-09 16:20:55 +01009378 return &intel_attached_encoder(connector)->base;
9379}
Jesse Barnes79e53942008-11-07 14:24:08 -08009380
Chris Wilsondf0e9242010-09-09 16:20:55 +01009381void intel_connector_attach_encoder(struct intel_connector *connector,
9382 struct intel_encoder *encoder)
9383{
9384 connector->encoder = encoder;
9385 drm_mode_connector_attach_encoder(&connector->base,
9386 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08009387}
Dave Airlie28d52042009-09-21 14:33:58 +10009388
9389/*
9390 * set vga decode state - true == enable VGA decode
9391 */
9392int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9393{
9394 struct drm_i915_private *dev_priv = dev->dev_private;
9395 u16 gmch_ctrl;
9396
9397 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9398 if (state)
9399 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9400 else
9401 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9402 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9403 return 0;
9404}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009405
9406#ifdef CONFIG_DEBUG_FS
9407#include <linux/seq_file.h>
9408
9409struct intel_display_error_state {
9410 struct intel_cursor_error_state {
9411 u32 control;
9412 u32 position;
9413 u32 base;
9414 u32 size;
Damien Lespiau52331302012-08-15 19:23:25 +01009415 } cursor[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009416
9417 struct intel_pipe_error_state {
9418 u32 conf;
9419 u32 source;
9420
9421 u32 htotal;
9422 u32 hblank;
9423 u32 hsync;
9424 u32 vtotal;
9425 u32 vblank;
9426 u32 vsync;
Damien Lespiau52331302012-08-15 19:23:25 +01009427 } pipe[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009428
9429 struct intel_plane_error_state {
9430 u32 control;
9431 u32 stride;
9432 u32 size;
9433 u32 pos;
9434 u32 addr;
9435 u32 surface;
9436 u32 tile_offset;
Damien Lespiau52331302012-08-15 19:23:25 +01009437 } plane[I915_MAX_PIPES];
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009438};
9439
9440struct intel_display_error_state *
9441intel_display_capture_error_state(struct drm_device *dev)
9442{
Akshay Joshi0206e352011-08-16 15:34:10 -04009443 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009444 struct intel_display_error_state *error;
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009445 enum transcoder cpu_transcoder;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009446 int i;
9447
9448 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9449 if (error == NULL)
9450 return NULL;
9451
Damien Lespiau52331302012-08-15 19:23:25 +01009452 for_each_pipe(i) {
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009453 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9454
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009455 error->cursor[i].control = I915_READ(CURCNTR(i));
9456 error->cursor[i].position = I915_READ(CURPOS(i));
9457 error->cursor[i].base = I915_READ(CURBASE(i));
9458
9459 error->plane[i].control = I915_READ(DSPCNTR(i));
9460 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9461 error->plane[i].size = I915_READ(DSPSIZE(i));
Akshay Joshi0206e352011-08-16 15:34:10 -04009462 error->plane[i].pos = I915_READ(DSPPOS(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009463 error->plane[i].addr = I915_READ(DSPADDR(i));
9464 if (INTEL_INFO(dev)->gen >= 4) {
9465 error->plane[i].surface = I915_READ(DSPSURF(i));
9466 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9467 }
9468
Paulo Zanoni702e7a52012-10-23 18:29:59 -02009469 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009470 error->pipe[i].source = I915_READ(PIPESRC(i));
Paulo Zanonife2b8f92012-10-23 18:30:02 -02009471 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9472 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9473 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9474 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9475 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9476 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009477 }
9478
9479 return error;
9480}
9481
9482void
9483intel_display_print_error_state(struct seq_file *m,
9484 struct drm_device *dev,
9485 struct intel_display_error_state *error)
9486{
Damien Lespiau52331302012-08-15 19:23:25 +01009487 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009488 int i;
9489
Damien Lespiau52331302012-08-15 19:23:25 +01009490 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9491 for_each_pipe(i) {
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009492 seq_printf(m, "Pipe [%d]:\n", i);
9493 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9494 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9495 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9496 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9497 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9498 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9499 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9500 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9501
9502 seq_printf(m, "Plane [%d]:\n", i);
9503 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9504 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9505 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9506 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9507 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9508 if (INTEL_INFO(dev)->gen >= 4) {
9509 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9510 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9511 }
9512
9513 seq_printf(m, "Cursor [%d]:\n", i);
9514 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9515 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9516 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9517 }
9518}
9519#endif