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gerrit-public.fairphone.software / kernel / msm-4.9 / c7e324f1bd17b25fcdca33bdad01cf6eb8be4933 / . / arch / arm / mach-omap1 / mux.c
blob: 062c905c2ba6704eda8e5248b58318e525acc975 [file] [log] [blame]
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]1/*
2 * linux/arch/arm/mach-omap1/mux.c
3 *
4 * OMAP1 pin multiplexing configurations
5 *
Tony Lindgren93308992008-01-24 17:24:15 -0800[diff] [blame]6 * Copyright (C) 2003 - 2008 Nokia Corporation
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]7 *
Tony Lindgren93308992008-01-24 17:24:15 -0800[diff] [blame]8 * Written by Tony Lindgren
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]25#include <linux/module.h>
26#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +0100[diff] [blame]27#include <linux/io.h>
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]28#include <linux/spinlock.h>
29
Russell Kingfced80c2008-09-06 12:10:45 +0100[diff] [blame]30#include <asm/system.h>
31
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]32#include <mach/mux.h>
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]33
34#ifdef CONFIG_OMAP_MUX
35
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]36static struct omap_mux_cfg arch_mux_cfg;
37
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]38#ifdef CONFIG_ARCH_OMAP730
Tony Lindgren93308992008-01-24 17:24:15 -0800[diff] [blame]39static struct pin_config __initdata_or_module omap730_pins[] = {
Tony Lindgren8d7f9f52006-04-02 17:46:22 +0100[diff] [blame]40MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 20, 1, 0)
41MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 24, 1, 0)
42MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 28, 1, 0)
43MUX_CFG_730("F3_730_KBR3", 13, 1, 0, 0, 1, 0)
44MUX_CFG_730("D2_730_KBR4", 13, 5, 0, 4, 1, 0)
45MUX_CFG_730("C2_730_KBC0", 13, 9, 0, 8, 1, 0)
46MUX_CFG_730("D3_730_KBC1", 13, 13, 0, 12, 1, 0)
47MUX_CFG_730("E4_730_KBC2", 13, 17, 0, 16, 1, 0)
48MUX_CFG_730("F4_730_KBC3", 13, 21, 0, 20, 1, 0)
49MUX_CFG_730("E3_730_KBC4", 13, 25, 0, 24, 1, 0)
50
51MUX_CFG_730("AA17_730_USB_DM", 2, 21, 0, 20, 0, 0)
52MUX_CFG_730("W16_730_USB_PU_EN", 2, 25, 0, 24, 0, 0)
53MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0)
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]54};
Tony Lindgren93308992008-01-24 17:24:15 -0800[diff] [blame]55#define OMAP730_PINS_SZ ARRAY_SIZE(omap730_pins)
56#else
57#define omap730_pins NULL
58#define OMAP730_PINS_SZ 0
59#endif /* CONFIG_ARCH_OMAP730 */
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]60
61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
Tony Lindgren93308992008-01-24 17:24:15 -0800[diff] [blame]62static struct pin_config __initdata_or_module omap1xxx_pins[] = {
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]63/*
64 * description mux mode mux pull pull pull pu_pd pu dbg
65 * reg offset mode reg bit ena reg
66 */
67MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
68MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
69
70/* UART2 (COM_UART_GATING), conflicts with USB2 */
71MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
72MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
73MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
74MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
75
76/* UART3 (GIGA_UART_GATING) */
77MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
78MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
79MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
80MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
81MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
82MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
83MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
84
85/* PWT & PWL, conflicts with UART3 */
Tony Lindgren8d7f9f52006-04-02 17:46:22 +0100[diff] [blame]86MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
87MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]88
89/* USB internal master generic */
90MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
91MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
92/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
93MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
94MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
95MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
96MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
97
98/* USB1 master */
99MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
100MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
101MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
102MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
103MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
104MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
105MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
106MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
107MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
108MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
109MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
110
111/* USB2 master */
112MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
113MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
114MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
115MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
116MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
117MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
118MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
119
120/* OMAP-1510 GPIO */
121MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
122MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
123MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
124
125/* OMAP1610 GPIO */
126MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
127MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
128
129/* OMAP-1710 GPIO */
130MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
131MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
132MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
133MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
134
135/* MPUIO */
136MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
137MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
138MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
139MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
140
141MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
142MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
143MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
144MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
145MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
146MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
147MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
148MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
149MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
150
151/* MCBSP2 */
152MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
153MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
154MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
155MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
156MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
157MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
158
159/* MCBSP3 NOTE: Mode must 1 for clock */
160MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
161
162/* Misc ballouts */
163MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
Tony Lindgren8d7f9f52006-04-02 17:46:22 +0100[diff] [blame]164MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]165
166/* OMAP-1610 MMC2 */
167MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
168MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
169MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
170MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
171MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
172MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
173MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
174MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
175MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
176MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
177
178/* OMAP-1610 External Trace Interface */
179MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
180MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
181MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
182MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
183MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
184MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
185
186/* OMAP16XX GPIO */
187MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
188MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
189MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
190MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
191MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
192MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
193MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
194MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
195MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
196MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
197MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
198MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
199MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
200
201/* OMAP-1610 uWire */
202MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
203MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
204MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
205MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
206MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
207MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
208
Mark Howell75a1d102006-09-25 12:41:29 +0300[diff] [blame]209/* OMAP-1610 SPI */
210MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
211MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
212MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
213MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
214MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
215MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
216MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
217MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
218MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
219
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]220/* OMAP-1610 Flash */
221MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
222MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
223
224/* First MMC interface, same on 1510, 1610 and 1710 */
225MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
226MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
227MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
228MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
229MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
230MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
231MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
232MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
233MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
234
235/* OMAP-1610 USB0 alternate configuration */
236MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
237MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
238MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
239MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
240MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
241MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
242MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
243MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
244
245/* USB2 interface */
246MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
247MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
248MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
249MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
250MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
251MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
252
253/* 16XX UART */
254MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
255MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
256MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
257MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
258MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
259MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
260
261/* I2C interface */
262MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
263MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
264
265/* Keypad */
266MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
267MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
268MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
269MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
270MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
271MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
272MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
273MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
274MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
275MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
276MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
277
278/* Power management */
279MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
280
281/* MCLK Settings */
282MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
283MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
284MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
285MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
286
287/* CompactFlash controller, conflicts with MMC1 */
288MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
289MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
290MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
291MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
292MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
David Brownellc72d8952006-12-11 14:14:11 -0800[diff] [blame]293
294/* parallel camera */
295MUX_CFG("J15_1610_CAM_LCLK", 4, 24, 0, 0, 18, 1, 0, 0, 0)
296MUX_CFG("J18_1610_CAM_D7", 4, 27, 0, 0, 19, 1, 0, 0, 0)
297MUX_CFG("J19_1610_CAM_D6", 5, 0, 0, 0, 20, 1, 0, 0, 0)
298MUX_CFG("J14_1610_CAM_D5", 5, 3, 0, 0, 21, 1, 0, 0, 0)
299MUX_CFG("K18_1610_CAM_D4", 5, 6, 0, 0, 22, 1, 0, 0, 0)
300MUX_CFG("K19_1610_CAM_D3", 5, 9, 0, 0, 23, 1, 0, 0, 0)
301MUX_CFG("K15_1610_CAM_D2", 5, 12, 0, 0, 24, 1, 0, 0, 0)
302MUX_CFG("K14_1610_CAM_D1", 5, 15, 0, 0, 25, 1, 0, 0, 0)
303MUX_CFG("L19_1610_CAM_D0", 5, 18, 0, 0, 26, 1, 0, 0, 0)
304MUX_CFG("L18_1610_CAM_VS", 5, 21, 0, 0, 27, 1, 0, 0, 0)
305MUX_CFG("L15_1610_CAM_HS", 5, 24, 0, 0, 28, 1, 0, 0, 0)
306MUX_CFG("M19_1610_CAM_RSTZ", 5, 27, 0, 0, 29, 0, 0, 0, 0)
307MUX_CFG("Y15_1610_CAM_OUTCLK", A, 0, 6, 2, 6, 0, 2, 0, 0)
308
309/* serial camera */
310MUX_CFG("H19_1610_CAM_EXCLK", 4, 21, 0, 0, 17, 0, 0, 0, 0)
311 /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */
312MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0)
313MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0)
314MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0)
315MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]316};
Tony Lindgren93308992008-01-24 17:24:15 -0800[diff] [blame]317#define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins)
318#else
319#define omap1xxx_pins NULL
320#define OMAP1XXX_PINS_SZ 0
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]321#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
322
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]323int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
324{
Tony Lindgren225dfda2008-01-25 00:42:48 -0800[diff] [blame]325 static DEFINE_SPINLOCK(mux_spin_lock);
326 unsigned long flags;
327 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
328 pull_orig = 0, pull = 0;
329 unsigned int mask, warn = 0;
330
331 /* Check the mux register in question */
332 if (cfg->mux_reg) {
333 unsigned tmp1, tmp2;
334
335 spin_lock_irqsave(&mux_spin_lock, flags);
336 reg_orig = omap_readl(cfg->mux_reg);
337
338 /* The mux registers always seem to be 3 bits long */
339 mask = (0x7 << cfg->mask_offset);
340 tmp1 = reg_orig & mask;
341 reg = reg_orig & ~mask;
342
343 tmp2 = (cfg->mask << cfg->mask_offset);
344 reg |= tmp2;
345
346 if (tmp1 != tmp2)
347 warn = 1;
348
349 omap_writel(reg, cfg->mux_reg);
350 spin_unlock_irqrestore(&mux_spin_lock, flags);
351 }
352
353 /* Check for pull up or pull down selection on 1610 */
354 if (!cpu_is_omap15xx()) {
355 if (cfg->pu_pd_reg && cfg->pull_val) {
356 spin_lock_irqsave(&mux_spin_lock, flags);
357 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
358 mask = 1 << cfg->pull_bit;
359
360 if (cfg->pu_pd_val) {
361 if (!(pu_pd_orig & mask))
362 warn = 1;
363 /* Use pull up */
364 pu_pd = pu_pd_orig | mask;
365 } else {
366 if (pu_pd_orig & mask)
367 warn = 1;
368 /* Use pull down */
369 pu_pd = pu_pd_orig & ~mask;
370 }
371 omap_writel(pu_pd, cfg->pu_pd_reg);
372 spin_unlock_irqrestore(&mux_spin_lock, flags);
373 }
374 }
375
376 /* Check for an associated pull down register */
377 if (cfg->pull_reg) {
378 spin_lock_irqsave(&mux_spin_lock, flags);
379 pull_orig = omap_readl(cfg->pull_reg);
380 mask = 1 << cfg->pull_bit;
381
382 if (cfg->pull_val) {
383 if (pull_orig & mask)
384 warn = 1;
385 /* Low bit = pull enabled */
386 pull = pull_orig & ~mask;
387 } else {
388 if (!(pull_orig & mask))
389 warn = 1;
390 /* High bit = pull disabled */
391 pull = pull_orig | mask;
392 }
393
394 omap_writel(pull, cfg->pull_reg);
395 spin_unlock_irqrestore(&mux_spin_lock, flags);
396 }
397
398 if (warn) {
399#ifdef CONFIG_OMAP_MUX_WARNINGS
400 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
401#endif
402 }
403
404#ifdef CONFIG_OMAP_MUX_DEBUG
405 if (cfg->debug || warn) {
406 printk("MUX: Setting register %s\n", cfg->name);
407 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
408 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
409
410 if (!cpu_is_omap15xx()) {
411 if (cfg->pu_pd_reg && cfg->pull_val) {
412 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
413 cfg->pu_pd_name, cfg->pu_pd_reg,
414 pu_pd_orig, pu_pd);
415 }
416 }
417
418 if (cfg->pull_reg)
419 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
420 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
421 }
422#endif
423
424#ifdef CONFIG_OMAP_MUX_ERRORS
425 return warn ? -ETXTBSY : 0;
426#else
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]427 return 0;
Tony Lindgren225dfda2008-01-25 00:42:48 -0800[diff] [blame]428#endif
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]429}
430
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]431int __init omap1_mux_init(void)
432{
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]433 if (cpu_is_omap730()) {
434 arch_mux_cfg.pins = omap730_pins;
Tony Lindgren93308992008-01-24 17:24:15 -0800[diff] [blame]435 arch_mux_cfg.size = OMAP730_PINS_SZ;
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]436 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
437 }
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]438
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]439 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
440 arch_mux_cfg.pins = omap1xxx_pins;
Tony Lindgren93308992008-01-24 17:24:15 -0800[diff] [blame]441 arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]442 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
443 }
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]444
Tony Lindgren7d7f6652008-01-25 00:42:48 -0800[diff] [blame]445 return omap_mux_register(&arch_mux_cfg);
Tony Lindgren3179a012005-11-10 14:26:48 +0000[diff] [blame]446}
447
448#endif