blob: c0059ca5834075e70f3fc59512d9ff69617bee29 [file] [log] [blame]
Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
4 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13 * The support for MPC8349 DMA contorller is also added.
14 *
15 * This is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/interrupt.h>
26#include <linux/dmaengine.h>
27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmapool.h>
30#include <linux/of_platform.h>
31
32#include "fsldma.h"
33
34static void dma_init(struct fsl_dma_chan *fsl_chan)
35{
36 /* Reset the channel */
37 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32);
38
39 switch (fsl_chan->feature & FSL_DMA_IP_MASK) {
40 case FSL_DMA_IP_85XX:
41 /* Set the channel to below modes:
42 * EIE - Error interrupt enable
43 * EOSIE - End of segments interrupt enable (basic mode)
44 * EOLNIE - End of links interrupt enable
45 */
46 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE
47 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
48 break;
49 case FSL_DMA_IP_83XX:
50 /* Set the channel to below modes:
51 * EOTIE - End-of-transfer interrupt enable
52 */
53 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE,
54 32);
55 break;
56 }
57
58}
59
Zhang Wei56822842008-03-13 10:45:27 -070060static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070061{
62 DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32);
63}
64
Zhang Wei56822842008-03-13 10:45:27 -070065static u32 get_sr(struct fsl_dma_chan *fsl_chan)
Zhang Wei173acc72008-03-01 07:42:48 -070066{
67 return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32);
68}
69
70static void set_desc_cnt(struct fsl_dma_chan *fsl_chan,
71 struct fsl_dma_ld_hw *hw, u32 count)
72{
73 hw->count = CPU_TO_DMA(fsl_chan, count, 32);
74}
75
76static void set_desc_src(struct fsl_dma_chan *fsl_chan,
77 struct fsl_dma_ld_hw *hw, dma_addr_t src)
78{
79 u64 snoop_bits;
80
81 snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
82 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
83 hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64);
84}
85
86static void set_desc_dest(struct fsl_dma_chan *fsl_chan,
87 struct fsl_dma_ld_hw *hw, dma_addr_t dest)
88{
89 u64 snoop_bits;
90
91 snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
92 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
93 hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64);
94}
95
96static void set_desc_next(struct fsl_dma_chan *fsl_chan,
97 struct fsl_dma_ld_hw *hw, dma_addr_t next)
98{
99 u64 snoop_bits;
100
101 snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
102 ? FSL_DMA_SNEN : 0;
103 hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64);
104}
105
106static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
107{
108 DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64);
109}
110
111static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan)
112{
113 return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN;
114}
115
116static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr)
117{
118 DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64);
119}
120
121static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan)
122{
123 return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64);
124}
125
Zhang Weif79abb62008-03-18 18:45:00 -0700126static u32 get_bcr(struct fsl_dma_chan *fsl_chan)
127{
128 return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32);
129}
130
Zhang Wei173acc72008-03-01 07:42:48 -0700131static int dma_is_idle(struct fsl_dma_chan *fsl_chan)
132{
133 u32 sr = get_sr(fsl_chan);
134 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
135}
136
137static void dma_start(struct fsl_dma_chan *fsl_chan)
138{
139 u32 mr_set = 0;;
140
141 if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
142 DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32);
143 mr_set |= FSL_DMA_MR_EMP_EN;
144 } else
145 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
146 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
147 & ~FSL_DMA_MR_EMP_EN, 32);
148
149 if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT)
150 mr_set |= FSL_DMA_MR_EMS_EN;
151 else
152 mr_set |= FSL_DMA_MR_CS;
153
154 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
155 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
156 | mr_set, 32);
157}
158
159static void dma_halt(struct fsl_dma_chan *fsl_chan)
160{
161 int i = 0;
162 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
163 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA,
164 32);
165 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
166 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS
167 | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32);
168
169 while (!dma_is_idle(fsl_chan) && (i++ < 100))
170 udelay(10);
171 if (i >= 100 && !dma_is_idle(fsl_chan))
172 dev_err(fsl_chan->dev, "DMA halt timeout!\n");
173}
174
175static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
176 struct fsl_desc_sw *desc)
177{
178 desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
179 DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL,
180 64);
181}
182
183static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
184 struct fsl_desc_sw *new_desc)
185{
186 struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev);
187
188 if (list_empty(&fsl_chan->ld_queue))
189 return;
190
191 /* Link to the new descriptor physical address and
192 * Enable End-of-segment interrupt for
193 * the last link descriptor.
194 * (the previous node's next link descriptor)
195 *
196 * For FSL_DMA_IP_83xx, the snoop enable bit need be set.
197 */
198 queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
199 new_desc->async_tx.phys | FSL_DMA_EOSIE |
200 (((fsl_chan->feature & FSL_DMA_IP_MASK)
201 == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64);
202}
203
204/**
205 * fsl_chan_set_src_loop_size - Set source address hold transfer size
206 * @fsl_chan : Freescale DMA channel
207 * @size : Address loop size, 0 for disable loop
208 *
209 * The set source address hold transfer size. The source
210 * address hold or loop transfer size is when the DMA transfer
211 * data from source address (SA), if the loop size is 4, the DMA will
212 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
213 * SA + 1 ... and so on.
214 */
215static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size)
216{
217 switch (size) {
218 case 0:
219 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
220 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
221 (~FSL_DMA_MR_SAHE), 32);
222 break;
223 case 1:
224 case 2:
225 case 4:
226 case 8:
227 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
228 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
229 FSL_DMA_MR_SAHE | (__ilog2(size) << 14),
230 32);
231 break;
232 }
233}
234
235/**
236 * fsl_chan_set_dest_loop_size - Set destination address hold transfer size
237 * @fsl_chan : Freescale DMA channel
238 * @size : Address loop size, 0 for disable loop
239 *
240 * The set destination address hold transfer size. The destination
241 * address hold or loop transfer size is when the DMA transfer
242 * data to destination address (TA), if the loop size is 4, the DMA will
243 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
244 * TA + 1 ... and so on.
245 */
246static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size)
247{
248 switch (size) {
249 case 0:
250 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
251 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) &
252 (~FSL_DMA_MR_DAHE), 32);
253 break;
254 case 1:
255 case 2:
256 case 4:
257 case 8:
258 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
259 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) |
260 FSL_DMA_MR_DAHE | (__ilog2(size) << 16),
261 32);
262 break;
263 }
264}
265
266/**
267 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
268 * @fsl_chan : Freescale DMA channel
269 * @size : Pause control size, 0 for disable external pause control.
270 * The maximum is 1024.
271 *
272 * The Freescale DMA channel can be controlled by the external
273 * signal DREQ#. The pause control size is how many bytes are allowed
274 * to transfer before pausing the channel, after which a new assertion
275 * of DREQ# resumes channel operation.
276 */
277static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size)
278{
279 if (size > 1024)
280 return;
281
282 if (size) {
283 DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr,
284 DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32)
285 | ((__ilog2(size) << 24) & 0x0f000000),
286 32);
287 fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
288 } else
289 fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
290}
291
292/**
293 * fsl_chan_toggle_ext_start - Toggle channel external start status
294 * @fsl_chan : Freescale DMA channel
295 * @enable : 0 is disabled, 1 is enabled.
296 *
297 * If enable the external start, the channel can be started by an
298 * external DMA start pin. So the dma_start() does not start the
299 * transfer immediately. The DMA channel will wait for the
300 * control pin asserted.
301 */
302static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
303{
304 if (enable)
305 fsl_chan->feature |= FSL_DMA_CHAN_START_EXT;
306 else
307 fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT;
308}
309
310static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
311{
312 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
313 struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
314 unsigned long flags;
315 dma_cookie_t cookie;
316
317 /* cookie increment and adding to ld_queue must be atomic */
318 spin_lock_irqsave(&fsl_chan->desc_lock, flags);
319
320 cookie = fsl_chan->common.cookie;
321 cookie++;
322 if (cookie < 0)
323 cookie = 1;
324 desc->async_tx.cookie = cookie;
325 fsl_chan->common.cookie = desc->async_tx.cookie;
326
327 append_ld_queue(fsl_chan, desc);
328 list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev);
329
330 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
331
332 return cookie;
333}
334
335/**
336 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
337 * @fsl_chan : Freescale DMA channel
338 *
339 * Return - The descriptor allocated. NULL for failed.
340 */
341static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
342 struct fsl_dma_chan *fsl_chan)
343{
344 dma_addr_t pdesc;
345 struct fsl_desc_sw *desc_sw;
346
347 desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc);
348 if (desc_sw) {
349 memset(desc_sw, 0, sizeof(struct fsl_desc_sw));
350 dma_async_tx_descriptor_init(&desc_sw->async_tx,
351 &fsl_chan->common);
352 desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
353 INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
354 desc_sw->async_tx.phys = pdesc;
355 }
356
357 return desc_sw;
358}
359
360
361/**
362 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
363 * @fsl_chan : Freescale DMA channel
364 *
365 * This function will create a dma pool for descriptor allocation.
366 *
367 * Return - The number of descriptors allocated.
368 */
Haavard Skinnemoen848c5362008-07-08 11:58:58 -0700369static int fsl_dma_alloc_chan_resources(struct dma_chan *chan,
370 struct dma_client *client)
Zhang Wei173acc72008-03-01 07:42:48 -0700371{
372 struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
373 LIST_HEAD(tmp_list);
374
375 /* We need the descriptor to be aligned to 32bytes
376 * for meeting FSL DMA specification requirement.
377 */
378 fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
379 fsl_chan->dev, sizeof(struct fsl_desc_sw),
380 32, 0);
381 if (!fsl_chan->desc_pool) {
382 dev_err(fsl_chan->dev, "No memory for channel %d "
383 "descriptor dma pool.\n", fsl_chan->id);
384 return 0;
385 }
386
387 return 1;
388}
389
390/**
391 * fsl_dma_free_chan_resources - Free all resources of the channel.
392 * @fsl_chan : Freescale DMA channel
393 */
394static void fsl_dma_free_chan_resources(struct dma_chan *chan)
395{
396 struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
397 struct fsl_desc_sw *desc, *_desc;
398 unsigned long flags;
399
400 dev_dbg(fsl_chan->dev, "Free all channel resources.\n");
401 spin_lock_irqsave(&fsl_chan->desc_lock, flags);
402 list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
403#ifdef FSL_DMA_LD_DEBUG
404 dev_dbg(fsl_chan->dev,
405 "LD %p will be released.\n", desc);
406#endif
407 list_del(&desc->node);
408 /* free link descriptor */
409 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
410 }
411 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
412 dma_pool_destroy(fsl_chan->desc_pool);
413}
414
Zhang Wei2187c262008-03-13 17:45:28 -0700415static struct dma_async_tx_descriptor *
Dan Williams636bdea2008-04-17 20:17:26 -0700416fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags)
Zhang Wei2187c262008-03-13 17:45:28 -0700417{
418 struct fsl_dma_chan *fsl_chan;
419 struct fsl_desc_sw *new;
420
421 if (!chan)
422 return NULL;
423
424 fsl_chan = to_fsl_chan(chan);
425
426 new = fsl_dma_alloc_descriptor(fsl_chan);
427 if (!new) {
428 dev_err(fsl_chan->dev, "No free memory for link descriptor\n");
429 return NULL;
430 }
431
432 new->async_tx.cookie = -EBUSY;
Dan Williams636bdea2008-04-17 20:17:26 -0700433 new->async_tx.flags = flags;
Zhang Wei2187c262008-03-13 17:45:28 -0700434
Zhang Weif79abb62008-03-18 18:45:00 -0700435 /* Insert the link descriptor to the LD ring */
436 list_add_tail(&new->node, &new->async_tx.tx_list);
437
Zhang Wei2187c262008-03-13 17:45:28 -0700438 /* Set End-of-link to the last link descriptor of new list*/
439 set_ld_eol(fsl_chan, new);
440
441 return &new->async_tx;
442}
443
Zhang Wei173acc72008-03-01 07:42:48 -0700444static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
445 struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
446 size_t len, unsigned long flags)
447{
448 struct fsl_dma_chan *fsl_chan;
449 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
450 size_t copy;
451 LIST_HEAD(link_chain);
452
453 if (!chan)
454 return NULL;
455
456 if (!len)
457 return NULL;
458
459 fsl_chan = to_fsl_chan(chan);
460
461 do {
462
463 /* Allocate the link descriptor from DMA pool */
464 new = fsl_dma_alloc_descriptor(fsl_chan);
465 if (!new) {
466 dev_err(fsl_chan->dev,
467 "No free memory for link descriptor\n");
468 return NULL;
469 }
470#ifdef FSL_DMA_LD_DEBUG
471 dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
472#endif
473
Zhang Wei56822842008-03-13 10:45:27 -0700474 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700475
476 set_desc_cnt(fsl_chan, &new->hw, copy);
477 set_desc_src(fsl_chan, &new->hw, dma_src);
478 set_desc_dest(fsl_chan, &new->hw, dma_dest);
479
480 if (!first)
481 first = new;
482 else
483 set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys);
484
485 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700486 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700487
488 prev = new;
489 len -= copy;
490 dma_src += copy;
491 dma_dest += copy;
492
493 /* Insert the link descriptor to the LD ring */
494 list_add_tail(&new->node, &first->async_tx.tx_list);
495 } while (len);
496
Dan Williams636bdea2008-04-17 20:17:26 -0700497 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700498 new->async_tx.cookie = -EBUSY;
499
500 /* Set End-of-link to the last link descriptor of new list*/
501 set_ld_eol(fsl_chan, new);
502
503 return first ? &first->async_tx : NULL;
504}
505
506/**
507 * fsl_dma_update_completed_cookie - Update the completed cookie.
508 * @fsl_chan : Freescale DMA channel
509 */
510static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan)
511{
512 struct fsl_desc_sw *cur_desc, *desc;
513 dma_addr_t ld_phy;
514
515 ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK;
516
517 if (ld_phy) {
518 cur_desc = NULL;
519 list_for_each_entry(desc, &fsl_chan->ld_queue, node)
520 if (desc->async_tx.phys == ld_phy) {
521 cur_desc = desc;
522 break;
523 }
524
525 if (cur_desc && cur_desc->async_tx.cookie) {
526 if (dma_is_idle(fsl_chan))
527 fsl_chan->completed_cookie =
528 cur_desc->async_tx.cookie;
529 else
530 fsl_chan->completed_cookie =
531 cur_desc->async_tx.cookie - 1;
532 }
533 }
534}
535
536/**
537 * fsl_chan_ld_cleanup - Clean up link descriptors
538 * @fsl_chan : Freescale DMA channel
539 *
540 * This function clean up the ld_queue of DMA channel.
541 * If 'in_intr' is set, the function will move the link descriptor to
542 * the recycle list. Otherwise, free it directly.
543 */
544static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan)
545{
546 struct fsl_desc_sw *desc, *_desc;
547 unsigned long flags;
548
549 spin_lock_irqsave(&fsl_chan->desc_lock, flags);
550
Zhang Wei173acc72008-03-01 07:42:48 -0700551 dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n",
552 fsl_chan->completed_cookie);
553 list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) {
554 dma_async_tx_callback callback;
555 void *callback_param;
556
557 if (dma_async_is_complete(desc->async_tx.cookie,
558 fsl_chan->completed_cookie, fsl_chan->common.cookie)
559 == DMA_IN_PROGRESS)
560 break;
561
562 callback = desc->async_tx.callback;
563 callback_param = desc->async_tx.callback_param;
564
565 /* Remove from ld_queue list */
566 list_del(&desc->node);
567
568 dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n",
569 desc);
570 dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys);
571
572 /* Run the link descriptor callback function */
573 if (callback) {
574 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
575 dev_dbg(fsl_chan->dev, "link descriptor %p callback\n",
576 desc);
577 callback(callback_param);
578 spin_lock_irqsave(&fsl_chan->desc_lock, flags);
579 }
580 }
581 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
582}
583
584/**
585 * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue.
586 * @fsl_chan : Freescale DMA channel
587 */
588static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
589{
590 struct list_head *ld_node;
591 dma_addr_t next_dest_addr;
592 unsigned long flags;
593
594 if (!dma_is_idle(fsl_chan))
595 return;
596
597 dma_halt(fsl_chan);
598
599 /* If there are some link descriptors
600 * not transfered in queue. We need to start it.
601 */
602 spin_lock_irqsave(&fsl_chan->desc_lock, flags);
603
604 /* Find the first un-transfer desciptor */
605 for (ld_node = fsl_chan->ld_queue.next;
606 (ld_node != &fsl_chan->ld_queue)
607 && (dma_async_is_complete(
608 to_fsl_desc(ld_node)->async_tx.cookie,
609 fsl_chan->completed_cookie,
610 fsl_chan->common.cookie) == DMA_SUCCESS);
611 ld_node = ld_node->next);
612
613 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
614
615 if (ld_node != &fsl_chan->ld_queue) {
616 /* Get the ld start address from ld_queue */
617 next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
Zhang Wei56822842008-03-13 10:45:27 -0700618 dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n",
619 (void *)next_dest_addr);
Zhang Wei173acc72008-03-01 07:42:48 -0700620 set_cdar(fsl_chan, next_dest_addr);
621 dma_start(fsl_chan);
622 } else {
623 set_cdar(fsl_chan, 0);
624 set_ndar(fsl_chan, 0);
625 }
626}
627
628/**
629 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
630 * @fsl_chan : Freescale DMA channel
631 */
632static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan)
633{
634 struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
635
636#ifdef FSL_DMA_LD_DEBUG
637 struct fsl_desc_sw *ld;
638 unsigned long flags;
639
640 spin_lock_irqsave(&fsl_chan->desc_lock, flags);
641 if (list_empty(&fsl_chan->ld_queue)) {
642 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
643 return;
644 }
645
646 dev_dbg(fsl_chan->dev, "--memcpy issue--\n");
647 list_for_each_entry(ld, &fsl_chan->ld_queue, node) {
648 int i;
649 dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n",
650 fsl_chan->id, ld->async_tx.phys);
651 for (i = 0; i < 8; i++)
652 dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n",
653 i, *(((u32 *)&ld->hw) + i));
654 }
655 dev_dbg(fsl_chan->dev, "----------------\n");
656 spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
657#endif
658
659 fsl_chan_xfer_ld_queue(fsl_chan);
660}
661
Zhang Wei173acc72008-03-01 07:42:48 -0700662/**
663 * fsl_dma_is_complete - Determine the DMA status
664 * @fsl_chan : Freescale DMA channel
665 */
666static enum dma_status fsl_dma_is_complete(struct dma_chan *chan,
667 dma_cookie_t cookie,
668 dma_cookie_t *done,
669 dma_cookie_t *used)
670{
671 struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan);
672 dma_cookie_t last_used;
673 dma_cookie_t last_complete;
674
675 fsl_chan_ld_cleanup(fsl_chan);
676
677 last_used = chan->cookie;
678 last_complete = fsl_chan->completed_cookie;
679
680 if (done)
681 *done = last_complete;
682
683 if (used)
684 *used = last_used;
685
686 return dma_async_is_complete(cookie, last_complete, last_used);
687}
688
689static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
690{
691 struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
Zhang Wei56822842008-03-13 10:45:27 -0700692 u32 stat;
Zhang Wei1c629792008-04-17 20:17:25 -0700693 int update_cookie = 0;
694 int xfer_ld_q = 0;
Zhang Wei173acc72008-03-01 07:42:48 -0700695
696 stat = get_sr(fsl_chan);
697 dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n",
698 fsl_chan->id, stat);
699 set_sr(fsl_chan, stat); /* Clear the event register */
700
701 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
702 if (!stat)
703 return IRQ_NONE;
704
705 if (stat & FSL_DMA_SR_TE)
706 dev_err(fsl_chan->dev, "Transfer Error!\n");
707
Zhang Weif79abb62008-03-18 18:45:00 -0700708 /* Programming Error
709 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
710 * triger a PE interrupt.
711 */
712 if (stat & FSL_DMA_SR_PE) {
713 dev_dbg(fsl_chan->dev, "event: Programming Error INT\n");
714 if (get_bcr(fsl_chan) == 0) {
715 /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
716 * Now, update the completed cookie, and continue the
717 * next uncompleted transfer.
718 */
Zhang Wei1c629792008-04-17 20:17:25 -0700719 update_cookie = 1;
720 xfer_ld_q = 1;
Zhang Weif79abb62008-03-18 18:45:00 -0700721 }
722 stat &= ~FSL_DMA_SR_PE;
723 }
724
Zhang Wei173acc72008-03-01 07:42:48 -0700725 /* If the link descriptor segment transfer finishes,
726 * we will recycle the used descriptor.
727 */
728 if (stat & FSL_DMA_SR_EOSI) {
729 dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
Zhang Wei56822842008-03-13 10:45:27 -0700730 dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n",
731 (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan));
Zhang Wei173acc72008-03-01 07:42:48 -0700732 stat &= ~FSL_DMA_SR_EOSI;
Zhang Wei1c629792008-04-17 20:17:25 -0700733 update_cookie = 1;
734 }
735
736 /* For MPC8349, EOCDI event need to update cookie
737 * and start the next transfer if it exist.
738 */
739 if (stat & FSL_DMA_SR_EOCDI) {
740 dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n");
741 stat &= ~FSL_DMA_SR_EOCDI;
742 update_cookie = 1;
743 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700744 }
745
746 /* If it current transfer is the end-of-transfer,
747 * we should clear the Channel Start bit for
748 * prepare next transfer.
749 */
Zhang Wei1c629792008-04-17 20:17:25 -0700750 if (stat & FSL_DMA_SR_EOLNI) {
Zhang Wei173acc72008-03-01 07:42:48 -0700751 dev_dbg(fsl_chan->dev, "event: End-of-link INT\n");
752 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei1c629792008-04-17 20:17:25 -0700753 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700754 }
755
Zhang Wei1c629792008-04-17 20:17:25 -0700756 if (update_cookie)
757 fsl_dma_update_completed_cookie(fsl_chan);
758 if (xfer_ld_q)
759 fsl_chan_xfer_ld_queue(fsl_chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700760 if (stat)
761 dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n",
762 stat);
763
764 dev_dbg(fsl_chan->dev, "event: Exit\n");
765 tasklet_schedule(&fsl_chan->tasklet);
766 return IRQ_HANDLED;
767}
768
769static irqreturn_t fsl_dma_do_interrupt(int irq, void *data)
770{
771 struct fsl_dma_device *fdev = (struct fsl_dma_device *)data;
772 u32 gsr;
773 int ch_nr;
774
775 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base)
776 : in_le32(fdev->reg_base);
777 ch_nr = (32 - ffs(gsr)) / 8;
778
779 return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq,
780 fdev->chan[ch_nr]) : IRQ_NONE;
781}
782
783static void dma_do_tasklet(unsigned long data)
784{
785 struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data;
786 fsl_chan_ld_cleanup(fsl_chan);
787}
788
Zhang Wei411e23d2008-04-17 20:17:25 -0700789static void fsl_dma_callback_test(void *param)
Zhang Wei173acc72008-03-01 07:42:48 -0700790{
Zhang Wei411e23d2008-04-17 20:17:25 -0700791 struct fsl_dma_chan *fsl_chan = param;
Zhang Wei173acc72008-03-01 07:42:48 -0700792 if (fsl_chan)
Zhang Wei411e23d2008-04-17 20:17:25 -0700793 dev_dbg(fsl_chan->dev, "selftest: callback is ok!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700794}
795
796static int fsl_dma_self_test(struct fsl_dma_chan *fsl_chan)
797{
798 struct dma_chan *chan;
799 int err = 0;
800 dma_addr_t dma_dest, dma_src;
801 dma_cookie_t cookie;
802 u8 *src, *dest;
803 int i;
804 size_t test_size;
805 struct dma_async_tx_descriptor *tx1, *tx2, *tx3;
806
807 test_size = 4096;
808
809 src = kmalloc(test_size * 2, GFP_KERNEL);
810 if (!src) {
811 dev_err(fsl_chan->dev,
812 "selftest: Cannot alloc memory for test!\n");
Li Yang51ee87f2008-05-29 23:25:45 -0700813 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700814 }
815
816 dest = src + test_size;
817
818 for (i = 0; i < test_size; i++)
819 src[i] = (u8) i;
820
821 chan = &fsl_chan->common;
822
Haavard Skinnemoen848c5362008-07-08 11:58:58 -0700823 if (fsl_dma_alloc_chan_resources(chan, NULL) < 1) {
Zhang Wei173acc72008-03-01 07:42:48 -0700824 dev_err(fsl_chan->dev,
825 "selftest: Cannot alloc resources for DMA\n");
826 err = -ENODEV;
827 goto out;
828 }
829
830 /* TX 1 */
831 dma_src = dma_map_single(fsl_chan->dev, src, test_size / 2,
832 DMA_TO_DEVICE);
833 dma_dest = dma_map_single(fsl_chan->dev, dest, test_size / 2,
834 DMA_FROM_DEVICE);
835 tx1 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 2, 0);
836 async_tx_ack(tx1);
837
838 cookie = fsl_dma_tx_submit(tx1);
839 fsl_dma_memcpy_issue_pending(chan);
840 msleep(2);
841
842 if (fsl_dma_is_complete(chan, cookie, NULL, NULL) != DMA_SUCCESS) {
843 dev_err(fsl_chan->dev, "selftest: Time out!\n");
844 err = -ENODEV;
Li Yang51ee87f2008-05-29 23:25:45 -0700845 goto free_resources;
Zhang Wei173acc72008-03-01 07:42:48 -0700846 }
847
848 /* Test free and re-alloc channel resources */
849 fsl_dma_free_chan_resources(chan);
850
Haavard Skinnemoen848c5362008-07-08 11:58:58 -0700851 if (fsl_dma_alloc_chan_resources(chan, NULL) < 1) {
Zhang Wei173acc72008-03-01 07:42:48 -0700852 dev_err(fsl_chan->dev,
853 "selftest: Cannot alloc resources for DMA\n");
854 err = -ENODEV;
855 goto free_resources;
856 }
857
858 /* Continue to test
859 * TX 2
860 */
861 dma_src = dma_map_single(fsl_chan->dev, src + test_size / 2,
862 test_size / 4, DMA_TO_DEVICE);
863 dma_dest = dma_map_single(fsl_chan->dev, dest + test_size / 2,
864 test_size / 4, DMA_FROM_DEVICE);
865 tx2 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 4, 0);
866 async_tx_ack(tx2);
867
868 /* TX 3 */
869 dma_src = dma_map_single(fsl_chan->dev, src + test_size * 3 / 4,
870 test_size / 4, DMA_TO_DEVICE);
871 dma_dest = dma_map_single(fsl_chan->dev, dest + test_size * 3 / 4,
872 test_size / 4, DMA_FROM_DEVICE);
873 tx3 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 4, 0);
874 async_tx_ack(tx3);
875
Zhang Weif79abb62008-03-18 18:45:00 -0700876 /* Interrupt tx test */
Dan Williams636bdea2008-04-17 20:17:26 -0700877 tx1 = fsl_dma_prep_interrupt(chan, 0);
Zhang Weif79abb62008-03-18 18:45:00 -0700878 async_tx_ack(tx1);
879 cookie = fsl_dma_tx_submit(tx1);
880
Zhang Wei173acc72008-03-01 07:42:48 -0700881 /* Test exchanging the prepared tx sort */
882 cookie = fsl_dma_tx_submit(tx3);
883 cookie = fsl_dma_tx_submit(tx2);
884
Zhang Wei173acc72008-03-01 07:42:48 -0700885 if (dma_has_cap(DMA_INTERRUPT, ((struct fsl_dma_device *)
886 dev_get_drvdata(fsl_chan->dev->parent))->common.cap_mask)) {
887 tx3->callback = fsl_dma_callback_test;
888 tx3->callback_param = fsl_chan;
889 }
Zhang Wei173acc72008-03-01 07:42:48 -0700890 fsl_dma_memcpy_issue_pending(chan);
891 msleep(2);
892
893 if (fsl_dma_is_complete(chan, cookie, NULL, NULL) != DMA_SUCCESS) {
894 dev_err(fsl_chan->dev, "selftest: Time out!\n");
895 err = -ENODEV;
896 goto free_resources;
897 }
898
899 err = memcmp(src, dest, test_size);
900 if (err) {
901 for (i = 0; (*(src + i) == *(dest + i)) && (i < test_size);
902 i++);
Zhang Wei56822842008-03-13 10:45:27 -0700903 dev_err(fsl_chan->dev, "selftest: Test failed, data %d/%ld is "
Zhang Wei173acc72008-03-01 07:42:48 -0700904 "error! src 0x%x, dest 0x%x\n",
Zhang Wei56822842008-03-13 10:45:27 -0700905 i, (long)test_size, *(src + i), *(dest + i));
Zhang Wei173acc72008-03-01 07:42:48 -0700906 }
907
908free_resources:
909 fsl_dma_free_chan_resources(chan);
910out:
911 kfree(src);
912 return err;
913}
914
915static int __devinit of_fsl_dma_chan_probe(struct of_device *dev,
916 const struct of_device_id *match)
917{
918 struct fsl_dma_device *fdev;
919 struct fsl_dma_chan *new_fsl_chan;
920 int err;
921
922 fdev = dev_get_drvdata(dev->dev.parent);
923 BUG_ON(!fdev);
924
925 /* alloc channel */
926 new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL);
927 if (!new_fsl_chan) {
928 dev_err(&dev->dev, "No free memory for allocating "
929 "dma channels!\n");
Li Yang51ee87f2008-05-29 23:25:45 -0700930 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700931 }
932
933 /* get dma channel register base */
934 err = of_address_to_resource(dev->node, 0, &new_fsl_chan->reg);
935 if (err) {
936 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
937 dev->node->full_name);
Li Yang51ee87f2008-05-29 23:25:45 -0700938 goto err_no_reg;
Zhang Wei173acc72008-03-01 07:42:48 -0700939 }
940
941 new_fsl_chan->feature = *(u32 *)match->data;
942
943 if (!fdev->feature)
944 fdev->feature = new_fsl_chan->feature;
945
946 /* If the DMA device's feature is different than its channels',
947 * report the bug.
948 */
949 WARN_ON(fdev->feature != new_fsl_chan->feature);
950
951 new_fsl_chan->dev = &dev->dev;
952 new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start,
953 new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
954
955 new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
956 if (new_fsl_chan->id > FSL_DMA_MAX_CHANS_PER_DEVICE) {
957 dev_err(&dev->dev, "There is no %d channel!\n",
958 new_fsl_chan->id);
959 err = -EINVAL;
Li Yang51ee87f2008-05-29 23:25:45 -0700960 goto err_no_chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700961 }
962 fdev->chan[new_fsl_chan->id] = new_fsl_chan;
963 tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet,
964 (unsigned long)new_fsl_chan);
965
966 /* Init the channel */
967 dma_init(new_fsl_chan);
968
969 /* Clear cdar registers */
970 set_cdar(new_fsl_chan, 0);
971
972 switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) {
973 case FSL_DMA_IP_85XX:
974 new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start;
975 new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
976 case FSL_DMA_IP_83XX:
977 new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size;
978 new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size;
979 }
980
981 spin_lock_init(&new_fsl_chan->desc_lock);
982 INIT_LIST_HEAD(&new_fsl_chan->ld_queue);
983
984 new_fsl_chan->common.device = &fdev->common;
985
986 /* Add the channel to DMA device channel list */
987 list_add_tail(&new_fsl_chan->common.device_node,
988 &fdev->common.channels);
989 fdev->common.chancnt++;
990
991 new_fsl_chan->irq = irq_of_parse_and_map(dev->node, 0);
992 if (new_fsl_chan->irq != NO_IRQ) {
993 err = request_irq(new_fsl_chan->irq,
994 &fsl_dma_chan_do_interrupt, IRQF_SHARED,
995 "fsldma-channel", new_fsl_chan);
996 if (err) {
997 dev_err(&dev->dev, "DMA channel %s request_irq error "
998 "with return %d\n", dev->node->full_name, err);
Li Yang51ee87f2008-05-29 23:25:45 -0700999 goto err_no_irq;
Zhang Wei173acc72008-03-01 07:42:48 -07001000 }
1001 }
1002
Zhang Wei173acc72008-03-01 07:42:48 -07001003 err = fsl_dma_self_test(new_fsl_chan);
1004 if (err)
Li Yang51ee87f2008-05-29 23:25:45 -07001005 goto err_self_test;
Zhang Wei173acc72008-03-01 07:42:48 -07001006
1007 dev_info(&dev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id,
1008 match->compatible, new_fsl_chan->irq);
1009
1010 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001011
1012err_self_test:
Zhang Wei173acc72008-03-01 07:42:48 -07001013 free_irq(new_fsl_chan->irq, new_fsl_chan);
Li Yang51ee87f2008-05-29 23:25:45 -07001014err_no_irq:
Zhang Wei173acc72008-03-01 07:42:48 -07001015 list_del(&new_fsl_chan->common.device_node);
Li Yang51ee87f2008-05-29 23:25:45 -07001016err_no_chan:
1017 iounmap(new_fsl_chan->reg_base);
1018err_no_reg:
Zhang Wei173acc72008-03-01 07:42:48 -07001019 kfree(new_fsl_chan);
1020 return err;
1021}
1022
1023const u32 mpc8540_dma_ip_feature = FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN;
1024const u32 mpc8349_dma_ip_feature = FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN;
1025
1026static struct of_device_id of_fsl_dma_chan_ids[] = {
1027 {
Kumar Gala049c9d42008-03-31 11:13:21 -05001028 .compatible = "fsl,eloplus-dma-channel",
Zhang Wei173acc72008-03-01 07:42:48 -07001029 .data = (void *)&mpc8540_dma_ip_feature,
1030 },
1031 {
Kumar Gala049c9d42008-03-31 11:13:21 -05001032 .compatible = "fsl,elo-dma-channel",
Zhang Wei173acc72008-03-01 07:42:48 -07001033 .data = (void *)&mpc8349_dma_ip_feature,
1034 },
1035 {}
1036};
1037
1038static struct of_platform_driver of_fsl_dma_chan_driver = {
1039 .name = "of-fsl-dma-channel",
1040 .match_table = of_fsl_dma_chan_ids,
1041 .probe = of_fsl_dma_chan_probe,
1042};
1043
1044static __init int of_fsl_dma_chan_init(void)
1045{
1046 return of_register_platform_driver(&of_fsl_dma_chan_driver);
1047}
1048
1049static int __devinit of_fsl_dma_probe(struct of_device *dev,
1050 const struct of_device_id *match)
1051{
1052 int err;
1053 unsigned int irq;
1054 struct fsl_dma_device *fdev;
1055
1056 fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL);
1057 if (!fdev) {
1058 dev_err(&dev->dev, "No enough memory for 'priv'\n");
Li Yang51ee87f2008-05-29 23:25:45 -07001059 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -07001060 }
1061 fdev->dev = &dev->dev;
1062 INIT_LIST_HEAD(&fdev->common.channels);
1063
1064 /* get DMA controller register base */
1065 err = of_address_to_resource(dev->node, 0, &fdev->reg);
1066 if (err) {
1067 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1068 dev->node->full_name);
Li Yang51ee87f2008-05-29 23:25:45 -07001069 goto err_no_reg;
Zhang Wei173acc72008-03-01 07:42:48 -07001070 }
1071
1072 dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
Zhang Wei56822842008-03-13 10:45:27 -07001073 "controller at %p...\n",
1074 match->compatible, (void *)fdev->reg.start);
Zhang Wei173acc72008-03-01 07:42:48 -07001075 fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
1076 - fdev->reg.start + 1);
1077
1078 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1079 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
1080 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1081 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei2187c262008-03-13 17:45:28 -07001082 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
Zhang Wei173acc72008-03-01 07:42:48 -07001083 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1084 fdev->common.device_is_tx_complete = fsl_dma_is_complete;
1085 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Zhang Wei173acc72008-03-01 07:42:48 -07001086 fdev->common.dev = &dev->dev;
1087
1088 irq = irq_of_parse_and_map(dev->node, 0);
1089 if (irq != NO_IRQ) {
1090 err = request_irq(irq, &fsl_dma_do_interrupt, IRQF_SHARED,
1091 "fsldma-device", fdev);
1092 if (err) {
1093 dev_err(&dev->dev, "DMA device request_irq error "
1094 "with return %d\n", err);
1095 goto err;
1096 }
1097 }
1098
1099 dev_set_drvdata(&(dev->dev), fdev);
1100 of_platform_bus_probe(dev->node, of_fsl_dma_chan_ids, &dev->dev);
1101
1102 dma_async_device_register(&fdev->common);
1103 return 0;
1104
1105err:
1106 iounmap(fdev->reg_base);
Li Yang51ee87f2008-05-29 23:25:45 -07001107err_no_reg:
Zhang Wei173acc72008-03-01 07:42:48 -07001108 kfree(fdev);
1109 return err;
1110}
1111
1112static struct of_device_id of_fsl_dma_ids[] = {
Kumar Gala049c9d42008-03-31 11:13:21 -05001113 { .compatible = "fsl,eloplus-dma", },
1114 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001115 {}
1116};
1117
1118static struct of_platform_driver of_fsl_dma_driver = {
1119 .name = "of-fsl-dma",
1120 .match_table = of_fsl_dma_ids,
1121 .probe = of_fsl_dma_probe,
1122};
1123
1124static __init int of_fsl_dma_init(void)
1125{
1126 return of_register_platform_driver(&of_fsl_dma_driver);
1127}
1128
1129subsys_initcall(of_fsl_dma_chan_init);
1130subsys_initcall(of_fsl_dma_init);