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gerrit-public.fairphone.software / kernel / msm-4.9 / c807660407a695f390034e402edfe544a1d2e40c / . / drivers / net / wireless / ath5k / phy.c
blob: 7ba18e09463b2ab981712bbfa87766e1a26a7caa [file] [log] [blame]
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1/*
2 * PHY functions
3 *
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300[diff] [blame]4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300[diff] [blame]22#define _ATH5K_PHY
23
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]24#include <linux/delay.h>
25
26#include "ath5k.h"
27#include "reg.h"
28#include "base.h"
29
30/* Struct to hold initial RF register values (RF Banks) */
31struct ath5k_ini_rf {
32 u8 rf_bank; /* check out ath5k_reg.h */
33 u16 rf_register; /* register address */
34 u32 rf_value[5]; /* register value for different modes (above) */
35};
36
37/*
38 * Mode-specific RF Gain table (64bytes) for RF5111/5112
39 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
40 * RF Gain values are included in AR5K_AR5210_INI)
41 */
42struct ath5k_ini_rfgain {
43 u16 rfg_register; /* RF Gain register address */
44 u32 rfg_value[2]; /* [freq (see below)] */
45};
46
47struct ath5k_gain_opt {
48 u32 go_default;
49 u32 go_steps_count;
50 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
51};
52
53/* RF5111 mode-specific init registers */
54static const struct ath5k_ini_rf rfregs_5111[] = {
55 { 0, 0x989c,
56 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
57 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
58 { 0, 0x989c,
59 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
60 { 0, 0x989c,
61 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
62 { 0, 0x989c,
63 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
64 { 0, 0x989c,
65 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
66 { 0, 0x989c,
67 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
68 { 0, 0x989c,
69 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
70 { 0, 0x989c,
71 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
72 { 0, 0x989c,
73 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
74 { 0, 0x989c,
75 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
76 { 0, 0x989c,
77 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
78 { 0, 0x989c,
79 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
80 { 0, 0x989c,
81 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
82 { 0, 0x989c,
83 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
84 { 0, 0x989c,
85 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
86 { 0, 0x989c,
87 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
88 { 0, 0x98d4,
89 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
90 { 1, 0x98d4,
91 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
92 { 2, 0x98d4,
93 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
94 { 3, 0x98d8,
95 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
96 { 6, 0x989c,
97 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
98 { 6, 0x989c,
99 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
100 { 6, 0x989c,
101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
102 { 6, 0x989c,
103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
104 { 6, 0x989c,
105 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
106 { 6, 0x989c,
107 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
108 { 6, 0x989c,
109 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
110 { 6, 0x989c,
111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
112 { 6, 0x989c,
113 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
114 { 6, 0x989c,
115 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
116 { 6, 0x989c,
117 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
118 { 6, 0x989c,
119 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
120 { 6, 0x989c,
121 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
122 { 6, 0x989c,
123 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
124 { 6, 0x989c,
125 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
126 { 6, 0x989c,
127 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
128 { 6, 0x98d4,
129 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
130 { 7, 0x989c,
131 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
132 { 7, 0x989c,
133 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
134 { 7, 0x989c,
135 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
136 { 7, 0x989c,
137 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
138 { 7, 0x989c,
139 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
140 { 7, 0x989c,
141 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
142 { 7, 0x989c,
143 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
144 { 7, 0x98cc,
145 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
146};
147
148/* Initial RF Gain settings for RF5111 */
149static const struct ath5k_ini_rfgain rfgain_5111[] = {
150 /* 5Ghz 2Ghz */
151 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
152 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
153 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
154 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
155 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
156 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
157 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
158 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
159 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
160 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
161 { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
162 { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
163 { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
164 { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
165 { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
166 { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
167 { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
168 { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
169 { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
170 { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
171 { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
172 { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
173 { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
174 { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
175 { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
176 { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
177 { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
178 { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
179 { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
180 { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
181 { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
182 { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
183 { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
184 { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
185 { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
186 { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
187 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
188 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
189 { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
190 { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
191 { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
192 { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
193 { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
194 { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
195 { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
196 { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
197 { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
198 { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
199 { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
200 { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
201 { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
202 { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
203 { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
204 { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
205 { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
206 { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
207 { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
208 { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
209 { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
210 { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
211 { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
212 { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
213 { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
214 { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
215};
216
217static const struct ath5k_gain_opt rfgain_opt_5111 = {
218 4,
219 9,
220 {
221 { { 4, 1, 1, 1 }, 6 },
222 { { 4, 0, 1, 1 }, 4 },
223 { { 3, 1, 1, 1 }, 3 },
224 { { 4, 0, 0, 1 }, 1 },
225 { { 4, 1, 1, 0 }, 0 },
226 { { 4, 0, 1, 0 }, -2 },
227 { { 3, 1, 1, 0 }, -3 },
228 { { 4, 0, 0, 0 }, -4 },
229 { { 2, 1, 1, 0 }, -6 }
230 }
231};
232
233/* RF5112 mode-specific init registers */
234static const struct ath5k_ini_rf rfregs_5112[] = {
235 { 1, 0x98d4,
236 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
237 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
238 { 2, 0x98d0,
239 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
240 { 3, 0x98dc,
241 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
242 { 6, 0x989c,
243 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
244 { 6, 0x989c,
245 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
246 { 6, 0x989c,
247 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
248 { 6, 0x989c,
249 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
250 { 6, 0x989c,
251 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
252 { 6, 0x989c,
253 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
254 { 6, 0x989c,
255 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
256 { 6, 0x989c,
257 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
258 { 6, 0x989c,
259 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
260 { 6, 0x989c,
261 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
262 { 6, 0x989c,
263 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
264 { 6, 0x989c,
265 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
266 { 6, 0x989c,
267 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
268 { 6, 0x989c,
269 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
270 { 6, 0x989c,
271 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
272 { 6, 0x989c,
273 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
274 { 6, 0x989c,
275 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
276 { 6, 0x989c,
277 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
278 { 6, 0x989c,
279 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
280 { 6, 0x989c,
281 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
282 { 6, 0x989c,
283 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
284 { 6, 0x989c,
285 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
286 { 6, 0x989c,
287 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
288 { 6, 0x989c,
289 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
290 { 6, 0x989c,
291 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
292 { 6, 0x989c,
293 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
294 { 6, 0x989c,
295 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
296 { 6, 0x989c,
297 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
298 { 6, 0x989c,
299 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
300 { 6, 0x989c,
301 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
302 { 6, 0x989c,
303 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
304 { 6, 0x989c,
305 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
306 { 6, 0x989c,
307 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
308 { 6, 0x989c,
309 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
310 { 6, 0x989c,
311 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
312 { 6, 0x989c,
313 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
314 { 6, 0x989c,
315 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
316 { 6, 0x98d0,
317 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
318 { 7, 0x989c,
319 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
320 { 7, 0x989c,
321 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
322 { 7, 0x989c,
323 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
324 { 7, 0x989c,
325 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
326 { 7, 0x989c,
327 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
328 { 7, 0x989c,
329 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
330 { 7, 0x989c,
331 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
332 { 7, 0x989c,
333 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
334 { 7, 0x989c,
335 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
336 { 7, 0x989c,
337 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
338 { 7, 0x989c,
339 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
340 { 7, 0x989c,
341 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
342 { 7, 0x98c4,
343 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
344};
345
346/* RF5112A mode-specific init registers */
347static const struct ath5k_ini_rf rfregs_5112a[] = {
348 { 1, 0x98d4,
349 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
350 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
351 { 2, 0x98d0,
352 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
353 { 3, 0x98dc,
354 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
355 { 6, 0x989c,
356 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
357 { 6, 0x989c,
358 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
359 { 6, 0x989c,
360 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
361 { 6, 0x989c,
362 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
363 { 6, 0x989c,
364 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
365 { 6, 0x989c,
366 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
367 { 6, 0x989c,
368 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
369 { 6, 0x989c,
370 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
371 { 6, 0x989c,
372 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
373 { 6, 0x989c,
374 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
375 { 6, 0x989c,
376 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
377 { 6, 0x989c,
378 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
379 { 6, 0x989c,
380 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
381 { 6, 0x989c,
382 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
383 { 6, 0x989c,
384 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
385 { 6, 0x989c,
386 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
387 { 6, 0x989c,
388 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
389 { 6, 0x989c,
390 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
391 { 6, 0x989c,
392 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
393 { 6, 0x989c,
394 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
395 { 6, 0x989c,
396 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
397 { 6, 0x989c,
398 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
399 { 6, 0x989c,
400 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
401 { 6, 0x989c,
402 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
403 { 6, 0x989c,
404 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
405 { 6, 0x989c,
406 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
407 { 6, 0x989c,
408 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
409 { 6, 0x989c,
410 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
411 { 6, 0x989c,
412 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
413 { 6, 0x989c,
414 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
415 { 6, 0x989c,
416 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
417 { 6, 0x989c,
418 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
419 { 6, 0x989c,
420 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
421 { 6, 0x989c,
422 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
423 { 6, 0x989c,
424 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
425 { 6, 0x989c,
426 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
427 { 6, 0x989c,
428 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
429 { 6, 0x989c,
430 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
431 { 6, 0x989c,
432 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
433 { 6, 0x98d8,
434 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
435 { 7, 0x989c,
436 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
437 { 7, 0x989c,
438 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
439 { 7, 0x989c,
440 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
441 { 7, 0x989c,
442 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
443 { 7, 0x989c,
444 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
445 { 7, 0x989c,
446 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
447 { 7, 0x989c,
448 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
449 { 7, 0x989c,
450 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
451 { 7, 0x989c,
452 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
453 { 7, 0x989c,
454 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
455 { 7, 0x989c,
456 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
457 { 7, 0x989c,
458 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
459 { 7, 0x98c4,
460 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
461};
462
463
464static const struct ath5k_ini_rf rfregs_2112a[] = {
465 { 1, AR5K_RF_BUFFER_CONTROL_4,
466 /* mode b mode g mode gTurbo */
467 { 0x00000020, 0x00000020, 0x00000020 } },
468 { 2, AR5K_RF_BUFFER_CONTROL_3,
469 { 0x03060408, 0x03060408, 0x03070408 } },
470 { 3, AR5K_RF_BUFFER_CONTROL_6,
471 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
472 { 6, AR5K_RF_BUFFER,
473 { 0x0a000000, 0x0a000000, 0x0a000000 } },
474 { 6, AR5K_RF_BUFFER,
475 { 0x00000000, 0x00000000, 0x00000000 } },
476 { 6, AR5K_RF_BUFFER,
477 { 0x00800000, 0x00800000, 0x00800000 } },
478 { 6, AR5K_RF_BUFFER,
479 { 0x002a0000, 0x002a0000, 0x002a0000 } },
480 { 6, AR5K_RF_BUFFER,
481 { 0x00010000, 0x00010000, 0x00010000 } },
482 { 6, AR5K_RF_BUFFER,
483 { 0x00000000, 0x00000000, 0x00000000 } },
484 { 6, AR5K_RF_BUFFER,
485 { 0x00180000, 0x00180000, 0x00180000 } },
486 { 6, AR5K_RF_BUFFER,
487 { 0x006e0000, 0x006e0000, 0x006e0000 } },
488 { 6, AR5K_RF_BUFFER,
489 { 0x00c70000, 0x00c70000, 0x00c70000 } },
490 { 6, AR5K_RF_BUFFER,
491 { 0x004b0000, 0x004b0000, 0x004b0000 } },
492 { 6, AR5K_RF_BUFFER,
493 { 0x04480000, 0x04480000, 0x04480000 } },
494 { 6, AR5K_RF_BUFFER,
495 { 0x002a0000, 0x002a0000, 0x002a0000 } },
496 { 6, AR5K_RF_BUFFER,
497 { 0x00e40000, 0x00e40000, 0x00e40000 } },
498 { 6, AR5K_RF_BUFFER,
499 { 0x00000000, 0x00000000, 0x00000000 } },
500 { 6, AR5K_RF_BUFFER,
501 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
502 { 6, AR5K_RF_BUFFER,
503 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
504 { 6, AR5K_RF_BUFFER,
505 { 0x043f0000, 0x043f0000, 0x043f0000 } },
506 { 6, AR5K_RF_BUFFER,
507 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
508 { 6, AR5K_RF_BUFFER,
509 { 0x02190000, 0x02190000, 0x02190000 } },
510 { 6, AR5K_RF_BUFFER,
511 { 0x00240000, 0x00240000, 0x00240000 } },
512 { 6, AR5K_RF_BUFFER,
513 { 0x00b40000, 0x00b40000, 0x00b40000 } },
514 { 6, AR5K_RF_BUFFER,
515 { 0x00990000, 0x00990000, 0x00990000 } },
516 { 6, AR5K_RF_BUFFER,
517 { 0x00500000, 0x00500000, 0x00500000 } },
518 { 6, AR5K_RF_BUFFER,
519 { 0x002a0000, 0x002a0000, 0x002a0000 } },
520 { 6, AR5K_RF_BUFFER,
521 { 0x00120000, 0x00120000, 0x00120000 } },
522 { 6, AR5K_RF_BUFFER,
523 { 0xc0320000, 0xc0320000, 0xc0320000 } },
524 { 6, AR5K_RF_BUFFER,
525 { 0x01740000, 0x01740000, 0x01740000 } },
526 { 6, AR5K_RF_BUFFER,
527 { 0x00110000, 0x00110000, 0x00110000 } },
528 { 6, AR5K_RF_BUFFER,
529 { 0x86280000, 0x86280000, 0x86280000 } },
530 { 6, AR5K_RF_BUFFER,
531 { 0x31840000, 0x31840000, 0x31840000 } },
532 { 6, AR5K_RF_BUFFER,
533 { 0x00f20080, 0x00f20080, 0x00f20080 } },
534 { 6, AR5K_RF_BUFFER,
535 { 0x00070019, 0x00070019, 0x00070019 } },
536 { 6, AR5K_RF_BUFFER,
537 { 0x00000000, 0x00000000, 0x00000000 } },
538 { 6, AR5K_RF_BUFFER,
539 { 0x00000000, 0x00000000, 0x00000000 } },
540 { 6, AR5K_RF_BUFFER,
541 { 0x000000b2, 0x000000b2, 0x000000b2 } },
542 { 6, AR5K_RF_BUFFER,
543 { 0x00b02184, 0x00b02184, 0x00b02184 } },
544 { 6, AR5K_RF_BUFFER,
545 { 0x004125a4, 0x004125a4, 0x004125a4 } },
546 { 6, AR5K_RF_BUFFER,
547 { 0x00119220, 0x00119220, 0x00119220 } },
548 { 6, AR5K_RF_BUFFER,
549 { 0x001a4800, 0x001a4800, 0x001a4800 } },
550 { 6, AR5K_RF_BUFFER_CONTROL_5,
551 { 0x000b0230, 0x000b0230, 0x000b0230 } },
552 { 7, AR5K_RF_BUFFER,
553 { 0x00000094, 0x00000094, 0x00000094 } },
554 { 7, AR5K_RF_BUFFER,
555 { 0x00000091, 0x00000091, 0x00000091 } },
556 { 7, AR5K_RF_BUFFER,
557 { 0x00000012, 0x00000012, 0x00000012 } },
558 { 7, AR5K_RF_BUFFER,
559 { 0x00000080, 0x00000080, 0x00000080 } },
560 { 7, AR5K_RF_BUFFER,
561 { 0x000000d9, 0x000000d9, 0x000000d9 } },
562 { 7, AR5K_RF_BUFFER,
563 { 0x00000060, 0x00000060, 0x00000060 } },
564 { 7, AR5K_RF_BUFFER,
565 { 0x000000f0, 0x000000f0, 0x000000f0 } },
566 { 7, AR5K_RF_BUFFER,
567 { 0x000000a2, 0x000000a2, 0x000000a2 } },
568 { 7, AR5K_RF_BUFFER,
569 { 0x00000052, 0x00000052, 0x00000052 } },
570 { 7, AR5K_RF_BUFFER,
571 { 0x000000d4, 0x000000d4, 0x000000d4 } },
572 { 7, AR5K_RF_BUFFER,
573 { 0x000014cc, 0x000014cc, 0x000014cc } },
574 { 7, AR5K_RF_BUFFER,
575 { 0x0000048c, 0x0000048c, 0x0000048c } },
576 { 7, AR5K_RF_BUFFER_CONTROL_1,
577 { 0x00000003, 0x00000003, 0x00000003 } },
578};
579
580/* RF5413/5414 mode-specific init registers */
581static const struct ath5k_ini_rf rfregs_5413[] = {
582 { 1, 0x98d4,
583 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
584 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
585 { 2, 0x98d0,
586 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
587 { 3, 0x98dc,
588 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
589 { 6, 0x989c,
590 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
591 { 6, 0x989c,
592 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
593 { 6, 0x989c,
594 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
595 { 6, 0x989c,
596 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
597 { 6, 0x989c,
598 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
599 { 6, 0x989c,
600 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
601 { 6, 0x989c,
602 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
603 { 6, 0x989c,
604 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
605 { 6, 0x989c,
606 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
607 { 6, 0x989c,
608 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
609 { 6, 0x989c,
610 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
611 { 6, 0x989c,
612 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
613 { 6, 0x989c,
614 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
615 { 6, 0x989c,
616 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
617 { 6, 0x989c,
618 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
619 { 6, 0x989c,
620 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
621 { 6, 0x989c,
622 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
623 { 6, 0x989c,
624 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
625 { 6, 0x989c,
626 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
627 { 6, 0x989c,
628 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
629 { 6, 0x989c,
630 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
631 { 6, 0x989c,
632 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
633 { 6, 0x989c,
634 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
635 { 6, 0x989c,
636 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
637 { 6, 0x989c,
638 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
639 { 6, 0x989c,
640 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
641 { 6, 0x989c,
642 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
643 { 6, 0x989c,
644 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
645 { 6, 0x989c,
646 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
647 { 6, 0x989c,
648 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
649 { 6, 0x989c,
650 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
651 { 6, 0x989c,
652 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
653 { 6, 0x989c,
654 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
655 { 6, 0x989c,
656 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
657 { 6, 0x989c,
658 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
659 { 6, 0x989c,
660 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
661 { 6, 0x98c8,
662 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
663 { 7, 0x989c,
664 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
665 { 7, 0x989c,
666 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
667 { 7, 0x98cc,
668 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
669};
670
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]671/* RF2413/2414 mode-specific init registers */
672static const struct ath5k_ini_rf rfregs_2413[] = {
673 { 1, AR5K_RF_BUFFER_CONTROL_4,
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]674 /* mode b mode g mode gTurbo */
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]675 { 0x00000020, 0x00000020, 0x00000020 } },
676 { 2, AR5K_RF_BUFFER_CONTROL_3,
677 { 0x02001408, 0x02001408, 0x02001408 } },
678 { 3, AR5K_RF_BUFFER_CONTROL_6,
679 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
680 { 6, AR5K_RF_BUFFER,
681 { 0xf0000000, 0xf0000000, 0xf0000000 } },
682 { 6, AR5K_RF_BUFFER,
683 { 0x00000000, 0x00000000, 0x00000000 } },
684 { 6, AR5K_RF_BUFFER,
685 { 0x03000000, 0x03000000, 0x03000000 } },
686 { 6, AR5K_RF_BUFFER,
687 { 0x00000000, 0x00000000, 0x00000000 } },
688 { 6, AR5K_RF_BUFFER,
689 { 0x00000000, 0x00000000, 0x00000000 } },
690 { 6, AR5K_RF_BUFFER,
691 { 0x00000000, 0x00000000, 0x00000000 } },
692 { 6, AR5K_RF_BUFFER,
693 { 0x00000000, 0x00000000, 0x00000000 } },
694 { 6, AR5K_RF_BUFFER,
695 { 0x00000000, 0x00000000, 0x00000000 } },
696 { 6, AR5K_RF_BUFFER,
697 { 0x40400000, 0x40400000, 0x40400000 } },
698 { 6, AR5K_RF_BUFFER,
699 { 0x65050000, 0x65050000, 0x65050000 } },
700 { 6, AR5K_RF_BUFFER,
701 { 0x00000000, 0x00000000, 0x00000000 } },
702 { 6, AR5K_RF_BUFFER,
703 { 0x00000000, 0x00000000, 0x00000000 } },
704 { 6, AR5K_RF_BUFFER,
705 { 0x00420000, 0x00420000, 0x00420000 } },
706 { 6, AR5K_RF_BUFFER,
707 { 0x00b50000, 0x00b50000, 0x00b50000 } },
708 { 6, AR5K_RF_BUFFER,
709 { 0x00030000, 0x00030000, 0x00030000 } },
710 { 6, AR5K_RF_BUFFER,
711 { 0x00f70000, 0x00f70000, 0x00f70000 } },
712 { 6, AR5K_RF_BUFFER,
713 { 0x009d0000, 0x009d0000, 0x009d0000 } },
714 { 6, AR5K_RF_BUFFER,
715 { 0x00220000, 0x00220000, 0x00220000 } },
716 { 6, AR5K_RF_BUFFER,
717 { 0x04220000, 0x04220000, 0x04220000 } },
718 { 6, AR5K_RF_BUFFER,
719 { 0x00230018, 0x00230018, 0x00230018 } },
720 { 6, AR5K_RF_BUFFER,
721 { 0x00280050, 0x00280050, 0x00280050 } },
722 { 6, AR5K_RF_BUFFER,
723 { 0x005000c3, 0x005000c3, 0x005000c3 } },
724 { 6, AR5K_RF_BUFFER,
725 { 0x0004007f, 0x0004007f, 0x0004007f } },
726 { 6, AR5K_RF_BUFFER,
727 { 0x00000458, 0x00000458, 0x00000458 } },
728 { 6, AR5K_RF_BUFFER,
729 { 0x00000000, 0x00000000, 0x00000000 } },
730 { 6, AR5K_RF_BUFFER,
731 { 0x0000c000, 0x0000c000, 0x0000c000 } },
732 { 6, AR5K_RF_BUFFER_CONTROL_5,
733 { 0x00400230, 0x00400230, 0x00400230 } },
734 { 7, AR5K_RF_BUFFER,
735 { 0x00006400, 0x00006400, 0x00006400 } },
736 { 7, AR5K_RF_BUFFER,
737 { 0x00000800, 0x00000800, 0x00000800 } },
738 { 7, AR5K_RF_BUFFER_CONTROL_2,
739 { 0x0000000e, 0x0000000e, 0x0000000e } },
740};
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]741
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]742/* RF2425 mode-specific init registers */
743static const struct ath5k_ini_rf rfregs_2425[] = {
744 { 1, AR5K_RF_BUFFER_CONTROL_4,
745 /* mode g mode gTurbo */
746 { 0x00000020, 0x00000020 } },
747 { 2, AR5K_RF_BUFFER_CONTROL_3,
748 { 0x02001408, 0x02001408 } },
749 { 3, AR5K_RF_BUFFER_CONTROL_6,
750 { 0x00e020c0, 0x00e020c0 } },
751 { 6, AR5K_RF_BUFFER,
752 { 0x10000000, 0x10000000 } },
753 { 6, AR5K_RF_BUFFER,
754 { 0x00000000, 0x00000000 } },
755 { 6, AR5K_RF_BUFFER,
756 { 0x00000000, 0x00000000 } },
757 { 6, AR5K_RF_BUFFER,
758 { 0x00000000, 0x00000000 } },
759 { 6, AR5K_RF_BUFFER,
760 { 0x00000000, 0x00000000 } },
761 { 6, AR5K_RF_BUFFER,
762 { 0x00000000, 0x00000000 } },
763 { 6, AR5K_RF_BUFFER,
764 { 0x00000000, 0x00000000 } },
765 { 6, AR5K_RF_BUFFER,
766 { 0x00000000, 0x00000000 } },
767 { 6, AR5K_RF_BUFFER,
768 { 0x00000000, 0x00000000 } },
769 { 6, AR5K_RF_BUFFER,
770 { 0x00000000, 0x00000000 } },
771 { 6, AR5K_RF_BUFFER,
772 { 0x00000000, 0x00000000 } },
773 { 6, AR5K_RF_BUFFER,
774 { 0x002a0000, 0x002a0000 } },
775 { 6, AR5K_RF_BUFFER,
776 { 0x00000000, 0x00000000 } },
777 { 6, AR5K_RF_BUFFER,
778 { 0x00000000, 0x00000000 } },
779 { 6, AR5K_RF_BUFFER,
780 { 0x00100000, 0x00100000 } },
781 { 6, AR5K_RF_BUFFER,
782 { 0x00020000, 0x00020000 } },
783 { 6, AR5K_RF_BUFFER,
784 { 0x00730000, 0x00730000 } },
785 { 6, AR5K_RF_BUFFER,
786 { 0x00f80000, 0x00f80000 } },
787 { 6, AR5K_RF_BUFFER,
788 { 0x00e70000, 0x00e70000 } },
789 { 6, AR5K_RF_BUFFER,
790 { 0x00140000, 0x00140000 } },
791 { 6, AR5K_RF_BUFFER,
792 { 0x00910040, 0x00910040 } },
793 { 6, AR5K_RF_BUFFER,
794 { 0x0007001a, 0x0007001a } },
795 { 6, AR5K_RF_BUFFER,
796 { 0x00410000, 0x00410000 } },
797 { 6, AR5K_RF_BUFFER,
798 { 0x00810060, 0x00810060 } },
799 { 6, AR5K_RF_BUFFER,
800 { 0x00020803, 0x00020803 } },
801 { 6, AR5K_RF_BUFFER,
802 { 0x00000000, 0x00000000 } },
803 { 6, AR5K_RF_BUFFER,
804 { 0x00000000, 0x00000000 } },
805 { 6, AR5K_RF_BUFFER,
806 { 0x00001660, 0x00001660 } },
807 { 6, AR5K_RF_BUFFER,
808 { 0x00001688, 0x00001688 } },
809 { 6, AR5K_RF_BUFFER_CONTROL_1,
810 { 0x00000001, 0x00000001 } },
811 { 7, AR5K_RF_BUFFER,
812 { 0x00006400, 0x00006400 } },
813 { 7, AR5K_RF_BUFFER,
814 { 0x00000800, 0x00000800 } },
815 { 7, AR5K_RF_BUFFER_CONTROL_2,
816 { 0x0000000e, 0x0000000e } },
817};
818
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]819/* Initial RF Gain settings for RF5112 */
820static const struct ath5k_ini_rfgain rfgain_5112[] = {
821 /* 5Ghz 2Ghz */
822 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
823 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
824 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
825 { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
826 { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
827 { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
828 { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
829 { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
830 { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
831 { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
832 { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
833 { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
834 { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
835 { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
836 { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
837 { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
838 { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
839 { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
840 { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
841 { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
842 { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
843 { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
844 { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
845 { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
846 { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
847 { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
848 { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
849 { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
850 { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
851 { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
852 { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
853 { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
854 { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
855 { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
856 { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
857 { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
858 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
859 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
860 { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
861 { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
862 { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
863 { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
864 { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
865 { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
866 { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
867 { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
868 { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
869 { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
870 { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
871 { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
872 { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
873 { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
874 { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
875 { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
876 { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
877 { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
878 { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
879 { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
880 { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
881 { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
882 { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
883 { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
884 { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
885 { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
886};
887
888/* Initial RF Gain settings for RF5413 */
889static const struct ath5k_ini_rfgain rfgain_5413[] = {
890 /* 5Ghz 2Ghz */
891 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
892 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
893 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
894 { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
895 { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
896 { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
897 { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
898 { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
899 { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
900 { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
901 { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
902 { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
903 { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
904 { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
905 { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
906 { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
907 { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
908 { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
909 { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
910 { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
911 { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
912 { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
913 { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
914 { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
915 { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
916 { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
917 { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
918 { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
919 { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
920 { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
921 { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
922 { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
923 { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
924 { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
925 { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
926 { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
927 { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
928 { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
929 { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
930 { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
931 { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
932 { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
933 { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
934 { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
935 { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
936 { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
937 { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
938 { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
939 { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
940 { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
941 { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
942 { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
943 { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
944 { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
945 { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
946 { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
947 { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
948 { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
949 { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
950 { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
951 { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
952 { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
953 { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
954 { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
955};
956
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]957/* Initial RF Gain settings for RF2413 */
958static const struct ath5k_ini_rfgain rfgain_2413[] = {
959 { AR5K_RF_GAIN(0), { 0x00000000 } },
960 { AR5K_RF_GAIN(1), { 0x00000040 } },
961 { AR5K_RF_GAIN(2), { 0x00000080 } },
962 { AR5K_RF_GAIN(3), { 0x00000181 } },
963 { AR5K_RF_GAIN(4), { 0x000001c1 } },
964 { AR5K_RF_GAIN(5), { 0x00000001 } },
965 { AR5K_RF_GAIN(6), { 0x00000041 } },
966 { AR5K_RF_GAIN(7), { 0x00000081 } },
967 { AR5K_RF_GAIN(8), { 0x00000168 } },
968 { AR5K_RF_GAIN(9), { 0x000001a8 } },
969 { AR5K_RF_GAIN(10), { 0x000001e8 } },
970 { AR5K_RF_GAIN(11), { 0x00000028 } },
971 { AR5K_RF_GAIN(12), { 0x00000068 } },
972 { AR5K_RF_GAIN(13), { 0x00000189 } },
973 { AR5K_RF_GAIN(14), { 0x000001c9 } },
974 { AR5K_RF_GAIN(15), { 0x00000009 } },
975 { AR5K_RF_GAIN(16), { 0x00000049 } },
976 { AR5K_RF_GAIN(17), { 0x00000089 } },
977 { AR5K_RF_GAIN(18), { 0x00000190 } },
978 { AR5K_RF_GAIN(19), { 0x000001d0 } },
979 { AR5K_RF_GAIN(20), { 0x00000010 } },
980 { AR5K_RF_GAIN(21), { 0x00000050 } },
981 { AR5K_RF_GAIN(22), { 0x00000090 } },
982 { AR5K_RF_GAIN(23), { 0x00000191 } },
983 { AR5K_RF_GAIN(24), { 0x000001d1 } },
984 { AR5K_RF_GAIN(25), { 0x00000011 } },
985 { AR5K_RF_GAIN(26), { 0x00000051 } },
986 { AR5K_RF_GAIN(27), { 0x00000091 } },
987 { AR5K_RF_GAIN(28), { 0x00000178 } },
988 { AR5K_RF_GAIN(29), { 0x000001b8 } },
989 { AR5K_RF_GAIN(30), { 0x000001f8 } },
990 { AR5K_RF_GAIN(31), { 0x00000038 } },
991 { AR5K_RF_GAIN(32), { 0x00000078 } },
992 { AR5K_RF_GAIN(33), { 0x00000199 } },
993 { AR5K_RF_GAIN(34), { 0x000001d9 } },
994 { AR5K_RF_GAIN(35), { 0x00000019 } },
995 { AR5K_RF_GAIN(36), { 0x00000059 } },
996 { AR5K_RF_GAIN(37), { 0x00000099 } },
997 { AR5K_RF_GAIN(38), { 0x000000d9 } },
998 { AR5K_RF_GAIN(39), { 0x000000f9 } },
999 { AR5K_RF_GAIN(40), { 0x000000f9 } },
1000 { AR5K_RF_GAIN(41), { 0x000000f9 } },
1001 { AR5K_RF_GAIN(42), { 0x000000f9 } },
1002 { AR5K_RF_GAIN(43), { 0x000000f9 } },
1003 { AR5K_RF_GAIN(44), { 0x000000f9 } },
1004 { AR5K_RF_GAIN(45), { 0x000000f9 } },
1005 { AR5K_RF_GAIN(46), { 0x000000f9 } },
1006 { AR5K_RF_GAIN(47), { 0x000000f9 } },
1007 { AR5K_RF_GAIN(48), { 0x000000f9 } },
1008 { AR5K_RF_GAIN(49), { 0x000000f9 } },
1009 { AR5K_RF_GAIN(50), { 0x000000f9 } },
1010 { AR5K_RF_GAIN(51), { 0x000000f9 } },
1011 { AR5K_RF_GAIN(52), { 0x000000f9 } },
1012 { AR5K_RF_GAIN(53), { 0x000000f9 } },
1013 { AR5K_RF_GAIN(54), { 0x000000f9 } },
1014 { AR5K_RF_GAIN(55), { 0x000000f9 } },
1015 { AR5K_RF_GAIN(56), { 0x000000f9 } },
1016 { AR5K_RF_GAIN(57), { 0x000000f9 } },
1017 { AR5K_RF_GAIN(58), { 0x000000f9 } },
1018 { AR5K_RF_GAIN(59), { 0x000000f9 } },
1019 { AR5K_RF_GAIN(60), { 0x000000f9 } },
1020 { AR5K_RF_GAIN(61), { 0x000000f9 } },
1021 { AR5K_RF_GAIN(62), { 0x000000f9 } },
1022 { AR5K_RF_GAIN(63), { 0x000000f9 } },
1023};
1024
Nick Kossifidis27bcdee2008-07-20 06:42:47 +0300[diff] [blame]1025/* Initial RF Gain settings for RF2425 */
1026static const struct ath5k_ini_rfgain rfgain_2425[] = {
1027 { AR5K_RF_GAIN(0), { 0x00000000 } },
1028 { AR5K_RF_GAIN(1), { 0x00000040 } },
1029 { AR5K_RF_GAIN(2), { 0x00000080 } },
1030 { AR5K_RF_GAIN(3), { 0x00000181 } },
1031 { AR5K_RF_GAIN(4), { 0x000001c1 } },
1032 { AR5K_RF_GAIN(5), { 0x00000001 } },
1033 { AR5K_RF_GAIN(6), { 0x00000041 } },
1034 { AR5K_RF_GAIN(7), { 0x00000081 } },
1035 { AR5K_RF_GAIN(8), { 0x00000188 } },
1036 { AR5K_RF_GAIN(9), { 0x000001c8 } },
1037 { AR5K_RF_GAIN(10), { 0x00000008 } },
1038 { AR5K_RF_GAIN(11), { 0x00000048 } },
1039 { AR5K_RF_GAIN(12), { 0x00000088 } },
1040 { AR5K_RF_GAIN(13), { 0x00000189 } },
1041 { AR5K_RF_GAIN(14), { 0x000001c9 } },
1042 { AR5K_RF_GAIN(15), { 0x00000009 } },
1043 { AR5K_RF_GAIN(16), { 0x00000049 } },
1044 { AR5K_RF_GAIN(17), { 0x00000089 } },
1045 { AR5K_RF_GAIN(18), { 0x000001b0 } },
1046 { AR5K_RF_GAIN(19), { 0x000001f0 } },
1047 { AR5K_RF_GAIN(20), { 0x00000030 } },
1048 { AR5K_RF_GAIN(21), { 0x00000070 } },
1049 { AR5K_RF_GAIN(22), { 0x00000171 } },
1050 { AR5K_RF_GAIN(23), { 0x000001b1 } },
1051 { AR5K_RF_GAIN(24), { 0x000001f1 } },
1052 { AR5K_RF_GAIN(25), { 0x00000031 } },
1053 { AR5K_RF_GAIN(26), { 0x00000071 } },
1054 { AR5K_RF_GAIN(27), { 0x000001b8 } },
1055 { AR5K_RF_GAIN(28), { 0x000001f8 } },
1056 { AR5K_RF_GAIN(29), { 0x00000038 } },
1057 { AR5K_RF_GAIN(30), { 0x00000078 } },
1058 { AR5K_RF_GAIN(31), { 0x000000b8 } },
1059 { AR5K_RF_GAIN(32), { 0x000001b9 } },
1060 { AR5K_RF_GAIN(33), { 0x000001f9 } },
1061 { AR5K_RF_GAIN(34), { 0x00000039 } },
1062 { AR5K_RF_GAIN(35), { 0x00000079 } },
1063 { AR5K_RF_GAIN(36), { 0x000000b9 } },
1064 { AR5K_RF_GAIN(37), { 0x000000f9 } },
1065 { AR5K_RF_GAIN(38), { 0x000000f9 } },
1066 { AR5K_RF_GAIN(39), { 0x000000f9 } },
1067 { AR5K_RF_GAIN(40), { 0x000000f9 } },
1068 { AR5K_RF_GAIN(41), { 0x000000f9 } },
1069 { AR5K_RF_GAIN(42), { 0x000000f9 } },
1070 { AR5K_RF_GAIN(43), { 0x000000f9 } },
1071 { AR5K_RF_GAIN(44), { 0x000000f9 } },
1072 { AR5K_RF_GAIN(45), { 0x000000f9 } },
1073 { AR5K_RF_GAIN(46), { 0x000000f9 } },
1074 { AR5K_RF_GAIN(47), { 0x000000f9 } },
1075 { AR5K_RF_GAIN(48), { 0x000000f9 } },
1076 { AR5K_RF_GAIN(49), { 0x000000f9 } },
1077 { AR5K_RF_GAIN(50), { 0x000000f9 } },
1078 { AR5K_RF_GAIN(51), { 0x000000f9 } },
1079 { AR5K_RF_GAIN(52), { 0x000000f9 } },
1080 { AR5K_RF_GAIN(53), { 0x000000f9 } },
1081 { AR5K_RF_GAIN(54), { 0x000000f9 } },
1082 { AR5K_RF_GAIN(55), { 0x000000f9 } },
1083 { AR5K_RF_GAIN(56), { 0x000000f9 } },
1084 { AR5K_RF_GAIN(57), { 0x000000f9 } },
1085 { AR5K_RF_GAIN(58), { 0x000000f9 } },
1086 { AR5K_RF_GAIN(59), { 0x000000f9 } },
1087 { AR5K_RF_GAIN(60), { 0x000000f9 } },
1088 { AR5K_RF_GAIN(61), { 0x000000f9 } },
1089 { AR5K_RF_GAIN(62), { 0x000000f9 } },
1090 { AR5K_RF_GAIN(63), { 0x000000f9 } },
1091};
1092
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1093static const struct ath5k_gain_opt rfgain_opt_5112 = {
1094 1,
1095 8,
1096 {
1097 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
1098 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
1099 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
1100 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
1101 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
1102 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
1103 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
1104 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
1105 }
1106};
1107
1108/*
1109 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
1110 */
1111static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
1112 u32 first, u32 col, bool set)
1113{
1114 u32 mask, entry, last, data, shift, position;
1115 s32 left;
1116 int i;
1117
1118 data = 0;
1119
1120 if (rf == NULL)
1121 /* should not happen */
1122 return 0;
1123
1124 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
1125 ATH5K_PRINTF("invalid values at offset %u\n", offset);
1126 return 0;
1127 }
1128
1129 entry = ((first - 1) / 8) + offset;
1130 position = (first - 1) % 8;
1131
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame]1132 if (set)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1133 data = ath5k_hw_bitswap(reg, bits);
1134
1135 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
1136 last = (position + left > 8) ? 8 : position + left;
1137 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
1138
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame]1139 if (set) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1140 rf[entry] &= ~mask;
1141 rf[entry] |= ((data << position) << (col * 8)) & mask;
1142 data >>= (8 - position);
1143 } else {
1144 data = (((rf[entry] & mask) >> (col * 8)) >> position)
1145 << shift;
1146 shift += last - position;
1147 }
1148
1149 left -= 8 - position;
1150 }
1151
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame]1152 data = set ? 1 : ath5k_hw_bitswap(data, bits);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1153
1154 return data;
1155}
1156
1157static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
1158{
1159 u32 mix, step;
1160 u32 *rf;
1161
1162 if (ah->ah_rf_banks == NULL)
1163 return 0;
1164
1165 rf = ah->ah_rf_banks;
1166 ah->ah_gain.g_f_corr = 0;
1167
1168 if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
1169 return 0;
1170
1171 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
1172 mix = ah->ah_gain.g_step->gos_param[0];
1173
1174 switch (mix) {
1175 case 3:
1176 ah->ah_gain.g_f_corr = step * 2;
1177 break;
1178 case 2:
1179 ah->ah_gain.g_f_corr = (step - 5) * 2;
1180 break;
1181 case 1:
1182 ah->ah_gain.g_f_corr = step;
1183 break;
1184 default:
1185 ah->ah_gain.g_f_corr = 0;
1186 break;
1187 }
1188
1189 return ah->ah_gain.g_f_corr;
1190}
1191
1192static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
1193{
1194 u32 step, mix, level[4];
1195 u32 *rf;
1196
1197 if (ah->ah_rf_banks == NULL)
1198 return false;
1199
1200 rf = ah->ah_rf_banks;
1201
1202 if (ah->ah_radio == AR5K_RF5111) {
1203 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
1204 false);
1205 level[0] = 0;
1206 level[1] = (step == 0x3f) ? 0x32 : step + 4;
1207 level[2] = (step != 0x3f) ? 0x40 : level[0];
1208 level[3] = level[2] + 0x32;
1209
1210 ah->ah_gain.g_high = level[3] -
1211 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
1212 ah->ah_gain.g_low = level[0] +
1213 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
1214 } else {
1215 mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
1216 false);
1217 level[0] = level[2] = 0;
1218
1219 if (mix == 1) {
1220 level[1] = level[3] = 83;
1221 } else {
1222 level[1] = level[3] = 107;
1223 ah->ah_gain.g_high = 55;
1224 }
1225 }
1226
1227 return (ah->ah_gain.g_current >= level[0] &&
1228 ah->ah_gain.g_current <= level[1]) ||
1229 (ah->ah_gain.g_current >= level[2] &&
1230 ah->ah_gain.g_current <= level[3]);
1231}
1232
1233static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
1234{
1235 const struct ath5k_gain_opt *go;
1236 int ret = 0;
1237
1238 switch (ah->ah_radio) {
1239 case AR5K_RF5111:
1240 go = &rfgain_opt_5111;
1241 break;
1242 case AR5K_RF5112:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1243 go = &rfgain_opt_5112;
1244 break;
1245 default:
1246 return 0;
1247 }
1248
1249 ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
1250
1251 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
1252 if (ah->ah_gain.g_step_idx == 0)
1253 return -1;
1254 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1255 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
1256 ah->ah_gain.g_step_idx > 0;
1257 ah->ah_gain.g_step =
1258 &go->go_step[ah->ah_gain.g_step_idx])
1259 ah->ah_gain.g_target -= 2 *
1260 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
1261 ah->ah_gain.g_step->gos_gain);
1262
1263 ret = 1;
1264 goto done;
1265 }
1266
1267 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
1268 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
1269 return -2;
1270 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1271 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
1272 ah->ah_gain.g_step_idx < go->go_steps_count-1;
1273 ah->ah_gain.g_step =
1274 &go->go_step[ah->ah_gain.g_step_idx])
1275 ah->ah_gain.g_target -= 2 *
1276 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
1277 ah->ah_gain.g_step->gos_gain);
1278
1279 ret = 2;
1280 goto done;
1281 }
1282
1283done:
1284 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1285 "ret %d, gain step %u, current gain %u, target gain %u\n",
1286 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
1287 ah->ah_gain.g_target);
1288
1289 return ret;
1290}
1291
1292/*
1293 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
1294 */
1295static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1296 struct ieee80211_channel *channel, unsigned int mode)
1297{
1298 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1299 u32 *rf;
1300 const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
1301 unsigned int i;
1302 int obdb = -1, bank = -1;
1303 u32 ee_mode;
1304
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1305 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1306
1307 rf = ah->ah_rf_banks;
1308
1309 /* Copy values to modify them */
1310 for (i = 0; i < rf_size; i++) {
1311 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1312 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1313 return -EINVAL;
1314 }
1315
1316 if (bank != rfregs_5111[i].rf_bank) {
1317 bank = rfregs_5111[i].rf_bank;
1318 ah->ah_offset[bank] = i;
1319 }
1320
1321 rf[i] = rfregs_5111[i].rf_value[mode];
1322 }
1323
1324 /* Modify bank 0 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1325 if (channel->hw_value & CHANNEL_2GHZ) {
1326 if (channel->hw_value & CHANNEL_CCK)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1327 ee_mode = AR5K_EEPROM_MODE_11B;
1328 else
1329 ee_mode = AR5K_EEPROM_MODE_11G;
1330 obdb = 0;
1331
1332 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1333 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
1334 return -EINVAL;
1335
1336 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1337 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
1338 return -EINVAL;
1339
1340 obdb = 1;
1341 /* Modify bank 6 */
1342 } else {
1343 /* For 11a, Turbo and XR */
1344 ee_mode = AR5K_EEPROM_MODE_11A;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1345 obdb = channel->center_freq >= 5725 ? 3 :
1346 (channel->center_freq >= 5500 ? 2 :
1347 (channel->center_freq >= 5260 ? 1 :
1348 (channel->center_freq > 4000 ? 0 : -1)));
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1349
1350 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1351 ee->ee_pwd_84, 1, 51, 3, true))
1352 return -EINVAL;
1353
1354 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1355 ee->ee_pwd_90, 1, 45, 3, true))
1356 return -EINVAL;
1357 }
1358
1359 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1360 !ee->ee_xpd[ee_mode], 1, 95, 0, true))
1361 return -EINVAL;
1362
1363 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1364 ee->ee_x_gain[ee_mode], 4, 96, 0, true))
1365 return -EINVAL;
1366
1367 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1368 ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
1369 return -EINVAL;
1370
1371 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1372 ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
1373 return -EINVAL;
1374
1375 /* Modify bank 7 */
1376 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1377 ee->ee_i_gain[ee_mode], 6, 29, 0, true))
1378 return -EINVAL;
1379
1380 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1381 ee->ee_xpd[ee_mode], 1, 4, 0, true))
1382 return -EINVAL;
1383
1384 /* Write RF values */
1385 for (i = 0; i < rf_size; i++) {
1386 AR5K_REG_WAIT(i);
1387 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
1388 }
1389
1390 return 0;
1391}
1392
1393/*
1394 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
1395 */
1396static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1397 struct ieee80211_channel *channel, unsigned int mode)
1398{
1399 const struct ath5k_ini_rf *rf_ini;
1400 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1401 u32 *rf;
1402 unsigned int rf_size, i;
1403 int obdb = -1, bank = -1;
1404 u32 ee_mode;
1405
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1406 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1407
1408 rf = ah->ah_rf_banks;
1409
1410 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1411 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1412 rf_ini = rfregs_2112a;
1413 rf_size = ARRAY_SIZE(rfregs_5112a);
1414 if (mode < 2) {
John Daiker0bbac082008-10-17 12:16:00 -0700[diff] [blame]1415 ATH5K_ERR(ah->ah_sc, "invalid channel mode: %i\n",
1416 mode);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1417 return -EINVAL;
1418 }
1419 mode = mode - 2; /*no a/turboa modes for 2112*/
1420 } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1421 rf_ini = rfregs_5112a;
1422 rf_size = ARRAY_SIZE(rfregs_5112a);
1423 } else {
1424 rf_ini = rfregs_5112;
1425 rf_size = ARRAY_SIZE(rfregs_5112);
1426 }
1427
1428 /* Copy values to modify them */
1429 for (i = 0; i < rf_size; i++) {
1430 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1431 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1432 return -EINVAL;
1433 }
1434
1435 if (bank != rf_ini[i].rf_bank) {
1436 bank = rf_ini[i].rf_bank;
1437 ah->ah_offset[bank] = i;
1438 }
1439
1440 rf[i] = rf_ini[i].rf_value[mode];
1441 }
1442
1443 /* Modify bank 6 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1444 if (channel->hw_value & CHANNEL_2GHZ) {
1445 if (channel->hw_value & CHANNEL_OFDM)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1446 ee_mode = AR5K_EEPROM_MODE_11G;
1447 else
1448 ee_mode = AR5K_EEPROM_MODE_11B;
1449 obdb = 0;
1450
1451 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1452 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
1453 return -EINVAL;
1454
1455 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1456 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
1457 return -EINVAL;
1458 } else {
1459 /* For 11a, Turbo and XR */
1460 ee_mode = AR5K_EEPROM_MODE_11A;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1461 obdb = channel->center_freq >= 5725 ? 3 :
1462 (channel->center_freq >= 5500 ? 2 :
1463 (channel->center_freq >= 5260 ? 1 :
1464 (channel->center_freq > 4000 ? 0 : -1)));
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1465
Luis R. Rodrigueze71c9fa2008-02-03 21:53:51 -0500[diff] [blame]1466 if (obdb == -1)
1467 return -EINVAL;
1468
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1469 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1470 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
1471 return -EINVAL;
1472
1473 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1474 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
1475 return -EINVAL;
1476 }
1477
1478 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1479 ee->ee_x_gain[ee_mode], 2, 270, 0, true);
1480 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1481 ee->ee_x_gain[ee_mode], 2, 257, 0, true);
1482
1483 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1484 ee->ee_xpd[ee_mode], 1, 302, 0, true))
1485 return -EINVAL;
1486
1487 /* Modify bank 7 */
1488 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1489 ee->ee_i_gain[ee_mode], 6, 14, 0, true))
1490 return -EINVAL;
1491
1492 /* Write RF values */
1493 for (i = 0; i < rf_size; i++)
1494 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1495
1496 return 0;
1497}
1498
1499/*
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1500 * Initialize RF5413/5414 and future chips
1501 * (until we come up with a better solution)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1502 */
1503static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1504 struct ieee80211_channel *channel, unsigned int mode)
1505{
1506 const struct ath5k_ini_rf *rf_ini;
1507 u32 *rf;
1508 unsigned int rf_size, i;
1509 int bank = -1;
1510
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1511 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1512
1513 rf = ah->ah_rf_banks;
1514
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1515 switch (ah->ah_radio) {
1516 case AR5K_RF5413:
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1517 rf_ini = rfregs_5413;
1518 rf_size = ARRAY_SIZE(rfregs_5413);
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1519 break;
1520 case AR5K_RF2413:
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1521 rf_ini = rfregs_2413;
1522 rf_size = ARRAY_SIZE(rfregs_2413);
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1523
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1524 if (mode < 2) {
1525 ATH5K_ERR(ah->ah_sc,
1526 "invalid channel mode: %i\n", mode);
1527 return -EINVAL;
1528 }
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1529
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1530 mode = mode - 2;
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1531 break;
1532 case AR5K_RF2425:
1533 rf_ini = rfregs_2425;
1534 rf_size = ARRAY_SIZE(rfregs_2425);
1535
1536 if (mode < 2) {
1537 ATH5K_ERR(ah->ah_sc,
1538 "invalid channel mode: %i\n", mode);
1539 return -EINVAL;
1540 }
1541
1542 /* Map b to g */
1543 if (mode == 2)
1544 mode = 0;
1545 else
1546 mode = mode - 3;
1547
1548 break;
1549 default:
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1550 return -EINVAL;
1551 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1552
1553 /* Copy values to modify them */
1554 for (i = 0; i < rf_size; i++) {
1555 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1556 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1557 return -EINVAL;
1558 }
1559
1560 if (bank != rf_ini[i].rf_bank) {
1561 bank = rf_ini[i].rf_bank;
1562 ah->ah_offset[bank] = i;
1563 }
1564
1565 rf[i] = rf_ini[i].rf_value[mode];
1566 }
1567
1568 /*
1569 * After compairing dumps from different cards
1570 * we get the same RF_BUFFER settings (diff returns
1571 * 0 lines). It seems that RF_BUFFER settings are static
1572 * and are written unmodified (no EEPROM stuff
1573 * is used because calibration data would be
1574 * different between different cards and would result
1575 * different RF_BUFFER settings)
1576 */
1577
1578 /* Write RF values */
1579 for (i = 0; i < rf_size; i++)
1580 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1581
1582 return 0;
1583}
1584
1585/*
1586 * Initialize RF
1587 */
1588int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1589 unsigned int mode)
1590{
1591 int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
1592 int ret;
1593
1594 switch (ah->ah_radio) {
1595 case AR5K_RF5111:
1596 ah->ah_rf_banks_size = sizeof(rfregs_5111);
1597 func = ath5k_hw_rf5111_rfregs;
1598 break;
1599 case AR5K_RF5112:
1600 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1601 ah->ah_rf_banks_size = sizeof(rfregs_5112a);
1602 else
1603 ah->ah_rf_banks_size = sizeof(rfregs_5112);
1604 func = ath5k_hw_rf5112_rfregs;
1605 break;
1606 case AR5K_RF5413:
1607 ah->ah_rf_banks_size = sizeof(rfregs_5413);
1608 func = ath5k_hw_rf5413_rfregs;
1609 break;
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1610 case AR5K_RF2413:
1611 ah->ah_rf_banks_size = sizeof(rfregs_2413);
1612 func = ath5k_hw_rf5413_rfregs;
1613 break;
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1614 case AR5K_RF2425:
1615 ah->ah_rf_banks_size = sizeof(rfregs_2425);
1616 func = ath5k_hw_rf5413_rfregs;
1617 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1618 default:
1619 return -EINVAL;
1620 }
1621
1622 if (ah->ah_rf_banks == NULL) {
1623 /* XXX do extra checks? */
1624 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
1625 if (ah->ah_rf_banks == NULL) {
1626 ATH5K_ERR(ah->ah_sc, "out of memory\n");
1627 return -ENOMEM;
1628 }
1629 }
1630
1631 ret = func(ah, channel, mode);
1632 if (!ret)
1633 ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
1634
1635 return ret;
1636}
1637
1638int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1639{
1640 const struct ath5k_ini_rfgain *ath5k_rfg;
1641 unsigned int i, size;
1642
1643 switch (ah->ah_radio) {
1644 case AR5K_RF5111:
1645 ath5k_rfg = rfgain_5111;
1646 size = ARRAY_SIZE(rfgain_5111);
1647 break;
1648 case AR5K_RF5112:
1649 ath5k_rfg = rfgain_5112;
1650 size = ARRAY_SIZE(rfgain_5112);
1651 break;
1652 case AR5K_RF5413:
1653 ath5k_rfg = rfgain_5413;
1654 size = ARRAY_SIZE(rfgain_5413);
1655 break;
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1656 case AR5K_RF2413:
1657 ath5k_rfg = rfgain_2413;
1658 size = ARRAY_SIZE(rfgain_2413);
1659 freq = 0; /* only 2Ghz */
1660 break;
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1661 case AR5K_RF2425:
Nick Kossifidis27bcdee2008-07-20 06:42:47 +0300[diff] [blame]1662 ath5k_rfg = rfgain_2425;
1663 size = ARRAY_SIZE(rfgain_2425);
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]1664 freq = 0; /* only 2Ghz */
1665 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1666 default:
1667 return -EINVAL;
1668 }
1669
1670 switch (freq) {
1671 case AR5K_INI_RFGAIN_2GHZ:
1672 case AR5K_INI_RFGAIN_5GHZ:
1673 break;
1674 default:
1675 return -EINVAL;
1676 }
1677
1678 for (i = 0; i < size; i++) {
1679 AR5K_REG_WAIT(i);
1680 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
1681 (u32)ath5k_rfg[i].rfg_register);
1682 }
1683
1684 return 0;
1685}
1686
1687enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
1688{
1689 u32 data, type;
1690
1691 ATH5K_TRACE(ah->ah_sc);
1692
1693 if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
1694 ah->ah_version <= AR5K_AR5211)
1695 return AR5K_RFGAIN_INACTIVE;
1696
1697 if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
1698 goto done;
1699
1700 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1701
1702 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
1703 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
1704 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
1705
1706 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
1707 ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
1708
1709 if (ah->ah_radio >= AR5K_RF5112) {
1710 ath5k_hw_rfregs_gainf_corr(ah);
1711 ah->ah_gain.g_current =
John Daiker0bbac082008-10-17 12:16:00 -0700[diff] [blame]1712 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1713 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
1714 0;
1715 }
1716
1717 if (ath5k_hw_rfregs_gain_readback(ah) &&
1718 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
1719 ath5k_hw_rfregs_gain_adjust(ah))
1720 ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
1721 }
1722
1723done:
1724 return ah->ah_rf_gain;
1725}
1726
1727int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
1728{
1729 /* Initialize the gain optimization values */
1730 switch (ah->ah_radio) {
1731 case AR5K_RF5111:
1732 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
1733 ah->ah_gain.g_step =
1734 &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
1735 ah->ah_gain.g_low = 20;
1736 ah->ah_gain.g_high = 35;
1737 ah->ah_gain.g_active = 1;
1738 break;
1739 case AR5K_RF5112:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1740 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
1741 ah->ah_gain.g_step =
1742 &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
1743 ah->ah_gain.g_low = 20;
1744 ah->ah_gain.g_high = 85;
1745 ah->ah_gain.g_active = 1;
1746 break;
1747 default:
1748 return -EINVAL;
1749 }
1750
1751 return 0;
1752}
1753
1754/**************************\
1755 PHY/RF channel functions
1756\**************************/
1757
1758/*
1759 * Check if a channel is supported
1760 */
1761bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
1762{
1763 /* Check if the channel is in our supported range */
1764 if (flags & CHANNEL_2GHZ) {
1765 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
1766 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
1767 return true;
1768 } else if (flags & CHANNEL_5GHZ)
1769 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
1770 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
1771 return true;
1772
1773 return false;
1774}
1775
1776/*
1777 * Convertion needed for RF5110
1778 */
1779static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1780{
1781 u32 athchan;
1782
1783 /*
1784 * Convert IEEE channel/MHz to an internal channel value used
1785 * by the AR5210 chipset. This has not been verified with
1786 * newer chipsets like the AR5212A who have a completely
1787 * different RF/PHY part.
1788 */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1789 athchan = (ath5k_hw_bitswap(
1790 (ieee80211_frequency_to_channel(
1791 channel->center_freq) - 24) / 2, 5)
1792 << 1) | (1 << 6) | 0x1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1793 return athchan;
1794}
1795
1796/*
1797 * Set channel on RF5110
1798 */
1799static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1800 struct ieee80211_channel *channel)
1801{
1802 u32 data;
1803
1804 /*
1805 * Set the channel and wait
1806 */
1807 data = ath5k_hw_rf5110_chan2athchan(channel);
1808 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1809 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1810 mdelay(1);
1811
1812 return 0;
1813}
1814
1815/*
1816 * Convertion needed for 5111
1817 */
1818static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1819 struct ath5k_athchan_2ghz *athchan)
1820{
1821 int channel;
1822
1823 /* Cast this value to catch negative channel numbers (>= -19) */
1824 channel = (int)ieee;
1825
1826 /*
1827 * Map 2GHz IEEE channel to 5GHz Atheros channel
1828 */
1829 if (channel <= 13) {
1830 athchan->a2_athchan = 115 + channel;
1831 athchan->a2_flags = 0x46;
1832 } else if (channel == 14) {
1833 athchan->a2_athchan = 124;
1834 athchan->a2_flags = 0x44;
1835 } else if (channel >= 15 && channel <= 26) {
1836 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1837 athchan->a2_flags = 0x46;
1838 } else
1839 return -EINVAL;
1840
1841 return 0;
1842}
1843
1844/*
1845 * Set channel on 5111
1846 */
1847static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1848 struct ieee80211_channel *channel)
1849{
1850 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1851 unsigned int ath5k_channel =
1852 ieee80211_frequency_to_channel(channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1853 u32 data0, data1, clock;
1854 int ret;
1855
1856 /*
1857 * Set the channel on the RF5111 radio
1858 */
1859 data0 = data1 = 0;
1860
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1861 if (channel->hw_value & CHANNEL_2GHZ) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1862 /* Map 2GHz channel to 5GHz Atheros channel ID */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1863 ret = ath5k_hw_rf5111_chan2athchan(
1864 ieee80211_frequency_to_channel(channel->center_freq),
1865 &ath5k_channel_2ghz);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1866 if (ret)
1867 return ret;
1868
1869 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1870 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1871 << 5) | (1 << 4);
1872 }
1873
1874 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1875 clock = 1;
1876 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1877 (clock << 1) | (1 << 10) | 1;
1878 } else {
1879 clock = 0;
1880 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1881 << 2) | (clock << 1) | (1 << 10) | 1;
1882 }
1883
1884 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1885 AR5K_RF_BUFFER);
1886 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1887 AR5K_RF_BUFFER_CONTROL_3);
1888
1889 return 0;
1890}
1891
1892/*
1893 * Set channel on 5112 and newer
1894 */
1895static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1896 struct ieee80211_channel *channel)
1897{
1898 u32 data, data0, data1, data2;
1899 u16 c;
1900
1901 data = data0 = data1 = data2 = 0;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1902 c = channel->center_freq;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1903
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1904 if (c < 4800) {
1905 if (!((c - 2224) % 5)) {
1906 data0 = ((2 * (c - 704)) - 3040) / 10;
1907 data1 = 1;
1908 } else if (!((c - 2192) % 5)) {
1909 data0 = ((2 * (c - 672)) - 3040) / 10;
1910 data1 = 0;
1911 } else
1912 return -EINVAL;
1913
1914 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
Nick Kossifidiscc6323c2008-07-20 06:44:43 +0300[diff] [blame]1915 } else if ((c - (c % 5)) != 2 || c > 5435) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1916 if (!(c % 20) && c >= 5120) {
1917 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1918 data2 = ath5k_hw_bitswap(3, 2);
1919 } else if (!(c % 10)) {
1920 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1921 data2 = ath5k_hw_bitswap(2, 2);
1922 } else if (!(c % 5)) {
1923 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1924 data2 = ath5k_hw_bitswap(1, 2);
1925 } else
1926 return -EINVAL;
Nick Kossifidiscc6323c2008-07-20 06:44:43 +0300[diff] [blame]1927 } else {
1928 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1929 data2 = ath5k_hw_bitswap(0, 2);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1930 }
1931
1932 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1933
1934 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1935 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1936
1937 return 0;
1938}
1939
1940/*
Nick Kossifidiscc6323c2008-07-20 06:44:43 +0300[diff] [blame]1941 * Set the channel on the RF2425
1942 */
1943static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1944 struct ieee80211_channel *channel)
1945{
1946 u32 data, data0, data2;
1947 u16 c;
1948
1949 data = data0 = data2 = 0;
1950 c = channel->center_freq;
1951
1952 if (c < 4800) {
1953 data0 = ath5k_hw_bitswap((c - 2272), 8);
1954 data2 = 0;
1955 /* ? 5GHz ? */
1956 } else if ((c - (c % 5)) != 2 || c > 5435) {
1957 if (!(c % 20) && c < 5120)
1958 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1959 else if (!(c % 10))
1960 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1961 else if (!(c % 5))
1962 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1963 else
1964 return -EINVAL;
1965 data2 = ath5k_hw_bitswap(1, 2);
1966 } else {
1967 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1968 data2 = ath5k_hw_bitswap(0, 2);
1969 }
1970
1971 data = (data0 << 4) | data2 << 2 | 0x1001;
1972
1973 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1974 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1975
1976 return 0;
1977}
1978
1979/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1980 * Set a channel on the radio chip
1981 */
1982int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1983{
1984 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1985 /*
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1986 * Check bounds supported by the PHY (we don't care about regultory
1987 * restrictions at this point). Note: hw_value already has the band
1988 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1989 * of the band by that */
1990 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1991 ATH5K_ERR(ah->ah_sc,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1992 "channel frequency (%u MHz) out of supported "
1993 "band range\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1994 channel->center_freq);
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1995 return -EINVAL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1996 }
1997
1998 /*
1999 * Set the channel and wait
2000 */
2001 switch (ah->ah_radio) {
2002 case AR5K_RF5110:
2003 ret = ath5k_hw_rf5110_channel(ah, channel);
2004 break;
2005 case AR5K_RF5111:
2006 ret = ath5k_hw_rf5111_channel(ah, channel);
2007 break;
Nick Kossifidiscc6323c2008-07-20 06:44:43 +0300[diff] [blame]2008 case AR5K_RF2425:
2009 ret = ath5k_hw_rf2425_channel(ah, channel);
2010 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2011 default:
2012 ret = ath5k_hw_rf5112_channel(ah, channel);
2013 break;
2014 }
2015
2016 if (ret)
2017 return ret;
2018
Nick Kossifidiscc6323c2008-07-20 06:44:43 +0300[diff] [blame]2019 /* Set JAPAN setting for channel 14 */
2020 if (channel->center_freq == 2484) {
2021 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
2022 AR5K_PHY_CCKTXCTL_JAPAN);
2023 } else {
2024 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
2025 AR5K_PHY_CCKTXCTL_WORLD);
2026 }
2027
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]2028 ah->ah_current_channel.center_freq = channel->center_freq;
2029 ah->ah_current_channel.hw_value = channel->hw_value;
2030 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2031
2032 return 0;
2033}
2034
2035/*****************\
2036 PHY calibration
2037\*****************/
2038
2039/**
2040 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
2041 *
2042 * @ah: struct ath5k_hw pointer we are operating on
2043 * @freq: the channel frequency, just used for error logging
2044 *
2045 * This function performs a noise floor calibration of the PHY and waits for
2046 * it to complete. Then the noise floor value is compared to some maximum
2047 * noise floor we consider valid.
2048 *
2049 * Note that this is different from what the madwifi HAL does: it reads the
2050 * noise floor and afterwards initiates the calibration. Since the noise floor
2051 * calibration can take some time to finish, depending on the current channel
2052 * use, that avoids the occasional timeout warnings we are seeing now.
2053 *
2054 * See the following link for an Atheros patent on noise floor calibration:
2055 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
2056 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
2057 *
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2058 * XXX: Since during noise floor calibration antennas are detached according to
2059 * the patent, we should stop tx queues here.
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2060 */
2061int
2062ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
2063{
2064 int ret;
2065 unsigned int i;
2066 s32 noise_floor;
2067
2068 /*
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2069 * Enable noise floor calibration
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2070 */
2071 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
2072 AR5K_PHY_AGCCTL_NF);
2073
2074 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2075 AR5K_PHY_AGCCTL_NF, 0, false);
2076 if (ret) {
2077 ATH5K_ERR(ah->ah_sc,
2078 "noise floor calibration timeout (%uMHz)\n", freq);
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2079 return -EAGAIN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2080 }
2081
2082 /* Wait until the noise floor is calibrated and read the value */
2083 for (i = 20; i > 0; i--) {
2084 mdelay(1);
2085 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
2086 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
2087 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
2088 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
2089
2090 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
2091 break;
2092 }
2093 }
2094
2095 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
2096 "noise floor %d\n", noise_floor);
2097
2098 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
2099 ATH5K_ERR(ah->ah_sc,
2100 "noise floor calibration failed (%uMHz)\n", freq);
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2101 return -EAGAIN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2102 }
2103
2104 ah->ah_noise_floor = noise_floor;
2105
2106 return 0;
2107}
2108
2109/*
2110 * Perform a PHY calibration on RF5110
2111 * -Fix BPSK/QAM Constellation (I/Q correction)
2112 * -Calculate Noise Floor
2113 */
2114static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
2115 struct ieee80211_channel *channel)
2116{
2117 u32 phy_sig, phy_agc, phy_sat, beacon;
2118 int ret;
2119
2120 /*
2121 * Disable beacons and RX/TX queues, wait
2122 */
2123 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
2124 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2125 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
2126 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
2127
Nick Kossifidis84e463f2008-09-17 03:33:19 +0300[diff] [blame]2128 mdelay(2);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2129
2130 /*
2131 * Set the channel (with AGC turned off)
2132 */
2133 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2134 udelay(10);
2135 ret = ath5k_hw_channel(ah, channel);
2136
2137 /*
2138 * Activate PHY and wait
2139 */
2140 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
2141 mdelay(1);
2142
2143 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2144
2145 if (ret)
2146 return ret;
2147
2148 /*
2149 * Calibrate the radio chip
2150 */
2151
2152 /* Remember normal state */
2153 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
2154 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
2155 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
2156
2157 /* Update radio registers */
2158 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
2159 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
2160
2161 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
2162 AR5K_PHY_AGCCOARSE_LO)) |
2163 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
2164 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
2165
2166 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
2167 AR5K_PHY_ADCSAT_THR)) |
2168 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
2169 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
2170
2171 udelay(20);
2172
2173 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2174 udelay(10);
2175 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
2176 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2177
2178 mdelay(1);
2179
2180 /*
2181 * Enable calibration and wait until completion
2182 */
2183 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
2184
2185 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2186 AR5K_PHY_AGCCTL_CAL, 0, false);
2187
2188 /* Reset to normal state */
2189 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
2190 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
2191 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
2192
2193 if (ret) {
2194 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]2195 channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2196 return ret;
2197 }
2198
Felix Fietkau8b0162a2008-11-03 11:27:38 +0100[diff] [blame]2199 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2200
2201 /*
2202 * Re-enable RX/TX and beacons
2203 */
2204 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
2205 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2206 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
2207
2208 return 0;
2209}
2210
2211/*
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2212 * Perform a PHY calibration on RF5111/5112 and newer chips
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2213 */
2214static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
2215 struct ieee80211_channel *channel)
2216{
2217 u32 i_pwr, q_pwr;
2218 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2219 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2220 ATH5K_TRACE(ah->ah_sc);
2221
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame]2222 if (!ah->ah_calibration ||
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2223 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2224 goto done;
2225
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2226 /* Calibration has finished, get the results and re-run */
2227 for (i = 0; i <= 10; i++) {
2228 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
2229 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
2230 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
2231 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2232
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2233 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2234 q_coffd = q_pwr >> 7;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2235
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2236 /* No correction */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2237 if (i_coffd == 0 || q_coffd == 0)
2238 goto done;
2239
2240 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2241
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2242 /* Boundary check */
2243 if (i_coff > 31)
2244 i_coff = 31;
2245 if (i_coff < -32)
2246 i_coff = -32;
2247
2248 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
2249
2250 /* Boundary check */
2251 if (q_coff > 15)
2252 q_coff = 15;
2253 if (q_coff < -16)
2254 q_coff = -16;
2255
2256 /* Commit new I/Q value */
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2257 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
2258 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
2259
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2260 /* Re-enable calibration -if we don't we'll commit
2261 * the same values again and again */
2262 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
2263 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
2264 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
2265
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2266done:
Nick Kossifidisf860ee22008-07-20 06:47:12 +0300[diff] [blame]2267
2268 /* TODO: Separate noise floor calibration from I/Q calibration
2269 * since noise floor calibration interrupts rx path while I/Q
2270 * calibration doesn't. We don't need to run noise floor calibration
2271 * as often as I/Q calibration.*/
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]2272 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2273
2274 /* Request RF gain */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]2275 if (channel->hw_value & CHANNEL_5GHZ) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2276 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
2277 AR5K_PHY_PAPD_PROBE_TXPOWER) |
2278 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
2279 ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
2280 }
2281
2282 return 0;
2283}
2284
2285/*
2286 * Perform a PHY calibration
2287 */
2288int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
2289 struct ieee80211_channel *channel)
2290{
2291 int ret;
2292
2293 if (ah->ah_radio == AR5K_RF5110)
2294 ret = ath5k_hw_rf5110_calibrate(ah, channel);
2295 else
2296 ret = ath5k_hw_rf511x_calibrate(ah, channel);
2297
2298 return ret;
2299}
2300
2301int ath5k_hw_phy_disable(struct ath5k_hw *ah)
2302{
2303 ATH5K_TRACE(ah->ah_sc);
2304 /*Just a try M.F.*/
2305 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
2306
2307 return 0;
2308}
2309
2310/********************\
2311 Misc PHY functions
2312\********************/
2313
2314/*
2315 * Get the PHY Chip revision
2316 */
2317u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
2318{
2319 unsigned int i;
2320 u32 srev;
2321 u16 ret;
2322
2323 ATH5K_TRACE(ah->ah_sc);
2324
2325 /*
2326 * Set the radio chip access register
2327 */
2328 switch (chan) {
2329 case CHANNEL_2GHZ:
2330 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
2331 break;
2332 case CHANNEL_5GHZ:
2333 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2334 break;
2335 default:
2336 return 0;
2337 }
2338
2339 mdelay(2);
2340
2341 /* ...wait until PHY is ready and read the selected radio revision */
2342 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
2343
2344 for (i = 0; i < 8; i++)
2345 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
2346
2347 if (ah->ah_version == AR5K_AR5210) {
2348 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
2349 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
2350 } else {
2351 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
2352 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
2353 ((srev & 0x0f) << 4), 8);
2354 }
2355
2356 /* Reset to the 5GHz mode */
2357 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2358
2359 return ret;
2360}
2361
2362void /*TODO:Boundary check*/
2363ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
2364{
2365 ATH5K_TRACE(ah->ah_sc);
2366 /*Just a try M.F.*/
2367 if (ah->ah_version != AR5K_AR5210)
2368 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
2369}
2370
2371unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
2372{
2373 ATH5K_TRACE(ah->ah_sc);
2374 /*Just a try M.F.*/
2375 if (ah->ah_version != AR5K_AR5210)
2376 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
2377
2378 return false; /*XXX: What do we return for 5210 ?*/
2379}
2380
2381/*
2382 * TX power setup
2383 */
2384
2385/*
2386 * Initialize the tx power table (not fully implemented)
2387 */
2388static void ath5k_txpower_table(struct ath5k_hw *ah,
2389 struct ieee80211_channel *channel, s16 max_power)
2390{
2391 unsigned int i, min, max, n;
2392 u16 txpower, *rates;
2393
2394 rates = ah->ah_txpower.txp_rates;
2395
2396 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
2397 if (max_power > txpower)
2398 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
2399 AR5K_TUNE_MAX_TXPOWER : max_power;
2400
2401 for (i = 0; i < AR5K_MAX_RATES; i++)
2402 rates[i] = txpower;
2403
2404 /* XXX setup target powers by rate */
2405
2406 ah->ah_txpower.txp_min = rates[7];
2407 ah->ah_txpower.txp_max = rates[0];
2408 ah->ah_txpower.txp_ofdm = rates[0];
2409
2410 /* Calculate the power table */
2411 n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
2412 min = AR5K_EEPROM_PCDAC_START;
2413 max = AR5K_EEPROM_PCDAC_STOP;
2414 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
2415 ah->ah_txpower.txp_pcdac[i] =
2416#ifdef notyet
2417 min + ((i * (max - min)) / n);
2418#else
2419 min;
2420#endif
2421}
2422
2423/*
2424 * Set transmition power
2425 */
2426int /*O.K. - txpower_table is unimplemented so this doesn't work*/
2427ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2428 unsigned int txpower)
2429{
2430 bool tpc = ah->ah_txpower.txp_tpc;
2431 unsigned int i;
2432
2433 ATH5K_TRACE(ah->ah_sc);
2434 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2435 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2436 return -EINVAL;
2437 }
2438
Nick Kossifidis903b4742008-02-28 14:50:50 -0500[diff] [blame]2439 /*
2440 * RF2413 for some reason can't
2441 * transmit anything if we call
2442 * this funtion, so we skip it
2443 * until we fix txpower.
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]2444 *
2445 * XXX: Assume same for RF2425
2446 * to be safe.
Nick Kossifidis903b4742008-02-28 14:50:50 -0500[diff] [blame]2447 */
Nick Kossifidis136bfc72008-04-16 18:42:48 +0300[diff] [blame]2448 if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425))
Nick Kossifidis903b4742008-02-28 14:50:50 -0500[diff] [blame]2449 return 0;
2450
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2451 /* Reset TX power values */
2452 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2453 ah->ah_txpower.txp_tpc = tpc;
2454
2455 /* Initialize TX power table */
2456 ath5k_txpower_table(ah, channel, txpower);
2457
2458 /*
2459 * Write TX power values
2460 */
2461 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2462 ath5k_hw_reg_write(ah,
2463 ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
2464 (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff),
2465 AR5K_PHY_PCDAC_TXPOWER(i));
2466 }
2467
2468 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2469 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2470 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2471
2472 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2473 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2474 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2475
2476 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2477 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2478 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2479
2480 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2481 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2482 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2483
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame]2484 if (ah->ah_txpower.txp_tpc)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2485 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2486 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2487 else
2488 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2489 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2490
2491 return 0;
2492}
2493
2494int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
2495{
2496 /*Just a try M.F.*/
2497 struct ieee80211_channel *channel = &ah->ah_current_channel;
2498
2499 ATH5K_TRACE(ah->ah_sc);
2500 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
2501 "changing txpower to %d\n", power);
2502
2503 return ath5k_hw_txpower(ah, channel, power);
2504}
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300[diff] [blame]2505
2506#undef _ATH5K_PHY