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Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
10
Jon Hunter9c8eddd2016-06-07 16:12:34 +010011config ARM_GIC_PM
12 bool
13 depends on PM
14 select ARM_GIC
15 select PM_CLK
16
Linus Walleija27d21e2015-12-18 10:44:53 +010017config ARM_GIC_MAX_NR
18 int
19 default 2 if ARCH_REALVIEW
20 default 1
21
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000022config ARM_GIC_V2M
23 bool
Arnd Bergmann3ee80362016-06-15 15:47:33 -050024 depends on PCI
25 select ARM_GIC
26 select PCI_MSI
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000027
Rob Herring81243e42012-11-20 21:21:40 -060028config GIC_NON_BANKED
29 bool
30
Marc Zyngier021f6532014-06-30 16:01:31 +010031config ARM_GIC_V3
32 bool
33 select IRQ_DOMAIN
34 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000035 select IRQ_DOMAIN_HIERARCHY
Marc Zyngiere3825ba2016-04-11 09:57:54 +010036 select PARTITION_PERCPU
Marc Zyngier021f6532014-06-30 16:01:31 +010037
Marc Zyngier19812722014-11-24 14:35:19 +000038config ARM_GIC_V3_ITS
39 bool
Arnd Bergmann3ee80362016-06-15 15:47:33 -050040 depends on PCI
41 depends on PCI_MSI
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +020042 select ACPI_IORT if ACPI
Uwe Kleine-König292ec082013-06-26 09:18:48 +020043
Rob Herring44430ec2012-10-27 17:25:26 -050044config ARM_NVIC
45 bool
46 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020047 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050048 select GENERIC_IRQ_CHIP
49
50config ARM_VIC
51 bool
52 select IRQ_DOMAIN
53 select MULTI_IRQ_HANDLER
54
55config ARM_VIC_NR
56 int
57 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050058 default 2
59 depends on ARM_VIC
60 help
61 The maximum number of VICs available in the system, for
62 power management.
63
Thomas Petazzonifed6d332016-02-10 15:46:56 +010064config ARMADA_370_XP_IRQ
65 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010066 select GENERIC_IRQ_CHIP
Arnd Bergmann3ee80362016-06-15 15:47:33 -050067 select PCI_MSI if PCI
Thomas Petazzonifed6d332016-02-10 15:46:56 +010068
Antoine Tenarte6b78f22016-02-19 16:22:44 +010069config ALPINE_MSI
70 bool
Arnd Bergmann3ee80362016-06-15 15:47:33 -050071 depends on PCI
72 select PCI_MSI
Antoine Tenarte6b78f22016-02-19 16:22:44 +010073 select GENERIC_IRQ_CHIP
Antoine Tenarte6b78f22016-02-19 16:22:44 +010074
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020075config ATMEL_AIC_IRQ
76 bool
77 select GENERIC_IRQ_CHIP
78 select IRQ_DOMAIN
79 select MULTI_IRQ_HANDLER
80 select SPARSE_IRQ
81
82config ATMEL_AIC5_IRQ
83 bool
84 select GENERIC_IRQ_CHIP
85 select IRQ_DOMAIN
86 select MULTI_IRQ_HANDLER
87 select SPARSE_IRQ
88
Ralf Baechle0509cfd2015-07-08 14:46:08 +020089config I8259
90 bool
91 select IRQ_DOMAIN
92
Simon Arlottc7c42ec2015-11-22 14:30:14 +000093config BCM6345_L1_IRQ
94 bool
95 select GENERIC_IRQ_CHIP
96 select IRQ_DOMAIN
97
Kevin Cernekee5f7f0312014-12-25 09:49:06 -080098config BCM7038_L1_IRQ
99 bool
100 select GENERIC_IRQ_CHIP
101 select IRQ_DOMAIN
102
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800103config BCM7120_L2_IRQ
104 bool
105 select GENERIC_IRQ_CHIP
106 select IRQ_DOMAIN
107
Florian Fainelli7f646e92014-05-23 17:40:53 -0700108config BRCMSTB_L2_IRQ
109 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700110 select GENERIC_IRQ_CHIP
111 select IRQ_DOMAIN
112
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200113config DW_APB_ICTL
114 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800115 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200116 select IRQ_DOMAIN
117
MaJun9a7c4ab2016-03-23 17:06:33 +0800118config HISILICON_IRQ_MBIGEN
119 bool
120 select ARM_GIC_V3
121 select ARM_GIC_V3_ITS
MaJun9a7c4ab2016-03-23 17:06:33 +0800122
James Hoganb6ef9162013-04-22 15:43:50 +0100123config IMGPDC_IRQ
124 bool
125 select GENERIC_IRQ_CHIP
126 select IRQ_DOMAIN
127
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200128config IRQ_MIPS_CPU
129 bool
130 select GENERIC_IRQ_CHIP
131 select IRQ_DOMAIN
132
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400133config CLPS711X_IRQCHIP
134 bool
135 depends on ARCH_CLPS711X
136 select IRQ_DOMAIN
137 select MULTI_IRQ_HANDLER
138 select SPARSE_IRQ
139 default y
140
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300141config OR1K_PIC
142 bool
143 select IRQ_DOMAIN
144
Felipe Balbi85980662014-09-15 16:15:02 -0500145config OMAP_IRQCHIP
146 bool
147 select GENERIC_IRQ_CHIP
148 select IRQ_DOMAIN
149
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200150config ORION_IRQCHIP
151 bool
152 select IRQ_DOMAIN
153 select MULTI_IRQ_HANDLER
154
Cristian Birsanaaa86662016-01-13 18:15:35 -0700155config PIC32_EVIC
156 bool
157 select GENERIC_IRQ_CHIP
158 select IRQ_DOMAIN
159
Rich Felker981b58f2016-08-04 04:30:37 +0000160config JCORE_AIC
Rich Felker3602ffd2016-10-19 17:53:52 +0000161 bool "J-Core integrated AIC" if COMPILE_TEST
162 depends on OF
Rich Felker981b58f2016-08-04 04:30:37 +0000163 select IRQ_DOMAIN
164 help
165 Support for the J-Core integrated AIC.
166
Magnus Damm44358042013-02-18 23:28:34 +0900167config RENESAS_INTC_IRQPIN
168 bool
169 select IRQ_DOMAIN
170
Magnus Dammfbc83b72013-02-27 17:15:01 +0900171config RENESAS_IRQC
172 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900173 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900174 select IRQ_DOMAIN
175
Lee Jones07088482015-02-18 15:13:58 +0000176config ST_IRQCHIP
177 bool
178 select REGMAP
179 select MFD_SYSCON
180 help
181 Enables SysCfg Controlled IRQs on STi based platforms.
182
Mans Rullgard4bba6682016-01-20 18:07:17 +0000183config TANGO_IRQ
184 bool
185 select IRQ_DOMAIN
186 select GENERIC_IRQ_CHIP
187
Christian Ruppertb06eb012013-06-25 18:29:57 +0200188config TB10X_IRQC
189 bool
190 select IRQ_DOMAIN
191 select GENERIC_IRQ_CHIP
192
Damien Riegeld01f8632015-12-21 15:11:23 -0500193config TS4800_IRQ
194 tristate "TS-4800 IRQ controller"
195 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100196 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100197 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500198 help
199 Support for the TS-4800 FPGA IRQ controller
200
Linus Walleij2389d502012-10-31 22:04:31 +0100201config VERSATILE_FPGA_IRQ
202 bool
203 select IRQ_DOMAIN
204
205config VERSATILE_FPGA_IRQ_NR
206 int
207 default 4
208 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400209
210config XTENSA_MX
211 bool
212 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530213
214config IRQ_CROSSBAR
215 bool
216 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900217 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530218 The primary irqchip invokes the crossbar's callback which inturn allocates
219 a free irq and configures the IP. Thus the peripheral interrupts are
220 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300221
222config KEYSTONE_IRQ
223 tristate "Keystone 2 IRQ controller IP"
224 depends on ARCH_KEYSTONE
225 help
226 Support for Texas Instruments Keystone 2 IRQ controller IP which
227 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700228
229config MIPS_GIC
230 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000231 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000232 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700233 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900234
Paul Burton44e08e72015-05-24 16:11:31 +0100235config INGENIC_IRQ
236 bool
237 depends on MACH_INGENIC
238 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700239
Yoshinori Sato8a764482015-05-10 02:30:47 +0900240config RENESAS_H8300H_INTC
241 bool
242 select IRQ_DOMAIN
243
244config RENESAS_H8S_INTC
245 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700246 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500247
248config IMX_GPCV2
249 bool
250 select IRQ_DOMAIN
251 help
252 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200253
254config IRQ_MXS
255 def_bool y if MACH_ASM9260 || ARCH_MXS
256 select IRQ_DOMAIN
257 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100258
259config MVEBU_ODMI
260 bool
Arnd Bergmann889163d2017-03-14 13:54:12 +0100261 select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100262
Thomas Petazzonia1098932016-08-05 16:55:19 +0200263config MVEBU_PIC
264 bool
265
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800266config LS_SCFG_MSI
267 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
268 depends on PCI && PCI_MSI
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800269
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100270config PARTITION_PERCPU
271 bool
Linus Torvalds0efacbb2016-05-19 09:46:18 -0700272
Noam Camus44df427c2015-10-29 00:26:22 +0200273config EZNPS_GIC
274 bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmannffd565e2016-05-12 23:03:35 +0200275 depends on ARC || (COMPILE_TEST && !64BIT)
Noam Camus44df427c2015-10-29 00:26:22 +0200276 select IRQ_DOMAIN
277 help
278 Support the EZchip NPS400 global interrupt controller
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200279
280config STM32_EXTI
281 bool
282 select IRQ_DOMAIN