Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 1 | /*************************************************************************************** |
| 2 | // |
| 3 | // Copyright (c) Beceem Communications Inc. |
| 4 | // |
| 5 | // Module Name: |
| 6 | // NVM.h |
| 7 | // |
| 8 | // Abstract: |
| 9 | // This file has the prototypes,preprocessors and definitions various NVM libraries. |
| 10 | // |
| 11 | // |
| 12 | // Revision History: |
| 13 | // Who When What |
| 14 | // -------- -------- ---------------------------------------------- |
| 15 | // Name Date Created/reviewed/modified |
| 16 | // |
| 17 | // Notes: |
| 18 | // |
| 19 | ****************************************************************************************/ |
| 20 | |
| 21 | |
| 22 | #ifndef _NVM_H_ |
| 23 | #define _NVM_H_ |
| 24 | |
| 25 | typedef struct _FLASH_SECTOR_INFO |
| 26 | { |
| 27 | UINT uiSectorSig; |
| 28 | UINT uiSectorSize; |
| 29 | |
| 30 | }FLASH_SECTOR_INFO,*PFLASH_SECTOR_INFO; |
| 31 | |
| 32 | typedef struct _FLASH_CS_INFO |
| 33 | { |
| 34 | B_UINT32 MagicNumber; |
| 35 | // let the magic number be 0xBECE-F1A5 - F1A5 for "flas-h" |
| 36 | |
| 37 | B_UINT32 FlashLayoutVersion ; |
| 38 | |
| 39 | // ISO Image/Format/BuildTool versioning |
| 40 | B_UINT32 ISOImageVersion; |
| 41 | |
| 42 | // SCSI/Flash BootLoader versioning |
| 43 | B_UINT32 SCSIFirmwareVersion; |
| 44 | |
| 45 | |
| 46 | B_UINT32 OffsetFromZeroForPart1ISOImage; |
| 47 | // typically 0 |
| 48 | |
| 49 | B_UINT32 OffsetFromZeroForScsiFirmware; |
| 50 | //typically at 12MB |
| 51 | |
| 52 | B_UINT32 SizeOfScsiFirmware ; |
| 53 | //size of the firmware - depends on binary size |
| 54 | |
| 55 | B_UINT32 OffsetFromZeroForPart2ISOImage; |
| 56 | // typically at first Word Aligned offset 12MB + sizeOfScsiFirmware. |
| 57 | |
| 58 | B_UINT32 OffsetFromZeroForCalibrationStart; |
| 59 | // typically at 15MB |
| 60 | |
| 61 | B_UINT32 OffsetFromZeroForCalibrationEnd; |
| 62 | |
| 63 | // VSA0 offsets |
| 64 | B_UINT32 OffsetFromZeroForVSAStart; |
| 65 | B_UINT32 OffsetFromZeroForVSAEnd; |
| 66 | |
| 67 | // Control Section offsets |
| 68 | B_UINT32 OffsetFromZeroForControlSectionStart; |
| 69 | B_UINT32 OffsetFromZeroForControlSectionData; |
| 70 | |
| 71 | // NO Data Activity timeout to switch from MSC to NW Mode |
| 72 | B_UINT32 CDLessInactivityTimeout; |
| 73 | |
| 74 | // New ISO Image Signature |
| 75 | B_UINT32 NewImageSignature; |
| 76 | |
| 77 | // Signature to validate the sector size. |
| 78 | B_UINT32 FlashSectorSizeSig; |
| 79 | |
| 80 | // Sector Size |
| 81 | B_UINT32 FlashSectorSize; |
| 82 | |
| 83 | // Write Size Support |
| 84 | B_UINT32 FlashWriteSupportSize; |
| 85 | |
| 86 | // Total Flash Size |
| 87 | B_UINT32 TotalFlashSize; |
| 88 | |
| 89 | // Flash Base Address for offset specified |
| 90 | B_UINT32 FlashBaseAddr; |
| 91 | |
| 92 | // Flash Part Max Size |
| 93 | B_UINT32 FlashPartMaxSize; |
| 94 | |
| 95 | // Is CDLess or Flash Bootloader |
| 96 | B_UINT32 IsCDLessDeviceBootSig; |
| 97 | |
| 98 | // MSC Timeout after reset to switch from MSC to NW Mode |
| 99 | B_UINT32 MassStorageTimeout; |
| 100 | |
| 101 | |
| 102 | }FLASH_CS_INFO,*PFLASH_CS_INFO; |
| 103 | |
| 104 | #define FLASH2X_TOTAL_SIZE (64*1024*1024) |
| 105 | #define DEFAULT_SECTOR_SIZE (64*1024) |
| 106 | |
| 107 | typedef struct _FLASH_2X_CS_INFO |
| 108 | { |
| 109 | |
| 110 | // magic number as 0xBECE-F1A5 - F1A5 for "flas-h" |
| 111 | B_UINT32 MagicNumber; |
| 112 | |
| 113 | B_UINT32 FlashLayoutVersion ; |
| 114 | |
| 115 | // ISO Image/Format/BuildTool versioning |
| 116 | B_UINT32 ISOImageVersion; |
| 117 | |
| 118 | // SCSI/Flash BootLoader versioning |
| 119 | B_UINT32 SCSIFirmwareVersion; |
| 120 | |
| 121 | // ISO Image1 Part1/SCSI Firmware/Flash Bootloader Start offset, size |
| 122 | B_UINT32 OffsetFromZeroForPart1ISOImage; |
| 123 | B_UINT32 OffsetFromZeroForScsiFirmware; |
| 124 | B_UINT32 SizeOfScsiFirmware ; |
| 125 | |
| 126 | // ISO Image1 Part2 start offset |
| 127 | B_UINT32 OffsetFromZeroForPart2ISOImage; |
| 128 | |
| 129 | |
| 130 | // DSD0 offset |
| 131 | B_UINT32 OffsetFromZeroForDSDStart; |
| 132 | B_UINT32 OffsetFromZeroForDSDEnd; |
| 133 | |
| 134 | // VSA0 offset |
| 135 | B_UINT32 OffsetFromZeroForVSAStart; |
| 136 | B_UINT32 OffsetFromZeroForVSAEnd; |
| 137 | |
| 138 | // Control Section offset |
| 139 | B_UINT32 OffsetFromZeroForControlSectionStart; |
| 140 | B_UINT32 OffsetFromZeroForControlSectionData; |
| 141 | |
| 142 | // NO Data Activity timeout to switch from MSC to NW Mode |
| 143 | B_UINT32 CDLessInactivityTimeout; |
| 144 | |
| 145 | // New ISO Image Signature |
| 146 | B_UINT32 NewImageSignature; |
| 147 | |
| 148 | B_UINT32 FlashSectorSizeSig; // Sector Size Signature |
| 149 | B_UINT32 FlashSectorSize; // Sector Size |
| 150 | B_UINT32 FlashWriteSupportSize; // Write Size Support |
| 151 | |
| 152 | B_UINT32 TotalFlashSize; // Total Flash Size |
| 153 | |
| 154 | // Flash Base Address for offset specified |
| 155 | B_UINT32 FlashBaseAddr; |
| 156 | B_UINT32 FlashPartMaxSize; // Flash Part Max Size |
| 157 | |
| 158 | // Is CDLess or Flash Bootloader |
| 159 | B_UINT32 IsCDLessDeviceBootSig; |
| 160 | |
| 161 | // MSC Timeout after reset to switch from MSC to NW Mode |
| 162 | B_UINT32 MassStorageTimeout; |
| 163 | |
| 164 | /* Flash Map 2.0 Field */ |
| 165 | B_UINT32 OffsetISOImage1Part1Start; // ISO Image1 Part1 offset |
| 166 | B_UINT32 OffsetISOImage1Part1End; |
| 167 | B_UINT32 OffsetISOImage1Part2Start; // ISO Image1 Part2 offset |
| 168 | B_UINT32 OffsetISOImage1Part2End; |
| 169 | B_UINT32 OffsetISOImage1Part3Start; // ISO Image1 Part3 offset |
| 170 | B_UINT32 OffsetISOImage1Part3End; |
| 171 | |
| 172 | B_UINT32 OffsetISOImage2Part1Start; // ISO Image2 Part1 offset |
| 173 | B_UINT32 OffsetISOImage2Part1End; |
| 174 | B_UINT32 OffsetISOImage2Part2Start; // ISO Image2 Part2 offset |
| 175 | B_UINT32 OffsetISOImage2Part2End; |
| 176 | B_UINT32 OffsetISOImage2Part3Start; // ISO Image2 Part3 offset |
| 177 | B_UINT32 OffsetISOImage2Part3End; |
| 178 | |
| 179 | |
| 180 | // DSD Header offset from start of DSD |
| 181 | B_UINT32 OffsetFromDSDStartForDSDHeader; |
| 182 | B_UINT32 OffsetFromZeroForDSD1Start; // DSD 1 offset |
| 183 | B_UINT32 OffsetFromZeroForDSD1End; |
| 184 | B_UINT32 OffsetFromZeroForDSD2Start; // DSD 2 offset |
| 185 | B_UINT32 OffsetFromZeroForDSD2End; |
| 186 | |
| 187 | B_UINT32 OffsetFromZeroForVSA1Start; // VSA 1 offset |
| 188 | B_UINT32 OffsetFromZeroForVSA1End; |
| 189 | B_UINT32 OffsetFromZeroForVSA2Start; // VSA 2 offset |
| 190 | B_UINT32 OffsetFromZeroForVSA2End; |
| 191 | |
| 192 | /* |
| 193 | * ACCESS_BITS_PER_SECTOR 2 |
| 194 | * ACCESS_RW 0 |
| 195 | * ACCESS_RO 1 |
| 196 | * ACCESS_RESVD 2 |
| 197 | * ACCESS_RESVD 3 |
| 198 | * */ |
| 199 | B_UINT32 SectorAccessBitMap[FLASH2X_TOTAL_SIZE/(DEFAULT_SECTOR_SIZE *16)]; |
| 200 | |
| 201 | // All expansions to the control data structure should add here |
| 202 | |
| 203 | }FLASH2X_CS_INFO,*PFLASH2X_CS_INFO; |
| 204 | |
| 205 | typedef struct _VENDOR_SECTION_INFO |
| 206 | { |
| 207 | B_UINT32 OffsetFromZeroForSectionStart; |
| 208 | B_UINT32 OffsetFromZeroForSectionEnd; |
| 209 | B_UINT32 AccessFlags; |
| 210 | B_UINT32 Reserved[16]; |
| 211 | |
| 212 | } VENDOR_SECTION_INFO, *PVENDOR_SECTION_INFO; |
| 213 | |
| 214 | typedef struct _FLASH2X_VENDORSPECIFIC_INFO |
| 215 | { |
| 216 | VENDOR_SECTION_INFO VendorSection[TOTAL_SECTIONS]; |
| 217 | B_UINT32 Reserved[16]; |
| 218 | |
| 219 | } FLASH2X_VENDORSPECIFIC_INFO, *PFLASH2X_VENDORSPECIFIC_INFO; |
| 220 | |
| 221 | typedef struct _DSD_HEADER |
| 222 | { |
| 223 | B_UINT32 DSDImageSize; |
| 224 | B_UINT32 DSDImageCRC; |
| 225 | B_UINT32 DSDImagePriority; |
| 226 | //We should not consider right now. Reading reserve is worthless. |
| 227 | B_UINT32 Reserved[252]; // Resvd for DSD Header |
| 228 | B_UINT32 DSDImageMagicNumber; |
| 229 | |
| 230 | }DSD_HEADER, *PDSD_HEADER; |
| 231 | |
| 232 | typedef struct _ISO_HEADER |
| 233 | { |
| 234 | B_UINT32 ISOImageMagicNumber; |
| 235 | B_UINT32 ISOImageSize; |
| 236 | B_UINT32 ISOImageCRC; |
| 237 | B_UINT32 ISOImagePriority; |
| 238 | //We should not consider right now. Reading reserve is worthless. |
| 239 | B_UINT32 Reserved[60]; //Resvd for ISO Header extension |
| 240 | |
| 241 | }ISO_HEADER, *PISO_HEADER; |
| 242 | |
| 243 | #define EEPROM_BEGIN_CIS (0) |
| 244 | #define EEPROM_BEGIN_NON_CIS (0x200) |
| 245 | #define EEPROM_END (0x2000) |
| 246 | |
| 247 | #define INIT_PARAMS_SIGNATURE (0x95a7a597) |
| 248 | |
| 249 | #define MAX_INIT_PARAMS_LENGTH (2048) |
| 250 | |
| 251 | |
| 252 | #define MAC_ADDRESS_OFFSET 0x200 |
| 253 | |
| 254 | |
| 255 | #define INIT_PARAMS_1_SIGNATURE_ADDRESS EEPROM_BEGIN_NON_CIS |
| 256 | #define INIT_PARAMS_1_DATA_ADDRESS (INIT_PARAMS_1_SIGNATURE_ADDRESS+16) |
| 257 | #define INIT_PARAMS_1_MACADDRESS_ADDRESS (MAC_ADDRESS_OFFSET) |
| 258 | #define INIT_PARAMS_1_LENGTH_ADDRESS (INIT_PARAMS_1_SIGNATURE_ADDRESS+4) |
| 259 | |
| 260 | #define INIT_PARAMS_2_SIGNATURE_ADDRESS (EEPROM_BEGIN_NON_CIS+2048+16) |
| 261 | #define INIT_PARAMS_2_DATA_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS+16) |
| 262 | #define INIT_PARAMS_2_MACADDRESS_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS+8) |
| 263 | #define INIT_PARAMS_2_LENGTH_ADDRESS (INIT_PARAMS_2_SIGNATURE_ADDRESS+4) |
| 264 | |
| 265 | #define EEPROM_SPI_DEV_CONFIG_REG 0x0F003000 |
| 266 | #define EEPROM_SPI_Q_STATUS1_REG 0x0F003004 |
| 267 | #define EEPROM_SPI_Q_STATUS1_MASK_REG 0x0F00300C |
| 268 | |
| 269 | #define EEPROM_SPI_Q_STATUS_REG 0x0F003008 |
| 270 | #define EEPROM_CMDQ_SPI_REG 0x0F003018 |
| 271 | #define EEPROM_WRITE_DATAQ_REG 0x0F00301C |
| 272 | #define EEPROM_READ_DATAQ_REG 0x0F003020 |
| 273 | #define SPI_FLUSH_REG 0x0F00304C |
| 274 | |
| 275 | #define EEPROM_WRITE_ENABLE 0x06000000 |
| 276 | #define EEPROM_READ_STATUS_REGISTER 0x05000000 |
| 277 | #define EEPROM_16_BYTE_PAGE_WRITE 0xFA000000 |
| 278 | #define EEPROM_WRITE_QUEUE_EMPTY 0x00001000 |
| 279 | #define EEPROM_WRITE_QUEUE_AVAIL 0x00002000 |
| 280 | #define EEPROM_WRITE_QUEUE_FULL 0x00004000 |
| 281 | #define EEPROM_16_BYTE_PAGE_READ 0xFB000000 |
| 282 | #define EEPROM_4_BYTE_PAGE_READ 0x3B000000 |
| 283 | |
| 284 | #define EEPROM_CMD_QUEUE_FLUSH 0x00000001 |
| 285 | #define EEPROM_WRITE_QUEUE_FLUSH 0x00000002 |
| 286 | #define EEPROM_READ_QUEUE_FLUSH 0x00000004 |
| 287 | #define EEPROM_ETH_QUEUE_FLUSH 0x00000008 |
| 288 | #define EEPROM_ALL_QUEUE_FLUSH 0x0000000f |
| 289 | #define EEPROM_READ_ENABLE 0x06000000 |
| 290 | #define EEPROM_16_BYTE_PAGE_WRITE 0xFA000000 |
| 291 | #define EEPROM_READ_DATA_FULL 0x00000010 |
| 292 | #define EEPROM_READ_DATA_AVAIL 0x00000020 |
| 293 | #define EEPROM_READ_QUEUE_EMPTY 0x00000002 |
| 294 | #define EEPROM_CMD_QUEUE_EMPTY 0x00000100 |
| 295 | #define EEPROM_CMD_QUEUE_AVAIL 0x00000200 |
| 296 | #define EEPROM_CMD_QUEUE_FULL 0x00000400 |
| 297 | |
| 298 | /* Most EEPROM status register bit 0 indicates if the EEPROM is busy |
| 299 | * with a write if set 1. See the details of the EEPROM Status Register |
| 300 | * in the EEPROM data sheet. */ |
| 301 | #define EEPROM_STATUS_REG_WRITE_BUSY 0x00000001 |
| 302 | |
| 303 | // We will have 1 mSec for every RETRIES_PER_DELAY count and have a max attempts of MAX_EEPROM_RETRIES |
| 304 | // This will give us 80 mSec minimum of delay = 80mSecs |
| 305 | #define MAX_EEPROM_RETRIES 80 |
| 306 | #define RETRIES_PER_DELAY 64 |
| 307 | |
| 308 | |
| 309 | #define MAX_RW_SIZE 0x10 |
| 310 | #define MAX_READ_SIZE 0x10 |
| 311 | #define MAX_SECTOR_SIZE (512*1024) |
| 312 | #define MIN_SECTOR_SIZE (1024) |
| 313 | #define FLASH_SECTOR_SIZE_OFFSET 0xEFFFC |
| 314 | #define FLASH_SECTOR_SIZE_SIG_OFFSET 0xEFFF8 |
| 315 | #define FLASH_SECTOR_SIZE_SIG 0xCAFEBABE |
| 316 | #define FLASH_CS_INFO_START_ADDR 0xFF0000 |
| 317 | #define FLASH_CONTROL_STRUCT_SIGNATURE 0xBECEF1A5 |
| 318 | #define SCSI_FIRMWARE_MAJOR_VERSION 0x1 |
| 319 | #define SCSI_FIRMWARE_MINOR_VERSION 0x5 |
| 320 | #define BYTE_WRITE_SUPPORT 0x1 |
| 321 | |
| 322 | #define FLASH_AUTO_INIT_BASE_ADDR 0xF00000 |
| 323 | |
| 324 | |
| 325 | |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 326 | |
| 327 | #define FLASH_CONTIGIOUS_START_ADDR_AFTER_INIT 0x1C000000 |
| 328 | #define FLASH_CONTIGIOUS_START_ADDR_BEFORE_INIT 0x1F000000 |
| 329 | |
| 330 | #define FLASH_CONTIGIOUS_START_ADDR_BCS350 0x08000000 |
| 331 | #define FLASH_CONTIGIOUS_END_ADDR_BCS350 0x08FFFFFF |
| 332 | |
| 333 | |
| 334 | |
| 335 | #define FLASH_SIZE_ADDR 0xFFFFEC |
| 336 | |
| 337 | #define FLASH_SPI_CMDQ_REG 0xAF003040 |
| 338 | #define FLASH_SPI_WRITEQ_REG 0xAF003044 |
| 339 | #define FLASH_SPI_READQ_REG 0xAF003048 |
| 340 | #define FLASH_CONFIG_REG 0xAF003050 |
| 341 | #define FLASH_GPIO_CONFIG_REG 0xAF000030 |
| 342 | |
| 343 | #define FLASH_CMD_WRITE_ENABLE 0x06 |
| 344 | #define FLASH_CMD_READ_ENABLE 0x03 |
| 345 | #define FLASH_CMD_RESET_WRITE_ENABLE 0x04 |
| 346 | #define FLASH_CMD_STATUS_REG_READ 0x05 |
| 347 | #define FLASH_CMD_STATUS_REG_WRITE 0x01 |
| 348 | #define FLASH_CMD_READ_ID 0x9F |
| 349 | |
| 350 | #define PAD_SELECT_REGISTER 0xAF000410 |
| 351 | |
| 352 | #define FLASH_PART_SST25VF080B 0xBF258E |
| 353 | |
| 354 | #define EEPROM_CAL_DATA_INTERNAL_LOC 0xbFB00008 |
| 355 | |
| 356 | #define EEPROM_CALPARAM_START 0x200 |
| 357 | #define EEPROM_SIZE_OFFSET 524 |
| 358 | |
| 359 | //As Read/Write time vaires from 1.5 to 3.0 ms. |
| 360 | //so After Ignoring the rdm/wrm time(that is dependent on many factor like interface etc.), |
| 361 | //here time calculated meets the worst case delay, 3.0 ms |
| 362 | #define MAX_FLASH_RETRIES 4 |
| 363 | #define FLASH_PER_RETRIES_DELAY 16 |
| 364 | |
| 365 | |
| 366 | #define EEPROM_MAX_CAL_AREA_SIZE 0xF0000 |
| 367 | |
| 368 | |
| 369 | |
| 370 | #define BECM ntohl(0x4245434d) |
| 371 | |
| 372 | #define FLASH_2X_MAJOR_NUMBER 0x2 |
| 373 | #define DSD_IMAGE_MAGIC_NUMBER 0xBECE0D5D |
| 374 | #define ISO_IMAGE_MAGIC_NUMBER 0xBECE0150 |
| 375 | #define NON_CDLESS_DEVICE_BOOT_SIG 0xBECEB007 |
| 376 | #define MINOR_VERSION(x) ((x >>16) & 0xFFFF) |
| 377 | #define MAJOR_VERSION(x) (x & 0xFFFF) |
| 378 | #define CORRUPTED_PATTERN 0x0 |
| 379 | #define UNINIT_PTR_IN_CS 0xBBBBDDDD |
| 380 | |
| 381 | #define VENDOR_PTR_IN_CS 0xAAAACCCC |
| 382 | |
| 383 | |
| 384 | #define FLASH2X_SECTION_PRESENT 1<<0 |
| 385 | #define FLASH2X_SECTION_VALID 1<<1 |
| 386 | #define FLASH2X_SECTION_RO 1<<2 |
| 387 | #define FLASH2X_SECTION_ACT 1<<3 |
| 388 | #define SECTOR_IS_NOT_WRITABLE STATUS_FAILURE |
| 389 | #define INVALID_OFFSET STATUS_FAILURE |
| 390 | #define INVALID_SECTION STATUS_FAILURE |
| 391 | #define SECTOR_1K 1024 |
| 392 | #define SECTOR_64K (64 *SECTOR_1K) |
| 393 | #define SECTOR_128K (2 * SECTOR_64K) |
| 394 | #define SECTOR_256k (2 * SECTOR_128K) |
| 395 | #define SECTOR_512K (2 * SECTOR_256k) |
| 396 | #define FLASH_PART_SIZE (16 * 1024 * 1024) |
| 397 | #define RESET_CHIP_SELECT -1 |
| 398 | #define CHIP_SELECT_BIT12 12 |
| 399 | |
| 400 | #define SECTOR_READWRITE_PERMISSION 0 |
| 401 | #define SECTOR_READONLY 1 |
| 402 | #define SIGNATURE_SIZE 4 |
| 403 | #define DEFAULT_BUFF_SIZE 0x10000 |
| 404 | |
| 405 | |
| 406 | #define FIELD_OFFSET_IN_HEADER(HeaderPointer,Field) ((PUCHAR)&((HeaderPointer)(NULL))->Field - (PUCHAR)(NULL)) |
| 407 | |
Stephen Hemminger | f8942e0 | 2010-09-08 14:46:36 -0700 | [diff] [blame] | 408 | #endif |
| 409 | |