blob: 42eb4315740b1488e26192b5ff0cb07747312df5 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
3 *
4 * Copyright (C) 1999-2001 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
Hyok S. Choid090ddd2006-06-28 14:10:01 +01006 * hacked for non-paged-MM by Hyok S. Choi, 2003.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm926.
25 *
26 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
27 */
28#include <linux/linkage.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <linux/init.h>
30#include <asm/assembler.h>
Russell King5ec94072008-09-07 19:15:31 +010031#include <asm/hwcap.h>
Russell King74945c82006-03-16 14:44:36 +000032#include <asm/pgtable-hwdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <asm/pgtable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include <asm/page.h>
35#include <asm/ptrace.h>
36#include "proc-macros.S"
37
38/*
39 * This is the maximum size of an area which will be invalidated
40 * using the single invalidate entry instructions. Anything larger
41 * than this, and we go for the whole cache.
42 *
43 * This value should be chosen such that we choose the cheapest
44 * alternative.
45 */
46#define CACHE_DLIMIT 16384
47
48/*
49 * the cache line size of the I and D cache
50 */
51#define CACHE_DLINESIZE 32
52
53 .text
54/*
55 * cpu_arm926_proc_init()
56 */
57ENTRY(cpu_arm926_proc_init)
58 mov pc, lr
59
60/*
61 * cpu_arm926_proc_fin()
62 */
63ENTRY(cpu_arm926_proc_fin)
Linus Torvalds1da177e2005-04-16 15:20:36 -070064 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
65 bic r0, r0, #0x1000 @ ...i............
66 bic r0, r0, #0x000e @ ............wca.
67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
Russell King9ca03a22010-07-26 12:22:12 +010068 mov pc, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
70/*
71 * cpu_arm926_reset(loc)
72 *
73 * Perform a soft reset of the system. Put the CPU into the
74 * same state as it would be if it had been reset, and branch
75 * to what would be the reset vector.
76 *
77 * loc: location to jump to for soft reset
78 */
79 .align 5
80ENTRY(cpu_arm926_reset)
81 mov ip, #0
82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Hyok S. Choid090ddd2006-06-28 14:10:01 +010084#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +010086#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070087 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
88 bic ip, ip, #0x000f @ ............wcam
89 bic ip, ip, #0x1100 @ ...i...s........
90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mov pc, r0
92
93/*
94 * cpu_arm926_do_idle()
95 *
96 * Called with IRQs disabled
97 */
98 .align 10
99ENTRY(cpu_arm926_do_idle)
100 mov r0, #0
101 mrc p15, 0, r1, c1, c0, 0 @ Read control register
102 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
103 bic r2, r1, #1 << 12
Russell King0214f922007-10-27 11:01:35 +0100104 mrs r3, cpsr @ Disable FIQs while Icache
105 orr ip, r3, #PSR_F_BIT @ is disabled
106 msr cpsr_c, ip
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
109 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
Russell King0214f922007-10-27 11:01:35 +0100110 msr cpsr_c, r3 @ Restore FIQ state
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 mov pc, lr
112
113/*
Mika Westerbergc8c90862010-10-28 11:27:40 +0100114 * flush_icache_all()
115 *
116 * Unconditionally clean and invalidate the entire icache.
117 */
118ENTRY(arm926_flush_icache_all)
119 mov r0, #0
120 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
121 mov pc, lr
122ENDPROC(arm926_flush_icache_all)
123
124/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 * flush_user_cache_all()
126 *
127 * Clean and invalidate all cache entries in a particular
128 * address space.
129 */
130ENTRY(arm926_flush_user_cache_all)
131 /* FALLTHROUGH */
132
133/*
134 * flush_kern_cache_all()
135 *
136 * Clean and invalidate the entire cache.
137 */
138ENTRY(arm926_flush_kern_cache_all)
139 mov r2, #VM_EXEC
140 mov ip, #0
141__flush_whole_cache:
142#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
143 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
144#else
1451: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
146 bne 1b
147#endif
148 tst r2, #VM_EXEC
149 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
150 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
151 mov pc, lr
152
153/*
154 * flush_user_cache_range(start, end, flags)
155 *
156 * Clean and invalidate a range of cache entries in the
157 * specified address range.
158 *
159 * - start - start address (inclusive)
160 * - end - end address (exclusive)
161 * - flags - vm_flags describing address space
162 */
163ENTRY(arm926_flush_user_cache_range)
164 mov ip, #0
165 sub r3, r1, r0 @ calculate total size
166 cmp r3, #CACHE_DLIMIT
167 bgt __flush_whole_cache
1681: tst r2, #VM_EXEC
169#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
170 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
171 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
172 add r0, r0, #CACHE_DLINESIZE
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176#else
177 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
178 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
179 add r0, r0, #CACHE_DLINESIZE
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
182 add r0, r0, #CACHE_DLINESIZE
183#endif
184 cmp r0, r1
185 blo 1b
186 tst r2, #VM_EXEC
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 mov pc, lr
189
190/*
191 * coherent_kern_range(start, end)
192 *
193 * Ensure coherency between the Icache and the Dcache in the
194 * region described by start, end. If you have non-snooping
195 * Harvard caches, you need to implement this function.
196 *
197 * - start - virtual start address
198 * - end - virtual end address
199 */
200ENTRY(arm926_coherent_kern_range)
201 /* FALLTHROUGH */
202
203/*
204 * coherent_user_range(start, end)
205 *
206 * Ensure coherency between the Icache and the Dcache in the
207 * region described by start, end. If you have non-snooping
208 * Harvard caches, you need to implement this function.
209 *
210 * - start - virtual start address
211 * - end - virtual end address
212 */
213ENTRY(arm926_coherent_user_range)
214 bic r0, r0, #CACHE_DLINESIZE - 1
2151: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 add r0, r0, #CACHE_DLINESIZE
218 cmp r0, r1
219 blo 1b
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
221 mov pc, lr
222
223/*
Russell King2c9b9c82009-11-26 12:56:21 +0000224 * flush_kern_dcache_area(void *addr, size_t size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 *
226 * Ensure no D cache aliasing occurs, either with itself or
227 * the I cache
228 *
Russell King2c9b9c82009-11-26 12:56:21 +0000229 * - addr - kernel address
230 * - size - region size
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 */
Russell King2c9b9c82009-11-26 12:56:21 +0000232ENTRY(arm926_flush_kern_dcache_area)
233 add r1, r0, r1
Linus Torvalds1da177e2005-04-16 15:20:36 -07002341: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
235 add r0, r0, #CACHE_DLINESIZE
236 cmp r0, r1
237 blo 1b
238 mov r0, #0
239 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
240 mcr p15, 0, r0, c7, c10, 4 @ drain WB
241 mov pc, lr
242
243/*
244 * dma_inv_range(start, end)
245 *
246 * Invalidate (discard) the specified virtual address range.
247 * May not write back any entries. If 'start' or 'end'
248 * are not cache line aligned, those lines must be written
249 * back.
250 *
251 * - start - virtual start address
252 * - end - virtual end address
253 *
254 * (same as v4wb)
255 */
Russell King702b94b2009-11-26 16:24:19 +0000256arm926_dma_inv_range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
258 tst r0, #CACHE_DLINESIZE - 1
259 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
260 tst r1, #CACHE_DLINESIZE - 1
261 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
262#endif
263 bic r0, r0, #CACHE_DLINESIZE - 1
2641: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
265 add r0, r0, #CACHE_DLINESIZE
266 cmp r0, r1
267 blo 1b
268 mcr p15, 0, r0, c7, c10, 4 @ drain WB
269 mov pc, lr
270
271/*
272 * dma_clean_range(start, end)
273 *
274 * Clean the specified virtual address range.
275 *
276 * - start - virtual start address
277 * - end - virtual end address
278 *
279 * (same as v4wb)
280 */
Russell King702b94b2009-11-26 16:24:19 +0000281arm926_dma_clean_range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
283 bic r0, r0, #CACHE_DLINESIZE - 1
2841: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
285 add r0, r0, #CACHE_DLINESIZE
286 cmp r0, r1
287 blo 1b
288#endif
289 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 mov pc, lr
291
292/*
293 * dma_flush_range(start, end)
294 *
295 * Clean and invalidate the specified virtual address range.
296 *
297 * - start - virtual start address
298 * - end - virtual end address
299 */
300ENTRY(arm926_dma_flush_range)
301 bic r0, r0, #CACHE_DLINESIZE - 1
3021:
303#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
304 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
305#else
Lennert Buytenhekb3a8b752008-05-10 21:05:31 +0100306 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307#endif
308 add r0, r0, #CACHE_DLINESIZE
309 cmp r0, r1
310 blo 1b
311 mcr p15, 0, r0, c7, c10, 4 @ drain WB
312 mov pc, lr
313
Russell Kinga9c91472009-11-26 16:19:58 +0000314/*
315 * dma_map_area(start, size, dir)
316 * - start - kernel virtual start address
317 * - size - size of region
318 * - dir - DMA direction
319 */
320ENTRY(arm926_dma_map_area)
321 add r1, r1, r0
322 cmp r2, #DMA_TO_DEVICE
323 beq arm926_dma_clean_range
324 bcs arm926_dma_inv_range
325 b arm926_dma_flush_range
326ENDPROC(arm926_dma_map_area)
327
328/*
329 * dma_unmap_area(start, size, dir)
330 * - start - kernel virtual start address
331 * - size - size of region
332 * - dir - DMA direction
333 */
334ENTRY(arm926_dma_unmap_area)
335 mov pc, lr
336ENDPROC(arm926_dma_unmap_area)
337
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338ENTRY(arm926_cache_fns)
Mika Westerbergc8c90862010-10-28 11:27:40 +0100339 .long arm926_flush_icache_all
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 .long arm926_flush_kern_cache_all
341 .long arm926_flush_user_cache_all
342 .long arm926_flush_user_cache_range
343 .long arm926_coherent_kern_range
344 .long arm926_coherent_user_range
Russell King2c9b9c82009-11-26 12:56:21 +0000345 .long arm926_flush_kern_dcache_area
Russell Kinga9c91472009-11-26 16:19:58 +0000346 .long arm926_dma_map_area
347 .long arm926_dma_unmap_area
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348 .long arm926_dma_flush_range
349
350ENTRY(cpu_arm926_dcache_clean_area)
351#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
3521: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
353 add r0, r0, #CACHE_DLINESIZE
354 subs r1, r1, #CACHE_DLINESIZE
355 bhi 1b
356#endif
357 mcr p15, 0, r0, c7, c10, 4 @ drain WB
358 mov pc, lr
359
360/* =============================== PageTable ============================== */
361
362/*
363 * cpu_arm926_switch_mm(pgd)
364 *
365 * Set the translation base pointer to be as described by pgd.
366 *
367 * pgd: new page tables
368 */
369 .align 5
370ENTRY(cpu_arm926_switch_mm)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100371#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372 mov ip, #0
373#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
374 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
375#else
376@ && 'Clean & Invalidate whole DCache'
3771: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
378 bne 1b
379#endif
380 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
381 mcr p15, 0, ip, c7, c10, 4 @ drain WB
382 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
383 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100384#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 mov pc, lr
386
387/*
Russell Kingad1ae2f2006-12-13 14:34:43 +0000388 * cpu_arm926_set_pte_ext(ptep, pte, ext)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 *
390 * Set a PTE and flush it out
391 */
392 .align 5
Russell Kingad1ae2f2006-12-13 14:34:43 +0000393ENTRY(cpu_arm926_set_pte_ext)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100394#ifdef CONFIG_MMU
Russell Kingda091652008-09-06 17:19:08 +0100395 armv3_set_pte_ext
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 mov r0, r0
397#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
398 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
399#endif
400 mcr p15, 0, r0, c7, c10, 4 @ drain WB
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100401#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402 mov pc, lr
403
Russell King5085f3f2010-10-01 15:37:05 +0100404 __CPUINIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405
406 .type __arm926_setup, #function
407__arm926_setup:
408 mov r0, #0
409 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
410 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100411#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100413#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414
415
416#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
417 mov r0, #4 @ disable write-back on caches explicitly
418 mcr p15, 7, r0, c15, c0, 0
419#endif
420
Russell King22b190862006-06-29 15:09:57 +0100421 adr r5, arm926_crval
422 ldmia r5, {r5, r6}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 mrc p15, 0, r0, c1, c0 @ get control register v4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 bic r0, r0, r5
Russell King22b190862006-06-29 15:09:57 +0100425 orr r0, r0, r6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
427 orr r0, r0, #0x4000 @ .1.. .... .... ....
428#endif
429 mov pc, lr
430 .size __arm926_setup, . - __arm926_setup
431
432 /*
433 * R
434 * .RVI ZFRS BLDP WCAM
435 * .011 0001 ..11 0101
436 *
437 */
Russell King22b190862006-06-29 15:09:57 +0100438 .type arm926_crval, #object
439arm926_crval:
440 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441
442 __INITDATA
443
444/*
445 * Purpose : Function pointers used to access above functions - all calls
446 * come through these
447 */
448 .type arm926_processor_functions, #object
449arm926_processor_functions:
450 .word v5tj_early_abort
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100451 .word legacy_pabort
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 .word cpu_arm926_proc_init
453 .word cpu_arm926_proc_fin
454 .word cpu_arm926_reset
455 .word cpu_arm926_do_idle
456 .word cpu_arm926_dcache_clean_area
457 .word cpu_arm926_switch_mm
Russell Kingad1ae2f2006-12-13 14:34:43 +0000458 .word cpu_arm926_set_pte_ext
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 .size arm926_processor_functions, . - arm926_processor_functions
460
461 .section ".rodata"
462
463 .type cpu_arch_name, #object
464cpu_arch_name:
465 .asciz "armv5tej"
466 .size cpu_arch_name, . - cpu_arch_name
467
468 .type cpu_elf_name, #object
469cpu_elf_name:
470 .asciz "v5"
471 .size cpu_elf_name, . - cpu_elf_name
472
473 .type cpu_arm926_name, #object
474cpu_arm926_name:
Russell King264edb32006-06-29 15:03:09 +0100475 .asciz "ARM926EJ-S"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476 .size cpu_arm926_name, . - cpu_arm926_name
477
478 .align
479
Ben Dooks02b7dd12005-09-20 16:35:03 +0100480 .section ".proc.info.init", #alloc, #execinstr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481
482 .type __arm926_proc_info,#object
483__arm926_proc_info:
484 .long 0x41069260 @ ARM926EJ-S (v5TEJ)
485 .long 0xff0ffff0
486 .long PMD_TYPE_SECT | \
487 PMD_SECT_BUFFERABLE | \
488 PMD_SECT_CACHEABLE | \
489 PMD_BIT4 | \
490 PMD_SECT_AP_WRITE | \
491 PMD_SECT_AP_READ
Russell King8799ee92006-06-29 18:24:21 +0100492 .long PMD_TYPE_SECT | \
493 PMD_BIT4 | \
494 PMD_SECT_AP_WRITE | \
495 PMD_SECT_AP_READ
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496 b __arm926_setup
497 .long cpu_arch_name
498 .long cpu_elf_name
Russell Kingefe90d22006-12-08 15:22:20 +0000499 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500 .long cpu_arm926_name
501 .long arm926_processor_functions
502 .long v4wbi_tlb_fns
503 .long v4wb_user_fns
504 .long arm926_cache_fns
505 .size __arm926_proc_info, . - __arm926_proc_info