blob: 6d1aab6316baec1a720f6fc4200e4b569bb9233e [file] [log] [blame]
Auke Kokbc7f75f2007-09-17 12:30:59 -07001/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
Bruce Allanad680762008-03-28 09:15:03 -07004 Copyright(c) 1999 - 2008 Intel Corporation.
Auke Kokbc7f75f2007-09-17 12:30:59 -07005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
Bruce Allan16059272008-11-21 16:51:06 -080030 * 82562G 10/100 Network Connection
Auke Kokbc7f75f2007-09-17 12:30:59 -070031 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
Bruce Allan97ac8ca2008-04-29 09:16:05 -070042 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
Bruce Allan16059272008-11-21 16:51:06 -080044 * 82567V Gigabit Network Connection
Bruce Allan97ac8ca2008-04-29 09:16:05 -070045 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
Bruce Allanf4187b52008-08-26 18:36:50 -070048 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
Bruce Allan2f15f9d2008-08-26 18:36:36 -070050 * 82567LM-4 Gigabit Network Connection
Auke Kokbc7f75f2007-09-17 12:30:59 -070051 */
52
53#include <linux/netdevice.h>
54#include <linux/ethtool.h>
55#include <linux/delay.h>
56#include <linux/pci.h>
57
58#include "e1000.h"
59
60#define ICH_FLASH_GFPREG 0x0000
61#define ICH_FLASH_HSFSTS 0x0004
62#define ICH_FLASH_HSFCTL 0x0006
63#define ICH_FLASH_FADDR 0x0008
64#define ICH_FLASH_FDATA0 0x0010
Bruce Allan4a770352008-10-01 17:18:35 -070065#define ICH_FLASH_PR0 0x0074
Auke Kokbc7f75f2007-09-17 12:30:59 -070066
67#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
68#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
69#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
70#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
71#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
72
73#define ICH_CYCLE_READ 0
74#define ICH_CYCLE_WRITE 2
75#define ICH_CYCLE_ERASE 3
76
77#define FLASH_GFPREG_BASE_MASK 0x1FFF
78#define FLASH_SECTOR_ADDR_SHIFT 12
79
80#define ICH_FLASH_SEG_SIZE_256 256
81#define ICH_FLASH_SEG_SIZE_4K 4096
82#define ICH_FLASH_SEG_SIZE_8K 8192
83#define ICH_FLASH_SEG_SIZE_64K 65536
84
85
86#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87
88#define E1000_ICH_MNG_IAMT_MODE 0x2
89
90#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
91 (ID_LED_DEF1_OFF2 << 8) | \
92 (ID_LED_DEF1_ON2 << 4) | \
93 (ID_LED_DEF1_DEF2))
94
95#define E1000_ICH_NVM_SIG_WORD 0x13
96#define E1000_ICH_NVM_SIG_MASK 0xC000
Bruce Allane2434552008-11-21 17:02:41 -080097#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
98#define E1000_ICH_NVM_SIG_VALUE 0x80
Auke Kokbc7f75f2007-09-17 12:30:59 -070099
100#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
101
102#define E1000_FEXTNVM_SW_CONFIG 1
103#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
104
105#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
106
107#define E1000_ICH_RAR_ENTRIES 7
108
109#define PHY_PAGE_SHIFT 5
110#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
111 ((reg) & MAX_PHY_REG_ADDRESS))
112#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
113#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
114
115#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
116#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
117#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
118
119/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
120/* Offset 04h HSFSTS */
121union ich8_hws_flash_status {
122 struct ich8_hsfsts {
123 u16 flcdone :1; /* bit 0 Flash Cycle Done */
124 u16 flcerr :1; /* bit 1 Flash Cycle Error */
125 u16 dael :1; /* bit 2 Direct Access error Log */
126 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
127 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
128 u16 reserved1 :2; /* bit 13:6 Reserved */
129 u16 reserved2 :6; /* bit 13:6 Reserved */
130 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
131 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
132 } hsf_status;
133 u16 regval;
134};
135
136/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
137/* Offset 06h FLCTL */
138union ich8_hws_flash_ctrl {
139 struct ich8_hsflctl {
140 u16 flcgo :1; /* 0 Flash Cycle Go */
141 u16 flcycle :2; /* 2:1 Flash Cycle */
142 u16 reserved :5; /* 7:3 Reserved */
143 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
144 u16 flockdn :6; /* 15:10 Reserved */
145 } hsf_ctrl;
146 u16 regval;
147};
148
149/* ICH Flash Region Access Permissions */
150union ich8_hws_flash_regacc {
151 struct ich8_flracc {
152 u32 grra :8; /* 0:7 GbE region Read Access */
153 u32 grwa :8; /* 8:15 GbE region Write Access */
154 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
155 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
156 } hsf_flregacc;
157 u16 regval;
158};
159
Bruce Allan4a770352008-10-01 17:18:35 -0700160/* ICH Flash Protected Region */
161union ich8_flash_protected_range {
162 struct ich8_pr {
163 u32 base:13; /* 0:12 Protected Range Base */
164 u32 reserved1:2; /* 13:14 Reserved */
165 u32 rpe:1; /* 15 Read Protection Enable */
166 u32 limit:13; /* 16:28 Protected Range Limit */
167 u32 reserved2:2; /* 29:30 Reserved */
168 u32 wpe:1; /* 31 Write Protection Enable */
169 } range;
170 u32 regval;
171};
172
Auke Kokbc7f75f2007-09-17 12:30:59 -0700173static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
174static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
175static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
176static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
177static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
178static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
179 u32 offset, u8 byte);
Bruce Allanf4187b52008-08-26 18:36:50 -0700180static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
181 u8 *data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700182static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
183 u16 *data);
184static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
185 u8 size, u16 *data);
186static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
187static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
Bruce Allanf4187b52008-08-26 18:36:50 -0700188static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700189
190static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
191{
192 return readw(hw->flash_address + reg);
193}
194
195static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
196{
197 return readl(hw->flash_address + reg);
198}
199
200static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
201{
202 writew(val, hw->flash_address + reg);
203}
204
205static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
206{
207 writel(val, hw->flash_address + reg);
208}
209
210#define er16flash(reg) __er16flash(hw, (reg))
211#define er32flash(reg) __er32flash(hw, (reg))
212#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
213#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
214
215/**
216 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
217 * @hw: pointer to the HW structure
218 *
219 * Initialize family-specific PHY parameters and function pointers.
220 **/
221static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
222{
223 struct e1000_phy_info *phy = &hw->phy;
224 s32 ret_val;
225 u16 i = 0;
226
227 phy->addr = 1;
228 phy->reset_delay_us = 100;
229
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700230 /*
231 * We may need to do this twice - once for IGP and if that fails,
232 * we'll set BM func pointers and try again
233 */
234 ret_val = e1000e_determine_phy_address(hw);
235 if (ret_val) {
236 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
237 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
238 ret_val = e1000e_determine_phy_address(hw);
239 if (ret_val)
240 return ret_val;
241 }
242
Auke Kokbc7f75f2007-09-17 12:30:59 -0700243 phy->id = 0;
244 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
245 (i++ < 100)) {
246 msleep(1);
247 ret_val = e1000e_get_phy_id(hw);
248 if (ret_val)
249 return ret_val;
250 }
251
252 /* Verify phy id */
253 switch (phy->id) {
254 case IGP03E1000_E_PHY_ID:
255 phy->type = e1000_phy_igp_3;
256 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
257 break;
258 case IFE_E_PHY_ID:
259 case IFE_PLUS_E_PHY_ID:
260 case IFE_C_E_PHY_ID:
261 phy->type = e1000_phy_ife;
262 phy->autoneg_mask = E1000_ALL_NOT_GIG;
263 break;
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700264 case BME1000_E_PHY_ID:
265 phy->type = e1000_phy_bm;
266 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
267 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
268 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
269 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
270 break;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700271 default:
272 return -E1000_ERR_PHY;
273 break;
274 }
275
276 return 0;
277}
278
279/**
280 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
281 * @hw: pointer to the HW structure
282 *
283 * Initialize family-specific NVM parameters and function
284 * pointers.
285 **/
286static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
287{
288 struct e1000_nvm_info *nvm = &hw->nvm;
289 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
290 u32 gfpreg;
291 u32 sector_base_addr;
292 u32 sector_end_addr;
293 u16 i;
294
Bruce Allanad680762008-03-28 09:15:03 -0700295 /* Can't read flash registers if the register set isn't mapped. */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700296 if (!hw->flash_address) {
297 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
298 return -E1000_ERR_CONFIG;
299 }
300
301 nvm->type = e1000_nvm_flash_sw;
302
303 gfpreg = er32flash(ICH_FLASH_GFPREG);
304
Bruce Allanad680762008-03-28 09:15:03 -0700305 /*
306 * sector_X_addr is a "sector"-aligned address (4096 bytes)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700307 * Add 1 to sector_end_addr since this sector is included in
Bruce Allanad680762008-03-28 09:15:03 -0700308 * the overall size.
309 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700310 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
311 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
312
313 /* flash_base_addr is byte-aligned */
314 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
315
Bruce Allanad680762008-03-28 09:15:03 -0700316 /*
317 * find total size of the NVM, then cut in half since the total
318 * size represents two separate NVM banks.
319 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700320 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
321 << FLASH_SECTOR_ADDR_SHIFT;
322 nvm->flash_bank_size /= 2;
323 /* Adjust to word count */
324 nvm->flash_bank_size /= sizeof(u16);
325
326 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
327
328 /* Clear shadow ram */
329 for (i = 0; i < nvm->word_size; i++) {
330 dev_spec->shadow_ram[i].modified = 0;
331 dev_spec->shadow_ram[i].value = 0xFFFF;
332 }
333
334 return 0;
335}
336
337/**
338 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
339 * @hw: pointer to the HW structure
340 *
341 * Initialize family-specific MAC parameters and function
342 * pointers.
343 **/
344static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
345{
346 struct e1000_hw *hw = &adapter->hw;
347 struct e1000_mac_info *mac = &hw->mac;
348
349 /* Set media type function pointer */
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700350 hw->phy.media_type = e1000_media_type_copper;
Auke Kokbc7f75f2007-09-17 12:30:59 -0700351
352 /* Set mta register count */
353 mac->mta_reg_count = 32;
354 /* Set rar entry count */
355 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
356 if (mac->type == e1000_ich8lan)
357 mac->rar_entry_count--;
358 /* Set if manageability features are enabled. */
359 mac->arc_subsystem_valid = 1;
360
361 /* Enable PCS Lock-loss workaround for ICH8 */
362 if (mac->type == e1000_ich8lan)
363 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
364
365 return 0;
366}
367
Jeff Kirsher69e3fd82008-04-02 13:48:18 -0700368static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700369{
370 struct e1000_hw *hw = &adapter->hw;
371 s32 rc;
372
373 rc = e1000_init_mac_params_ich8lan(adapter);
374 if (rc)
375 return rc;
376
377 rc = e1000_init_nvm_params_ich8lan(hw);
378 if (rc)
379 return rc;
380
381 rc = e1000_init_phy_params_ich8lan(hw);
382 if (rc)
383 return rc;
384
385 if ((adapter->hw.mac.type == e1000_ich8lan) &&
386 (adapter->hw.phy.type == e1000_phy_igp_3))
387 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
388
389 return 0;
390}
391
Thomas Gleixner717d4382008-10-02 16:33:40 -0700392static DEFINE_MUTEX(nvm_mutex);
Thomas Gleixner717d4382008-10-02 16:33:40 -0700393
Auke Kokbc7f75f2007-09-17 12:30:59 -0700394/**
395 * e1000_acquire_swflag_ich8lan - Acquire software control flag
396 * @hw: pointer to the HW structure
397 *
398 * Acquires the software control flag for performing NVM and PHY
399 * operations. This is a function pointer entry point only called by
400 * read/write routines for the PHY and NVM parts.
401 **/
402static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
403{
404 u32 extcnf_ctrl;
405 u32 timeout = PHY_CFG_TIMEOUT;
406
Linus Torvalds95b866d2008-10-03 09:18:17 -0700407 might_sleep();
Thomas Gleixner717d4382008-10-02 16:33:40 -0700408
dave graham0a834a32009-02-14 23:46:10 -0800409 mutex_lock(&nvm_mutex);
Thomas Gleixner717d4382008-10-02 16:33:40 -0700410
Auke Kokbc7f75f2007-09-17 12:30:59 -0700411 while (timeout) {
412 extcnf_ctrl = er32(EXTCNF_CTRL);
413 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
414 ew32(EXTCNF_CTRL, extcnf_ctrl);
415
416 extcnf_ctrl = er32(EXTCNF_CTRL);
417 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
418 break;
419 mdelay(1);
420 timeout--;
421 }
422
423 if (!timeout) {
424 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
Bruce Allan2e2e8d52008-09-23 15:46:38 -0700425 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
426 ew32(EXTCNF_CTRL, extcnf_ctrl);
Thomas Gleixner717d4382008-10-02 16:33:40 -0700427 mutex_unlock(&nvm_mutex);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700428 return -E1000_ERR_CONFIG;
429 }
430
431 return 0;
432}
433
434/**
435 * e1000_release_swflag_ich8lan - Release software control flag
436 * @hw: pointer to the HW structure
437 *
438 * Releases the software control flag for performing NVM and PHY operations.
439 * This is a function pointer entry point only called by read/write
440 * routines for the PHY and NVM parts.
441 **/
442static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
443{
444 u32 extcnf_ctrl;
445
446 extcnf_ctrl = er32(EXTCNF_CTRL);
447 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
448 ew32(EXTCNF_CTRL, extcnf_ctrl);
Thomas Gleixner717d4382008-10-02 16:33:40 -0700449
Thomas Gleixner717d4382008-10-02 16:33:40 -0700450 mutex_unlock(&nvm_mutex);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700451}
452
453/**
Bruce Allan4662e822008-08-26 18:37:06 -0700454 * e1000_check_mng_mode_ich8lan - Checks management mode
455 * @hw: pointer to the HW structure
456 *
457 * This checks if the adapter has manageability enabled.
458 * This is a function pointer entry point only called by read/write
459 * routines for the PHY and NVM parts.
460 **/
461static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
462{
463 u32 fwsm = er32(FWSM);
464
465 return (fwsm & E1000_FWSM_MODE_MASK) ==
466 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
467}
468
469/**
Auke Kokbc7f75f2007-09-17 12:30:59 -0700470 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
471 * @hw: pointer to the HW structure
472 *
473 * Checks if firmware is blocking the reset of the PHY.
474 * This is a function pointer entry point only called by
475 * reset routines.
476 **/
477static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
478{
479 u32 fwsm;
480
481 fwsm = er32(FWSM);
482
483 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
484}
485
486/**
487 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
488 * @hw: pointer to the HW structure
489 *
490 * Forces the speed and duplex settings of the PHY.
491 * This is a function pointer entry point only called by
492 * PHY setup routines.
493 **/
494static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
495{
496 struct e1000_phy_info *phy = &hw->phy;
497 s32 ret_val;
498 u16 data;
499 bool link;
500
501 if (phy->type != e1000_phy_ife) {
502 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
503 return ret_val;
504 }
505
506 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
507 if (ret_val)
508 return ret_val;
509
510 e1000e_phy_force_speed_duplex_setup(hw, &data);
511
512 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
513 if (ret_val)
514 return ret_val;
515
516 /* Disable MDI-X support for 10/100 */
517 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
518 if (ret_val)
519 return ret_val;
520
521 data &= ~IFE_PMC_AUTO_MDIX;
522 data &= ~IFE_PMC_FORCE_MDIX;
523
524 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
525 if (ret_val)
526 return ret_val;
527
528 hw_dbg(hw, "IFE PMC: %X\n", data);
529
530 udelay(1);
531
Jeff Kirsher318a94d2008-03-28 09:15:16 -0700532 if (phy->autoneg_wait_to_complete) {
Auke Kokbc7f75f2007-09-17 12:30:59 -0700533 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
534
535 ret_val = e1000e_phy_has_link_generic(hw,
536 PHY_FORCE_LIMIT,
537 100000,
538 &link);
539 if (ret_val)
540 return ret_val;
541
542 if (!link)
543 hw_dbg(hw, "Link taking longer than expected.\n");
544
545 /* Try once more */
546 ret_val = e1000e_phy_has_link_generic(hw,
547 PHY_FORCE_LIMIT,
548 100000,
549 &link);
550 if (ret_val)
551 return ret_val;
552 }
553
554 return 0;
555}
556
557/**
558 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
559 * @hw: pointer to the HW structure
560 *
561 * Resets the PHY
562 * This is a function pointer entry point called by drivers
563 * or other shared routines.
564 **/
565static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
566{
567 struct e1000_phy_info *phy = &hw->phy;
568 u32 i;
569 u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
570 s32 ret_val;
571 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
572 u16 word_addr, reg_data, reg_addr, phy_page = 0;
573
574 ret_val = e1000e_phy_hw_reset_generic(hw);
575 if (ret_val)
576 return ret_val;
577
Bruce Allanad680762008-03-28 09:15:03 -0700578 /*
579 * Initialize the PHY from the NVM on ICH platforms. This
Auke Kokbc7f75f2007-09-17 12:30:59 -0700580 * is needed due to an issue where the NVM configuration is
581 * not properly autoloaded after power transitions.
582 * Therefore, after each PHY reset, we will load the
583 * configuration data out of the NVM manually.
584 */
585 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
586 struct e1000_adapter *adapter = hw->adapter;
587
588 /* Check if SW needs configure the PHY */
589 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
590 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
591 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
592 else
593 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
594
595 data = er32(FEXTNVM);
596 if (!(data & sw_cfg_mask))
597 return 0;
598
599 /* Wait for basic configuration completes before proceeding*/
600 do {
601 data = er32(STATUS);
602 data &= E1000_STATUS_LAN_INIT_DONE;
603 udelay(100);
604 } while ((!data) && --loop);
605
Bruce Allanad680762008-03-28 09:15:03 -0700606 /*
607 * If basic configuration is incomplete before the above loop
Auke Kokbc7f75f2007-09-17 12:30:59 -0700608 * count reaches 0, loading the configuration from NVM will
609 * leave the PHY in a bad state possibly resulting in no link.
610 */
611 if (loop == 0) {
612 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
613 }
614
615 /* Clear the Init Done bit for the next init event */
616 data = er32(STATUS);
617 data &= ~E1000_STATUS_LAN_INIT_DONE;
618 ew32(STATUS, data);
619
Bruce Allanad680762008-03-28 09:15:03 -0700620 /*
621 * Make sure HW does not configure LCD from PHY
622 * extended configuration before SW configuration
623 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700624 data = er32(EXTCNF_CTRL);
625 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
626 return 0;
627
628 cnf_size = er32(EXTCNF_SIZE);
629 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
630 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
631 if (!cnf_size)
632 return 0;
633
634 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
635 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
636
Bruce Allanad680762008-03-28 09:15:03 -0700637 /* Configure LCD from extended configuration region. */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700638
639 /* cnf_base_addr is in DWORD */
640 word_addr = (u16)(cnf_base_addr << 1);
641
642 for (i = 0; i < cnf_size; i++) {
643 ret_val = e1000_read_nvm(hw,
644 (word_addr + i * 2),
645 1,
646 &reg_data);
647 if (ret_val)
648 return ret_val;
649
650 ret_val = e1000_read_nvm(hw,
651 (word_addr + i * 2 + 1),
652 1,
653 &reg_addr);
654 if (ret_val)
655 return ret_val;
656
657 /* Save off the PHY page for future writes. */
658 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
659 phy_page = reg_data;
660 continue;
661 }
662
663 reg_addr |= phy_page;
664
665 ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
666 if (ret_val)
667 return ret_val;
668 }
669 }
670
671 return 0;
672}
673
674/**
675 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
676 * @hw: pointer to the HW structure
677 *
678 * Populates "phy" structure with various feature states.
679 * This function is only called by other family-specific
680 * routines.
681 **/
682static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
683{
684 struct e1000_phy_info *phy = &hw->phy;
685 s32 ret_val;
686 u16 data;
687 bool link;
688
689 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
690 if (ret_val)
691 return ret_val;
692
693 if (!link) {
694 hw_dbg(hw, "Phy info is only valid if link is up\n");
695 return -E1000_ERR_CONFIG;
696 }
697
698 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
699 if (ret_val)
700 return ret_val;
701 phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
702
703 if (phy->polarity_correction) {
704 ret_val = e1000_check_polarity_ife_ich8lan(hw);
705 if (ret_val)
706 return ret_val;
707 } else {
708 /* Polarity is forced */
709 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
710 ? e1000_rev_polarity_reversed
711 : e1000_rev_polarity_normal;
712 }
713
714 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
715 if (ret_val)
716 return ret_val;
717
718 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
719
720 /* The following parameters are undefined for 10/100 operation. */
721 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
722 phy->local_rx = e1000_1000t_rx_status_undefined;
723 phy->remote_rx = e1000_1000t_rx_status_undefined;
724
725 return 0;
726}
727
728/**
729 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
730 * @hw: pointer to the HW structure
731 *
732 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
733 * This is a function pointer entry point called by drivers
734 * or other shared routines.
735 **/
736static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
737{
738 switch (hw->phy.type) {
739 case e1000_phy_ife:
740 return e1000_get_phy_info_ife_ich8lan(hw);
741 break;
742 case e1000_phy_igp_3:
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700743 case e1000_phy_bm:
Auke Kokbc7f75f2007-09-17 12:30:59 -0700744 return e1000e_get_phy_info_igp(hw);
745 break;
746 default:
747 break;
748 }
749
750 return -E1000_ERR_PHY_TYPE;
751}
752
753/**
754 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
755 * @hw: pointer to the HW structure
756 *
Auke Kok489815c2008-02-21 15:11:07 -0800757 * Polarity is determined on the polarity reversal feature being enabled.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700758 * This function is only called by other family-specific
759 * routines.
760 **/
761static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
762{
763 struct e1000_phy_info *phy = &hw->phy;
764 s32 ret_val;
765 u16 phy_data, offset, mask;
766
Bruce Allanad680762008-03-28 09:15:03 -0700767 /*
768 * Polarity is determined based on the reversal feature being enabled.
Auke Kokbc7f75f2007-09-17 12:30:59 -0700769 */
770 if (phy->polarity_correction) {
771 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
772 mask = IFE_PESC_POLARITY_REVERSED;
773 } else {
774 offset = IFE_PHY_SPECIAL_CONTROL;
775 mask = IFE_PSC_FORCE_POLARITY;
776 }
777
778 ret_val = e1e_rphy(hw, offset, &phy_data);
779
780 if (!ret_val)
781 phy->cable_polarity = (phy_data & mask)
782 ? e1000_rev_polarity_reversed
783 : e1000_rev_polarity_normal;
784
785 return ret_val;
786}
787
788/**
789 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
790 * @hw: pointer to the HW structure
791 * @active: TRUE to enable LPLU, FALSE to disable
792 *
793 * Sets the LPLU D0 state according to the active flag. When
794 * activating LPLU this function also disables smart speed
795 * and vice versa. LPLU will not be activated unless the
796 * device autonegotiation advertisement meets standards of
797 * either 10 or 10/100 or 10/100/1000 at all duplexes.
798 * This is a function pointer entry point only called by
799 * PHY setup routines.
800 **/
801static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
802{
803 struct e1000_phy_info *phy = &hw->phy;
804 u32 phy_ctrl;
805 s32 ret_val = 0;
806 u16 data;
807
Bruce Allan97ac8ca2008-04-29 09:16:05 -0700808 if (phy->type == e1000_phy_ife)
Auke Kokbc7f75f2007-09-17 12:30:59 -0700809 return ret_val;
810
811 phy_ctrl = er32(PHY_CTRL);
812
813 if (active) {
814 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
815 ew32(PHY_CTRL, phy_ctrl);
816
Bruce Allanad680762008-03-28 09:15:03 -0700817 /*
818 * Call gig speed drop workaround on LPLU before accessing
819 * any PHY registers
820 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700821 if ((hw->mac.type == e1000_ich8lan) &&
822 (hw->phy.type == e1000_phy_igp_3))
823 e1000e_gig_downshift_workaround_ich8lan(hw);
824
825 /* When LPLU is enabled, we should disable SmartSpeed */
826 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
827 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
828 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
829 if (ret_val)
830 return ret_val;
831 } else {
832 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
833 ew32(PHY_CTRL, phy_ctrl);
834
Bruce Allanad680762008-03-28 09:15:03 -0700835 /*
836 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
Auke Kokbc7f75f2007-09-17 12:30:59 -0700837 * during Dx states where the power conservation is most
838 * important. During driver activity we should enable
Bruce Allanad680762008-03-28 09:15:03 -0700839 * SmartSpeed, so performance is maintained.
840 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700841 if (phy->smart_speed == e1000_smart_speed_on) {
842 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -0700843 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700844 if (ret_val)
845 return ret_val;
846
847 data |= IGP01E1000_PSCFR_SMART_SPEED;
848 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -0700849 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700850 if (ret_val)
851 return ret_val;
852 } else if (phy->smart_speed == e1000_smart_speed_off) {
853 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -0700854 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700855 if (ret_val)
856 return ret_val;
857
858 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
859 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
Bruce Allanad680762008-03-28 09:15:03 -0700860 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700861 if (ret_val)
862 return ret_val;
863 }
864 }
865
866 return 0;
867}
868
869/**
870 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
871 * @hw: pointer to the HW structure
872 * @active: TRUE to enable LPLU, FALSE to disable
873 *
874 * Sets the LPLU D3 state according to the active flag. When
875 * activating LPLU this function also disables smart speed
876 * and vice versa. LPLU will not be activated unless the
877 * device autonegotiation advertisement meets standards of
878 * either 10 or 10/100 or 10/100/1000 at all duplexes.
879 * This is a function pointer entry point only called by
880 * PHY setup routines.
881 **/
882static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
883{
884 struct e1000_phy_info *phy = &hw->phy;
885 u32 phy_ctrl;
886 s32 ret_val;
887 u16 data;
888
889 phy_ctrl = er32(PHY_CTRL);
890
891 if (!active) {
892 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
893 ew32(PHY_CTRL, phy_ctrl);
Bruce Allanad680762008-03-28 09:15:03 -0700894 /*
895 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
Auke Kokbc7f75f2007-09-17 12:30:59 -0700896 * during Dx states where the power conservation is most
897 * important. During driver activity we should enable
Bruce Allanad680762008-03-28 09:15:03 -0700898 * SmartSpeed, so performance is maintained.
899 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700900 if (phy->smart_speed == e1000_smart_speed_on) {
Bruce Allanad680762008-03-28 09:15:03 -0700901 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
902 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700903 if (ret_val)
904 return ret_val;
905
906 data |= IGP01E1000_PSCFR_SMART_SPEED;
Bruce Allanad680762008-03-28 09:15:03 -0700907 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
908 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700909 if (ret_val)
910 return ret_val;
911 } else if (phy->smart_speed == e1000_smart_speed_off) {
Bruce Allanad680762008-03-28 09:15:03 -0700912 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
913 &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700914 if (ret_val)
915 return ret_val;
916
917 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
Bruce Allanad680762008-03-28 09:15:03 -0700918 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
919 data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700920 if (ret_val)
921 return ret_val;
922 }
923 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
924 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
925 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
926 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
927 ew32(PHY_CTRL, phy_ctrl);
928
Bruce Allanad680762008-03-28 09:15:03 -0700929 /*
930 * Call gig speed drop workaround on LPLU before accessing
931 * any PHY registers
932 */
Auke Kokbc7f75f2007-09-17 12:30:59 -0700933 if ((hw->mac.type == e1000_ich8lan) &&
934 (hw->phy.type == e1000_phy_igp_3))
935 e1000e_gig_downshift_workaround_ich8lan(hw);
936
937 /* When LPLU is enabled, we should disable SmartSpeed */
Bruce Allanad680762008-03-28 09:15:03 -0700938 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700939 if (ret_val)
940 return ret_val;
941
942 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
Bruce Allanad680762008-03-28 09:15:03 -0700943 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
Auke Kokbc7f75f2007-09-17 12:30:59 -0700944 }
945
946 return 0;
947}
948
949/**
Bruce Allanf4187b52008-08-26 18:36:50 -0700950 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
951 * @hw: pointer to the HW structure
952 * @bank: pointer to the variable that returns the active bank
953 *
954 * Reads signature byte from the NVM using the flash access registers.
Bruce Allane2434552008-11-21 17:02:41 -0800955 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
Bruce Allanf4187b52008-08-26 18:36:50 -0700956 **/
957static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
958{
Bruce Allane2434552008-11-21 17:02:41 -0800959 u32 eecd;
Bruce Allanf4187b52008-08-26 18:36:50 -0700960 struct e1000_nvm_info *nvm = &hw->nvm;
Bruce Allanf4187b52008-08-26 18:36:50 -0700961 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
962 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
Bruce Allane2434552008-11-21 17:02:41 -0800963 u8 sig_byte = 0;
964 s32 ret_val = 0;
Bruce Allanf4187b52008-08-26 18:36:50 -0700965
Bruce Allane2434552008-11-21 17:02:41 -0800966 switch (hw->mac.type) {
967 case e1000_ich8lan:
968 case e1000_ich9lan:
969 eecd = er32(EECD);
970 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
971 E1000_EECD_SEC1VAL_VALID_MASK) {
972 if (eecd & E1000_EECD_SEC1VAL)
Bruce Allanf4187b52008-08-26 18:36:50 -0700973 *bank = 1;
Bruce Allane2434552008-11-21 17:02:41 -0800974 else
975 *bank = 0;
976
977 return 0;
Bruce Allanf4187b52008-08-26 18:36:50 -0700978 }
Bruce Allane2434552008-11-21 17:02:41 -0800979 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
980 "reading flash signature\n");
981 /* fall-thru */
982 default:
983 /* set bank to 0 in case flash read fails */
984 *bank = 0;
985
986 /* Check bank 0 */
987 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
988 &sig_byte);
989 if (ret_val)
990 return ret_val;
991 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
992 E1000_ICH_NVM_SIG_VALUE) {
993 *bank = 0;
994 return 0;
995 }
996
997 /* Check bank 1 */
998 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
999 bank1_offset,
1000 &sig_byte);
1001 if (ret_val)
1002 return ret_val;
1003 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1004 E1000_ICH_NVM_SIG_VALUE) {
1005 *bank = 1;
1006 return 0;
1007 }
1008
1009 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1010 return -E1000_ERR_NVM;
Bruce Allanf4187b52008-08-26 18:36:50 -07001011 }
1012
1013 return 0;
1014}
1015
1016/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07001017 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1018 * @hw: pointer to the HW structure
1019 * @offset: The offset (in bytes) of the word(s) to read.
1020 * @words: Size of data to read in words
1021 * @data: Pointer to the word(s) to read at offset.
1022 *
1023 * Reads a word(s) from the NVM using the flash access registers.
1024 **/
1025static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1026 u16 *data)
1027{
1028 struct e1000_nvm_info *nvm = &hw->nvm;
1029 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1030 u32 act_offset;
1031 s32 ret_val;
Bruce Allanf4187b52008-08-26 18:36:50 -07001032 u32 bank = 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001033 u16 i, word;
1034
1035 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1036 (words == 0)) {
1037 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1038 return -E1000_ERR_NVM;
1039 }
1040
1041 ret_val = e1000_acquire_swflag_ich8lan(hw);
1042 if (ret_val)
Bruce Allane2434552008-11-21 17:02:41 -08001043 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001044
Bruce Allanf4187b52008-08-26 18:36:50 -07001045 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1046 if (ret_val)
Bruce Allane2434552008-11-21 17:02:41 -08001047 goto release;
Bruce Allanf4187b52008-08-26 18:36:50 -07001048
1049 act_offset = (bank) ? nvm->flash_bank_size : 0;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001050 act_offset += offset;
1051
1052 for (i = 0; i < words; i++) {
1053 if ((dev_spec->shadow_ram) &&
1054 (dev_spec->shadow_ram[offset+i].modified)) {
1055 data[i] = dev_spec->shadow_ram[offset+i].value;
1056 } else {
1057 ret_val = e1000_read_flash_word_ich8lan(hw,
1058 act_offset + i,
1059 &word);
1060 if (ret_val)
1061 break;
1062 data[i] = word;
1063 }
1064 }
1065
Bruce Allane2434552008-11-21 17:02:41 -08001066release:
Auke Kokbc7f75f2007-09-17 12:30:59 -07001067 e1000_release_swflag_ich8lan(hw);
1068
Bruce Allane2434552008-11-21 17:02:41 -08001069out:
1070 if (ret_val)
1071 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1072
Auke Kokbc7f75f2007-09-17 12:30:59 -07001073 return ret_val;
1074}
1075
1076/**
1077 * e1000_flash_cycle_init_ich8lan - Initialize flash
1078 * @hw: pointer to the HW structure
1079 *
1080 * This function does initial flash setup so that a new read/write/erase cycle
1081 * can be started.
1082 **/
1083static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1084{
1085 union ich8_hws_flash_status hsfsts;
1086 s32 ret_val = -E1000_ERR_NVM;
1087 s32 i = 0;
1088
1089 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1090
1091 /* Check if the flash descriptor is valid */
1092 if (hsfsts.hsf_status.fldesvalid == 0) {
1093 hw_dbg(hw, "Flash descriptor invalid. "
1094 "SW Sequencing must be used.");
1095 return -E1000_ERR_NVM;
1096 }
1097
1098 /* Clear FCERR and DAEL in hw status by writing 1 */
1099 hsfsts.hsf_status.flcerr = 1;
1100 hsfsts.hsf_status.dael = 1;
1101
1102 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1103
Bruce Allanad680762008-03-28 09:15:03 -07001104 /*
1105 * Either we should have a hardware SPI cycle in progress
Auke Kokbc7f75f2007-09-17 12:30:59 -07001106 * bit to check against, in order to start a new cycle or
1107 * FDONE bit should be changed in the hardware so that it
Auke Kok489815c2008-02-21 15:11:07 -08001108 * is 1 after hardware reset, which can then be used as an
Auke Kokbc7f75f2007-09-17 12:30:59 -07001109 * indication whether a cycle is in progress or has been
1110 * completed.
1111 */
1112
1113 if (hsfsts.hsf_status.flcinprog == 0) {
Bruce Allanad680762008-03-28 09:15:03 -07001114 /*
1115 * There is no cycle running at present,
1116 * so we can start a cycle
1117 * Begin by setting Flash Cycle Done.
1118 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001119 hsfsts.hsf_status.flcdone = 1;
1120 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1121 ret_val = 0;
1122 } else {
Bruce Allanad680762008-03-28 09:15:03 -07001123 /*
1124 * otherwise poll for sometime so the current
1125 * cycle has a chance to end before giving up.
1126 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001127 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1128 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1129 if (hsfsts.hsf_status.flcinprog == 0) {
1130 ret_val = 0;
1131 break;
1132 }
1133 udelay(1);
1134 }
1135 if (ret_val == 0) {
Bruce Allanad680762008-03-28 09:15:03 -07001136 /*
1137 * Successful in waiting for previous cycle to timeout,
1138 * now set the Flash Cycle Done.
1139 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001140 hsfsts.hsf_status.flcdone = 1;
1141 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1142 } else {
1143 hw_dbg(hw, "Flash controller busy, cannot get access");
1144 }
1145 }
1146
1147 return ret_val;
1148}
1149
1150/**
1151 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1152 * @hw: pointer to the HW structure
1153 * @timeout: maximum time to wait for completion
1154 *
1155 * This function starts a flash cycle and waits for its completion.
1156 **/
1157static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1158{
1159 union ich8_hws_flash_ctrl hsflctl;
1160 union ich8_hws_flash_status hsfsts;
1161 s32 ret_val = -E1000_ERR_NVM;
1162 u32 i = 0;
1163
1164 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1165 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1166 hsflctl.hsf_ctrl.flcgo = 1;
1167 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1168
1169 /* wait till FDONE bit is set to 1 */
1170 do {
1171 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1172 if (hsfsts.hsf_status.flcdone == 1)
1173 break;
1174 udelay(1);
1175 } while (i++ < timeout);
1176
1177 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1178 return 0;
1179
1180 return ret_val;
1181}
1182
1183/**
1184 * e1000_read_flash_word_ich8lan - Read word from flash
1185 * @hw: pointer to the HW structure
1186 * @offset: offset to data location
1187 * @data: pointer to the location for storing the data
1188 *
1189 * Reads the flash word at offset into data. Offset is converted
1190 * to bytes before read.
1191 **/
1192static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1193 u16 *data)
1194{
1195 /* Must convert offset into bytes. */
1196 offset <<= 1;
1197
1198 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1199}
1200
1201/**
Bruce Allanf4187b52008-08-26 18:36:50 -07001202 * e1000_read_flash_byte_ich8lan - Read byte from flash
1203 * @hw: pointer to the HW structure
1204 * @offset: The offset of the byte to read.
1205 * @data: Pointer to a byte to store the value read.
1206 *
1207 * Reads a single byte from the NVM using the flash access registers.
1208 **/
1209static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1210 u8 *data)
1211{
1212 s32 ret_val;
1213 u16 word = 0;
1214
1215 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1216 if (ret_val)
1217 return ret_val;
1218
1219 *data = (u8)word;
1220
1221 return 0;
1222}
1223
1224/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07001225 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1226 * @hw: pointer to the HW structure
1227 * @offset: The offset (in bytes) of the byte or word to read.
1228 * @size: Size of data to read, 1=byte 2=word
1229 * @data: Pointer to the word to store the value read.
1230 *
1231 * Reads a byte or word from the NVM using the flash access registers.
1232 **/
1233static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1234 u8 size, u16 *data)
1235{
1236 union ich8_hws_flash_status hsfsts;
1237 union ich8_hws_flash_ctrl hsflctl;
1238 u32 flash_linear_addr;
1239 u32 flash_data = 0;
1240 s32 ret_val = -E1000_ERR_NVM;
1241 u8 count = 0;
1242
1243 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1244 return -E1000_ERR_NVM;
1245
1246 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1247 hw->nvm.flash_base_addr;
1248
1249 do {
1250 udelay(1);
1251 /* Steps */
1252 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1253 if (ret_val != 0)
1254 break;
1255
1256 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1257 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1258 hsflctl.hsf_ctrl.fldbcount = size - 1;
1259 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1260 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1261
1262 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1263
1264 ret_val = e1000_flash_cycle_ich8lan(hw,
1265 ICH_FLASH_READ_COMMAND_TIMEOUT);
1266
Bruce Allanad680762008-03-28 09:15:03 -07001267 /*
1268 * Check if FCERR is set to 1, if set to 1, clear it
Auke Kokbc7f75f2007-09-17 12:30:59 -07001269 * and try the whole sequence a few more times, else
1270 * read in (shift in) the Flash Data0, the order is
Bruce Allanad680762008-03-28 09:15:03 -07001271 * least significant byte first msb to lsb
1272 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001273 if (ret_val == 0) {
1274 flash_data = er32flash(ICH_FLASH_FDATA0);
1275 if (size == 1) {
1276 *data = (u8)(flash_data & 0x000000FF);
1277 } else if (size == 2) {
1278 *data = (u16)(flash_data & 0x0000FFFF);
1279 }
1280 break;
1281 } else {
Bruce Allanad680762008-03-28 09:15:03 -07001282 /*
1283 * If we've gotten here, then things are probably
Auke Kokbc7f75f2007-09-17 12:30:59 -07001284 * completely hosed, but if the error condition is
1285 * detected, it won't hurt to give it another try...
1286 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1287 */
1288 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1289 if (hsfsts.hsf_status.flcerr == 1) {
1290 /* Repeat for some time before giving up. */
1291 continue;
1292 } else if (hsfsts.hsf_status.flcdone == 0) {
1293 hw_dbg(hw, "Timeout error - flash cycle "
1294 "did not complete.");
1295 break;
1296 }
1297 }
1298 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1299
1300 return ret_val;
1301}
1302
1303/**
1304 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1305 * @hw: pointer to the HW structure
1306 * @offset: The offset (in bytes) of the word(s) to write.
1307 * @words: Size of data to write in words
1308 * @data: Pointer to the word(s) to write at offset.
1309 *
1310 * Writes a byte or word to the NVM using the flash access registers.
1311 **/
1312static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1313 u16 *data)
1314{
1315 struct e1000_nvm_info *nvm = &hw->nvm;
1316 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1317 s32 ret_val;
1318 u16 i;
1319
1320 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1321 (words == 0)) {
1322 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1323 return -E1000_ERR_NVM;
1324 }
1325
1326 ret_val = e1000_acquire_swflag_ich8lan(hw);
1327 if (ret_val)
1328 return ret_val;
1329
1330 for (i = 0; i < words; i++) {
1331 dev_spec->shadow_ram[offset+i].modified = 1;
1332 dev_spec->shadow_ram[offset+i].value = data[i];
1333 }
1334
1335 e1000_release_swflag_ich8lan(hw);
1336
1337 return 0;
1338}
1339
1340/**
1341 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1342 * @hw: pointer to the HW structure
1343 *
1344 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1345 * which writes the checksum to the shadow ram. The changes in the shadow
1346 * ram are then committed to the EEPROM by processing each bank at a time
1347 * checking for the modified bit and writing only the pending changes.
Auke Kok489815c2008-02-21 15:11:07 -08001348 * After a successful commit, the shadow ram is cleared and is ready for
Auke Kokbc7f75f2007-09-17 12:30:59 -07001349 * future writes.
1350 **/
1351static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1352{
1353 struct e1000_nvm_info *nvm = &hw->nvm;
1354 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
Bruce Allanf4187b52008-08-26 18:36:50 -07001355 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001356 s32 ret_val;
1357 u16 data;
1358
1359 ret_val = e1000e_update_nvm_checksum_generic(hw);
1360 if (ret_val)
Bruce Allane2434552008-11-21 17:02:41 -08001361 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001362
1363 if (nvm->type != e1000_nvm_flash_sw)
Bruce Allane2434552008-11-21 17:02:41 -08001364 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001365
1366 ret_val = e1000_acquire_swflag_ich8lan(hw);
1367 if (ret_val)
Bruce Allane2434552008-11-21 17:02:41 -08001368 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001369
Bruce Allanad680762008-03-28 09:15:03 -07001370 /*
1371 * We're writing to the opposite bank so if we're on bank 1,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001372 * write to bank 0 etc. We also need to erase the segment that
Bruce Allanad680762008-03-28 09:15:03 -07001373 * is going to be written
1374 */
Bruce Allanf4187b52008-08-26 18:36:50 -07001375 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
Bruce Allane2434552008-11-21 17:02:41 -08001376 if (ret_val) {
1377 e1000_release_swflag_ich8lan(hw);
1378 goto out;
1379 }
Bruce Allanf4187b52008-08-26 18:36:50 -07001380
1381 if (bank == 0) {
Auke Kokbc7f75f2007-09-17 12:30:59 -07001382 new_bank_offset = nvm->flash_bank_size;
1383 old_bank_offset = 0;
Bruce Allane2434552008-11-21 17:02:41 -08001384 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1385 if (ret_val) {
1386 e1000_release_swflag_ich8lan(hw);
1387 goto out;
1388 }
Auke Kokbc7f75f2007-09-17 12:30:59 -07001389 } else {
1390 old_bank_offset = nvm->flash_bank_size;
1391 new_bank_offset = 0;
Bruce Allane2434552008-11-21 17:02:41 -08001392 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1393 if (ret_val) {
1394 e1000_release_swflag_ich8lan(hw);
1395 goto out;
1396 }
Auke Kokbc7f75f2007-09-17 12:30:59 -07001397 }
1398
1399 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
Bruce Allanad680762008-03-28 09:15:03 -07001400 /*
1401 * Determine whether to write the value stored
Auke Kokbc7f75f2007-09-17 12:30:59 -07001402 * in the other NVM bank or a modified value stored
Bruce Allanad680762008-03-28 09:15:03 -07001403 * in the shadow RAM
1404 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001405 if (dev_spec->shadow_ram[i].modified) {
1406 data = dev_spec->shadow_ram[i].value;
1407 } else {
Bruce Allane2434552008-11-21 17:02:41 -08001408 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1409 old_bank_offset,
1410 &data);
1411 if (ret_val)
1412 break;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001413 }
1414
Bruce Allanad680762008-03-28 09:15:03 -07001415 /*
1416 * If the word is 0x13, then make sure the signature bits
Auke Kokbc7f75f2007-09-17 12:30:59 -07001417 * (15:14) are 11b until the commit has completed.
1418 * This will allow us to write 10b which indicates the
1419 * signature is valid. We want to do this after the write
1420 * has completed so that we don't mark the segment valid
Bruce Allanad680762008-03-28 09:15:03 -07001421 * while the write is still in progress
1422 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001423 if (i == E1000_ICH_NVM_SIG_WORD)
1424 data |= E1000_ICH_NVM_SIG_MASK;
1425
1426 /* Convert offset to bytes. */
1427 act_offset = (i + new_bank_offset) << 1;
1428
1429 udelay(100);
1430 /* Write the bytes to the new bank. */
1431 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1432 act_offset,
1433 (u8)data);
1434 if (ret_val)
1435 break;
1436
1437 udelay(100);
1438 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1439 act_offset + 1,
1440 (u8)(data >> 8));
1441 if (ret_val)
1442 break;
1443 }
1444
Bruce Allanad680762008-03-28 09:15:03 -07001445 /*
1446 * Don't bother writing the segment valid bits if sector
1447 * programming failed.
1448 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001449 if (ret_val) {
Bruce Allan4a770352008-10-01 17:18:35 -07001450 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001451 hw_dbg(hw, "Flash commit failed.\n");
1452 e1000_release_swflag_ich8lan(hw);
Bruce Allane2434552008-11-21 17:02:41 -08001453 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001454 }
1455
Bruce Allanad680762008-03-28 09:15:03 -07001456 /*
1457 * Finally validate the new segment by setting bit 15:14
Auke Kokbc7f75f2007-09-17 12:30:59 -07001458 * to 10b in word 0x13 , this can be done without an
1459 * erase as well since these bits are 11 to start with
Bruce Allanad680762008-03-28 09:15:03 -07001460 * and we need to change bit 14 to 0b
1461 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001462 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
Bruce Allane2434552008-11-21 17:02:41 -08001463 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1464 if (ret_val) {
1465 e1000_release_swflag_ich8lan(hw);
1466 goto out;
1467 }
Auke Kokbc7f75f2007-09-17 12:30:59 -07001468 data &= 0xBFFF;
1469 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1470 act_offset * 2 + 1,
1471 (u8)(data >> 8));
1472 if (ret_val) {
1473 e1000_release_swflag_ich8lan(hw);
Bruce Allane2434552008-11-21 17:02:41 -08001474 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001475 }
1476
Bruce Allanad680762008-03-28 09:15:03 -07001477 /*
1478 * And invalidate the previously valid segment by setting
Auke Kokbc7f75f2007-09-17 12:30:59 -07001479 * its signature word (0x13) high_byte to 0b. This can be
1480 * done without an erase because flash erase sets all bits
Bruce Allanad680762008-03-28 09:15:03 -07001481 * to 1's. We can write 1's to 0's without an erase
1482 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001483 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1484 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1485 if (ret_val) {
1486 e1000_release_swflag_ich8lan(hw);
Bruce Allane2434552008-11-21 17:02:41 -08001487 goto out;
Auke Kokbc7f75f2007-09-17 12:30:59 -07001488 }
1489
1490 /* Great! Everything worked, we can now clear the cached entries. */
1491 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1492 dev_spec->shadow_ram[i].modified = 0;
1493 dev_spec->shadow_ram[i].value = 0xFFFF;
1494 }
1495
1496 e1000_release_swflag_ich8lan(hw);
1497
Bruce Allanad680762008-03-28 09:15:03 -07001498 /*
1499 * Reload the EEPROM, or else modifications will not appear
Auke Kokbc7f75f2007-09-17 12:30:59 -07001500 * until after the next adapter reset.
1501 */
1502 e1000e_reload_nvm(hw);
1503 msleep(10);
1504
Bruce Allane2434552008-11-21 17:02:41 -08001505out:
1506 if (ret_val)
1507 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1508
Auke Kokbc7f75f2007-09-17 12:30:59 -07001509 return ret_val;
1510}
1511
1512/**
1513 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1514 * @hw: pointer to the HW structure
1515 *
1516 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1517 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1518 * calculated, in which case we need to calculate the checksum and set bit 6.
1519 **/
1520static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1521{
1522 s32 ret_val;
1523 u16 data;
1524
Bruce Allanad680762008-03-28 09:15:03 -07001525 /*
1526 * Read 0x19 and check bit 6. If this bit is 0, the checksum
Auke Kokbc7f75f2007-09-17 12:30:59 -07001527 * needs to be fixed. This bit is an indication that the NVM
1528 * was prepared by OEM software and did not calculate the
1529 * checksum...a likely scenario.
1530 */
1531 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 if ((data & 0x40) == 0) {
1536 data |= 0x40;
1537 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1538 if (ret_val)
1539 return ret_val;
1540 ret_val = e1000e_update_nvm_checksum(hw);
1541 if (ret_val)
1542 return ret_val;
1543 }
1544
1545 return e1000e_validate_nvm_checksum_generic(hw);
1546}
1547
1548/**
Bruce Allan4a770352008-10-01 17:18:35 -07001549 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1550 * @hw: pointer to the HW structure
1551 *
1552 * To prevent malicious write/erase of the NVM, set it to be read-only
1553 * so that the hardware ignores all write/erase cycles of the NVM via
1554 * the flash control registers. The shadow-ram copy of the NVM will
1555 * still be updated, however any updates to this copy will not stick
1556 * across driver reloads.
1557 **/
1558void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1559{
1560 union ich8_flash_protected_range pr0;
1561 union ich8_hws_flash_status hsfsts;
1562 u32 gfpreg;
1563 s32 ret_val;
1564
1565 ret_val = e1000_acquire_swflag_ich8lan(hw);
1566 if (ret_val)
1567 return;
1568
1569 gfpreg = er32flash(ICH_FLASH_GFPREG);
1570
1571 /* Write-protect GbE Sector of NVM */
1572 pr0.regval = er32flash(ICH_FLASH_PR0);
1573 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1574 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1575 pr0.range.wpe = true;
1576 ew32flash(ICH_FLASH_PR0, pr0.regval);
1577
1578 /*
1579 * Lock down a subset of GbE Flash Control Registers, e.g.
1580 * PR0 to prevent the write-protection from being lifted.
1581 * Once FLOCKDN is set, the registers protected by it cannot
1582 * be written until FLOCKDN is cleared by a hardware reset.
1583 */
1584 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1585 hsfsts.hsf_status.flockdn = true;
1586 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1587
1588 e1000_release_swflag_ich8lan(hw);
1589}
1590
1591/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07001592 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1593 * @hw: pointer to the HW structure
1594 * @offset: The offset (in bytes) of the byte/word to read.
1595 * @size: Size of data to read, 1=byte 2=word
1596 * @data: The byte(s) to write to the NVM.
1597 *
1598 * Writes one/two bytes to the NVM using the flash access registers.
1599 **/
1600static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1601 u8 size, u16 data)
1602{
1603 union ich8_hws_flash_status hsfsts;
1604 union ich8_hws_flash_ctrl hsflctl;
1605 u32 flash_linear_addr;
1606 u32 flash_data = 0;
1607 s32 ret_val;
1608 u8 count = 0;
1609
1610 if (size < 1 || size > 2 || data > size * 0xff ||
1611 offset > ICH_FLASH_LINEAR_ADDR_MASK)
1612 return -E1000_ERR_NVM;
1613
1614 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1615 hw->nvm.flash_base_addr;
1616
1617 do {
1618 udelay(1);
1619 /* Steps */
1620 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1621 if (ret_val)
1622 break;
1623
1624 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1625 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1626 hsflctl.hsf_ctrl.fldbcount = size -1;
1627 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1628 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1629
1630 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1631
1632 if (size == 1)
1633 flash_data = (u32)data & 0x00FF;
1634 else
1635 flash_data = (u32)data;
1636
1637 ew32flash(ICH_FLASH_FDATA0, flash_data);
1638
Bruce Allanad680762008-03-28 09:15:03 -07001639 /*
1640 * check if FCERR is set to 1 , if set to 1, clear it
1641 * and try the whole sequence a few more times else done
1642 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001643 ret_val = e1000_flash_cycle_ich8lan(hw,
1644 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1645 if (!ret_val)
1646 break;
1647
Bruce Allanad680762008-03-28 09:15:03 -07001648 /*
1649 * If we're here, then things are most likely
Auke Kokbc7f75f2007-09-17 12:30:59 -07001650 * completely hosed, but if the error condition
1651 * is detected, it won't hurt to give it another
1652 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1653 */
1654 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1655 if (hsfsts.hsf_status.flcerr == 1)
1656 /* Repeat for some time before giving up. */
1657 continue;
1658 if (hsfsts.hsf_status.flcdone == 0) {
1659 hw_dbg(hw, "Timeout error - flash cycle "
1660 "did not complete.");
1661 break;
1662 }
1663 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1664
1665 return ret_val;
1666}
1667
1668/**
1669 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1670 * @hw: pointer to the HW structure
1671 * @offset: The index of the byte to read.
1672 * @data: The byte to write to the NVM.
1673 *
1674 * Writes a single byte to the NVM using the flash access registers.
1675 **/
1676static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1677 u8 data)
1678{
1679 u16 word = (u16)data;
1680
1681 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1682}
1683
1684/**
1685 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1686 * @hw: pointer to the HW structure
1687 * @offset: The offset of the byte to write.
1688 * @byte: The byte to write to the NVM.
1689 *
1690 * Writes a single byte to the NVM using the flash access registers.
1691 * Goes through a retry algorithm before giving up.
1692 **/
1693static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1694 u32 offset, u8 byte)
1695{
1696 s32 ret_val;
1697 u16 program_retries;
1698
1699 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1700 if (!ret_val)
1701 return ret_val;
1702
1703 for (program_retries = 0; program_retries < 100; program_retries++) {
1704 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1705 udelay(100);
1706 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1707 if (!ret_val)
1708 break;
1709 }
1710 if (program_retries == 100)
1711 return -E1000_ERR_NVM;
1712
1713 return 0;
1714}
1715
1716/**
1717 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1718 * @hw: pointer to the HW structure
1719 * @bank: 0 for first bank, 1 for second bank, etc.
1720 *
1721 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1722 * bank N is 4096 * N + flash_reg_addr.
1723 **/
1724static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1725{
1726 struct e1000_nvm_info *nvm = &hw->nvm;
1727 union ich8_hws_flash_status hsfsts;
1728 union ich8_hws_flash_ctrl hsflctl;
1729 u32 flash_linear_addr;
1730 /* bank size is in 16bit words - adjust to bytes */
1731 u32 flash_bank_size = nvm->flash_bank_size * 2;
1732 s32 ret_val;
1733 s32 count = 0;
1734 s32 iteration;
1735 s32 sector_size;
1736 s32 j;
1737
1738 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1739
Bruce Allanad680762008-03-28 09:15:03 -07001740 /*
1741 * Determine HW Sector size: Read BERASE bits of hw flash status
1742 * register
1743 * 00: The Hw sector is 256 bytes, hence we need to erase 16
Auke Kokbc7f75f2007-09-17 12:30:59 -07001744 * consecutive sectors. The start index for the nth Hw sector
1745 * can be calculated as = bank * 4096 + n * 256
1746 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1747 * The start index for the nth Hw sector can be calculated
1748 * as = bank * 4096
1749 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1750 * (ich9 only, otherwise error condition)
1751 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1752 */
1753 switch (hsfsts.hsf_status.berasesz) {
1754 case 0:
1755 /* Hw sector size 256 */
1756 sector_size = ICH_FLASH_SEG_SIZE_256;
1757 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1758 break;
1759 case 1:
1760 sector_size = ICH_FLASH_SEG_SIZE_4K;
1761 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1762 break;
1763 case 2:
1764 if (hw->mac.type == e1000_ich9lan) {
1765 sector_size = ICH_FLASH_SEG_SIZE_8K;
1766 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1767 } else {
1768 return -E1000_ERR_NVM;
1769 }
1770 break;
1771 case 3:
1772 sector_size = ICH_FLASH_SEG_SIZE_64K;
1773 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1774 break;
1775 default:
1776 return -E1000_ERR_NVM;
1777 }
1778
1779 /* Start with the base address, then add the sector offset. */
1780 flash_linear_addr = hw->nvm.flash_base_addr;
1781 flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1782
1783 for (j = 0; j < iteration ; j++) {
1784 do {
1785 /* Steps */
1786 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1787 if (ret_val)
1788 return ret_val;
1789
Bruce Allanad680762008-03-28 09:15:03 -07001790 /*
1791 * Write a value 11 (block Erase) in Flash
1792 * Cycle field in hw flash control
1793 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001794 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1795 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1796 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1797
Bruce Allanad680762008-03-28 09:15:03 -07001798 /*
1799 * Write the last 24 bits of an index within the
Auke Kokbc7f75f2007-09-17 12:30:59 -07001800 * block into Flash Linear address field in Flash
1801 * Address.
1802 */
1803 flash_linear_addr += (j * sector_size);
1804 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1805
1806 ret_val = e1000_flash_cycle_ich8lan(hw,
1807 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1808 if (ret_val == 0)
1809 break;
1810
Bruce Allanad680762008-03-28 09:15:03 -07001811 /*
1812 * Check if FCERR is set to 1. If 1,
Auke Kokbc7f75f2007-09-17 12:30:59 -07001813 * clear it and try the whole sequence
Bruce Allanad680762008-03-28 09:15:03 -07001814 * a few more times else Done
1815 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001816 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1817 if (hsfsts.hsf_status.flcerr == 1)
Bruce Allanad680762008-03-28 09:15:03 -07001818 /* repeat for some time before giving up */
Auke Kokbc7f75f2007-09-17 12:30:59 -07001819 continue;
1820 else if (hsfsts.hsf_status.flcdone == 0)
1821 return ret_val;
1822 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1823 }
1824
1825 return 0;
1826}
1827
1828/**
1829 * e1000_valid_led_default_ich8lan - Set the default LED settings
1830 * @hw: pointer to the HW structure
1831 * @data: Pointer to the LED settings
1832 *
1833 * Reads the LED default settings from the NVM to data. If the NVM LED
1834 * settings is all 0's or F's, set the LED default to a valid LED default
1835 * setting.
1836 **/
1837static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1838{
1839 s32 ret_val;
1840
1841 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1842 if (ret_val) {
1843 hw_dbg(hw, "NVM Read Error\n");
1844 return ret_val;
1845 }
1846
1847 if (*data == ID_LED_RESERVED_0000 ||
1848 *data == ID_LED_RESERVED_FFFF)
1849 *data = ID_LED_DEFAULT_ICH8LAN;
1850
1851 return 0;
1852}
1853
1854/**
1855 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1856 * @hw: pointer to the HW structure
1857 *
1858 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1859 * register, so the the bus width is hard coded.
1860 **/
1861static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1862{
1863 struct e1000_bus_info *bus = &hw->bus;
1864 s32 ret_val;
1865
1866 ret_val = e1000e_get_bus_info_pcie(hw);
1867
Bruce Allanad680762008-03-28 09:15:03 -07001868 /*
1869 * ICH devices are "PCI Express"-ish. They have
Auke Kokbc7f75f2007-09-17 12:30:59 -07001870 * a configuration space, but do not contain
1871 * PCI Express Capability registers, so bus width
1872 * must be hardcoded.
1873 */
1874 if (bus->width == e1000_bus_width_unknown)
1875 bus->width = e1000_bus_width_pcie_x1;
1876
1877 return ret_val;
1878}
1879
1880/**
1881 * e1000_reset_hw_ich8lan - Reset the hardware
1882 * @hw: pointer to the HW structure
1883 *
1884 * Does a full reset of the hardware which includes a reset of the PHY and
1885 * MAC.
1886 **/
1887static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1888{
1889 u32 ctrl, icr, kab;
1890 s32 ret_val;
1891
Bruce Allanad680762008-03-28 09:15:03 -07001892 /*
1893 * Prevent the PCI-E bus from sticking if there is no TLP connection
Auke Kokbc7f75f2007-09-17 12:30:59 -07001894 * on the last TLP read/write transaction when MAC is reset.
1895 */
1896 ret_val = e1000e_disable_pcie_master(hw);
1897 if (ret_val) {
1898 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1899 }
1900
1901 hw_dbg(hw, "Masking off all interrupts\n");
1902 ew32(IMC, 0xffffffff);
1903
Bruce Allanad680762008-03-28 09:15:03 -07001904 /*
1905 * Disable the Transmit and Receive units. Then delay to allow
Auke Kokbc7f75f2007-09-17 12:30:59 -07001906 * any pending transactions to complete before we hit the MAC
1907 * with the global reset.
1908 */
1909 ew32(RCTL, 0);
1910 ew32(TCTL, E1000_TCTL_PSP);
1911 e1e_flush();
1912
1913 msleep(10);
1914
1915 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1916 if (hw->mac.type == e1000_ich8lan) {
1917 /* Set Tx and Rx buffer allocation to 8k apiece. */
1918 ew32(PBA, E1000_PBA_8K);
1919 /* Set Packet Buffer Size to 16k. */
1920 ew32(PBS, E1000_PBS_16K);
1921 }
1922
1923 ctrl = er32(CTRL);
1924
1925 if (!e1000_check_reset_block(hw)) {
Bruce Allanad680762008-03-28 09:15:03 -07001926 /*
1927 * PHY HW reset requires MAC CORE reset at the same
Auke Kokbc7f75f2007-09-17 12:30:59 -07001928 * time to make sure the interface between MAC and the
1929 * external PHY is reset.
1930 */
1931 ctrl |= E1000_CTRL_PHY_RST;
1932 }
1933 ret_val = e1000_acquire_swflag_ich8lan(hw);
Jeff Kirsher30bb0e02008-12-11 21:28:11 -08001934 /* Whether or not the swflag was acquired, we need to reset the part */
Bruce Allan0285c8d2008-11-21 16:59:54 -08001935 hw_dbg(hw, "Issuing a global reset to ich8lan\n");
Auke Kokbc7f75f2007-09-17 12:30:59 -07001936 ew32(CTRL, (ctrl | E1000_CTRL_RST));
1937 msleep(20);
1938
Jeff Kirsher30bb0e02008-12-11 21:28:11 -08001939 if (!ret_val) {
1940 /* release the swflag because it is not reset by
1941 * hardware reset
1942 */
1943 e1000_release_swflag_ich8lan(hw);
1944 }
Jesse Brandeburg37f40232008-10-02 16:33:20 -07001945
Auke Kokbc7f75f2007-09-17 12:30:59 -07001946 ret_val = e1000e_get_auto_rd_done(hw);
1947 if (ret_val) {
1948 /*
1949 * When auto config read does not complete, do not
1950 * return with an error. This can happen in situations
1951 * where there is no eeprom and prevents getting link.
1952 */
1953 hw_dbg(hw, "Auto Read Done did not complete\n");
1954 }
1955
1956 ew32(IMC, 0xffffffff);
1957 icr = er32(ICR);
1958
1959 kab = er32(KABGTXD);
1960 kab |= E1000_KABGTXD_BGSQLBIAS;
1961 ew32(KABGTXD, kab);
1962
1963 return ret_val;
1964}
1965
1966/**
1967 * e1000_init_hw_ich8lan - Initialize the hardware
1968 * @hw: pointer to the HW structure
1969 *
1970 * Prepares the hardware for transmit and receive by doing the following:
1971 * - initialize hardware bits
1972 * - initialize LED identification
1973 * - setup receive address registers
1974 * - setup flow control
Auke Kok489815c2008-02-21 15:11:07 -08001975 * - setup transmit descriptors
Auke Kokbc7f75f2007-09-17 12:30:59 -07001976 * - clear statistics
1977 **/
1978static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1979{
1980 struct e1000_mac_info *mac = &hw->mac;
1981 u32 ctrl_ext, txdctl, snoop;
1982 s32 ret_val;
1983 u16 i;
1984
1985 e1000_initialize_hw_bits_ich8lan(hw);
1986
1987 /* Initialize identification LED */
1988 ret_val = e1000e_id_led_init(hw);
1989 if (ret_val) {
1990 hw_dbg(hw, "Error initializing identification LED\n");
1991 return ret_val;
1992 }
1993
1994 /* Setup the receive address. */
1995 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1996
1997 /* Zero out the Multicast HASH table */
1998 hw_dbg(hw, "Zeroing the MTA\n");
1999 for (i = 0; i < mac->mta_reg_count; i++)
2000 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2001
2002 /* Setup link and flow control */
2003 ret_val = e1000_setup_link_ich8lan(hw);
2004
2005 /* Set the transmit descriptor write-back policy for both queues */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002006 txdctl = er32(TXDCTL(0));
Auke Kokbc7f75f2007-09-17 12:30:59 -07002007 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2008 E1000_TXDCTL_FULL_TX_DESC_WB;
2009 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2010 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002011 ew32(TXDCTL(0), txdctl);
2012 txdctl = er32(TXDCTL(1));
Auke Kokbc7f75f2007-09-17 12:30:59 -07002013 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2014 E1000_TXDCTL_FULL_TX_DESC_WB;
2015 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2016 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002017 ew32(TXDCTL(1), txdctl);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002018
Bruce Allanad680762008-03-28 09:15:03 -07002019 /*
2020 * ICH8 has opposite polarity of no_snoop bits.
2021 * By default, we should use snoop behavior.
2022 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07002023 if (mac->type == e1000_ich8lan)
2024 snoop = PCIE_ICH8_SNOOP_ALL;
2025 else
2026 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2027 e1000e_set_pcie_no_snoop(hw, snoop);
2028
2029 ctrl_ext = er32(CTRL_EXT);
2030 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2031 ew32(CTRL_EXT, ctrl_ext);
2032
Bruce Allanad680762008-03-28 09:15:03 -07002033 /*
2034 * Clear all of the statistics registers (clear on read). It is
Auke Kokbc7f75f2007-09-17 12:30:59 -07002035 * important that we do this after we have tried to establish link
2036 * because the symbol error count will increment wildly if there
2037 * is no link.
2038 */
2039 e1000_clear_hw_cntrs_ich8lan(hw);
2040
2041 return 0;
2042}
2043/**
2044 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2045 * @hw: pointer to the HW structure
2046 *
2047 * Sets/Clears required hardware bits necessary for correctly setting up the
2048 * hardware for transmit and receive.
2049 **/
2050static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2051{
2052 u32 reg;
2053
2054 /* Extended Device Control */
2055 reg = er32(CTRL_EXT);
2056 reg |= (1 << 22);
2057 ew32(CTRL_EXT, reg);
2058
2059 /* Transmit Descriptor Control 0 */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002060 reg = er32(TXDCTL(0));
Auke Kokbc7f75f2007-09-17 12:30:59 -07002061 reg |= (1 << 22);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002062 ew32(TXDCTL(0), reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002063
2064 /* Transmit Descriptor Control 1 */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002065 reg = er32(TXDCTL(1));
Auke Kokbc7f75f2007-09-17 12:30:59 -07002066 reg |= (1 << 22);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002067 ew32(TXDCTL(1), reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002068
2069 /* Transmit Arbitration Control 0 */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002070 reg = er32(TARC(0));
Auke Kokbc7f75f2007-09-17 12:30:59 -07002071 if (hw->mac.type == e1000_ich8lan)
2072 reg |= (1 << 28) | (1 << 29);
2073 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002074 ew32(TARC(0), reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002075
2076 /* Transmit Arbitration Control 1 */
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002077 reg = er32(TARC(1));
Auke Kokbc7f75f2007-09-17 12:30:59 -07002078 if (er32(TCTL) & E1000_TCTL_MULR)
2079 reg &= ~(1 << 28);
2080 else
2081 reg |= (1 << 28);
2082 reg |= (1 << 24) | (1 << 26) | (1 << 30);
Jeff Kirshere9ec2c02008-04-02 13:48:13 -07002083 ew32(TARC(1), reg);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002084
2085 /* Device Status */
2086 if (hw->mac.type == e1000_ich8lan) {
2087 reg = er32(STATUS);
2088 reg &= ~(1 << 31);
2089 ew32(STATUS, reg);
2090 }
2091}
2092
2093/**
2094 * e1000_setup_link_ich8lan - Setup flow control and link settings
2095 * @hw: pointer to the HW structure
2096 *
2097 * Determines which flow control settings to use, then configures flow
2098 * control. Calls the appropriate media-specific link configuration
2099 * function. Assuming the adapter has a valid link partner, a valid link
2100 * should be established. Assumes the hardware has previously been reset
2101 * and the transmitter and receiver are not enabled.
2102 **/
2103static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2104{
Auke Kokbc7f75f2007-09-17 12:30:59 -07002105 s32 ret_val;
2106
2107 if (e1000_check_reset_block(hw))
2108 return 0;
2109
Bruce Allanad680762008-03-28 09:15:03 -07002110 /*
2111 * ICH parts do not have a word in the NVM to determine
Auke Kokbc7f75f2007-09-17 12:30:59 -07002112 * the default flow control setting, so we explicitly
2113 * set it to full.
2114 */
Bruce Allan5c48ef3e22008-11-21 16:57:36 -08002115 if (hw->fc.requested_mode == e1000_fc_default)
2116 hw->fc.requested_mode = e1000_fc_full;
Auke Kokbc7f75f2007-09-17 12:30:59 -07002117
Bruce Allan5c48ef3e22008-11-21 16:57:36 -08002118 /*
2119 * Save off the requested flow control mode for use later. Depending
2120 * on the link partner's capabilities, we may or may not use this mode.
2121 */
2122 hw->fc.current_mode = hw->fc.requested_mode;
Auke Kokbc7f75f2007-09-17 12:30:59 -07002123
Bruce Allan5c48ef3e22008-11-21 16:57:36 -08002124 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2125 hw->fc.current_mode);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002126
2127 /* Continue to configure the copper link. */
2128 ret_val = e1000_setup_copper_link_ich8lan(hw);
2129 if (ret_val)
2130 return ret_val;
2131
Jeff Kirsher318a94d2008-03-28 09:15:16 -07002132 ew32(FCTTV, hw->fc.pause_time);
Auke Kokbc7f75f2007-09-17 12:30:59 -07002133
2134 return e1000e_set_fc_watermarks(hw);
2135}
2136
2137/**
2138 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2139 * @hw: pointer to the HW structure
2140 *
2141 * Configures the kumeran interface to the PHY to wait the appropriate time
2142 * when polling the PHY, then call the generic setup_copper_link to finish
2143 * configuring the copper link.
2144 **/
2145static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2146{
2147 u32 ctrl;
2148 s32 ret_val;
2149 u16 reg_data;
2150
2151 ctrl = er32(CTRL);
2152 ctrl |= E1000_CTRL_SLU;
2153 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2154 ew32(CTRL, ctrl);
2155
Bruce Allanad680762008-03-28 09:15:03 -07002156 /*
2157 * Set the mac to wait the maximum time between each iteration
Auke Kokbc7f75f2007-09-17 12:30:59 -07002158 * and increase the max iterations when polling the phy;
Bruce Allanad680762008-03-28 09:15:03 -07002159 * this fixes erroneous timeouts at 10Mbps.
2160 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07002161 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2162 if (ret_val)
2163 return ret_val;
2164 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2165 if (ret_val)
2166 return ret_val;
2167 reg_data |= 0x3F;
2168 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2169 if (ret_val)
2170 return ret_val;
2171
2172 if (hw->phy.type == e1000_phy_igp_3) {
2173 ret_val = e1000e_copper_link_setup_igp(hw);
2174 if (ret_val)
2175 return ret_val;
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002176 } else if (hw->phy.type == e1000_phy_bm) {
2177 ret_val = e1000e_copper_link_setup_m88(hw);
2178 if (ret_val)
2179 return ret_val;
Auke Kokbc7f75f2007-09-17 12:30:59 -07002180 }
2181
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002182 if (hw->phy.type == e1000_phy_ife) {
2183 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2184 if (ret_val)
2185 return ret_val;
2186
2187 reg_data &= ~IFE_PMC_AUTO_MDIX;
2188
2189 switch (hw->phy.mdix) {
2190 case 1:
2191 reg_data &= ~IFE_PMC_FORCE_MDIX;
2192 break;
2193 case 2:
2194 reg_data |= IFE_PMC_FORCE_MDIX;
2195 break;
2196 case 0:
2197 default:
2198 reg_data |= IFE_PMC_AUTO_MDIX;
2199 break;
2200 }
2201 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2202 if (ret_val)
2203 return ret_val;
2204 }
Auke Kokbc7f75f2007-09-17 12:30:59 -07002205 return e1000e_setup_copper_link(hw);
2206}
2207
2208/**
2209 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2210 * @hw: pointer to the HW structure
2211 * @speed: pointer to store current link speed
2212 * @duplex: pointer to store the current link duplex
2213 *
Bruce Allanad680762008-03-28 09:15:03 -07002214 * Calls the generic get_speed_and_duplex to retrieve the current link
Auke Kokbc7f75f2007-09-17 12:30:59 -07002215 * information and then calls the Kumeran lock loss workaround for links at
2216 * gigabit speeds.
2217 **/
2218static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2219 u16 *duplex)
2220{
2221 s32 ret_val;
2222
2223 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2224 if (ret_val)
2225 return ret_val;
2226
2227 if ((hw->mac.type == e1000_ich8lan) &&
2228 (hw->phy.type == e1000_phy_igp_3) &&
2229 (*speed == SPEED_1000)) {
2230 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2231 }
2232
2233 return ret_val;
2234}
2235
2236/**
2237 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2238 * @hw: pointer to the HW structure
2239 *
2240 * Work-around for 82566 Kumeran PCS lock loss:
2241 * On link status change (i.e. PCI reset, speed change) and link is up and
2242 * speed is gigabit-
2243 * 0) if workaround is optionally disabled do nothing
2244 * 1) wait 1ms for Kumeran link to come up
2245 * 2) check Kumeran Diagnostic register PCS lock loss bit
2246 * 3) if not set the link is locked (all is good), otherwise...
2247 * 4) reset the PHY
2248 * 5) repeat up to 10 times
2249 * Note: this is only called for IGP3 copper when speed is 1gb.
2250 **/
2251static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2252{
2253 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2254 u32 phy_ctrl;
2255 s32 ret_val;
2256 u16 i, data;
2257 bool link;
2258
2259 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2260 return 0;
2261
Bruce Allanad680762008-03-28 09:15:03 -07002262 /*
2263 * Make sure link is up before proceeding. If not just return.
Auke Kokbc7f75f2007-09-17 12:30:59 -07002264 * Attempting this while link is negotiating fouled up link
Bruce Allanad680762008-03-28 09:15:03 -07002265 * stability
2266 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07002267 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2268 if (!link)
2269 return 0;
2270
2271 for (i = 0; i < 10; i++) {
2272 /* read once to clear */
2273 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2274 if (ret_val)
2275 return ret_val;
2276 /* and again to get new status */
2277 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2278 if (ret_val)
2279 return ret_val;
2280
2281 /* check for PCS lock */
2282 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2283 return 0;
2284
2285 /* Issue PHY reset */
2286 e1000_phy_hw_reset(hw);
2287 mdelay(5);
2288 }
2289 /* Disable GigE link negotiation */
2290 phy_ctrl = er32(PHY_CTRL);
2291 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2292 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2293 ew32(PHY_CTRL, phy_ctrl);
2294
Bruce Allanad680762008-03-28 09:15:03 -07002295 /*
2296 * Call gig speed drop workaround on Gig disable before accessing
2297 * any PHY registers
2298 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07002299 e1000e_gig_downshift_workaround_ich8lan(hw);
2300
2301 /* unable to acquire PCS lock */
2302 return -E1000_ERR_PHY;
2303}
2304
2305/**
Bruce Allanad680762008-03-28 09:15:03 -07002306 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
Auke Kokbc7f75f2007-09-17 12:30:59 -07002307 * @hw: pointer to the HW structure
Auke Kok489815c2008-02-21 15:11:07 -08002308 * @state: boolean value used to set the current Kumeran workaround state
Auke Kokbc7f75f2007-09-17 12:30:59 -07002309 *
2310 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2311 * /disabled - FALSE).
2312 **/
2313void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2314 bool state)
2315{
2316 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2317
2318 if (hw->mac.type != e1000_ich8lan) {
2319 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2320 return;
2321 }
2322
2323 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2324}
2325
2326/**
2327 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2328 * @hw: pointer to the HW structure
2329 *
2330 * Workaround for 82566 power-down on D3 entry:
2331 * 1) disable gigabit link
2332 * 2) write VR power-down enable
2333 * 3) read it back
2334 * Continue if successful, else issue LCD reset and repeat
2335 **/
2336void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2337{
2338 u32 reg;
2339 u16 data;
2340 u8 retry = 0;
2341
2342 if (hw->phy.type != e1000_phy_igp_3)
2343 return;
2344
2345 /* Try the workaround twice (if needed) */
2346 do {
2347 /* Disable link */
2348 reg = er32(PHY_CTRL);
2349 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2350 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2351 ew32(PHY_CTRL, reg);
2352
Bruce Allanad680762008-03-28 09:15:03 -07002353 /*
2354 * Call gig speed drop workaround on Gig disable before
2355 * accessing any PHY registers
2356 */
Auke Kokbc7f75f2007-09-17 12:30:59 -07002357 if (hw->mac.type == e1000_ich8lan)
2358 e1000e_gig_downshift_workaround_ich8lan(hw);
2359
2360 /* Write VR power-down enable */
2361 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2362 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2363 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2364
2365 /* Read it back and test */
2366 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2367 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2368 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2369 break;
2370
2371 /* Issue PHY reset and repeat at most one more time */
2372 reg = er32(CTRL);
2373 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2374 retry++;
2375 } while (retry);
2376}
2377
2378/**
2379 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2380 * @hw: pointer to the HW structure
2381 *
2382 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
Auke Kok489815c2008-02-21 15:11:07 -08002383 * LPLU, Gig disable, MDIC PHY reset):
Auke Kokbc7f75f2007-09-17 12:30:59 -07002384 * 1) Set Kumeran Near-end loopback
2385 * 2) Clear Kumeran Near-end loopback
2386 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2387 **/
2388void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2389{
2390 s32 ret_val;
2391 u16 reg_data;
2392
2393 if ((hw->mac.type != e1000_ich8lan) ||
2394 (hw->phy.type != e1000_phy_igp_3))
2395 return;
2396
2397 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2398 &reg_data);
2399 if (ret_val)
2400 return;
2401 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2402 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2403 reg_data);
2404 if (ret_val)
2405 return;
2406 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2407 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2408 reg_data);
2409}
2410
2411/**
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002412 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2413 * @hw: pointer to the HW structure
2414 *
2415 * During S0 to Sx transition, it is possible the link remains at gig
2416 * instead of negotiating to a lower speed. Before going to Sx, set
2417 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2418 * to a lower speed.
2419 *
Bruce Allanf4187b52008-08-26 18:36:50 -07002420 * Should only be called for ICH9 and ICH10 devices.
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002421 **/
2422void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2423{
2424 u32 phy_ctrl;
2425
Bruce Allanf4187b52008-08-26 18:36:50 -07002426 if ((hw->mac.type == e1000_ich10lan) ||
2427 (hw->mac.type == e1000_ich9lan)) {
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002428 phy_ctrl = er32(PHY_CTRL);
2429 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2430 E1000_PHY_CTRL_GBE_DISABLE;
2431 ew32(PHY_CTRL, phy_ctrl);
2432 }
2433
2434 return;
2435}
2436
2437/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07002438 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2439 * @hw: pointer to the HW structure
2440 *
2441 * Return the LED back to the default configuration.
2442 **/
2443static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2444{
2445 if (hw->phy.type == e1000_phy_ife)
2446 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2447
2448 ew32(LEDCTL, hw->mac.ledctl_default);
2449 return 0;
2450}
2451
2452/**
Auke Kok489815c2008-02-21 15:11:07 -08002453 * e1000_led_on_ich8lan - Turn LEDs on
Auke Kokbc7f75f2007-09-17 12:30:59 -07002454 * @hw: pointer to the HW structure
2455 *
Auke Kok489815c2008-02-21 15:11:07 -08002456 * Turn on the LEDs.
Auke Kokbc7f75f2007-09-17 12:30:59 -07002457 **/
2458static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2459{
2460 if (hw->phy.type == e1000_phy_ife)
2461 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2462 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2463
2464 ew32(LEDCTL, hw->mac.ledctl_mode2);
2465 return 0;
2466}
2467
2468/**
Auke Kok489815c2008-02-21 15:11:07 -08002469 * e1000_led_off_ich8lan - Turn LEDs off
Auke Kokbc7f75f2007-09-17 12:30:59 -07002470 * @hw: pointer to the HW structure
2471 *
Auke Kok489815c2008-02-21 15:11:07 -08002472 * Turn off the LEDs.
Auke Kokbc7f75f2007-09-17 12:30:59 -07002473 **/
2474static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2475{
2476 if (hw->phy.type == e1000_phy_ife)
2477 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2478 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2479
2480 ew32(LEDCTL, hw->mac.ledctl_mode1);
2481 return 0;
2482}
2483
2484/**
Bruce Allanf4187b52008-08-26 18:36:50 -07002485 * e1000_get_cfg_done_ich8lan - Read config done bit
2486 * @hw: pointer to the HW structure
2487 *
2488 * Read the management control register for the config done bit for
2489 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2490 * to read the config done bit, so an error is *ONLY* logged and returns
2491 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2492 * would not be able to be reset or change link.
2493 **/
2494static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2495{
2496 u32 bank = 0;
2497
2498 e1000e_get_cfg_done(hw);
2499
2500 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2501 if (hw->mac.type != e1000_ich10lan) {
2502 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2503 (hw->phy.type == e1000_phy_igp_3)) {
2504 e1000e_phy_init_script_igp3(hw);
2505 }
2506 } else {
2507 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2508 /* Maybe we should do a basic PHY config */
2509 hw_dbg(hw, "EEPROM not present\n");
2510 return -E1000_ERR_CONFIG;
2511 }
2512 }
2513
2514 return 0;
2515}
2516
2517/**
Auke Kokbc7f75f2007-09-17 12:30:59 -07002518 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2519 * @hw: pointer to the HW structure
2520 *
2521 * Clears hardware counters specific to the silicon family and calls
2522 * clear_hw_cntrs_generic to clear all general purpose counters.
2523 **/
2524static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2525{
2526 u32 temp;
2527
2528 e1000e_clear_hw_cntrs_base(hw);
2529
2530 temp = er32(ALGNERRC);
2531 temp = er32(RXERRC);
2532 temp = er32(TNCRS);
2533 temp = er32(CEXTERR);
2534 temp = er32(TSCTC);
2535 temp = er32(TSCTFC);
2536
2537 temp = er32(MGTPRC);
2538 temp = er32(MGTPDC);
2539 temp = er32(MGTPTC);
2540
2541 temp = er32(IAC);
2542 temp = er32(ICRXOC);
2543
2544}
2545
2546static struct e1000_mac_operations ich8_mac_ops = {
Bruce Allan4662e822008-08-26 18:37:06 -07002547 .check_mng_mode = e1000_check_mng_mode_ich8lan,
Auke Kokbc7f75f2007-09-17 12:30:59 -07002548 .check_for_link = e1000e_check_for_copper_link,
2549 .cleanup_led = e1000_cleanup_led_ich8lan,
2550 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
2551 .get_bus_info = e1000_get_bus_info_ich8lan,
2552 .get_link_up_info = e1000_get_link_up_info_ich8lan,
2553 .led_on = e1000_led_on_ich8lan,
2554 .led_off = e1000_led_off_ich8lan,
Jeff Kirshere2de3eb2008-03-28 09:15:11 -07002555 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
Auke Kokbc7f75f2007-09-17 12:30:59 -07002556 .reset_hw = e1000_reset_hw_ich8lan,
2557 .init_hw = e1000_init_hw_ich8lan,
2558 .setup_link = e1000_setup_link_ich8lan,
2559 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2560};
2561
2562static struct e1000_phy_operations ich8_phy_ops = {
2563 .acquire_phy = e1000_acquire_swflag_ich8lan,
2564 .check_reset_block = e1000_check_reset_block_ich8lan,
2565 .commit_phy = NULL,
2566 .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan,
Bruce Allanf4187b52008-08-26 18:36:50 -07002567 .get_cfg_done = e1000_get_cfg_done_ich8lan,
Auke Kokbc7f75f2007-09-17 12:30:59 -07002568 .get_cable_length = e1000e_get_cable_length_igp_2,
2569 .get_phy_info = e1000_get_phy_info_ich8lan,
2570 .read_phy_reg = e1000e_read_phy_reg_igp,
2571 .release_phy = e1000_release_swflag_ich8lan,
2572 .reset_phy = e1000_phy_hw_reset_ich8lan,
2573 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
2574 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
2575 .write_phy_reg = e1000e_write_phy_reg_igp,
2576};
2577
2578static struct e1000_nvm_operations ich8_nvm_ops = {
2579 .acquire_nvm = e1000_acquire_swflag_ich8lan,
2580 .read_nvm = e1000_read_nvm_ich8lan,
2581 .release_nvm = e1000_release_swflag_ich8lan,
2582 .update_nvm = e1000_update_nvm_checksum_ich8lan,
2583 .valid_led_default = e1000_valid_led_default_ich8lan,
2584 .validate_nvm = e1000_validate_nvm_checksum_ich8lan,
2585 .write_nvm = e1000_write_nvm_ich8lan,
2586};
2587
2588struct e1000_info e1000_ich8_info = {
2589 .mac = e1000_ich8lan,
2590 .flags = FLAG_HAS_WOL
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002591 | FLAG_IS_ICH
Auke Kokbc7f75f2007-09-17 12:30:59 -07002592 | FLAG_RX_CSUM_ENABLED
2593 | FLAG_HAS_CTRLEXT_ON_LOAD
2594 | FLAG_HAS_AMT
2595 | FLAG_HAS_FLASH
2596 | FLAG_APME_IN_WUC,
2597 .pba = 8,
Jeff Kirsher69e3fd82008-04-02 13:48:18 -07002598 .get_variants = e1000_get_variants_ich8lan,
Auke Kokbc7f75f2007-09-17 12:30:59 -07002599 .mac_ops = &ich8_mac_ops,
2600 .phy_ops = &ich8_phy_ops,
2601 .nvm_ops = &ich8_nvm_ops,
2602};
2603
2604struct e1000_info e1000_ich9_info = {
2605 .mac = e1000_ich9lan,
2606 .flags = FLAG_HAS_JUMBO_FRAMES
Bruce Allan97ac8ca2008-04-29 09:16:05 -07002607 | FLAG_IS_ICH
Auke Kokbc7f75f2007-09-17 12:30:59 -07002608 | FLAG_HAS_WOL
2609 | FLAG_RX_CSUM_ENABLED
2610 | FLAG_HAS_CTRLEXT_ON_LOAD
2611 | FLAG_HAS_AMT
2612 | FLAG_HAS_ERT
2613 | FLAG_HAS_FLASH
2614 | FLAG_APME_IN_WUC,
2615 .pba = 10,
Jeff Kirsher69e3fd82008-04-02 13:48:18 -07002616 .get_variants = e1000_get_variants_ich8lan,
Auke Kokbc7f75f2007-09-17 12:30:59 -07002617 .mac_ops = &ich8_mac_ops,
2618 .phy_ops = &ich8_phy_ops,
2619 .nvm_ops = &ich8_nvm_ops,
2620};
2621
Bruce Allanf4187b52008-08-26 18:36:50 -07002622struct e1000_info e1000_ich10_info = {
2623 .mac = e1000_ich10lan,
2624 .flags = FLAG_HAS_JUMBO_FRAMES
2625 | FLAG_IS_ICH
2626 | FLAG_HAS_WOL
2627 | FLAG_RX_CSUM_ENABLED
2628 | FLAG_HAS_CTRLEXT_ON_LOAD
2629 | FLAG_HAS_AMT
2630 | FLAG_HAS_ERT
2631 | FLAG_HAS_FLASH
2632 | FLAG_APME_IN_WUC,
2633 .pba = 10,
2634 .get_variants = e1000_get_variants_ich8lan,
2635 .mac_ops = &ich8_mac_ops,
2636 .phy_ops = &ich8_phy_ops,
2637 .nvm_ops = &ich8_nvm_ops,
2638};