blob: 6c2269b6bd3c0d74cc079548681ccbf15935f067 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_atiixp.c - ATI PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on
7 *
8 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
9 *
10 * Copyright (C) 2003 ATI Inc. <hyu@ati.com>
11 * Copyright (C) 2004 Bartlomiej Zolnierkiewicz
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/blkdev.h>
20#include <linux/delay.h>
21#include <scsi/scsi_host.h>
22#include <linux/libata.h>
23
24#define DRV_NAME "pata_atiixp"
Alan Coxc9619222006-09-26 17:53:38 +010025#define DRV_VERSION "0.4.3"
Jeff Garzik669a5db2006-08-29 18:12:40 -040026
27enum {
28 ATIIXP_IDE_PIO_TIMING = 0x40,
29 ATIIXP_IDE_MWDMA_TIMING = 0x44,
30 ATIIXP_IDE_PIO_CONTROL = 0x48,
31 ATIIXP_IDE_PIO_MODE = 0x4a,
32 ATIIXP_IDE_UDMA_CONTROL = 0x54,
33 ATIIXP_IDE_UDMA_MODE = 0x56
34};
35
36static int atiixp_pre_reset(struct ata_port *ap)
37{
38 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
39 static struct pci_bits atiixp_enable_bits[] = {
40 { 0x48, 1, 0x01, 0x00 },
41 { 0x48, 1, 0x08, 0x00 }
42 };
43
Alan Coxc9619222006-09-26 17:53:38 +010044 if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
45 return -ENOENT;
46
Jeff Garzik669a5db2006-08-29 18:12:40 -040047 ap->cbl = ATA_CBL_PATA80;
48 return ata_std_prereset(ap);
49}
50
51static void atiixp_error_handler(struct ata_port *ap)
52{
53 ata_bmdma_drive_eh(ap, atiixp_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
54}
55
56/**
57 * atiixp_set_pio_timing - set initial PIO mode data
58 * @ap: ATA interface
59 * @adev: ATA device
60 *
61 * Called by both the pio and dma setup functions to set the controller
62 * timings for PIO transfers. We must load both the mode number and
63 * timing values into the controller.
64 */
65
66static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
67{
68 static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
69
70 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
71 int dn = 2 * ap->port_no + adev->devno;
72
73 /* Check this is correct - the order is odd in both drivers */
74 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
75 u16 pio_mode_data, pio_timing_data;
76
77 pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
78 pio_mode_data &= ~(0x7 << (4 * dn));
79 pio_mode_data |= pio << (4 * dn);
80 pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
81
82 pci_read_config_word(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
83 pio_mode_data &= ~(0xFF << timing_shift);
84 pio_mode_data |= (pio_timings[pio] << timing_shift);
85 pci_write_config_word(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
86}
87
88/**
89 * atiixp_set_piomode - set initial PIO mode data
90 * @ap: ATA interface
91 * @adev: ATA device
92 *
93 * Called to do the PIO mode setup. We use a shared helper for this
94 * as the DMA setup must also adjust the PIO timing information.
95 */
96
97static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
98{
99 atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
100}
101
102/**
103 * atiixp_set_dmamode - set initial DMA mode data
104 * @ap: ATA interface
105 * @adev: ATA device
106 *
107 * Called to do the DMA mode setup. We use timing tables for most
108 * modes but must tune an appropriate PIO mode to match.
109 */
110
111static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
112{
113 static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
114
115 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
116 int dma = adev->dma_mode;
117 int dn = 2 * ap->port_no + adev->devno;
118 int wanted_pio;
119
120 if (adev->dma_mode >= XFER_UDMA_0) {
121 u16 udma_mode_data;
122
123 dma -= XFER_UDMA_0;
124
125 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
126 udma_mode_data &= ~(0x7 << (4 * dn));
127 udma_mode_data |= dma << (4 * dn);
128 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
129 } else {
130 u16 mwdma_timing_data;
131 /* Check this is correct - the order is odd in both drivers */
132 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
133
134 dma -= XFER_MW_DMA_0;
135
136 pci_read_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, &mwdma_timing_data);
137 mwdma_timing_data &= ~(0xFF << timing_shift);
138 mwdma_timing_data |= (mwdma_timings[dma] << timing_shift);
139 pci_write_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, mwdma_timing_data);
140 }
141 /*
142 * We must now look at the PIO mode situation. We may need to
143 * adjust the PIO mode to keep the timings acceptable
144 */
145 if (adev->dma_mode >= XFER_MW_DMA_2)
146 wanted_pio = 4;
147 else if (adev->dma_mode == XFER_MW_DMA_1)
148 wanted_pio = 3;
149 else if (adev->dma_mode == XFER_MW_DMA_0)
150 wanted_pio = 0;
151 else BUG();
152
153 if (adev->pio_mode != wanted_pio)
154 atiixp_set_pio_timing(ap, adev, wanted_pio);
155}
156
157/**
158 * atiixp_bmdma_start - DMA start callback
159 * @qc: Command in progress
160 *
161 * When DMA begins we need to ensure that the UDMA control
162 * register for the channel is correctly set.
163 */
164
165static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
166{
167 struct ata_port *ap = qc->ap;
168 struct ata_device *adev = qc->dev;
169
170 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
171 int dn = (2 * ap->port_no) + adev->devno;
172 u16 tmp16;
173
174 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
175 if (adev->dma_mode >= XFER_UDMA_0)
176 tmp16 |= (1 << dn);
177 else
178 tmp16 &= ~(1 << dn);
179 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
180 ata_bmdma_start(qc);
181}
182
183/**
184 * atiixp_dma_stop - DMA stop callback
185 * @qc: Command in progress
186 *
187 * DMA has completed. Clear the UDMA flag as the next operations will
188 * be PIO ones not UDMA data transfer.
189 */
190
191static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
192{
193 struct ata_port *ap = qc->ap;
194 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
195 int dn = (2 * ap->port_no) + qc->dev->devno;
196 u16 tmp16;
197
198 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
199 tmp16 &= ~(1 << dn);
200 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
201 ata_bmdma_stop(qc);
202}
203
204static struct scsi_host_template atiixp_sht = {
205 .module = THIS_MODULE,
206 .name = DRV_NAME,
207 .ioctl = ata_scsi_ioctl,
208 .queuecommand = ata_scsi_queuecmd,
209 .can_queue = ATA_DEF_QUEUE,
210 .this_id = ATA_SHT_THIS_ID,
211 .sg_tablesize = LIBATA_MAX_PRD,
212 .max_sectors = ATA_MAX_SECTORS,
213 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
214 .emulated = ATA_SHT_EMULATED,
215 .use_clustering = ATA_SHT_USE_CLUSTERING,
216 .proc_name = DRV_NAME,
217 .dma_boundary = ATA_DMA_BOUNDARY,
218 .slave_configure = ata_scsi_slave_config,
219 .bios_param = ata_std_bios_param,
220};
221
222static struct ata_port_operations atiixp_port_ops = {
223 .port_disable = ata_port_disable,
224 .set_piomode = atiixp_set_piomode,
225 .set_dmamode = atiixp_set_dmamode,
226 .mode_filter = ata_pci_default_filter,
227 .tf_load = ata_tf_load,
228 .tf_read = ata_tf_read,
229 .check_status = ata_check_status,
230 .exec_command = ata_exec_command,
231 .dev_select = ata_std_dev_select,
232
233 .freeze = ata_bmdma_freeze,
234 .thaw = ata_bmdma_thaw,
235 .error_handler = atiixp_error_handler,
236 .post_internal_cmd = ata_bmdma_post_internal_cmd,
237
238 .bmdma_setup = ata_bmdma_setup,
239 .bmdma_start = atiixp_bmdma_start,
240 .bmdma_stop = atiixp_bmdma_stop,
241 .bmdma_status = ata_bmdma_status,
242
243 .qc_prep = ata_qc_prep,
244 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400245
Jeff Garzik669a5db2006-08-29 18:12:40 -0400246 .data_xfer = ata_pio_data_xfer,
247
248 .irq_handler = ata_interrupt,
249 .irq_clear = ata_bmdma_irq_clear,
250
251 .port_start = ata_port_start,
252 .port_stop = ata_port_stop,
253 .host_stop = ata_host_stop
254};
255
256static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
257{
258 static struct ata_port_info info = {
259 .sht = &atiixp_sht,
260 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
261 .pio_mask = 0x1f,
262 .mwdma_mask = 0x06, /* No MWDMA0 support */
263 .udma_mask = 0x3F,
264 .port_ops = &atiixp_port_ops
265 };
266 static struct ata_port_info *port_info[2] = { &info, &info };
267 return ata_pci_init_one(dev, port_info, 2);
268}
269
270static struct pci_device_id atiixp[] = {
271 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
272 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
273 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
274 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
275 { 0, },
276};
277
278static struct pci_driver atiixp_pci_driver = {
279 .name = DRV_NAME,
280 .id_table = atiixp,
281 .probe = atiixp_init_one,
282 .remove = ata_pci_remove_one
283};
284
285static int __init atiixp_init(void)
286{
287 return pci_register_driver(&atiixp_pci_driver);
288}
289
290
291static void __exit atiixp_exit(void)
292{
293 pci_unregister_driver(&atiixp_pci_driver);
294}
295
296
297MODULE_AUTHOR("Alan Cox");
298MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
299MODULE_LICENSE("GPL");
300MODULE_DEVICE_TABLE(pci, atiixp);
301MODULE_VERSION(DRV_VERSION);
302
303module_init(atiixp_init);
304module_exit(atiixp_exit);