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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Driver for Cirrus Logic CS4281 based PCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <sound/driver.h>
23#include <asm/io.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/gameport.h>
30#include <linux/moduleparam.h>
31#include <sound/core.h>
32#include <sound/control.h>
33#include <sound/pcm.h>
34#include <sound/rawmidi.h>
35#include <sound/ac97_codec.h>
36#include <sound/opl3.h>
37#include <sound/initval.h>
38
39
40MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
41MODULE_DESCRIPTION("Cirrus Logic CS4281");
42MODULE_LICENSE("GPL");
43MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
44
45static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
46static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
47static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
48static int dual_codec[SNDRV_CARDS]; /* dual codec */
49
50module_param_array(index, int, NULL, 0444);
51MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
52module_param_array(id, charp, NULL, 0444);
53MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
54module_param_array(enable, bool, NULL, 0444);
55MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
56module_param_array(dual_codec, bool, NULL, 0444);
57MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
58
59/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070060 * Direct registers
61 */
62
63#define CS4281_BA0_SIZE 0x1000
64#define CS4281_BA1_SIZE 0x10000
65
66/*
67 * BA0 registers
68 */
69#define BA0_HISR 0x0000 /* Host Interrupt Status Register */
70#define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
71#define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
72#define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
73#define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
74#define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
75#define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
76#define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
77#define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
78#define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
79#define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
80#define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
81#define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
82
83#define BA0_HICR 0x0008 /* Host Interrupt Control Register */
84#define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
85#define BA0_HICR_IEV (1<<0) /* INTENA Value */
86#define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
87
88#define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
89 /* Use same contants as for BA0_HISR */
90
91#define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
92
93#define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
94#define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
95#define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
96#define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
97
98#define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
99#define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
100#define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
101#define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
102#define BA0_HDSR_DRUN (1<<15) /* DMA Running */
103#define BA0_HDSR_RQ (1<<7) /* Pending Request */
104
105#define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
106#define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
107#define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
108#define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
109#define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
110#define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
111#define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
112#define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
113#define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
114#define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
115#define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
116#define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
117#define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
118#define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
119#define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
120#define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
121#define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
122#define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
123#define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
124#define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
125#define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
126#define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
127#define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
128#define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
129
130#define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
131#define BA0_DMR_POLL (1<<28) /* Enable poll mode */
132#define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
133#define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
134#define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
135#define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
136#define BA0_DMR_USIGN (1<<19) /* Unsigned */
137#define BA0_DMR_BEND (1<<18) /* Big Endian */
138#define BA0_DMR_MONO (1<<17) /* Mono */
139#define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
140#define BA0_DMR_TYPE_DEMAND (0<<6)
141#define BA0_DMR_TYPE_SINGLE (1<<6)
142#define BA0_DMR_TYPE_BLOCK (2<<6)
143#define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
144#define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
145#define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
146#define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
147#define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
148#define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
149
150#define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
151#define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
152#define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
153
154#define BA0_FCR0 0x0180 /* FIFO Control 0 */
155#define BA0_FCR1 0x0184 /* FIFO Control 1 */
156#define BA0_FCR2 0x0188 /* FIFO Control 2 */
157#define BA0_FCR3 0x018c /* FIFO Control 3 */
158
159#define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
160#define BA0_FCR_DACZ (1<<30) /* DAC Zero */
161#define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
162#define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
163#define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
164#define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
165#define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
166
167#define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
168#define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
169#define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
170#define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
171
172#define BA0_FCHS 0x020c /* FIFO Channel Status */
173#define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
174#define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
175#define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
176#define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
177#define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
178#define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
179#define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
180#define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
181
182#define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
183#define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
184#define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
185#define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
186
187#define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
188#define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
189#define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
190#define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
191#define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
192#define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
193#define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
194#define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
195
196#define BA0_PMCS 0x0344 /* Power Management Control/Status */
197#define BA0_CWPR 0x03e0 /* Configuration Write Protect */
Arnaud Patarda488e032005-05-07 18:51:51 +0200198
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199#define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
Arnaud Patarda488e032005-05-07 18:51:51 +0200200#define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
201
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202#define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
203
204#define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
205#define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
206#define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
207#define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
208#define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
209#define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
210#define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
211#define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
212#define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
213#define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
214
215#define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
216#define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
217#define BA0_IISR 0x03f4 /* ISA Interrupt Select */
218#define BA0_TMS 0x03f8 /* Test Register */
219#define BA0_SSVID 0x03fc /* Subsystem ID register */
220
221#define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
222#define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
223#define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
224#define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
225#define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
226#define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
227#define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
228
229#define BA0_FRR 0x0410 /* Feature Reporting Register */
230#define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
231
232#define BA0_SERMC 0x0420 /* Serial Port Master Control */
233#define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
234#define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
235#define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
236#define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
237#define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
238#define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
239#define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
240#define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
241#define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
242#define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
243#define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
244#define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
245
246#define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
247#define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
248#define BA0_SERC1_AC97 (1<<1)
249#define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
250
251#define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
252#define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
253#define BA0_SERC2_AC97 (1<<1)
254#define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
255
256#define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
257
258#define BA0_ACCTL 0x0460 /* AC'97 Control */
259#define BA0_ACCTL_TC (1<<6) /* Target Codec */
260#define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
261#define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
262#define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
263#define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
264
265#define BA0_ACSTS 0x0464 /* AC'97 Status */
266#define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
267#define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
268
269#define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
270#define BA0_ACOSV_SLV(x) (1<<((x)-3))
271
272#define BA0_ACCAD 0x046c /* AC'97 Command Address */
273#define BA0_ACCDA 0x0470 /* AC'97 Command Data */
274
275#define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
276#define BA0_ACISV_SLV(x) (1<<((x)-3))
277
278#define BA0_ACSAD 0x0478 /* AC'97 Status Address */
279#define BA0_ACSDA 0x047c /* AC'97 Status Data */
280#define BA0_JSPT 0x0480 /* Joystick poll/trigger */
281#define BA0_JSCTL 0x0484 /* Joystick control */
282#define BA0_JSC1 0x0488 /* Joystick control */
283#define BA0_JSC2 0x048c /* Joystick control */
284#define BA0_JSIO 0x04a0
285
286#define BA0_MIDCR 0x0490 /* MIDI Control */
287#define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
288#define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
289#define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
290#define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
291#define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
292#define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
293
294#define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
295
296#define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
297#define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
298#define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
299#define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
300#define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
301
302#define BA0_MIDWP 0x0498 /* MIDI Write */
303#define BA0_MIDRP 0x049c /* MIDI Read (ro) */
304
305#define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
306#define BA0_AODSD1_NDS(x) (1<<((x)-3))
307
308#define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
309#define BA0_AODSD2_NDS(x) (1<<((x)-3))
310
311#define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
312#define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
313#define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
314#define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
315#define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
316#define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
317#define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
318#define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
319#define BA0_FMDP 0x0734 /* FM Data Port */
320#define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
321#define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
322
323#define BA0_SSPM 0x0740 /* Sound System Power Management */
324#define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
325#define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
326#define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
327#define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
328#define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
329#define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
330
331#define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
332#define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
333
334#define BA0_SSCR 0x074c /* Sound System Control Register */
335#define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
336#define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
337#define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
338#define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
339#define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
340#define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
341#define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
342#define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
343#define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
344
345#define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
346#define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
347#define BA0_SRCSA 0x075c /* SRC Slot Assignments */
348#define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
349#define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
350#define BA0_PASR 0x0768 /* playback sample rate */
351#define BA0_CASR 0x076C /* capture sample rate */
352
353/* Source Slot Numbers - Playback */
354#define SRCSLOT_LEFT_PCM_PLAYBACK 0
355#define SRCSLOT_RIGHT_PCM_PLAYBACK 1
356#define SRCSLOT_PHONE_LINE_1_DAC 2
357#define SRCSLOT_CENTER_PCM_PLAYBACK 3
358#define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
359#define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
360#define SRCSLOT_LFE_PCM_PLAYBACK 6
361#define SRCSLOT_PHONE_LINE_2_DAC 7
362#define SRCSLOT_HEADSET_DAC 8
363#define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
364#define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
365
366/* Source Slot Numbers - Capture */
367#define SRCSLOT_LEFT_PCM_RECORD 10
368#define SRCSLOT_RIGHT_PCM_RECORD 11
369#define SRCSLOT_PHONE_LINE_1_ADC 12
370#define SRCSLOT_MIC_ADC 13
371#define SRCSLOT_PHONE_LINE_2_ADC 17
372#define SRCSLOT_HEADSET_ADC 18
373#define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
374#define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
375#define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
376#define SRCSLOT_SECONDARY_MIC_ADC 23
377#define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
378#define SRCSLOT_SECONDARY_HEADSET_ADC 28
379
380/* Source Slot Numbers - Others */
381#define SRCSLOT_POWER_DOWN 31
382
383/* MIDI modes */
384#define CS4281_MODE_OUTPUT (1<<0)
385#define CS4281_MODE_INPUT (1<<1)
386
387/* joystick bits */
388/* Bits for JSPT */
389#define JSPT_CAX 0x00000001
390#define JSPT_CAY 0x00000002
391#define JSPT_CBX 0x00000004
392#define JSPT_CBY 0x00000008
393#define JSPT_BA1 0x00000010
394#define JSPT_BA2 0x00000020
395#define JSPT_BB1 0x00000040
396#define JSPT_BB2 0x00000080
397
398/* Bits for JSCTL */
399#define JSCTL_SP_MASK 0x00000003
400#define JSCTL_SP_SLOW 0x00000000
401#define JSCTL_SP_MEDIUM_SLOW 0x00000001
402#define JSCTL_SP_MEDIUM_FAST 0x00000002
403#define JSCTL_SP_FAST 0x00000003
404#define JSCTL_ARE 0x00000004
405
406/* Data register pairs masks */
407#define JSC1_Y1V_MASK 0x0000FFFF
408#define JSC1_X1V_MASK 0xFFFF0000
409#define JSC1_Y1V_SHIFT 0
410#define JSC1_X1V_SHIFT 16
411#define JSC2_Y2V_MASK 0x0000FFFF
412#define JSC2_X2V_MASK 0xFFFF0000
413#define JSC2_Y2V_SHIFT 0
414#define JSC2_X2V_SHIFT 16
415
416/* JS GPIO */
417#define JSIO_DAX 0x00000001
418#define JSIO_DAY 0x00000002
419#define JSIO_DBX 0x00000004
420#define JSIO_DBY 0x00000008
421#define JSIO_AXOE 0x00000010
422#define JSIO_AYOE 0x00000020
423#define JSIO_BXOE 0x00000040
424#define JSIO_BYOE 0x00000080
425
426/*
427 *
428 */
429
430typedef struct snd_cs4281 cs4281_t;
431typedef struct snd_cs4281_dma cs4281_dma_t;
432
433struct snd_cs4281_dma {
434 snd_pcm_substream_t *substream;
435 unsigned int regDBA; /* offset to DBA register */
436 unsigned int regDCA; /* offset to DCA register */
437 unsigned int regDBC; /* offset to DBC register */
438 unsigned int regDCC; /* offset to DCC register */
439 unsigned int regDMR; /* offset to DMR register */
440 unsigned int regDCR; /* offset to DCR register */
441 unsigned int regHDSR; /* offset to HDSR register */
442 unsigned int regFCR; /* offset to FCR register */
443 unsigned int regFSIC; /* offset to FSIC register */
444 unsigned int valDMR; /* DMA mode */
445 unsigned int valDCR; /* DMA command */
446 unsigned int valFCR; /* FIFO control */
447 unsigned int fifo_offset; /* FIFO offset within BA1 */
448 unsigned char left_slot; /* FIFO left slot */
449 unsigned char right_slot; /* FIFO right slot */
450 int frag; /* period number */
451};
452
453#define SUSPEND_REGISTERS 20
454
455struct snd_cs4281 {
456 int irq;
457
458 void __iomem *ba0; /* virtual (accessible) address */
459 void __iomem *ba1; /* virtual (accessible) address */
460 unsigned long ba0_addr;
461 unsigned long ba1_addr;
462
463 int dual_codec;
464
465 ac97_bus_t *ac97_bus;
466 ac97_t *ac97;
467 ac97_t *ac97_secondary;
468
469 struct pci_dev *pci;
470 snd_card_t *card;
471 snd_pcm_t *pcm;
472 snd_rawmidi_t *rmidi;
473 snd_rawmidi_substream_t *midi_input;
474 snd_rawmidi_substream_t *midi_output;
475
476 cs4281_dma_t dma[4];
477
478 unsigned char src_left_play_slot;
479 unsigned char src_right_play_slot;
480 unsigned char src_left_rec_slot;
481 unsigned char src_right_rec_slot;
482
483 unsigned int spurious_dhtc_irq;
484 unsigned int spurious_dtc_irq;
485
486 spinlock_t reg_lock;
487 unsigned int midcr;
488 unsigned int uartm;
489
490 struct gameport *gameport;
491
492#ifdef CONFIG_PM
493 u32 suspend_regs[SUSPEND_REGISTERS];
494#endif
495
496};
497
498static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
499
500static struct pci_device_id snd_cs4281_ids[] = {
501 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
502 { 0, }
503};
504
505MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
506
507/*
508 * constants
509 */
510
511#define CS4281_FIFO_SIZE 32
512
513/*
514 * common I/O routines
515 */
516
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
518{
519 writel(val, chip->ba0 + offset);
520}
521
522static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset)
523{
524 return readl(chip->ba0 + offset);
525}
526
527static void snd_cs4281_ac97_write(ac97_t *ac97,
528 unsigned short reg, unsigned short val)
529{
530 /*
531 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
532 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
533 * 3. Write ACCTL = Control Register = 460h for initiating the write
534 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
535 * 5. if DCV not cleared, break and return error
536 */
537 cs4281_t *chip = ac97->private_data;
538 int count;
539
540 /*
541 * Setup the AC97 control registers on the CS461x to send the
542 * appropriate command to the AC97 to perform the read.
543 * ACCAD = Command Address Register = 46Ch
544 * ACCDA = Command Data Register = 470h
545 * ACCTL = Control Register = 460h
546 * set DCV - will clear when process completed
547 * reset CRW - Write command
548 * set VFRM - valid frame enabled
549 * set ESYN - ASYNC generation enabled
550 * set RSTN - ARST# inactive, AC97 codec not reset
551 */
552 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
553 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
554 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
555 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
556 for (count = 0; count < 2000; count++) {
557 /*
558 * First, we want to wait for a short time.
559 */
560 udelay(10);
561 /*
562 * Now, check to see if the write has completed.
563 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
564 */
565 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
566 return;
567 }
568 }
569 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
570}
571
572static unsigned short snd_cs4281_ac97_read(ac97_t *ac97,
573 unsigned short reg)
574{
575 cs4281_t *chip = ac97->private_data;
576 int count;
577 unsigned short result;
578 // FIXME: volatile is necessary in the following due to a bug of
579 // some gcc versions
580 volatile int ac97_num = ((volatile ac97_t *)ac97)->num;
581
582 /*
583 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
584 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
585 * 3. Write ACCTL = Control Register = 460h for initiating the write
586 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
587 * 5. if DCV not cleared, break and return error
588 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
589 */
590
591 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
592
593 /*
594 * Setup the AC97 control registers on the CS461x to send the
595 * appropriate command to the AC97 to perform the read.
596 * ACCAD = Command Address Register = 46Ch
597 * ACCDA = Command Data Register = 470h
598 * ACCTL = Control Register = 460h
599 * set DCV - will clear when process completed
600 * set CRW - Read command
601 * set VFRM - valid frame enabled
602 * set ESYN - ASYNC generation enabled
603 * set RSTN - ARST# inactive, AC97 codec not reset
604 */
605
606 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
607 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
608 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
609 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
610 (ac97_num ? BA0_ACCTL_TC : 0));
611
612
613 /*
614 * Wait for the read to occur.
615 */
616 for (count = 0; count < 500; count++) {
617 /*
618 * First, we want to wait for a short time.
619 */
620 udelay(10);
621 /*
622 * Now, check to see if the read has completed.
623 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
624 */
625 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
626 goto __ok1;
627 }
628
629 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
630 result = 0xffff;
631 goto __end;
632
633 __ok1:
634 /*
635 * Wait for the valid status bit to go active.
636 */
637 for (count = 0; count < 100; count++) {
638 /*
639 * Read the AC97 status register.
640 * ACSTS = Status Register = 464h
641 * VSTS - Valid Status
642 */
643 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
644 goto __ok2;
645 udelay(10);
646 }
647
648 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
649 result = 0xffff;
650 goto __end;
651
652 __ok2:
653 /*
654 * Read the data returned from the AC97 register.
655 * ACSDA = Status Data Register = 474h
656 */
657 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
658
659 __end:
660 return result;
661}
662
663/*
664 * PCM part
665 */
666
667static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd)
668{
669 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
670 cs4281_t *chip = snd_pcm_substream_chip(substream);
671
672 spin_lock(&chip->reg_lock);
673 switch (cmd) {
674 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
675 dma->valDCR |= BA0_DCR_MSK;
676 dma->valFCR |= BA0_FCR_FEN;
677 break;
678 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
679 dma->valDCR &= ~BA0_DCR_MSK;
680 dma->valFCR &= ~BA0_FCR_FEN;
681 break;
682 case SNDRV_PCM_TRIGGER_START:
683 case SNDRV_PCM_TRIGGER_RESUME:
684 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
685 dma->valDMR |= BA0_DMR_DMA;
686 dma->valDCR &= ~BA0_DCR_MSK;
687 dma->valFCR |= BA0_FCR_FEN;
688 break;
689 case SNDRV_PCM_TRIGGER_STOP:
690 case SNDRV_PCM_TRIGGER_SUSPEND:
691 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
692 dma->valDCR |= BA0_DCR_MSK;
693 dma->valFCR &= ~BA0_FCR_FEN;
694 /* Leave wave playback FIFO enabled for FM */
695 if (dma->regFCR != BA0_FCR0)
696 dma->valFCR &= ~BA0_FCR_FEN;
697 break;
698 default:
699 spin_unlock(&chip->reg_lock);
700 return -EINVAL;
701 }
702 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
703 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
704 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
705 spin_unlock(&chip->reg_lock);
706 return 0;
707}
708
709static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
710{
711 unsigned int val = ~0;
712
713 if (real_rate)
714 *real_rate = rate;
715 /* special "hardcoded" rates */
716 switch (rate) {
717 case 8000: return 5;
718 case 11025: return 4;
719 case 16000: return 3;
720 case 22050: return 2;
721 case 44100: return 1;
722 case 48000: return 0;
723 default:
724 goto __variable;
725 }
726 __variable:
727 val = 1536000 / rate;
728 if (real_rate)
729 *real_rate = 1536000 / val;
730 return val;
731}
732
733static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src)
734{
735 int rec_mono;
736
737 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
738 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
739 if (runtime->channels == 1)
740 dma->valDMR |= BA0_DMR_MONO;
741 if (snd_pcm_format_unsigned(runtime->format) > 0)
742 dma->valDMR |= BA0_DMR_USIGN;
743 if (snd_pcm_format_big_endian(runtime->format) > 0)
744 dma->valDMR |= BA0_DMR_BEND;
745 switch (snd_pcm_format_width(runtime->format)) {
746 case 8: dma->valDMR |= BA0_DMR_SIZE8;
747 if (runtime->channels == 1)
748 dma->valDMR |= BA0_DMR_SWAPC;
749 break;
750 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
751 }
752 dma->frag = 0; /* for workaround */
753 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
754 if (runtime->buffer_size != runtime->period_size)
755 dma->valDCR |= BA0_DCR_HTCIE;
756 /* Initialize DMA */
757 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
758 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
759 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
760 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
761 (chip->src_right_play_slot << 8) |
762 (chip->src_left_rec_slot << 16) |
763 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
764 if (!src)
765 goto __skip_src;
766 if (!capture) {
767 if (dma->left_slot == chip->src_left_play_slot) {
768 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
769 snd_assert(dma->right_slot == chip->src_right_play_slot, );
770 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
771 }
772 } else {
773 if (dma->left_slot == chip->src_left_rec_slot) {
774 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
775 snd_assert(dma->right_slot == chip->src_right_rec_slot, );
776 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
777 }
778 }
779 __skip_src:
780 /* Deactivate wave playback FIFO before changing slot assignments */
781 if (dma->regFCR == BA0_FCR0)
782 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
783 /* Initialize FIFO */
784 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
785 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
786 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
787 BA0_FCR_OF(dma->fifo_offset);
788 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
789 /* Activate FIFO again for FM playback */
790 if (dma->regFCR == BA0_FCR0)
791 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
792 /* Clear FIFO Status and Interrupt Control Register */
793 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
794}
795
796static int snd_cs4281_hw_params(snd_pcm_substream_t * substream,
797 snd_pcm_hw_params_t * hw_params)
798{
799 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
800}
801
802static int snd_cs4281_hw_free(snd_pcm_substream_t * substream)
803{
804 return snd_pcm_lib_free_pages(substream);
805}
806
807static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream)
808{
809 snd_pcm_runtime_t *runtime = substream->runtime;
810 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
811 cs4281_t *chip = snd_pcm_substream_chip(substream);
812
813 spin_lock_irq(&chip->reg_lock);
814 snd_cs4281_mode(chip, dma, runtime, 0, 1);
815 spin_unlock_irq(&chip->reg_lock);
816 return 0;
817}
818
819static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream)
820{
821 snd_pcm_runtime_t *runtime = substream->runtime;
822 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
823 cs4281_t *chip = snd_pcm_substream_chip(substream);
824
825 spin_lock_irq(&chip->reg_lock);
826 snd_cs4281_mode(chip, dma, runtime, 1, 1);
827 spin_unlock_irq(&chip->reg_lock);
828 return 0;
829}
830
831static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream)
832{
833 snd_pcm_runtime_t *runtime = substream->runtime;
834 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data;
835 cs4281_t *chip = snd_pcm_substream_chip(substream);
836
837 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies);
838 return runtime->buffer_size -
839 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
840}
841
842static snd_pcm_hardware_t snd_cs4281_playback =
843{
844 .info = (SNDRV_PCM_INFO_MMAP |
845 SNDRV_PCM_INFO_INTERLEAVED |
846 SNDRV_PCM_INFO_MMAP_VALID |
847 SNDRV_PCM_INFO_PAUSE |
848 SNDRV_PCM_INFO_RESUME |
849 SNDRV_PCM_INFO_SYNC_START),
850 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
851 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
852 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
853 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
854 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
855 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
856 .rate_min = 4000,
857 .rate_max = 48000,
858 .channels_min = 1,
859 .channels_max = 2,
860 .buffer_bytes_max = (512*1024),
861 .period_bytes_min = 64,
862 .period_bytes_max = (512*1024),
863 .periods_min = 1,
864 .periods_max = 2,
865 .fifo_size = CS4281_FIFO_SIZE,
866};
867
868static snd_pcm_hardware_t snd_cs4281_capture =
869{
870 .info = (SNDRV_PCM_INFO_MMAP |
871 SNDRV_PCM_INFO_INTERLEAVED |
872 SNDRV_PCM_INFO_MMAP_VALID |
873 SNDRV_PCM_INFO_PAUSE |
874 SNDRV_PCM_INFO_RESUME |
875 SNDRV_PCM_INFO_SYNC_START),
876 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
877 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
878 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
879 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
880 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
881 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
882 .rate_min = 4000,
883 .rate_max = 48000,
884 .channels_min = 1,
885 .channels_max = 2,
886 .buffer_bytes_max = (512*1024),
887 .period_bytes_min = 64,
888 .period_bytes_max = (512*1024),
889 .periods_min = 1,
890 .periods_max = 2,
891 .fifo_size = CS4281_FIFO_SIZE,
892};
893
894static int snd_cs4281_playback_open(snd_pcm_substream_t * substream)
895{
896 cs4281_t *chip = snd_pcm_substream_chip(substream);
897 snd_pcm_runtime_t *runtime = substream->runtime;
898 cs4281_dma_t *dma;
899
900 dma = &chip->dma[0];
901 dma->substream = substream;
902 dma->left_slot = 0;
903 dma->right_slot = 1;
904 runtime->private_data = dma;
905 runtime->hw = snd_cs4281_playback;
906 snd_pcm_set_sync(substream);
907 /* should be detected from the AC'97 layer, but it seems
908 that although CS4297A rev B reports 18-bit ADC resolution,
909 samples are 20-bit */
910 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
911 return 0;
912}
913
914static int snd_cs4281_capture_open(snd_pcm_substream_t * substream)
915{
916 cs4281_t *chip = snd_pcm_substream_chip(substream);
917 snd_pcm_runtime_t *runtime = substream->runtime;
918 cs4281_dma_t *dma;
919
920 dma = &chip->dma[1];
921 dma->substream = substream;
922 dma->left_slot = 10;
923 dma->right_slot = 11;
924 runtime->private_data = dma;
925 runtime->hw = snd_cs4281_capture;
926 snd_pcm_set_sync(substream);
927 /* should be detected from the AC'97 layer, but it seems
928 that although CS4297A rev B reports 18-bit ADC resolution,
929 samples are 20-bit */
930 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
931 return 0;
932}
933
934static int snd_cs4281_playback_close(snd_pcm_substream_t * substream)
935{
936 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
937
938 dma->substream = NULL;
939 return 0;
940}
941
942static int snd_cs4281_capture_close(snd_pcm_substream_t * substream)
943{
944 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data;
945
946 dma->substream = NULL;
947 return 0;
948}
949
950static snd_pcm_ops_t snd_cs4281_playback_ops = {
951 .open = snd_cs4281_playback_open,
952 .close = snd_cs4281_playback_close,
953 .ioctl = snd_pcm_lib_ioctl,
954 .hw_params = snd_cs4281_hw_params,
955 .hw_free = snd_cs4281_hw_free,
956 .prepare = snd_cs4281_playback_prepare,
957 .trigger = snd_cs4281_trigger,
958 .pointer = snd_cs4281_pointer,
959};
960
961static snd_pcm_ops_t snd_cs4281_capture_ops = {
962 .open = snd_cs4281_capture_open,
963 .close = snd_cs4281_capture_close,
964 .ioctl = snd_pcm_lib_ioctl,
965 .hw_params = snd_cs4281_hw_params,
966 .hw_free = snd_cs4281_hw_free,
967 .prepare = snd_cs4281_capture_prepare,
968 .trigger = snd_cs4281_trigger,
969 .pointer = snd_cs4281_pointer,
970};
971
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm)
973{
974 snd_pcm_t *pcm;
975 int err;
976
977 if (rpcm)
978 *rpcm = NULL;
979 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
980 if (err < 0)
981 return err;
982
983 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
984 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
985
986 pcm->private_data = chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987 pcm->info_flags = 0;
988 strcpy(pcm->name, "CS4281");
989 chip->pcm = pcm;
990
991 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
992 snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
993
994 if (rpcm)
995 *rpcm = pcm;
996 return 0;
997}
998
999/*
1000 * Mixer section
1001 */
1002
1003#define CS_VOL_MASK 0x1f
1004
1005static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1006{
1007 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1008 uinfo->count = 2;
1009 uinfo->value.integer.min = 0;
1010 uinfo->value.integer.max = CS_VOL_MASK;
1011 return 0;
1012}
1013
1014static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1015{
1016 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1017 int regL = (kcontrol->private_value >> 16) & 0xffff;
1018 int regR = kcontrol->private_value & 0xffff;
1019 int volL, volR;
1020
1021 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1022 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1023
1024 ucontrol->value.integer.value[0] = volL;
1025 ucontrol->value.integer.value[1] = volR;
1026 return 0;
1027}
1028
1029static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1030{
1031 cs4281_t *chip = snd_kcontrol_chip(kcontrol);
1032 int change = 0;
1033 int regL = (kcontrol->private_value >> 16) & 0xffff;
1034 int regR = kcontrol->private_value & 0xffff;
1035 int volL, volR;
1036
1037 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1038 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1039
1040 if (ucontrol->value.integer.value[0] != volL) {
1041 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1042 snd_cs4281_pokeBA0(chip, regL, volL);
1043 change = 1;
1044 }
1045 if (ucontrol->value.integer.value[0] != volL) {
1046 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1047 snd_cs4281_pokeBA0(chip, regR, volR);
1048 change = 1;
1049 }
1050 return change;
1051}
1052
1053static snd_kcontrol_new_t snd_cs4281_fm_vol =
1054{
1055 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1056 .name = "Synth Playback Volume",
1057 .info = snd_cs4281_info_volume,
1058 .get = snd_cs4281_get_volume,
1059 .put = snd_cs4281_put_volume,
1060 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1061};
1062
1063static snd_kcontrol_new_t snd_cs4281_pcm_vol =
1064{
1065 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1066 .name = "PCM Stream Playback Volume",
1067 .info = snd_cs4281_info_volume,
1068 .get = snd_cs4281_get_volume,
1069 .put = snd_cs4281_put_volume,
1070 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1071};
1072
1073static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus)
1074{
1075 cs4281_t *chip = bus->private_data;
1076 chip->ac97_bus = NULL;
1077}
1078
1079static void snd_cs4281_mixer_free_ac97(ac97_t *ac97)
1080{
1081 cs4281_t *chip = ac97->private_data;
1082 if (ac97->num)
1083 chip->ac97_secondary = NULL;
1084 else
1085 chip->ac97 = NULL;
1086}
1087
1088static int __devinit snd_cs4281_mixer(cs4281_t * chip)
1089{
1090 snd_card_t *card = chip->card;
1091 ac97_template_t ac97;
1092 int err;
1093 static ac97_bus_ops_t ops = {
1094 .write = snd_cs4281_ac97_write,
1095 .read = snd_cs4281_ac97_read,
1096 };
1097
1098 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1099 return err;
1100 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1101
1102 memset(&ac97, 0, sizeof(ac97));
1103 ac97.private_data = chip;
1104 ac97.private_free = snd_cs4281_mixer_free_ac97;
1105 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1106 return err;
1107 if (chip->dual_codec) {
1108 ac97.num = 1;
1109 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1110 return err;
1111 }
1112 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1113 return err;
1114 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1115 return err;
1116 return 0;
1117}
1118
1119
1120/*
1121 * proc interface
1122 */
1123
1124static void snd_cs4281_proc_read(snd_info_entry_t *entry,
1125 snd_info_buffer_t * buffer)
1126{
1127 cs4281_t *chip = entry->private_data;
1128
1129 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1130 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1131 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1132}
1133
1134static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data,
1135 struct file *file, char __user *buf,
1136 unsigned long count, unsigned long pos)
1137{
1138 long size;
1139 cs4281_t *chip = entry->private_data;
1140
1141 size = count;
1142 if (pos + size > CS4281_BA0_SIZE)
1143 size = (long)CS4281_BA0_SIZE - pos;
1144 if (size > 0) {
1145 if (copy_to_user_fromio(buf, chip->ba0 + pos, size))
1146 return -EFAULT;
1147 }
1148 return size;
1149}
1150
1151static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data,
1152 struct file *file, char __user *buf,
1153 unsigned long count, unsigned long pos)
1154{
1155 long size;
1156 cs4281_t *chip = entry->private_data;
1157
1158 size = count;
1159 if (pos + size > CS4281_BA1_SIZE)
1160 size = (long)CS4281_BA1_SIZE - pos;
1161 if (size > 0) {
1162 if (copy_to_user_fromio(buf, chip->ba1 + pos, size))
1163 return -EFAULT;
1164 }
1165 return size;
1166}
1167
1168static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1169 .read = snd_cs4281_BA0_read,
1170};
1171
1172static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1173 .read = snd_cs4281_BA1_read,
1174};
1175
1176static void __devinit snd_cs4281_proc_init(cs4281_t * chip)
1177{
1178 snd_info_entry_t *entry;
1179
1180 if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1181 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read);
1182 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1183 entry->content = SNDRV_INFO_CONTENT_DATA;
1184 entry->private_data = chip;
1185 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1186 entry->size = CS4281_BA0_SIZE;
1187 }
1188 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1189 entry->content = SNDRV_INFO_CONTENT_DATA;
1190 entry->private_data = chip;
1191 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1192 entry->size = CS4281_BA1_SIZE;
1193 }
1194}
1195
1196/*
1197 * joystick support
1198 */
1199
1200#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1201
1202static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1203{
1204 cs4281_t *chip = gameport_get_port_data(gameport);
1205
1206 snd_assert(chip, return);
1207 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1208}
1209
1210static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1211{
1212 cs4281_t *chip = gameport_get_port_data(gameport);
1213
1214 snd_assert(chip, return 0);
1215 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1216}
1217
1218#ifdef COOKED_MODE
1219static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
1220{
1221 cs4281_t *chip = gameport_get_port_data(gameport);
1222 unsigned js1, js2, jst;
1223
1224 snd_assert(chip, return 0);
1225
1226 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1227 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1228 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1229
1230 *buttons = (~jst >> 4) & 0x0F;
1231
1232 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1233 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1234 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1235 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1236
1237 for (jst = 0; jst < 4; ++jst)
1238 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1239 return 0;
1240}
1241#else
1242#define snd_cs4281_gameport_cooked_read NULL
1243#endif
1244
1245static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1246{
1247 switch (mode) {
1248#ifdef COOKED_MODE
1249 case GAMEPORT_MODE_COOKED:
1250 return 0;
1251#endif
1252 case GAMEPORT_MODE_RAW:
1253 return 0;
1254 default:
1255 return -1;
1256 }
1257 return 0;
1258}
1259
1260static int __devinit snd_cs4281_create_gameport(cs4281_t *chip)
1261{
1262 struct gameport *gp;
1263
1264 chip->gameport = gp = gameport_allocate_port();
1265 if (!gp) {
1266 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n");
1267 return -ENOMEM;
1268 }
1269
1270 gameport_set_name(gp, "CS4281 Gameport");
1271 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1272 gameport_set_dev_parent(gp, &chip->pci->dev);
1273 gp->open = snd_cs4281_gameport_open;
1274 gp->read = snd_cs4281_gameport_read;
1275 gp->trigger = snd_cs4281_gameport_trigger;
1276 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1277 gameport_set_port_data(gp, chip);
1278
1279 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1280 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1281
1282 gameport_register_port(gp);
1283
1284 return 0;
1285}
1286
1287static void snd_cs4281_free_gameport(cs4281_t *chip)
1288{
1289 if (chip->gameport) {
1290 gameport_unregister_port(chip->gameport);
1291 chip->gameport = NULL;
1292 }
1293}
1294#else
1295static inline int snd_cs4281_create_gameport(cs4281_t *chip) { return -ENOSYS; }
1296static inline void snd_cs4281_free_gameport(cs4281_t *chip) { }
1297#endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1298
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299static int snd_cs4281_free(cs4281_t *chip)
1300{
1301 snd_cs4281_free_gameport(chip);
1302
1303 if (chip->irq >= 0)
1304 synchronize_irq(chip->irq);
1305
1306 /* Mask interrupts */
1307 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1308 /* Stop the DLL Clock logic. */
1309 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1310 /* Sound System Power Management - Turn Everything OFF */
1311 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1312 /* PCI interface - D3 state */
1313 pci_set_power_state(chip->pci, 3);
1314
1315 if (chip->irq >= 0)
1316 free_irq(chip->irq, (void *)chip);
1317 if (chip->ba0)
1318 iounmap(chip->ba0);
1319 if (chip->ba1)
1320 iounmap(chip->ba1);
1321 pci_release_regions(chip->pci);
1322 pci_disable_device(chip->pci);
1323
1324 kfree(chip);
1325 return 0;
1326}
1327
1328static int snd_cs4281_dev_free(snd_device_t *device)
1329{
1330 cs4281_t *chip = device->device_data;
1331 return snd_cs4281_free(chip);
1332}
1333
1334static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
1335#ifdef CONFIG_PM
1336static int cs4281_suspend(snd_card_t *card, pm_message_t state);
1337static int cs4281_resume(snd_card_t *card);
1338#endif
1339
1340static int __devinit snd_cs4281_create(snd_card_t * card,
1341 struct pci_dev *pci,
1342 cs4281_t ** rchip,
1343 int dual_codec)
1344{
1345 cs4281_t *chip;
1346 unsigned int tmp;
1347 int err;
1348 static snd_device_ops_t ops = {
1349 .dev_free = snd_cs4281_dev_free,
1350 };
1351
1352 *rchip = NULL;
1353 if ((err = pci_enable_device(pci)) < 0)
1354 return err;
Takashi Iwaie560d8d2005-09-09 14:21:46 +02001355 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356 if (chip == NULL) {
1357 pci_disable_device(pci);
1358 return -ENOMEM;
1359 }
1360 spin_lock_init(&chip->reg_lock);
1361 chip->card = card;
1362 chip->pci = pci;
1363 chip->irq = -1;
1364 pci_set_master(pci);
1365 if (dual_codec < 0 || dual_codec > 3) {
1366 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1367 dual_codec = 0;
1368 }
1369 chip->dual_codec = dual_codec;
1370
1371 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1372 kfree(chip);
1373 pci_disable_device(pci);
1374 return err;
1375 }
1376 chip->ba0_addr = pci_resource_start(pci, 0);
1377 chip->ba1_addr = pci_resource_start(pci, 1);
1378
1379 if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) {
1380 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1381 snd_cs4281_free(chip);
1382 return -ENOMEM;
1383 }
1384 chip->irq = pci->irq;
1385
1386 chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0));
1387 chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1));
1388 if (!chip->ba0 || !chip->ba1) {
1389 snd_cs4281_free(chip);
1390 return -ENOMEM;
1391 }
1392
1393 tmp = snd_cs4281_chip_init(chip);
1394 if (tmp) {
1395 snd_cs4281_free(chip);
1396 return tmp;
1397 }
1398
1399 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1400 snd_cs4281_free(chip);
1401 return err;
1402 }
1403
1404 snd_cs4281_proc_init(chip);
1405
1406 snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip);
1407
1408 snd_card_set_dev(card, &pci->dev);
1409
1410 *rchip = chip;
1411 return 0;
1412}
1413
1414static int snd_cs4281_chip_init(cs4281_t *chip)
1415{
1416 unsigned int tmp;
1417 int timeout;
1418 int retry_count = 2;
1419
Arnaud Patarda488e032005-05-07 18:51:51 +02001420 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1421 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1422 if (tmp & BA0_EPPMC_FPDN)
1423 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1424
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425 __retry:
1426 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1427 if (tmp != BA0_CFLR_DEFAULT) {
1428 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1429 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1430 if (tmp != BA0_CFLR_DEFAULT) {
1431 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1432 return -EIO;
1433 }
1434 }
1435
1436 /* Set the 'Configuration Write Protect' register
1437 * to 4281h. Allows vendor-defined configuration
1438 * space between 0e4h and 0ffh to be written. */
1439 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1440
1441 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1442 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1443 return -EIO;
1444 }
1445 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1446 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1447 return -EIO;
1448 }
1449
1450 /* Sound System Power Management */
1451 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1452 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1453 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1454
1455 /* Serial Port Power Management */
1456 /* Blast the clock control register to zero so that the
1457 * PLL starts out in a known state, and blast the master serial
1458 * port control register to zero so that the serial ports also
1459 * start out in a known state. */
1460 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1461 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1462
1463 /* Make ESYN go to zero to turn off
1464 * the Sync pulse on the AC97 link. */
1465 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1466 udelay(50);
1467
1468 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1469 * spec) and then drive it high. This is done for non AC97 modes since
1470 * there might be logic external to the CS4281 that uses the ARST# line
1471 * for a reset. */
1472 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1473 udelay(50);
1474 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001475 msleep(50);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476
1477 if (chip->dual_codec)
1478 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1479
1480 /*
1481 * Set the serial port timing configuration.
1482 */
1483 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1484 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1485 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1486
1487 /*
1488 * Start the DLL Clock logic.
1489 */
1490 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001491 msleep(50);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1493
1494 /*
1495 * Wait for the DLL ready signal from the clock logic.
1496 */
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001497 timeout = 100;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498 do {
1499 /*
1500 * Read the AC97 status register to see if we've seen a CODEC
1501 * signal from the AC97 codec.
1502 */
1503 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1504 goto __ok0;
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001505 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506 } while (timeout-- > 0);
1507
1508 snd_printk(KERN_ERR "DLLRDY not seen\n");
1509 return -EIO;
1510
1511 __ok0:
1512
1513 /*
1514 * The first thing we do here is to enable sync generation. As soon
1515 * as we start receiving bit clock, we'll start producing the SYNC
1516 * signal.
1517 */
1518 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1519
1520 /*
1521 * Wait for the codec ready signal from the AC97 codec.
1522 */
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001523 timeout = 100;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524 do {
1525 /*
1526 * Read the AC97 status register to see if we've seen a CODEC
1527 * signal from the AC97 codec.
1528 */
1529 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1530 goto __ok1;
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001531 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532 } while (timeout-- > 0);
1533
1534 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1535 return -EIO;
1536
1537 __ok1:
1538 if (chip->dual_codec) {
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001539 timeout = 100;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540 do {
1541 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1542 goto __codec2_ok;
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001543 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544 } while (timeout-- > 0);
1545 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1546 chip->dual_codec = 0;
1547 __codec2_ok: ;
1548 }
1549
1550 /*
1551 * Assert the valid frame signal so that we can start sending commands
1552 * to the AC97 codec.
1553 */
1554
1555 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1556
1557 /*
1558 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1559 * the codec is pumping ADC data across the AC-link.
1560 */
1561
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001562 timeout = 100;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563 do {
1564 /*
1565 * Read the input slot valid register and see if input slots 3
1566 * 4 are valid yet.
1567 */
1568 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1569 goto __ok2;
Takashi Iwaic9a49bb2005-11-17 10:36:57 +01001570 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001571 } while (timeout-- > 0);
1572
1573 if (--retry_count > 0)
1574 goto __retry;
1575 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1576 return -EIO;
1577
1578 __ok2:
1579
1580 /*
1581 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1582 * commense the transfer of digital audio data to the AC97 codec.
1583 */
1584 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1585
1586 /*
1587 * Initialize DMA structures
1588 */
1589 for (tmp = 0; tmp < 4; tmp++) {
1590 cs4281_dma_t *dma = &chip->dma[tmp];
1591 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1592 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1593 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1594 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1595 dma->regDMR = BA0_DMR0 + (tmp * 8);
1596 dma->regDCR = BA0_DCR0 + (tmp * 8);
1597 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1598 dma->regFCR = BA0_FCR0 + (tmp * 4);
1599 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1600 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1601 snd_cs4281_pokeBA0(chip, dma->regFCR,
1602 BA0_FCR_LS(31) |
1603 BA0_FCR_RS(31) |
1604 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1605 BA0_FCR_OF(dma->fifo_offset));
1606 }
1607
1608 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1609 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1610 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1611 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1612
1613 /* Activate wave playback FIFO for FM playback */
1614 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1615 BA0_FCR_RS(1) |
1616 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1617 BA0_FCR_OF(chip->dma[0].fifo_offset);
1618 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1619 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1620 (chip->src_right_play_slot << 8) |
1621 (chip->src_left_rec_slot << 16) |
1622 (chip->src_right_rec_slot << 24));
1623
1624 /* Initialize digital volume */
1625 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1626 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1627
1628 /* Enable IRQs */
1629 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1630 /* Unmask interrupts */
1631 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1632 BA0_HISR_MIDI |
1633 BA0_HISR_DMAI |
1634 BA0_HISR_DMA(0) |
1635 BA0_HISR_DMA(1) |
1636 BA0_HISR_DMA(2) |
1637 BA0_HISR_DMA(3)));
1638 synchronize_irq(chip->irq);
1639
1640 return 0;
1641}
1642
1643/*
1644 * MIDI section
1645 */
1646
1647static void snd_cs4281_midi_reset(cs4281_t *chip)
1648{
1649 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1650 udelay(100);
1651 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1652}
1653
1654static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream)
1655{
1656 cs4281_t *chip = substream->rmidi->private_data;
1657
1658 spin_lock_irq(&chip->reg_lock);
1659 chip->midcr |= BA0_MIDCR_RXE;
1660 chip->midi_input = substream;
1661 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1662 snd_cs4281_midi_reset(chip);
1663 } else {
1664 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1665 }
1666 spin_unlock_irq(&chip->reg_lock);
1667 return 0;
1668}
1669
1670static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream)
1671{
1672 cs4281_t *chip = substream->rmidi->private_data;
1673
1674 spin_lock_irq(&chip->reg_lock);
1675 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1676 chip->midi_input = NULL;
1677 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1678 snd_cs4281_midi_reset(chip);
1679 } else {
1680 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1681 }
1682 chip->uartm &= ~CS4281_MODE_INPUT;
1683 spin_unlock_irq(&chip->reg_lock);
1684 return 0;
1685}
1686
1687static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream)
1688{
1689 cs4281_t *chip = substream->rmidi->private_data;
1690
1691 spin_lock_irq(&chip->reg_lock);
1692 chip->uartm |= CS4281_MODE_OUTPUT;
1693 chip->midcr |= BA0_MIDCR_TXE;
1694 chip->midi_output = substream;
1695 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1696 snd_cs4281_midi_reset(chip);
1697 } else {
1698 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1699 }
1700 spin_unlock_irq(&chip->reg_lock);
1701 return 0;
1702}
1703
1704static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream)
1705{
1706 cs4281_t *chip = substream->rmidi->private_data;
1707
1708 spin_lock_irq(&chip->reg_lock);
1709 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1710 chip->midi_output = NULL;
1711 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1712 snd_cs4281_midi_reset(chip);
1713 } else {
1714 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1715 }
1716 chip->uartm &= ~CS4281_MODE_OUTPUT;
1717 spin_unlock_irq(&chip->reg_lock);
1718 return 0;
1719}
1720
1721static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1722{
1723 unsigned long flags;
1724 cs4281_t *chip = substream->rmidi->private_data;
1725
1726 spin_lock_irqsave(&chip->reg_lock, flags);
1727 if (up) {
1728 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1729 chip->midcr |= BA0_MIDCR_RIE;
1730 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1731 }
1732 } else {
1733 if (chip->midcr & BA0_MIDCR_RIE) {
1734 chip->midcr &= ~BA0_MIDCR_RIE;
1735 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1736 }
1737 }
1738 spin_unlock_irqrestore(&chip->reg_lock, flags);
1739}
1740
1741static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1742{
1743 unsigned long flags;
1744 cs4281_t *chip = substream->rmidi->private_data;
1745 unsigned char byte;
1746
1747 spin_lock_irqsave(&chip->reg_lock, flags);
1748 if (up) {
1749 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1750 chip->midcr |= BA0_MIDCR_TIE;
1751 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1752 while ((chip->midcr & BA0_MIDCR_TIE) &&
1753 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1754 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1755 chip->midcr &= ~BA0_MIDCR_TIE;
1756 } else {
1757 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1758 }
1759 }
1760 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1761 }
1762 } else {
1763 if (chip->midcr & BA0_MIDCR_TIE) {
1764 chip->midcr &= ~BA0_MIDCR_TIE;
1765 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1766 }
1767 }
1768 spin_unlock_irqrestore(&chip->reg_lock, flags);
1769}
1770
1771static snd_rawmidi_ops_t snd_cs4281_midi_output =
1772{
1773 .open = snd_cs4281_midi_output_open,
1774 .close = snd_cs4281_midi_output_close,
1775 .trigger = snd_cs4281_midi_output_trigger,
1776};
1777
1778static snd_rawmidi_ops_t snd_cs4281_midi_input =
1779{
1780 .open = snd_cs4281_midi_input_open,
1781 .close = snd_cs4281_midi_input_close,
1782 .trigger = snd_cs4281_midi_input_trigger,
1783};
1784
1785static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi)
1786{
1787 snd_rawmidi_t *rmidi;
1788 int err;
1789
1790 if (rrawmidi)
1791 *rrawmidi = NULL;
1792 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1793 return err;
1794 strcpy(rmidi->name, "CS4281");
1795 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1796 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1797 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1798 rmidi->private_data = chip;
1799 chip->rmidi = rmidi;
1800 if (rrawmidi)
1801 *rrawmidi = rmidi;
1802 return 0;
1803}
1804
1805/*
1806 * Interrupt handler
1807 */
1808
1809static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1810{
1811 cs4281_t *chip = dev_id;
1812 unsigned int status, dma, val;
1813 cs4281_dma_t *cdma;
1814
1815 if (chip == NULL)
1816 return IRQ_NONE;
1817 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1818 if ((status & 0x7fffffff) == 0) {
1819 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1820 return IRQ_NONE;
1821 }
1822
1823 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1824 for (dma = 0; dma < 4; dma++)
1825 if (status & BA0_HISR_DMA(dma)) {
1826 cdma = &chip->dma[dma];
1827 spin_lock(&chip->reg_lock);
1828 /* ack DMA IRQ */
1829 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1830 /* workaround, sometimes CS4281 acknowledges */
1831 /* end or middle transfer position twice */
1832 cdma->frag++;
1833 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1834 cdma->frag--;
1835 chip->spurious_dhtc_irq++;
1836 spin_unlock(&chip->reg_lock);
1837 continue;
1838 }
1839 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1840 cdma->frag--;
1841 chip->spurious_dtc_irq++;
1842 spin_unlock(&chip->reg_lock);
1843 continue;
1844 }
1845 spin_unlock(&chip->reg_lock);
1846 snd_pcm_period_elapsed(cdma->substream);
1847 }
1848 }
1849
1850 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1851 unsigned char c;
1852
1853 spin_lock(&chip->reg_lock);
1854 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1855 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1856 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1857 continue;
1858 snd_rawmidi_receive(chip->midi_input, &c, 1);
1859 }
1860 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1861 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1862 break;
1863 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1864 chip->midcr &= ~BA0_MIDCR_TIE;
1865 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1866 break;
1867 }
1868 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1869 }
1870 spin_unlock(&chip->reg_lock);
1871 }
1872
1873 /* EOI to the PCI part... reenables interrupts */
1874 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1875
1876 return IRQ_HANDLED;
1877}
1878
1879
1880/*
1881 * OPL3 command
1882 */
1883static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val)
1884{
1885 unsigned long flags;
1886 cs4281_t *chip = opl3->private_data;
1887 void __iomem *port;
1888
1889 if (cmd & OPL3_RIGHT)
1890 port = chip->ba0 + BA0_B1AP; /* right port */
1891 else
1892 port = chip->ba0 + BA0_B0AP; /* left port */
1893
1894 spin_lock_irqsave(&opl3->reg_lock, flags);
1895
1896 writel((unsigned int)cmd, port);
1897 udelay(10);
1898
1899 writel((unsigned int)val, port + 4);
1900 udelay(30);
1901
1902 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1903}
1904
1905static int __devinit snd_cs4281_probe(struct pci_dev *pci,
1906 const struct pci_device_id *pci_id)
1907{
1908 static int dev;
1909 snd_card_t *card;
1910 cs4281_t *chip;
1911 opl3_t *opl3;
1912 int err;
1913
1914 if (dev >= SNDRV_CARDS)
1915 return -ENODEV;
1916 if (!enable[dev]) {
1917 dev++;
1918 return -ENOENT;
1919 }
1920
1921 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1922 if (card == NULL)
1923 return -ENOMEM;
1924
1925 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1926 snd_card_free(card);
1927 return err;
1928 }
1929
1930 if ((err = snd_cs4281_mixer(chip)) < 0) {
1931 snd_card_free(card);
1932 return err;
1933 }
1934 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1935 snd_card_free(card);
1936 return err;
1937 }
1938 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1939 snd_card_free(card);
1940 return err;
1941 }
1942 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1943 snd_card_free(card);
1944 return err;
1945 }
1946 opl3->private_data = chip;
1947 opl3->command = snd_cs4281_opl3_command;
1948 snd_opl3_init(opl3);
1949 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1950 snd_card_free(card);
1951 return err;
1952 }
1953 snd_cs4281_create_gameport(chip);
1954 strcpy(card->driver, "CS4281");
1955 strcpy(card->shortname, "Cirrus Logic CS4281");
1956 sprintf(card->longname, "%s at 0x%lx, irq %d",
1957 card->shortname,
1958 chip->ba0_addr,
1959 chip->irq);
1960
1961 if ((err = snd_card_register(card)) < 0) {
1962 snd_card_free(card);
1963 return err;
1964 }
1965
1966 pci_set_drvdata(pci, card);
1967 dev++;
1968 return 0;
1969}
1970
1971static void __devexit snd_cs4281_remove(struct pci_dev *pci)
1972{
1973 snd_card_free(pci_get_drvdata(pci));
1974 pci_set_drvdata(pci, NULL);
1975}
1976
1977/*
1978 * Power Management
1979 */
1980#ifdef CONFIG_PM
1981
1982static int saved_regs[SUSPEND_REGISTERS] = {
1983 BA0_JSCTL,
1984 BA0_GPIOR,
1985 BA0_SSCR,
1986 BA0_MIDCR,
1987 BA0_SRCSA,
1988 BA0_PASR,
1989 BA0_CASR,
1990 BA0_DACSR,
1991 BA0_ADCSR,
1992 BA0_FMLVC,
1993 BA0_FMRVC,
1994 BA0_PPLVC,
1995 BA0_PPRVC,
1996};
1997
1998#define CLKCR1_CKRA 0x00010000L
1999
2000static int cs4281_suspend(snd_card_t *card, pm_message_t state)
2001{
2002 cs4281_t *chip = card->pm_private_data;
2003 u32 ulCLK;
2004 unsigned int i;
2005
2006 snd_pcm_suspend_all(chip->pcm);
2007
2008 if (chip->ac97)
2009 snd_ac97_suspend(chip->ac97);
2010 if (chip->ac97_secondary)
2011 snd_ac97_suspend(chip->ac97_secondary);
2012
2013 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2014 ulCLK |= CLKCR1_CKRA;
2015 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2016
2017 /* Disable interrupts. */
2018 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2019
2020 /* remember the status registers */
2021 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2022 if (saved_regs[i])
2023 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2024
2025 /* Turn off the serial ports. */
2026 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2027
2028 /* Power off FM, Joystick, AC link, */
2029 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2030
2031 /* DLL off. */
2032 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2033
2034 /* AC link off. */
2035 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2036
2037 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2038 ulCLK &= ~CLKCR1_CKRA;
2039 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2040
2041 pci_disable_device(chip->pci);
2042 return 0;
2043}
2044
2045static int cs4281_resume(snd_card_t *card)
2046{
2047 cs4281_t *chip = card->pm_private_data;
2048 unsigned int i;
2049 u32 ulCLK;
2050
2051 pci_enable_device(chip->pci);
2052 pci_set_master(chip->pci);
2053
2054 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2055 ulCLK |= CLKCR1_CKRA;
2056 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2057
2058 snd_cs4281_chip_init(chip);
2059
2060 /* restore the status registers */
2061 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2062 if (saved_regs[i])
2063 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2064
2065 if (chip->ac97)
2066 snd_ac97_resume(chip->ac97);
2067 if (chip->ac97_secondary)
2068 snd_ac97_resume(chip->ac97_secondary);
2069
2070 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2071 ulCLK &= ~CLKCR1_CKRA;
2072 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2073
2074 return 0;
2075}
2076#endif /* CONFIG_PM */
2077
2078static struct pci_driver driver = {
2079 .name = "CS4281",
2080 .id_table = snd_cs4281_ids,
2081 .probe = snd_cs4281_probe,
2082 .remove = __devexit_p(snd_cs4281_remove),
2083 SND_PCI_PM_CALLBACKS
2084};
2085
2086static int __init alsa_card_cs4281_init(void)
2087{
Takashi Iwai01d25d42005-04-11 16:58:24 +02002088 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089}
2090
2091static void __exit alsa_card_cs4281_exit(void)
2092{
2093 pci_unregister_driver(&driver);
2094}
2095
2096module_init(alsa_card_cs4281_init)
2097module_exit(alsa_card_cs4281_exit)