blob: aaac3b2fb746d3e61019f9e0804d7bf2913f8de2 [file] [log] [blame]
Andreas Herrmann23ac4ae2010-09-17 18:03:43 +02001#ifndef _ASM_X86_AMD_NB_H
2#define _ASM_X86_AMD_NB_H
Andi Kleena32073b2006-06-26 13:56:40 +02003
Bjorn Helgaas24d25db2012-01-05 14:27:19 -07004#include <linux/ioport.h>
Andi Kleena32073b2006-06-26 13:56:40 +02005#include <linux/pci.h>
6
Jan Beulich24d9b702011-01-10 16:20:23 +00007struct amd_nb_bus_dev_range {
8 u8 bus;
9 u8 dev_base;
10 u8 dev_limit;
11};
12
Jan Beulich691269f2011-02-09 08:26:53 +000013extern const struct pci_device_id amd_nb_misc_ids[];
Jan Beulich24d9b702011-01-10 16:20:23 +000014extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
Andi Kleena32073b2006-06-26 13:56:40 +020015
Borislav Petkov84fd1d32011-03-03 12:59:32 +010016extern bool early_is_amd_nb(u32 value);
Bjorn Helgaas24d25db2012-01-05 14:27:19 -070017extern struct resource *amd_get_mmconfig_range(struct resource *res);
Hans Rosenfeld9653a5c2010-10-29 17:14:31 +020018extern int amd_cache_northbridges(void);
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +020019extern void amd_flush_garts(void);
Tejun Heo940fed22011-02-16 12:13:06 +010020extern int amd_numa_init(void);
Hans Rosenfeldcabb5bd2011-02-07 18:10:39 +010021extern int amd_get_subcaches(int);
Dan Carpenter2993ae32014-01-21 10:22:09 +030022extern int amd_set_subcaches(int, unsigned long);
Andi Kleena32073b2006-06-26 13:56:40 +020023
Thomas Gleixnerd2946042011-07-24 09:46:09 +000024struct amd_l3_cache {
25 unsigned indices;
26 u8 subcaches[4];
27};
28
Borislav Petkov019f34f2012-05-02 17:16:59 +020029struct threshold_block {
30 unsigned int block;
31 unsigned int bank;
32 unsigned int cpu;
33 u32 address;
34 u16 interrupt_enable;
35 bool interrupt_capable;
36 u16 threshold_limit;
37 struct kobject kobj;
38 struct list_head miscj;
39};
40
41struct threshold_bank {
42 struct kobject *kobj;
43 struct threshold_block *blocks;
44
45 /* initialized to the number of CPUs on the node sharing this bank */
46 atomic_t cpus;
47};
48
Hans Rosenfeld9653a5c2010-10-29 17:14:31 +020049struct amd_northbridge {
50 struct pci_dev *misc;
Hans Rosenfeld41b26102011-01-24 16:05:42 +010051 struct pci_dev *link;
Thomas Gleixnerd2946042011-07-24 09:46:09 +000052 struct amd_l3_cache l3_cache;
Borislav Petkov019f34f2012-05-02 17:16:59 +020053 struct threshold_bank *bank4;
Hans Rosenfeld9653a5c2010-10-29 17:14:31 +020054};
55
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +020056struct amd_northbridge_info {
Andreas Herrmann900f9ac2010-09-17 18:02:54 +020057 u16 num;
Hans Rosenfeld9653a5c2010-10-29 17:14:31 +020058 u64 flags;
59 struct amd_northbridge *nb;
Andreas Herrmann900f9ac2010-09-17 18:02:54 +020060};
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +020061extern struct amd_northbridge_info amd_northbridges;
Andreas Herrmann900f9ac2010-09-17 18:02:54 +020062
Borislav Petkov84fd1d32011-03-03 12:59:32 +010063#define AMD_NB_GART BIT(0)
64#define AMD_NB_L3_INDEX_DISABLE BIT(1)
65#define AMD_NB_L3_PARTITIONING BIT(2)
Hans Rosenfeld9653a5c2010-10-29 17:14:31 +020066
Andreas Herrmann23ac4ae2010-09-17 18:03:43 +020067#ifdef CONFIG_AMD_NB
Borislav Petkovade029e2010-04-24 09:56:53 +020068
Borislav Petkov84fd1d32011-03-03 12:59:32 +010069static inline u16 amd_nb_num(void)
Jaswinder Singh Rajputb2065252009-04-14 23:04:37 +053070{
Hans Rosenfeld9653a5c2010-10-29 17:14:31 +020071 return amd_northbridges.num;
72}
73
Borislav Petkov84fd1d32011-03-03 12:59:32 +010074static inline bool amd_nb_has_feature(unsigned feature)
Hans Rosenfeld9653a5c2010-10-29 17:14:31 +020075{
76 return ((amd_northbridges.flags & feature) == feature);
77}
78
79static inline struct amd_northbridge *node_to_amd_nb(int node)
80{
81 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
Jaswinder Singh Rajputb2065252009-04-14 23:04:37 +053082}
Borislav Petkovade029e2010-04-24 09:56:53 +020083
Daniel J Blueman772c3ff2012-11-27 14:32:09 +080084static inline u16 amd_get_node_id(struct pci_dev *pdev)
85{
86 struct pci_dev *misc;
87 int i;
88
89 for (i = 0; i != amd_nb_num(); i++) {
90 misc = node_to_amd_nb(i)->misc;
91
92 if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
93 PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
94 return i;
95 }
96
97 WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
98 return 0;
99}
100
Andreas Herrmannafd9fce2009-04-09 15:16:17 +0200101#else
Borislav Petkovade029e2010-04-24 09:56:53 +0200102
Hans Rosenfeld9653a5c2010-10-29 17:14:31 +0200103#define amd_nb_num(x) 0
104#define amd_nb_has_feature(x) false
105#define node_to_amd_nb(x) NULL
106
Andreas Herrmannafd9fce2009-04-09 15:16:17 +0200107#endif
108
109
Andreas Herrmann23ac4ae2010-09-17 18:03:43 +0200110#endif /* _ASM_X86_AMD_NB_H */