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MyungJoo Ham527e7e92011-03-04 15:50:26 +09001/*
Laszlo Pappf876a972013-12-19 13:08:43 +00002 * max8997-private.h - Voltage regulator driver for the Maxim 8997
MyungJoo Ham527e7e92011-03-04 15:50:26 +09003 *
4 * Copyright (C) 2010 Samsung Electrnoics
5 * MyungJoo Ham <myungjoo.ham@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __LINUX_MFD_MAX8997_PRIV_H
23#define __LINUX_MFD_MAX8997_PRIV_H
24
25#include <linux/i2c.h>
Thomas Abrahamb41511f2012-07-02 09:02:55 +090026#include <linux/export.h>
27#include <linux/irqdomain.h>
MyungJoo Ham527e7e92011-03-04 15:50:26 +090028
MyungJoo Ham8de6bc72011-03-24 15:54:45 +090029#define MAX8997_REG_INVALID (0xff)
30
MyungJoo Ham527e7e92011-03-04 15:50:26 +090031enum max8997_pmic_reg {
32 MAX8997_REG_PMIC_ID0 = 0x00,
33 MAX8997_REG_PMIC_ID1 = 0x01,
34 MAX8997_REG_INTSRC = 0x02,
35 MAX8997_REG_INT1 = 0x03,
36 MAX8997_REG_INT2 = 0x04,
37 MAX8997_REG_INT3 = 0x05,
38 MAX8997_REG_INT4 = 0x06,
39
40 MAX8997_REG_INT1MSK = 0x08,
41 MAX8997_REG_INT2MSK = 0x09,
42 MAX8997_REG_INT3MSK = 0x0a,
43 MAX8997_REG_INT4MSK = 0x0b,
44
45 MAX8997_REG_STATUS1 = 0x0d,
46 MAX8997_REG_STATUS2 = 0x0e,
47 MAX8997_REG_STATUS3 = 0x0f,
48 MAX8997_REG_STATUS4 = 0x10,
49
50 MAX8997_REG_MAINCON1 = 0x13,
51 MAX8997_REG_MAINCON2 = 0x14,
52 MAX8997_REG_BUCKRAMP = 0x15,
53
54 MAX8997_REG_BUCK1CTRL = 0x18,
55 MAX8997_REG_BUCK1DVS1 = 0x19,
56 MAX8997_REG_BUCK1DVS2 = 0x1a,
57 MAX8997_REG_BUCK1DVS3 = 0x1b,
58 MAX8997_REG_BUCK1DVS4 = 0x1c,
59 MAX8997_REG_BUCK1DVS5 = 0x1d,
60 MAX8997_REG_BUCK1DVS6 = 0x1e,
61 MAX8997_REG_BUCK1DVS7 = 0x1f,
62 MAX8997_REG_BUCK1DVS8 = 0x20,
63 MAX8997_REG_BUCK2CTRL = 0x21,
64 MAX8997_REG_BUCK2DVS1 = 0x22,
65 MAX8997_REG_BUCK2DVS2 = 0x23,
66 MAX8997_REG_BUCK2DVS3 = 0x24,
67 MAX8997_REG_BUCK2DVS4 = 0x25,
68 MAX8997_REG_BUCK2DVS5 = 0x26,
69 MAX8997_REG_BUCK2DVS6 = 0x27,
70 MAX8997_REG_BUCK2DVS7 = 0x28,
71 MAX8997_REG_BUCK2DVS8 = 0x29,
72 MAX8997_REG_BUCK3CTRL = 0x2a,
73 MAX8997_REG_BUCK3DVS = 0x2b,
74 MAX8997_REG_BUCK4CTRL = 0x2c,
75 MAX8997_REG_BUCK4DVS = 0x2d,
76 MAX8997_REG_BUCK5CTRL = 0x2e,
77 MAX8997_REG_BUCK5DVS1 = 0x2f,
78 MAX8997_REG_BUCK5DVS2 = 0x30,
79 MAX8997_REG_BUCK5DVS3 = 0x31,
80 MAX8997_REG_BUCK5DVS4 = 0x32,
81 MAX8997_REG_BUCK5DVS5 = 0x33,
82 MAX8997_REG_BUCK5DVS6 = 0x34,
83 MAX8997_REG_BUCK5DVS7 = 0x35,
84 MAX8997_REG_BUCK5DVS8 = 0x36,
85 MAX8997_REG_BUCK6CTRL = 0x37,
86 MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
87 MAX8997_REG_BUCK7CTRL = 0x39,
88 MAX8997_REG_BUCK7DVS = 0x3a,
89 MAX8997_REG_LDO1CTRL = 0x3b,
90 MAX8997_REG_LDO2CTRL = 0x3c,
91 MAX8997_REG_LDO3CTRL = 0x3d,
92 MAX8997_REG_LDO4CTRL = 0x3e,
93 MAX8997_REG_LDO5CTRL = 0x3f,
94 MAX8997_REG_LDO6CTRL = 0x40,
95 MAX8997_REG_LDO7CTRL = 0x41,
96 MAX8997_REG_LDO8CTRL = 0x42,
97 MAX8997_REG_LDO9CTRL = 0x43,
98 MAX8997_REG_LDO10CTRL = 0x44,
99 MAX8997_REG_LDO11CTRL = 0x45,
100 MAX8997_REG_LDO12CTRL = 0x46,
101 MAX8997_REG_LDO13CTRL = 0x47,
102 MAX8997_REG_LDO14CTRL = 0x48,
103 MAX8997_REG_LDO15CTRL = 0x49,
104 MAX8997_REG_LDO16CTRL = 0x4a,
105 MAX8997_REG_LDO17CTRL = 0x4b,
106 MAX8997_REG_LDO18CTRL = 0x4c,
107 MAX8997_REG_LDO21CTRL = 0x4d,
108
109 MAX8997_REG_MBCCTRL1 = 0x50,
110 MAX8997_REG_MBCCTRL2 = 0x51,
111 MAX8997_REG_MBCCTRL3 = 0x52,
112 MAX8997_REG_MBCCTRL4 = 0x53,
113 MAX8997_REG_MBCCTRL5 = 0x54,
114 MAX8997_REG_MBCCTRL6 = 0x55,
115 MAX8997_REG_OTPCGHCVS = 0x56,
116
117 MAX8997_REG_SAFEOUTCTRL = 0x5a,
118
119 MAX8997_REG_LBCNFG1 = 0x5e,
120 MAX8997_REG_LBCNFG2 = 0x5f,
121 MAX8997_REG_BBCCTRL = 0x60,
122
123 MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */
124 MAX8997_REG_FLASH2_CUR = 0x64,
125 MAX8997_REG_MOVIE_CUR = 0x65,
126 MAX8997_REG_GSMB_CUR = 0x66,
127 MAX8997_REG_BOOST_CNTL = 0x67,
128 MAX8997_REG_LEN_CNTL = 0x68,
129 MAX8997_REG_FLASH_CNTL = 0x69,
130 MAX8997_REG_WDT_CNTL = 0x6a,
131 MAX8997_REG_MAXFLASH1 = 0x6b,
132 MAX8997_REG_MAXFLASH2 = 0x6c,
133 MAX8997_REG_FLASHSTATUS = 0x6d,
134 MAX8997_REG_FLASHSTATUSMASK = 0x6e,
135
136 MAX8997_REG_GPIOCNTL1 = 0x70,
137 MAX8997_REG_GPIOCNTL2 = 0x71,
138 MAX8997_REG_GPIOCNTL3 = 0x72,
139 MAX8997_REG_GPIOCNTL4 = 0x73,
140 MAX8997_REG_GPIOCNTL5 = 0x74,
141 MAX8997_REG_GPIOCNTL6 = 0x75,
142 MAX8997_REG_GPIOCNTL7 = 0x76,
143 MAX8997_REG_GPIOCNTL8 = 0x77,
144 MAX8997_REG_GPIOCNTL9 = 0x78,
145 MAX8997_REG_GPIOCNTL10 = 0x79,
146 MAX8997_REG_GPIOCNTL11 = 0x7a,
147 MAX8997_REG_GPIOCNTL12 = 0x7b,
148
149 MAX8997_REG_LDO1CONFIG = 0x80,
150 MAX8997_REG_LDO2CONFIG = 0x81,
151 MAX8997_REG_LDO3CONFIG = 0x82,
152 MAX8997_REG_LDO4CONFIG = 0x83,
153 MAX8997_REG_LDO5CONFIG = 0x84,
154 MAX8997_REG_LDO6CONFIG = 0x85,
155 MAX8997_REG_LDO7CONFIG = 0x86,
156 MAX8997_REG_LDO8CONFIG = 0x87,
157 MAX8997_REG_LDO9CONFIG = 0x88,
158 MAX8997_REG_LDO10CONFIG = 0x89,
159 MAX8997_REG_LDO11CONFIG = 0x8a,
160 MAX8997_REG_LDO12CONFIG = 0x8b,
161 MAX8997_REG_LDO13CONFIG = 0x8c,
162 MAX8997_REG_LDO14CONFIG = 0x8d,
163 MAX8997_REG_LDO15CONFIG = 0x8e,
164 MAX8997_REG_LDO16CONFIG = 0x8f,
165 MAX8997_REG_LDO17CONFIG = 0x90,
166 MAX8997_REG_LDO18CONFIG = 0x91,
167 MAX8997_REG_LDO21CONFIG = 0x92,
168
169 MAX8997_REG_DVSOKTIMER1 = 0x97,
170 MAX8997_REG_DVSOKTIMER2 = 0x98,
171 MAX8997_REG_DVSOKTIMER4 = 0x99,
172 MAX8997_REG_DVSOKTIMER5 = 0x9a,
173
174 MAX8997_REG_PMIC_END = 0x9b,
175};
176
177enum max8997_muic_reg {
178 MAX8997_MUIC_REG_ID = 0x0,
179 MAX8997_MUIC_REG_INT1 = 0x1,
180 MAX8997_MUIC_REG_INT2 = 0x2,
181 MAX8997_MUIC_REG_INT3 = 0x3,
182 MAX8997_MUIC_REG_STATUS1 = 0x4,
183 MAX8997_MUIC_REG_STATUS2 = 0x5,
184 MAX8997_MUIC_REG_STATUS3 = 0x6,
185 MAX8997_MUIC_REG_INTMASK1 = 0x7,
186 MAX8997_MUIC_REG_INTMASK2 = 0x8,
187 MAX8997_MUIC_REG_INTMASK3 = 0x9,
188 MAX8997_MUIC_REG_CDETCTRL = 0xa,
189
190 MAX8997_MUIC_REG_CONTROL1 = 0xc,
191 MAX8997_MUIC_REG_CONTROL2 = 0xd,
192 MAX8997_MUIC_REG_CONTROL3 = 0xe,
193
194 MAX8997_MUIC_REG_END = 0xf,
195};
196
Chanwoo Choie3e5bc02013-02-12 20:44:19 +0900197/* MAX8997-MUIC STATUS1 register */
198#define STATUS1_ADC_SHIFT 0
199#define STATUS1_ADCLOW_SHIFT 5
200#define STATUS1_ADCERR_SHIFT 6
201#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
202#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
203#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
204
205/* MAX8997-MUIC STATUS2 register */
206#define STATUS2_CHGTYP_SHIFT 0
207#define STATUS2_CHGDETRUN_SHIFT 3
208#define STATUS2_DCDTMR_SHIFT 4
209#define STATUS2_DBCHG_SHIFT 5
210#define STATUS2_VBVOLT_SHIFT 6
211#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
212#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
213#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
214#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
215#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
216
217/* MAX8997-MUIC STATUS3 register */
218#define STATUS3_OVP_SHIFT 2
219#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
220
221/* MAX8997-MUIC CONTROL1 register */
222#define COMN1SW_SHIFT 0
223#define COMP2SW_SHIFT 3
224#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
225#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
Chanwoo Choi07c70502013-02-13 08:42:37 +0900226#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
Chanwoo Choie3e5bc02013-02-12 20:44:19 +0900227
228#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
229 | (1 << COMN1SW_SHIFT))
230#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
231 | (2 << COMN1SW_SHIFT))
232#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
233 | (3 << COMN1SW_SHIFT))
234#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
235 | (0 << COMN1SW_SHIFT))
236
Chanwoo Choi07c70502013-02-13 08:42:37 +0900237#define CONTROL2_LOWPWR_SHIFT (0)
238#define CONTROL2_ADCEN_SHIFT (1)
239#define CONTROL2_CPEN_SHIFT (2)
240#define CONTROL2_SFOUTASRT_SHIFT (3)
241#define CONTROL2_SFOUTORD_SHIFT (4)
242#define CONTROL2_ACCDET_SHIFT (5)
243#define CONTROL2_USBCPINT_SHIFT (6)
244#define CONTROL2_RCPS_SHIFT (7)
245#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
246#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
247#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
248#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
249#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
250#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
251#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
252#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
253
Chanwoo Choi027fcd52013-02-13 08:50:00 +0900254#define CONTROL3_JIGSET_SHIFT (0)
255#define CONTROL3_BTLDSET_SHIFT (2)
256#define CONTROL3_ADCDBSET_SHIFT (4)
257#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
258#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
259#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
260
MyungJoo Ham527e7e92011-03-04 15:50:26 +0900261enum max8997_haptic_reg {
262 MAX8997_HAPTIC_REG_GENERAL = 0x00,
263 MAX8997_HAPTIC_REG_CONF1 = 0x01,
264 MAX8997_HAPTIC_REG_CONF2 = 0x02,
265 MAX8997_HAPTIC_REG_DRVCONF = 0x03,
266 MAX8997_HAPTIC_REG_CYCLECONF1 = 0x04,
267 MAX8997_HAPTIC_REG_CYCLECONF2 = 0x05,
268 MAX8997_HAPTIC_REG_SIGCONF1 = 0x06,
269 MAX8997_HAPTIC_REG_SIGCONF2 = 0x07,
270 MAX8997_HAPTIC_REG_SIGCONF3 = 0x08,
271 MAX8997_HAPTIC_REG_SIGCONF4 = 0x09,
272 MAX8997_HAPTIC_REG_SIGDC1 = 0x0a,
273 MAX8997_HAPTIC_REG_SIGDC2 = 0x0b,
274 MAX8997_HAPTIC_REG_SIGPWMDC1 = 0x0c,
275 MAX8997_HAPTIC_REG_SIGPWMDC2 = 0x0d,
276 MAX8997_HAPTIC_REG_SIGPWMDC3 = 0x0e,
277 MAX8997_HAPTIC_REG_SIGPWMDC4 = 0x0f,
278 MAX8997_HAPTIC_REG_MTR_REV = 0x10,
279
280 MAX8997_HAPTIC_REG_END = 0x11,
281};
282
283/* slave addr = 0x0c: using "2nd part" of rev4 datasheet */
284enum max8997_rtc_reg {
285 MAX8997_RTC_CTRLMASK = 0x02,
286 MAX8997_RTC_CTRL = 0x03,
287 MAX8997_RTC_UPDATE1 = 0x04,
288 MAX8997_RTC_UPDATE2 = 0x05,
289 MAX8997_RTC_WTSR_SMPL = 0x06,
290
291 MAX8997_RTC_SEC = 0x10,
292 MAX8997_RTC_MIN = 0x11,
293 MAX8997_RTC_HOUR = 0x12,
294 MAX8997_RTC_DAY_OF_WEEK = 0x13,
295 MAX8997_RTC_MONTH = 0x14,
296 MAX8997_RTC_YEAR = 0x15,
297 MAX8997_RTC_DAY_OF_MONTH = 0x16,
298 MAX8997_RTC_ALARM1_SEC = 0x17,
299 MAX8997_RTC_ALARM1_MIN = 0x18,
300 MAX8997_RTC_ALARM1_HOUR = 0x19,
301 MAX8997_RTC_ALARM1_DAY_OF_WEEK = 0x1a,
302 MAX8997_RTC_ALARM1_MONTH = 0x1b,
303 MAX8997_RTC_ALARM1_YEAR = 0x1c,
304 MAX8997_RTC_ALARM1_DAY_OF_MONTH = 0x1d,
305 MAX8997_RTC_ALARM2_SEC = 0x1e,
306 MAX8997_RTC_ALARM2_MIN = 0x1f,
307 MAX8997_RTC_ALARM2_HOUR = 0x20,
308 MAX8997_RTC_ALARM2_DAY_OF_WEEK = 0x21,
309 MAX8997_RTC_ALARM2_MONTH = 0x22,
310 MAX8997_RTC_ALARM2_YEAR = 0x23,
311 MAX8997_RTC_ALARM2_DAY_OF_MONTH = 0x24,
312};
313
314enum max8997_irq_source {
315 PMIC_INT1 = 0,
316 PMIC_INT2,
317 PMIC_INT3,
318 PMIC_INT4,
319
320 FUEL_GAUGE, /* Ignored (MAX17042 driver handles) */
321
322 MUIC_INT1,
323 MUIC_INT2,
324 MUIC_INT3,
325
326 GPIO_LOW, /* Not implemented */
327 GPIO_HI, /* Not implemented */
328
329 FLASH_STATUS, /* Not implemented */
330
331 MAX8997_IRQ_GROUP_NR,
332};
333
334enum max8997_irq {
335 MAX8997_PMICIRQ_PWRONR,
336 MAX8997_PMICIRQ_PWRONF,
337 MAX8997_PMICIRQ_PWRON1SEC,
338 MAX8997_PMICIRQ_JIGONR,
339 MAX8997_PMICIRQ_JIGONF,
340 MAX8997_PMICIRQ_LOWBAT2,
341 MAX8997_PMICIRQ_LOWBAT1,
342
343 MAX8997_PMICIRQ_JIGR,
344 MAX8997_PMICIRQ_JIGF,
345 MAX8997_PMICIRQ_MR,
346 MAX8997_PMICIRQ_DVS1OK,
347 MAX8997_PMICIRQ_DVS2OK,
348 MAX8997_PMICIRQ_DVS3OK,
349 MAX8997_PMICIRQ_DVS4OK,
350
351 MAX8997_PMICIRQ_CHGINS,
352 MAX8997_PMICIRQ_CHGRM,
353 MAX8997_PMICIRQ_DCINOVP,
354 MAX8997_PMICIRQ_TOPOFFR,
355 MAX8997_PMICIRQ_CHGRSTF,
356 MAX8997_PMICIRQ_MBCHGTMEXPD,
357
358 MAX8997_PMICIRQ_RTC60S,
359 MAX8997_PMICIRQ_RTCA1,
360 MAX8997_PMICIRQ_RTCA2,
361 MAX8997_PMICIRQ_SMPL_INT,
362 MAX8997_PMICIRQ_RTC1S,
363 MAX8997_PMICIRQ_WTSR,
364
365 MAX8997_MUICIRQ_ADCError,
366 MAX8997_MUICIRQ_ADCLow,
367 MAX8997_MUICIRQ_ADC,
368
369 MAX8997_MUICIRQ_VBVolt,
370 MAX8997_MUICIRQ_DBChg,
371 MAX8997_MUICIRQ_DCDTmr,
372 MAX8997_MUICIRQ_ChgDetRun,
373 MAX8997_MUICIRQ_ChgTyp,
374
375 MAX8997_MUICIRQ_OVP,
376
377 MAX8997_IRQ_NR,
378};
379
MyungJoo Ham8de6bc72011-03-24 15:54:45 +0900380#define MAX8997_NUM_GPIO 12
MyungJoo Ham527e7e92011-03-04 15:50:26 +0900381struct max8997_dev {
382 struct device *dev;
Thomas Abraham77b71b32012-11-27 14:04:32 +0530383 struct max8997_platform_data *pdata;
MyungJoo Ham527e7e92011-03-04 15:50:26 +0900384 struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
385 struct i2c_client *rtc; /* slave addr 0x0c */
386 struct i2c_client *haptic; /* slave addr 0x90 */
387 struct i2c_client *muic; /* slave addr 0x4a */
388 struct mutex iolock;
389
Lee Jones05fb7a52014-01-23 14:35:28 +0000390 unsigned long type;
MyungJoo Ham527e7e92011-03-04 15:50:26 +0900391 struct platform_device *battery; /* battery control (not fuel gauge) */
392
MyungJoo Ham8de6bc72011-03-24 15:54:45 +0900393 int irq;
394 int ono;
Thomas Abrahamb41511f2012-07-02 09:02:55 +0900395 struct irq_domain *irq_domain;
MyungJoo Ham8de6bc72011-03-24 15:54:45 +0900396 struct mutex irqlock;
397 int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
398 int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
MyungJoo Ham527e7e92011-03-04 15:50:26 +0900399
400 /* For hibernation */
401 u8 reg_dump[MAX8997_REG_PMIC_END + MAX8997_MUIC_REG_END +
402 MAX8997_HAPTIC_REG_END];
MyungJoo Ham8de6bc72011-03-24 15:54:45 +0900403
404 bool gpio_status[MAX8997_NUM_GPIO];
MyungJoo Ham527e7e92011-03-04 15:50:26 +0900405};
406
407enum max8997_types {
408 TYPE_MAX8997,
409 TYPE_MAX8966,
410};
411
MyungJoo Ham8de6bc72011-03-24 15:54:45 +0900412extern int max8997_irq_init(struct max8997_dev *max8997);
413extern void max8997_irq_exit(struct max8997_dev *max8997);
414extern int max8997_irq_resume(struct max8997_dev *max8997);
415
MyungJoo Ham527e7e92011-03-04 15:50:26 +0900416extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
417extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count,
418 u8 *buf);
419extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
420extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count,
421 u8 *buf);
422extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
423
MyungJoo Ham8de6bc72011-03-24 15:54:45 +0900424#define MAX8997_GPIO_INT_BOTH (0x3 << 4)
425#define MAX8997_GPIO_INT_RISE (0x2 << 4)
426#define MAX8997_GPIO_INT_FALL (0x1 << 4)
427
428#define MAX8997_GPIO_INT_MASK (0x3 << 4)
429#define MAX8997_GPIO_DATA_MASK (0x1 << 2)
MyungJoo Ham527e7e92011-03-04 15:50:26 +0900430#endif /* __LINUX_MFD_MAX8997_PRIV_H */