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Linus Walleijb43d65f2009-06-09 08:11:42 +01001/*
Linus Walleijb43d65f2009-06-09 08:11:42 +01002 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
3 *
Linus Walleijaeef9912012-09-26 16:48:36 +02004 * Copyright (C) 2008-2012 ST-Ericsson AB
Linus Walleijb43d65f2009-06-09 08:11:42 +01005 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
6 *
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 *
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
Linus Walleijb43d65f2009-06-09 08:11:42 +010025#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <linux/ioport.h>
29#include <linux/errno.h>
30#include <linux/interrupt.h>
31#include <linux/spi/spi.h>
Linus Walleijb43d65f2009-06-09 08:11:42 +010032#include <linux/delay.h>
33#include <linux/clk.h>
34#include <linux/err.h>
35#include <linux/amba/bus.h>
36#include <linux/amba/pl022.h>
37#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090038#include <linux/slab.h>
Linus Walleijb1b6b9a2010-09-29 17:31:35 +090039#include <linux/dmaengine.h>
40#include <linux/dma-mapping.h>
41#include <linux/scatterlist.h>
Rabin Vincentbcda6ff2011-06-16 10:14:40 +020042#include <linux/pm_runtime.h>
Roland Stiggef6f46de2012-08-22 15:49:17 +020043#include <linux/gpio.h>
Roland Stigge6d3952a2012-08-22 15:49:18 +020044#include <linux/of_gpio.h>
Patrice Chotard4f5e1b32012-09-19 14:23:46 +020045#include <linux/pinctrl/consumer.h>
Linus Walleijb43d65f2009-06-09 08:11:42 +010046
47/*
48 * This macro is used to define some register default values.
49 * reg is masked with mask, the OR:ed with an (again masked)
50 * val shifted sb steps to the left.
51 */
52#define SSP_WRITE_BITS(reg, val, mask, sb) \
53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
54
55/*
56 * This macro is also used to define some default values.
57 * It will just shift val by sb steps to the left and mask
58 * the result with mask.
59 */
60#define GEN_MASK_BITS(val, mask, sb) \
61 (((val)<<(sb)) & (mask))
62
63#define DRIVE_TX 0
64#define DO_NOT_DRIVE_TX 1
65
66#define DO_NOT_QUEUE_DMA 0
67#define QUEUE_DMA 1
68
69#define RX_TRANSFER 1
70#define TX_TRANSFER 2
71
72/*
73 * Macros to access SSP Registers with their offsets
74 */
75#define SSP_CR0(r) (r + 0x000)
76#define SSP_CR1(r) (r + 0x004)
77#define SSP_DR(r) (r + 0x008)
78#define SSP_SR(r) (r + 0x00C)
79#define SSP_CPSR(r) (r + 0x010)
80#define SSP_IMSC(r) (r + 0x014)
81#define SSP_RIS(r) (r + 0x018)
82#define SSP_MIS(r) (r + 0x01C)
83#define SSP_ICR(r) (r + 0x020)
84#define SSP_DMACR(r) (r + 0x024)
85#define SSP_ITCR(r) (r + 0x080)
86#define SSP_ITIP(r) (r + 0x084)
87#define SSP_ITOP(r) (r + 0x088)
88#define SSP_TDR(r) (r + 0x08C)
89
90#define SSP_PID0(r) (r + 0xFE0)
91#define SSP_PID1(r) (r + 0xFE4)
92#define SSP_PID2(r) (r + 0xFE8)
93#define SSP_PID3(r) (r + 0xFEC)
94
95#define SSP_CID0(r) (r + 0xFF0)
96#define SSP_CID1(r) (r + 0xFF4)
97#define SSP_CID2(r) (r + 0xFF8)
98#define SSP_CID3(r) (r + 0xFFC)
99
100/*
101 * SSP Control Register 0 - SSP_CR0
102 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000103#define SSP_CR0_MASK_DSS (0x0FUL << 0)
104#define SSP_CR0_MASK_FRF (0x3UL << 4)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100105#define SSP_CR0_MASK_SPO (0x1UL << 6)
106#define SSP_CR0_MASK_SPH (0x1UL << 7)
107#define SSP_CR0_MASK_SCR (0xFFUL << 8)
Linus Walleij556f4ae2010-05-05 09:28:15 +0000108
109/*
110 * The ST version of this block moves som bits
111 * in SSP_CR0 and extends it to 32 bits
112 */
113#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
114#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
115#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
116#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
117
Linus Walleijb43d65f2009-06-09 08:11:42 +0100118/*
119 * SSP Control Register 0 - SSP_CR1
120 */
121#define SSP_CR1_MASK_LBM (0x1UL << 0)
122#define SSP_CR1_MASK_SSE (0x1UL << 1)
123#define SSP_CR1_MASK_MS (0x1UL << 2)
124#define SSP_CR1_MASK_SOD (0x1UL << 3)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100125
126/*
Linus Walleij556f4ae2010-05-05 09:28:15 +0000127 * The ST version of this block adds some bits
128 * in SSP_CR1
Linus Walleijb43d65f2009-06-09 08:11:42 +0100129 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000130#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
131#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
132#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
133#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
134#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
Linus Walleij781c7b12010-05-07 08:40:53 +0000135/* This one is only in the PL023 variant */
136#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100137
138/*
139 * SSP Status Register - SSP_SR
140 */
141#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
142#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
143#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000144#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100145#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
146
147/*
148 * SSP Clock Prescale Register - SSP_CPSR
149 */
150#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
151
152/*
153 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
154 */
155#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
156#define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
157#define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
158#define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
159
160/*
161 * SSP Raw Interrupt Status Register - SSP_RIS
162 */
163/* Receive Overrun Raw Interrupt status */
164#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
165/* Receive Timeout Raw Interrupt status */
166#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
167/* Receive FIFO Raw Interrupt status */
168#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
169/* Transmit FIFO Raw Interrupt status */
170#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
171
172/*
173 * SSP Masked Interrupt Status Register - SSP_MIS
174 */
175/* Receive Overrun Masked Interrupt status */
176#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
177/* Receive Timeout Masked Interrupt status */
178#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
179/* Receive FIFO Masked Interrupt status */
180#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
181/* Transmit FIFO Masked Interrupt status */
182#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
183
184/*
185 * SSP Interrupt Clear Register - SSP_ICR
186 */
187/* Receive Overrun Raw Clear Interrupt bit */
188#define SSP_ICR_MASK_RORIC (0x1UL << 0)
189/* Receive Timeout Clear Interrupt bit */
190#define SSP_ICR_MASK_RTIC (0x1UL << 1)
191
192/*
193 * SSP DMA Control Register - SSP_DMACR
194 */
195/* Receive DMA Enable bit */
196#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
197/* Transmit DMA Enable bit */
198#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
199
200/*
201 * SSP Integration Test control Register - SSP_ITCR
202 */
203#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
204#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
205
206/*
207 * SSP Integration Test Input Register - SSP_ITIP
208 */
209#define ITIP_MASK_SSPRXD (0x1UL << 0)
210#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
211#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
212#define ITIP_MASK_RXDMAC (0x1UL << 3)
213#define ITIP_MASK_TXDMAC (0x1UL << 4)
214#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
215
216/*
217 * SSP Integration Test output Register - SSP_ITOP
218 */
219#define ITOP_MASK_SSPTXD (0x1UL << 0)
220#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
221#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
222#define ITOP_MASK_SSPOEn (0x1UL << 3)
223#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
224#define ITOP_MASK_RORINTR (0x1UL << 5)
225#define ITOP_MASK_RTINTR (0x1UL << 6)
226#define ITOP_MASK_RXINTR (0x1UL << 7)
227#define ITOP_MASK_TXINTR (0x1UL << 8)
228#define ITOP_MASK_INTR (0x1UL << 9)
229#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
230#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
231#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
232#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
233
234/*
235 * SSP Test Data Register - SSP_TDR
236 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000237#define TDR_MASK_TESTDATA (0xFFFFFFFF)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100238
239/*
240 * Message State
241 * we use the spi_message.state (void *) pointer to
242 * hold a single state value, that's why all this
243 * (void *) casting is done here.
244 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000245#define STATE_START ((void *) 0)
246#define STATE_RUNNING ((void *) 1)
247#define STATE_DONE ((void *) 2)
248#define STATE_ERROR ((void *) -1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100249
250/*
Linus Walleijb43d65f2009-06-09 08:11:42 +0100251 * SSP State - Whether Enabled or Disabled
252 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000253#define SSP_DISABLED (0)
254#define SSP_ENABLED (1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100255
256/*
257 * SSP DMA State - Whether DMA Enabled or Disabled
258 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000259#define SSP_DMA_DISABLED (0)
260#define SSP_DMA_ENABLED (1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100261
262/*
263 * SSP Clock Defaults
264 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000265#define SSP_DEFAULT_CLKRATE 0x2
266#define SSP_DEFAULT_PRESCALE 0x40
Linus Walleijb43d65f2009-06-09 08:11:42 +0100267
268/*
269 * SSP Clock Parameter ranges
270 */
271#define CPSDVR_MIN 0x02
272#define CPSDVR_MAX 0xFE
273#define SCR_MIN 0x00
274#define SCR_MAX 0xFF
275
276/*
277 * SSP Interrupt related Macros
278 */
279#define DEFAULT_SSP_REG_IMSC 0x0UL
280#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
281#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
282
283#define CLEAR_ALL_INTERRUPTS 0x3
284
Magnus Templinga18c2662011-05-19 18:05:34 +0200285#define SPI_POLLING_TIMEOUT 1000
286
Linus Walleijb43d65f2009-06-09 08:11:42 +0100287/*
288 * The type of reading going on on this chip
289 */
290enum ssp_reading {
291 READING_NULL,
292 READING_U8,
293 READING_U16,
294 READING_U32
295};
296
297/**
298 * The type of writing going on on this chip
299 */
300enum ssp_writing {
301 WRITING_NULL,
302 WRITING_U8,
303 WRITING_U16,
304 WRITING_U32
305};
306
307/**
308 * struct vendor_data - vendor-specific config parameters
309 * for PL022 derivates
310 * @fifodepth: depth of FIFOs (both)
311 * @max_bpw: maximum number of bits per word
312 * @unidir: supports unidirection transfers
Linus Walleij556f4ae2010-05-05 09:28:15 +0000313 * @extended_cr: 32 bit wide control register 0 with extra
314 * features and extra features in CR1 as found in the ST variants
Linus Walleij781c7b12010-05-07 08:40:53 +0000315 * @pl023: supports a subset of the ST extensions called "PL023"
Linus Walleijb43d65f2009-06-09 08:11:42 +0100316 */
317struct vendor_data {
318 int fifodepth;
319 int max_bpw;
320 bool unidir;
Linus Walleij556f4ae2010-05-05 09:28:15 +0000321 bool extended_cr;
Linus Walleij781c7b12010-05-07 08:40:53 +0000322 bool pl023;
Philippe Langlais06fb01f2011-03-23 11:05:16 +0100323 bool loopback;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100324};
325
326/**
327 * struct pl022 - This is the private SSP driver data structure
328 * @adev: AMBA device model hookup
Linus Walleij12e8b322011-02-08 13:03:55 +0100329 * @vendor: vendor data for the IP block
330 * @phybase: the physical memory where the SSP device resides
331 * @virtbase: the virtual memory where the SSP is mapped
332 * @clk: outgoing clock "SPICLK" for the SPI bus
Linus Walleijb43d65f2009-06-09 08:11:42 +0100333 * @master: SPI framework hookup
334 * @master_info: controller-specific data from machine setup
Chris Blair14af60b2012-02-02 13:59:34 +0100335 * @kworker: thread struct for message pump
336 * @kworker_task: pointer to task for message pump kworker thread
337 * @pump_messages: work struct for scheduling work to the message pump
Linus Walleij12e8b322011-02-08 13:03:55 +0100338 * @queue_lock: spinlock to syncronise access to message queue
339 * @queue: message queue
Chris Blair14af60b2012-02-02 13:59:34 +0100340 * @busy: message pump is busy
341 * @running: message pump is running
Linus Walleijb43d65f2009-06-09 08:11:42 +0100342 * @pump_transfers: Tasklet used in Interrupt Transfer mode
343 * @cur_msg: Pointer to current spi_message being processed
344 * @cur_transfer: Pointer to current spi_transfer
345 * @cur_chip: pointer to current clients chip(assigned from controller_state)
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530346 * @next_msg_cs_active: the next message in the queue has been examined
347 * and it was found that it uses the same chip select as the previous
348 * message, so we left it active after the previous transfer, and it's
349 * active already.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100350 * @tx: current position in TX buffer to be read
351 * @tx_end: end position in TX buffer to be read
352 * @rx: current position in RX buffer to be written
353 * @rx_end: end position in RX buffer to be written
Linus Walleij12e8b322011-02-08 13:03:55 +0100354 * @read: the type of read currently going on
355 * @write: the type of write currently going on
356 * @exp_fifo_level: expected FIFO level
357 * @dma_rx_channel: optional channel for RX DMA
358 * @dma_tx_channel: optional channel for TX DMA
359 * @sgt_rx: scattertable for the RX transfer
360 * @sgt_tx: scattertable for the TX transfer
361 * @dummypage: a dummy page used for driving data on the bus with DMA
Roland Stiggef6f46de2012-08-22 15:49:17 +0200362 * @cur_cs: current chip select (gpio)
363 * @chipselects: list of chipselects (gpios)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100364 */
365struct pl022 {
366 struct amba_device *adev;
367 struct vendor_data *vendor;
368 resource_size_t phybase;
369 void __iomem *virtbase;
370 struct clk *clk;
371 struct spi_master *master;
372 struct pl022_ssp_controller *master_info;
Linus Walleijffbbdd212012-02-22 10:05:38 +0100373 /* Message per-transfer pump */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100374 struct tasklet_struct pump_transfers;
375 struct spi_message *cur_msg;
376 struct spi_transfer *cur_transfer;
377 struct chip_data *cur_chip;
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530378 bool next_msg_cs_active;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100379 void *tx;
380 void *tx_end;
381 void *rx;
382 void *rx_end;
383 enum ssp_reading read;
384 enum ssp_writing write;
Linus Walleijfc054752010-01-22 13:53:30 +0100385 u32 exp_fifo_level;
Linus Walleij083be3f2011-06-16 10:14:28 +0200386 enum ssp_rx_level_trig rx_lev_trig;
387 enum ssp_tx_level_trig tx_lev_trig;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900388 /* DMA settings */
389#ifdef CONFIG_DMA_ENGINE
390 struct dma_chan *dma_rx_channel;
391 struct dma_chan *dma_tx_channel;
392 struct sg_table sgt_rx;
393 struct sg_table sgt_tx;
394 char *dummypage;
Linus Walleijffbbdd212012-02-22 10:05:38 +0100395 bool dma_running;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900396#endif
Roland Stiggef6f46de2012-08-22 15:49:17 +0200397 int cur_cs;
398 int *chipselects;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100399};
400
401/**
402 * struct chip_data - To maintain runtime state of SSP for each client chip
Linus Walleij556f4ae2010-05-05 09:28:15 +0000403 * @cr0: Value of control register CR0 of SSP - on later ST variants this
404 * register is 32 bits wide rather than just 16
Linus Walleijb43d65f2009-06-09 08:11:42 +0100405 * @cr1: Value of control register CR1 of SSP
406 * @dmacr: Value of DMA control Register of SSP
407 * @cpsr: Value of Clock prescale register
408 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
409 * @enable_dma: Whether to enable DMA or not
Linus Walleijb43d65f2009-06-09 08:11:42 +0100410 * @read: function ptr to be used to read when doing xfer for this chip
Linus Walleij12e8b322011-02-08 13:03:55 +0100411 * @write: function ptr to be used to write when doing xfer for this chip
Linus Walleijb43d65f2009-06-09 08:11:42 +0100412 * @cs_control: chip select callback provided by chip
413 * @xfer_type: polling/interrupt/DMA
414 *
415 * Runtime state of the SSP controller, maintained per chip,
416 * This would be set according to the current message that would be served
417 */
418struct chip_data {
Linus Walleij556f4ae2010-05-05 09:28:15 +0000419 u32 cr0;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100420 u16 cr1;
421 u16 dmacr;
422 u16 cpsr;
423 u8 n_bytes;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900424 bool enable_dma;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100425 enum ssp_reading read;
426 enum ssp_writing write;
427 void (*cs_control) (u32 command);
428 int xfer_type;
429};
430
431/**
432 * null_cs_control - Dummy chip select function
433 * @command: select/delect the chip
434 *
435 * If no chip select function is provided by client this is used as dummy
436 * chip select
437 */
438static void null_cs_control(u32 command)
439{
440 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
441}
442
Roland Stiggef6f46de2012-08-22 15:49:17 +0200443static void pl022_cs_control(struct pl022 *pl022, u32 command)
444{
445 if (gpio_is_valid(pl022->cur_cs))
446 gpio_set_value(pl022->cur_cs, command);
447 else
448 pl022->cur_chip->cs_control(command);
449}
450
Linus Walleijb43d65f2009-06-09 08:11:42 +0100451/**
452 * giveback - current spi_message is over, schedule next message and call
453 * callback of this message. Assumes that caller already
454 * set message->status; dma and pio irqs are blocked
455 * @pl022: SSP driver private data structure
456 */
457static void giveback(struct pl022 *pl022)
458{
459 struct spi_transfer *last_transfer;
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530460 pl022->next_msg_cs_active = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100461
Axel Lin23e2c2a2014-02-12 22:13:27 +0800462 last_transfer = list_last_entry(&pl022->cur_msg->transfers,
463 struct spi_transfer, transfer_list);
Linus Walleijb43d65f2009-06-09 08:11:42 +0100464
465 /* Delay if requested before any change in chip select */
466 if (last_transfer->delay_usecs)
467 /*
468 * FIXME: This runs in interrupt context.
469 * Is this really smart?
470 */
471 udelay(last_transfer->delay_usecs);
472
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530473 if (!last_transfer->cs_change) {
Linus Walleijb43d65f2009-06-09 08:11:42 +0100474 struct spi_message *next_msg;
475
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530476 /*
477 * cs_change was not set. We can keep the chip select
478 * enabled if there is message in the queue and it is
479 * for the same spi device.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100480 *
481 * We cannot postpone this until pump_messages, because
482 * after calling msg->complete (below) the driver that
483 * sent the current message could be unloaded, which
484 * could invalidate the cs_control() callback...
485 */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100486 /* get a pointer to the next message, if any */
Linus Walleijffbbdd212012-02-22 10:05:38 +0100487 next_msg = spi_get_next_queued_message(pl022->master);
Linus Walleijb43d65f2009-06-09 08:11:42 +0100488
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530489 /*
490 * see if the next and current messages point
491 * to the same spi device.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100492 */
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530493 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100494 next_msg = NULL;
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530495 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
Roland Stiggef6f46de2012-08-22 15:49:17 +0200496 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530497 else
498 pl022->next_msg_cs_active = true;
Linus Walleijffbbdd212012-02-22 10:05:38 +0100499
Linus Walleijb43d65f2009-06-09 08:11:42 +0100500 }
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530501
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530502 pl022->cur_msg = NULL;
503 pl022->cur_transfer = NULL;
504 pl022->cur_chip = NULL;
Linus Walleijffbbdd212012-02-22 10:05:38 +0100505 spi_finalize_current_message(pl022->master);
Virupax Sadashivpetimathfd316942012-06-12 15:10:58 +0200506
507 /* disable the SPI/SSP operation */
508 writew((readw(SSP_CR1(pl022->virtbase)) &
509 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
510
Linus Walleijb43d65f2009-06-09 08:11:42 +0100511}
512
513/**
514 * flush - flush the FIFO to reach a clean state
515 * @pl022: SSP driver private data structure
516 */
517static int flush(struct pl022 *pl022)
518{
519 unsigned long limit = loops_per_jiffy << 1;
520
521 dev_dbg(&pl022->adev->dev, "flush\n");
522 do {
523 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
524 readw(SSP_DR(pl022->virtbase));
525 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
Linus Walleijfc054752010-01-22 13:53:30 +0100526
527 pl022->exp_fifo_level = 0;
528
Linus Walleijb43d65f2009-06-09 08:11:42 +0100529 return limit;
530}
531
532/**
533 * restore_state - Load configuration of current chip
534 * @pl022: SSP driver private data structure
535 */
536static void restore_state(struct pl022 *pl022)
537{
538 struct chip_data *chip = pl022->cur_chip;
539
Linus Walleij556f4ae2010-05-05 09:28:15 +0000540 if (pl022->vendor->extended_cr)
541 writel(chip->cr0, SSP_CR0(pl022->virtbase));
542 else
543 writew(chip->cr0, SSP_CR0(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +0100544 writew(chip->cr1, SSP_CR1(pl022->virtbase));
545 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
546 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
547 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
548 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
549}
550
Linus Walleijb43d65f2009-06-09 08:11:42 +0100551/*
552 * Default SSP Register Values
553 */
554#define DEFAULT_SSP_REG_CR0 ( \
555 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000556 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100557 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
Linus Walleijee2b8052009-08-15 15:12:05 +0100558 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000559 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
560)
561
562/* ST versions have slightly different bit layout */
563#define DEFAULT_SSP_REG_CR0_ST ( \
564 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
565 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
566 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
567 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
568 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
569 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
570 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100571)
572
Linus Walleij781c7b12010-05-07 08:40:53 +0000573/* The PL023 version is slightly different again */
574#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
575 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
576 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
577 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
578 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
579)
580
Linus Walleijb43d65f2009-06-09 08:11:42 +0100581#define DEFAULT_SSP_REG_CR1 ( \
582 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
583 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
584 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000585 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100586)
587
Linus Walleij556f4ae2010-05-05 09:28:15 +0000588/* ST versions extend this register to use all 16 bits */
589#define DEFAULT_SSP_REG_CR1_ST ( \
590 DEFAULT_SSP_REG_CR1 | \
591 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
592 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
593 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
594 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
595 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
596)
597
Linus Walleij781c7b12010-05-07 08:40:53 +0000598/*
599 * The PL023 variant has further differences: no loopback mode, no microwire
600 * support, and a new clock feedback delay setting.
601 */
602#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
603 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
604 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
605 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
606 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
607 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
608 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
609 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
610 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
611)
Linus Walleij556f4ae2010-05-05 09:28:15 +0000612
Linus Walleijb43d65f2009-06-09 08:11:42 +0100613#define DEFAULT_SSP_REG_CPSR ( \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000614 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100615)
616
617#define DEFAULT_SSP_REG_DMACR (\
618 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
619 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
620)
621
Linus Walleij781c7b12010-05-07 08:40:53 +0000622/**
623 * load_ssp_default_config - Load default configuration for SSP
624 * @pl022: SSP driver private data structure
625 */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100626static void load_ssp_default_config(struct pl022 *pl022)
627{
Linus Walleij781c7b12010-05-07 08:40:53 +0000628 if (pl022->vendor->pl023) {
629 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
630 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
631 } else if (pl022->vendor->extended_cr) {
Linus Walleij556f4ae2010-05-05 09:28:15 +0000632 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
633 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
634 } else {
635 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
636 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
637 }
Linus Walleijb43d65f2009-06-09 08:11:42 +0100638 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
639 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
640 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
641 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
642}
643
644/**
645 * This will write to TX and read from RX according to the parameters
646 * set in pl022.
647 */
648static void readwriter(struct pl022 *pl022)
649{
650
651 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300652 * The FIFO depth is different between primecell variants.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100653 * I believe filling in too much in the FIFO might cause
654 * errons in 8bit wide transfers on ARM variants (just 8 words
655 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
656 *
Linus Walleijfc054752010-01-22 13:53:30 +0100657 * To prevent this issue, the TX FIFO is only filled to the
658 * unused RX FIFO fill length, regardless of what the TX
659 * FIFO status flag indicates.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100660 */
661 dev_dbg(&pl022->adev->dev,
662 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
663 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
664
665 /* Read as much as you can */
666 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
667 && (pl022->rx < pl022->rx_end)) {
668 switch (pl022->read) {
669 case READING_NULL:
670 readw(SSP_DR(pl022->virtbase));
671 break;
672 case READING_U8:
673 *(u8 *) (pl022->rx) =
674 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
675 break;
676 case READING_U16:
677 *(u16 *) (pl022->rx) =
678 (u16) readw(SSP_DR(pl022->virtbase));
679 break;
680 case READING_U32:
681 *(u32 *) (pl022->rx) =
682 readl(SSP_DR(pl022->virtbase));
683 break;
684 }
685 pl022->rx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100686 pl022->exp_fifo_level--;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100687 }
688 /*
Linus Walleijfc054752010-01-22 13:53:30 +0100689 * Write as much as possible up to the RX FIFO size
Linus Walleijb43d65f2009-06-09 08:11:42 +0100690 */
Linus Walleijfc054752010-01-22 13:53:30 +0100691 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100692 && (pl022->tx < pl022->tx_end)) {
693 switch (pl022->write) {
694 case WRITING_NULL:
695 writew(0x0, SSP_DR(pl022->virtbase));
696 break;
697 case WRITING_U8:
698 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
699 break;
700 case WRITING_U16:
701 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
702 break;
703 case WRITING_U32:
704 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
705 break;
706 }
707 pl022->tx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100708 pl022->exp_fifo_level++;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100709 /*
710 * This inner reader takes care of things appearing in the RX
711 * FIFO as we're transmitting. This will happen a lot since the
712 * clock starts running when you put things into the TX FIFO,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300713 * and then things are continuously clocked into the RX FIFO.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100714 */
715 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
716 && (pl022->rx < pl022->rx_end)) {
717 switch (pl022->read) {
718 case READING_NULL:
719 readw(SSP_DR(pl022->virtbase));
720 break;
721 case READING_U8:
722 *(u8 *) (pl022->rx) =
723 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
724 break;
725 case READING_U16:
726 *(u16 *) (pl022->rx) =
727 (u16) readw(SSP_DR(pl022->virtbase));
728 break;
729 case READING_U32:
730 *(u32 *) (pl022->rx) =
731 readl(SSP_DR(pl022->virtbase));
732 break;
733 }
734 pl022->rx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100735 pl022->exp_fifo_level--;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100736 }
737 }
738 /*
739 * When we exit here the TX FIFO should be full and the RX FIFO
740 * should be empty
741 */
742}
743
Linus Walleijb43d65f2009-06-09 08:11:42 +0100744/**
745 * next_transfer - Move to the Next transfer in the current spi message
746 * @pl022: SSP driver private data structure
747 *
748 * This function moves though the linked list of spi transfers in the
749 * current spi message and returns with the state of current spi
750 * message i.e whether its last transfer is done(STATE_DONE) or
751 * Next transfer is ready(STATE_RUNNING)
752 */
753static void *next_transfer(struct pl022 *pl022)
754{
755 struct spi_message *msg = pl022->cur_msg;
756 struct spi_transfer *trans = pl022->cur_transfer;
757
758 /* Move to next transfer */
759 if (trans->transfer_list.next != &msg->transfers) {
760 pl022->cur_transfer =
761 list_entry(trans->transfer_list.next,
762 struct spi_transfer, transfer_list);
763 return STATE_RUNNING;
764 }
765 return STATE_DONE;
766}
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900767
768/*
769 * This DMA functionality is only compiled in if we have
770 * access to the generic DMA devices/DMA engine.
771 */
772#ifdef CONFIG_DMA_ENGINE
773static void unmap_free_dma_scatter(struct pl022 *pl022)
774{
775 /* Unmap and free the SG tables */
Linus Walleijb7298892010-12-22 23:13:07 +0100776 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900777 pl022->sgt_tx.nents, DMA_TO_DEVICE);
Linus Walleijb7298892010-12-22 23:13:07 +0100778 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900779 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
780 sg_free_table(&pl022->sgt_rx);
781 sg_free_table(&pl022->sgt_tx);
782}
783
784static void dma_callback(void *data)
785{
786 struct pl022 *pl022 = data;
787 struct spi_message *msg = pl022->cur_msg;
788
789 BUG_ON(!pl022->sgt_rx.sgl);
790
791#ifdef VERBOSE_DEBUG
792 /*
793 * Optionally dump out buffers to inspect contents, this is
794 * good if you want to convince yourself that the loopback
795 * read/write contents are the same, when adopting to a new
796 * DMA engine.
797 */
798 {
799 struct scatterlist *sg;
800 unsigned int i;
801
802 dma_sync_sg_for_cpu(&pl022->adev->dev,
803 pl022->sgt_rx.sgl,
804 pl022->sgt_rx.nents,
805 DMA_FROM_DEVICE);
806
807 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
808 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
809 print_hex_dump(KERN_ERR, "SPI RX: ",
810 DUMP_PREFIX_OFFSET,
811 16,
812 1,
813 sg_virt(sg),
814 sg_dma_len(sg),
815 1);
816 }
817 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
818 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
819 print_hex_dump(KERN_ERR, "SPI TX: ",
820 DUMP_PREFIX_OFFSET,
821 16,
822 1,
823 sg_virt(sg),
824 sg_dma_len(sg),
825 1);
826 }
827 }
828#endif
829
830 unmap_free_dma_scatter(pl022);
831
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300832 /* Update total bytes transferred */
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900833 msg->actual_length += pl022->cur_transfer->len;
834 if (pl022->cur_transfer->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +0200835 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900836
837 /* Move to next transfer */
838 msg->state = next_transfer(pl022);
839 tasklet_schedule(&pl022->pump_transfers);
840}
841
842static void setup_dma_scatter(struct pl022 *pl022,
843 void *buffer,
844 unsigned int length,
845 struct sg_table *sgtab)
846{
847 struct scatterlist *sg;
848 int bytesleft = length;
849 void *bufp = buffer;
850 int mapbytes;
851 int i;
852
853 if (buffer) {
854 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
855 /*
856 * If there are less bytes left than what fits
857 * in the current page (plus page alignment offset)
858 * we just feed in this, else we stuff in as much
859 * as we can.
860 */
861 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
862 mapbytes = bytesleft;
863 else
864 mapbytes = PAGE_SIZE - offset_in_page(bufp);
865 sg_set_page(sg, virt_to_page(bufp),
866 mapbytes, offset_in_page(bufp));
867 bufp += mapbytes;
868 bytesleft -= mapbytes;
869 dev_dbg(&pl022->adev->dev,
870 "set RX/TX target page @ %p, %d bytes, %d left\n",
871 bufp, mapbytes, bytesleft);
872 }
873 } else {
874 /* Map the dummy buffer on every page */
875 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
876 if (bytesleft < PAGE_SIZE)
877 mapbytes = bytesleft;
878 else
879 mapbytes = PAGE_SIZE;
880 sg_set_page(sg, virt_to_page(pl022->dummypage),
881 mapbytes, 0);
882 bytesleft -= mapbytes;
883 dev_dbg(&pl022->adev->dev,
884 "set RX/TX to dummy page %d bytes, %d left\n",
885 mapbytes, bytesleft);
886
887 }
888 }
889 BUG_ON(bytesleft);
890}
891
892/**
893 * configure_dma - configures the channels for the next transfer
894 * @pl022: SSP driver's private data structure
895 */
896static int configure_dma(struct pl022 *pl022)
897{
898 struct dma_slave_config rx_conf = {
899 .src_addr = SSP_DR(pl022->phybase),
Vinod Koula485df42011-10-14 10:47:38 +0530900 .direction = DMA_DEV_TO_MEM,
Viresh Kumar258aea72012-02-01 16:12:19 +0530901 .device_fc = false,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900902 };
903 struct dma_slave_config tx_conf = {
904 .dst_addr = SSP_DR(pl022->phybase),
Vinod Koula485df42011-10-14 10:47:38 +0530905 .direction = DMA_MEM_TO_DEV,
Viresh Kumar258aea72012-02-01 16:12:19 +0530906 .device_fc = false,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900907 };
908 unsigned int pages;
909 int ret;
Linus Walleij082086f2010-12-22 23:13:37 +0100910 int rx_sglen, tx_sglen;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900911 struct dma_chan *rxchan = pl022->dma_rx_channel;
912 struct dma_chan *txchan = pl022->dma_tx_channel;
913 struct dma_async_tx_descriptor *rxdesc;
914 struct dma_async_tx_descriptor *txdesc;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900915
916 /* Check that the channels are available */
917 if (!rxchan || !txchan)
918 return -ENODEV;
919
Linus Walleij083be3f2011-06-16 10:14:28 +0200920 /*
921 * If supplied, the DMA burstsize should equal the FIFO trigger level.
922 * Notice that the DMA engine uses one-to-one mapping. Since we can
923 * not trigger on 2 elements this needs explicit mapping rather than
924 * calculation.
925 */
926 switch (pl022->rx_lev_trig) {
927 case SSP_RX_1_OR_MORE_ELEM:
928 rx_conf.src_maxburst = 1;
929 break;
930 case SSP_RX_4_OR_MORE_ELEM:
931 rx_conf.src_maxburst = 4;
932 break;
933 case SSP_RX_8_OR_MORE_ELEM:
934 rx_conf.src_maxburst = 8;
935 break;
936 case SSP_RX_16_OR_MORE_ELEM:
937 rx_conf.src_maxburst = 16;
938 break;
939 case SSP_RX_32_OR_MORE_ELEM:
940 rx_conf.src_maxburst = 32;
941 break;
942 default:
943 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
944 break;
945 }
946
947 switch (pl022->tx_lev_trig) {
948 case SSP_TX_1_OR_MORE_EMPTY_LOC:
949 tx_conf.dst_maxburst = 1;
950 break;
951 case SSP_TX_4_OR_MORE_EMPTY_LOC:
952 tx_conf.dst_maxburst = 4;
953 break;
954 case SSP_TX_8_OR_MORE_EMPTY_LOC:
955 tx_conf.dst_maxburst = 8;
956 break;
957 case SSP_TX_16_OR_MORE_EMPTY_LOC:
958 tx_conf.dst_maxburst = 16;
959 break;
960 case SSP_TX_32_OR_MORE_EMPTY_LOC:
961 tx_conf.dst_maxburst = 32;
962 break;
963 default:
964 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
965 break;
966 }
967
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900968 switch (pl022->read) {
969 case READING_NULL:
970 /* Use the same as for writing */
971 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
972 break;
973 case READING_U8:
974 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
975 break;
976 case READING_U16:
977 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
978 break;
979 case READING_U32:
980 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
981 break;
982 }
983
984 switch (pl022->write) {
985 case WRITING_NULL:
986 /* Use the same as for reading */
987 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
988 break;
989 case WRITING_U8:
990 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
991 break;
992 case WRITING_U16:
993 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
994 break;
995 case WRITING_U32:
Joe Perchesbc3f67a2010-11-14 19:04:47 -0800996 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900997 break;
998 }
999
1000 /* SPI pecularity: we need to read and write the same width */
1001 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1002 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1003 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1004 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1005 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1006
Linus Walleijecd442f2011-02-08 13:03:12 +01001007 dmaengine_slave_config(rxchan, &rx_conf);
1008 dmaengine_slave_config(txchan, &tx_conf);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001009
1010 /* Create sglists for the transfers */
Viresh Kumarb1815652011-08-10 17:12:11 +05301011 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001012 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1013
Viresh Kumar538a18d2011-08-10 14:20:55 +05301014 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001015 if (ret)
1016 goto err_alloc_rx_sg;
1017
Viresh Kumar538a18d2011-08-10 14:20:55 +05301018 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001019 if (ret)
1020 goto err_alloc_tx_sg;
1021
1022 /* Fill in the scatterlists for the RX+TX buffers */
1023 setup_dma_scatter(pl022, pl022->rx,
1024 pl022->cur_transfer->len, &pl022->sgt_rx);
1025 setup_dma_scatter(pl022, pl022->tx,
1026 pl022->cur_transfer->len, &pl022->sgt_tx);
1027
1028 /* Map DMA buffers */
Linus Walleij082086f2010-12-22 23:13:37 +01001029 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001030 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
Linus Walleij082086f2010-12-22 23:13:37 +01001031 if (!rx_sglen)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001032 goto err_rx_sgmap;
1033
Linus Walleij082086f2010-12-22 23:13:37 +01001034 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001035 pl022->sgt_tx.nents, DMA_TO_DEVICE);
Linus Walleij082086f2010-12-22 23:13:37 +01001036 if (!tx_sglen)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001037 goto err_tx_sgmap;
1038
1039 /* Send both scatterlists */
Alexandre Bounine16052822012-03-08 16:11:18 -05001040 rxdesc = dmaengine_prep_slave_sg(rxchan,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001041 pl022->sgt_rx.sgl,
Linus Walleij082086f2010-12-22 23:13:37 +01001042 rx_sglen,
Vinod Koula485df42011-10-14 10:47:38 +05301043 DMA_DEV_TO_MEM,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001044 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1045 if (!rxdesc)
1046 goto err_rxdesc;
1047
Alexandre Bounine16052822012-03-08 16:11:18 -05001048 txdesc = dmaengine_prep_slave_sg(txchan,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001049 pl022->sgt_tx.sgl,
Linus Walleij082086f2010-12-22 23:13:37 +01001050 tx_sglen,
Vinod Koula485df42011-10-14 10:47:38 +05301051 DMA_MEM_TO_DEV,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001052 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1053 if (!txdesc)
1054 goto err_txdesc;
1055
1056 /* Put the callback on the RX transfer only, that should finish last */
1057 rxdesc->callback = dma_callback;
1058 rxdesc->callback_param = pl022;
1059
1060 /* Submit and fire RX and TX with TX last so we're ready to read! */
Linus Walleijecd442f2011-02-08 13:03:12 +01001061 dmaengine_submit(rxdesc);
1062 dmaengine_submit(txdesc);
1063 dma_async_issue_pending(rxchan);
1064 dma_async_issue_pending(txchan);
Linus Walleijffbbdd212012-02-22 10:05:38 +01001065 pl022->dma_running = true;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001066
1067 return 0;
1068
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001069err_txdesc:
Linus Walleijecd442f2011-02-08 13:03:12 +01001070 dmaengine_terminate_all(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001071err_rxdesc:
Linus Walleijecd442f2011-02-08 13:03:12 +01001072 dmaengine_terminate_all(rxchan);
Linus Walleijb7298892010-12-22 23:13:07 +01001073 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001074 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1075err_tx_sgmap:
Linus Walleijb7298892010-12-22 23:13:07 +01001076 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001077 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1078err_rx_sgmap:
1079 sg_free_table(&pl022->sgt_tx);
1080err_alloc_tx_sg:
1081 sg_free_table(&pl022->sgt_rx);
1082err_alloc_rx_sg:
1083 return -ENOMEM;
1084}
1085
Grant Likelyfd4a3192012-12-07 16:57:14 +00001086static int pl022_dma_probe(struct pl022 *pl022)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001087{
1088 dma_cap_mask_t mask;
1089
1090 /* Try to acquire a generic DMA engine slave channel */
1091 dma_cap_zero(mask);
1092 dma_cap_set(DMA_SLAVE, mask);
1093 /*
1094 * We need both RX and TX channels to do DMA, else do none
1095 * of them.
1096 */
1097 pl022->dma_rx_channel = dma_request_channel(mask,
1098 pl022->master_info->dma_filter,
1099 pl022->master_info->dma_rx_param);
1100 if (!pl022->dma_rx_channel) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301101 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001102 goto err_no_rxchan;
1103 }
1104
1105 pl022->dma_tx_channel = dma_request_channel(mask,
1106 pl022->master_info->dma_filter,
1107 pl022->master_info->dma_tx_param);
1108 if (!pl022->dma_tx_channel) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301109 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001110 goto err_no_txchan;
1111 }
1112
1113 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1114 if (!pl022->dummypage) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301115 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001116 goto err_no_dummypage;
1117 }
1118
1119 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1120 dma_chan_name(pl022->dma_rx_channel),
1121 dma_chan_name(pl022->dma_tx_channel));
1122
1123 return 0;
1124
1125err_no_dummypage:
1126 dma_release_channel(pl022->dma_tx_channel);
1127err_no_txchan:
1128 dma_release_channel(pl022->dma_rx_channel);
1129 pl022->dma_rx_channel = NULL;
1130err_no_rxchan:
Viresh Kumar43c64012011-05-16 09:40:10 +05301131 dev_err(&pl022->adev->dev,
1132 "Failed to work in dma mode, work without dma!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001133 return -ENODEV;
1134}
1135
Arnd Bergmanndc715452013-01-28 16:24:37 +00001136static int pl022_dma_autoprobe(struct pl022 *pl022)
1137{
1138 struct device *dev = &pl022->adev->dev;
1139
1140 /* automatically configure DMA channels from platform, normally using DT */
1141 pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
1142 if (!pl022->dma_rx_channel)
1143 goto err_no_rxchan;
1144
1145 pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
1146 if (!pl022->dma_tx_channel)
1147 goto err_no_txchan;
1148
1149 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1150 if (!pl022->dummypage)
1151 goto err_no_dummypage;
1152
1153 return 0;
1154
1155err_no_dummypage:
1156 dma_release_channel(pl022->dma_tx_channel);
1157 pl022->dma_tx_channel = NULL;
1158err_no_txchan:
1159 dma_release_channel(pl022->dma_rx_channel);
1160 pl022->dma_rx_channel = NULL;
1161err_no_rxchan:
1162 return -ENODEV;
1163}
1164
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001165static void terminate_dma(struct pl022 *pl022)
1166{
1167 struct dma_chan *rxchan = pl022->dma_rx_channel;
1168 struct dma_chan *txchan = pl022->dma_tx_channel;
1169
Linus Walleijecd442f2011-02-08 13:03:12 +01001170 dmaengine_terminate_all(rxchan);
1171 dmaengine_terminate_all(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001172 unmap_free_dma_scatter(pl022);
Linus Walleijffbbdd212012-02-22 10:05:38 +01001173 pl022->dma_running = false;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001174}
1175
1176static void pl022_dma_remove(struct pl022 *pl022)
1177{
Linus Walleijffbbdd212012-02-22 10:05:38 +01001178 if (pl022->dma_running)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001179 terminate_dma(pl022);
1180 if (pl022->dma_tx_channel)
1181 dma_release_channel(pl022->dma_tx_channel);
1182 if (pl022->dma_rx_channel)
1183 dma_release_channel(pl022->dma_rx_channel);
1184 kfree(pl022->dummypage);
1185}
1186
1187#else
1188static inline int configure_dma(struct pl022 *pl022)
1189{
1190 return -ENODEV;
1191}
1192
Arnd Bergmanndc715452013-01-28 16:24:37 +00001193static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1194{
1195 return 0;
1196}
1197
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001198static inline int pl022_dma_probe(struct pl022 *pl022)
1199{
1200 return 0;
1201}
1202
1203static inline void pl022_dma_remove(struct pl022 *pl022)
1204{
1205}
1206#endif
1207
Linus Walleijb43d65f2009-06-09 08:11:42 +01001208/**
1209 * pl022_interrupt_handler - Interrupt handler for SSP controller
1210 *
1211 * This function handles interrupts generated for an interrupt based transfer.
1212 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1213 * current message's state as STATE_ERROR and schedule the tasklet
1214 * pump_transfers which will do the postprocessing of the current message by
1215 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1216 * more data, and writes data in TX FIFO till it is not full. If we complete
1217 * the transfer we move to the next transfer and schedule the tasklet.
1218 */
1219static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1220{
1221 struct pl022 *pl022 = dev_id;
1222 struct spi_message *msg = pl022->cur_msg;
1223 u16 irq_status = 0;
1224 u16 flag = 0;
1225
1226 if (unlikely(!msg)) {
1227 dev_err(&pl022->adev->dev,
1228 "bad message state in interrupt handler");
1229 /* Never fail */
1230 return IRQ_HANDLED;
1231 }
1232
1233 /* Read the Interrupt Status Register */
1234 irq_status = readw(SSP_MIS(pl022->virtbase));
1235
1236 if (unlikely(!irq_status))
1237 return IRQ_NONE;
1238
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001239 /*
1240 * This handles the FIFO interrupts, the timeout
1241 * interrupts are flatly ignored, they cannot be
1242 * trusted.
1243 */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001244 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1245 /*
1246 * Overrun interrupt - bail out since our Data has been
1247 * corrupted
1248 */
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001249 dev_err(&pl022->adev->dev, "FIFO overrun\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001250 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1251 dev_err(&pl022->adev->dev,
1252 "RXFIFO is full\n");
1253 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1254 dev_err(&pl022->adev->dev,
1255 "TXFIFO is full\n");
1256
1257 /*
1258 * Disable and clear interrupts, disable SSP,
1259 * mark message with bad status so it can be
1260 * retried.
1261 */
1262 writew(DISABLE_ALL_INTERRUPTS,
1263 SSP_IMSC(pl022->virtbase));
1264 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1265 writew((readw(SSP_CR1(pl022->virtbase)) &
1266 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1267 msg->state = STATE_ERROR;
1268
1269 /* Schedule message queue handler */
1270 tasklet_schedule(&pl022->pump_transfers);
1271 return IRQ_HANDLED;
1272 }
1273
1274 readwriter(pl022);
1275
1276 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1277 flag = 1;
Chris Blair172289d2011-06-04 07:57:47 +01001278 /* Disable Transmit interrupt, enable receive interrupt */
1279 writew((readw(SSP_IMSC(pl022->virtbase)) &
1280 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001281 SSP_IMSC(pl022->virtbase));
1282 }
1283
1284 /*
1285 * Since all transactions must write as much as shall be read,
1286 * we can conclude the entire transaction once RX is complete.
1287 * At this point, all TX will always be finished.
1288 */
1289 if (pl022->rx >= pl022->rx_end) {
1290 writew(DISABLE_ALL_INTERRUPTS,
1291 SSP_IMSC(pl022->virtbase));
1292 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1293 if (unlikely(pl022->rx > pl022->rx_end)) {
1294 dev_warn(&pl022->adev->dev, "read %u surplus "
1295 "bytes (did you request an odd "
1296 "number of bytes on a 16bit bus?)\n",
1297 (u32) (pl022->rx - pl022->rx_end));
1298 }
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001299 /* Update total bytes transferred */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001300 msg->actual_length += pl022->cur_transfer->len;
1301 if (pl022->cur_transfer->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001302 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001303 /* Move to next transfer */
1304 msg->state = next_transfer(pl022);
1305 tasklet_schedule(&pl022->pump_transfers);
1306 return IRQ_HANDLED;
1307 }
1308
1309 return IRQ_HANDLED;
1310}
1311
1312/**
1313 * This sets up the pointers to memory for the next message to
1314 * send out on the SPI bus.
1315 */
1316static int set_up_next_transfer(struct pl022 *pl022,
1317 struct spi_transfer *transfer)
1318{
1319 int residue;
1320
1321 /* Sanity check the message for this bus width */
1322 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1323 if (unlikely(residue != 0)) {
1324 dev_err(&pl022->adev->dev,
1325 "message of %u bytes to transmit but the current "
1326 "chip bus has a data width of %u bytes!\n",
1327 pl022->cur_transfer->len,
1328 pl022->cur_chip->n_bytes);
1329 dev_err(&pl022->adev->dev, "skipping this message\n");
1330 return -EIO;
1331 }
1332 pl022->tx = (void *)transfer->tx_buf;
1333 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1334 pl022->rx = (void *)transfer->rx_buf;
1335 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1336 pl022->write =
1337 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1338 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1339 return 0;
1340}
1341
1342/**
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001343 * pump_transfers - Tasklet function which schedules next transfer
1344 * when running in interrupt or DMA transfer mode.
Linus Walleijb43d65f2009-06-09 08:11:42 +01001345 * @data: SSP driver private data structure
1346 *
1347 */
1348static void pump_transfers(unsigned long data)
1349{
1350 struct pl022 *pl022 = (struct pl022 *) data;
1351 struct spi_message *message = NULL;
1352 struct spi_transfer *transfer = NULL;
1353 struct spi_transfer *previous = NULL;
1354
1355 /* Get current state information */
1356 message = pl022->cur_msg;
1357 transfer = pl022->cur_transfer;
1358
1359 /* Handle for abort */
1360 if (message->state == STATE_ERROR) {
1361 message->status = -EIO;
1362 giveback(pl022);
1363 return;
1364 }
1365
1366 /* Handle end of message */
1367 if (message->state == STATE_DONE) {
1368 message->status = 0;
1369 giveback(pl022);
1370 return;
1371 }
1372
1373 /* Delay if requested at end of transfer before CS change */
1374 if (message->state == STATE_RUNNING) {
1375 previous = list_entry(transfer->transfer_list.prev,
1376 struct spi_transfer,
1377 transfer_list);
1378 if (previous->delay_usecs)
1379 /*
1380 * FIXME: This runs in interrupt context.
1381 * Is this really smart?
1382 */
1383 udelay(previous->delay_usecs);
1384
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +05301385 /* Reselect chip select only if cs_change was requested */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001386 if (previous->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001387 pl022_cs_control(pl022, SSP_CHIP_SELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001388 } else {
1389 /* STATE_START */
1390 message->state = STATE_RUNNING;
1391 }
1392
1393 if (set_up_next_transfer(pl022, transfer)) {
1394 message->state = STATE_ERROR;
1395 message->status = -EIO;
1396 giveback(pl022);
1397 return;
1398 }
1399 /* Flush the FIFOs and let's go! */
1400 flush(pl022);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001401
1402 if (pl022->cur_chip->enable_dma) {
1403 if (configure_dma(pl022)) {
1404 dev_dbg(&pl022->adev->dev,
1405 "configuration of DMA failed, fall back to interrupt mode\n");
1406 goto err_config_dma;
1407 }
1408 return;
1409 }
1410
1411err_config_dma:
Chris Blair172289d2011-06-04 07:57:47 +01001412 /* enable all interrupts except RX */
1413 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +01001414}
1415
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001416static void do_interrupt_dma_transfer(struct pl022 *pl022)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001417{
Chris Blair172289d2011-06-04 07:57:47 +01001418 /*
1419 * Default is to enable all interrupts except RX -
1420 * this will be enabled once TX is complete
1421 */
1422 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001423
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +05301424 /* Enable target chip, if not already active */
1425 if (!pl022->next_msg_cs_active)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001426 pl022_cs_control(pl022, SSP_CHIP_SELECT);
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +05301427
Linus Walleijb43d65f2009-06-09 08:11:42 +01001428 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1429 /* Error path */
1430 pl022->cur_msg->state = STATE_ERROR;
1431 pl022->cur_msg->status = -EIO;
1432 giveback(pl022);
1433 return;
1434 }
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001435 /* If we're using DMA, set up DMA here */
1436 if (pl022->cur_chip->enable_dma) {
1437 /* Configure DMA transfer */
1438 if (configure_dma(pl022)) {
1439 dev_dbg(&pl022->adev->dev,
1440 "configuration of DMA failed, fall back to interrupt mode\n");
1441 goto err_config_dma;
1442 }
1443 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1444 irqflags = DISABLE_ALL_INTERRUPTS;
1445 }
1446err_config_dma:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001447 /* Enable SSP, turn on interrupts */
1448 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1449 SSP_CR1(pl022->virtbase));
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001450 writew(irqflags, SSP_IMSC(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +01001451}
1452
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001453static void do_polling_transfer(struct pl022 *pl022)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001454{
Linus Walleijb43d65f2009-06-09 08:11:42 +01001455 struct spi_message *message = NULL;
1456 struct spi_transfer *transfer = NULL;
1457 struct spi_transfer *previous = NULL;
1458 struct chip_data *chip;
Magnus Templinga18c2662011-05-19 18:05:34 +02001459 unsigned long time, timeout;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001460
1461 chip = pl022->cur_chip;
1462 message = pl022->cur_msg;
1463
1464 while (message->state != STATE_DONE) {
1465 /* Handle for abort */
1466 if (message->state == STATE_ERROR)
1467 break;
1468 transfer = pl022->cur_transfer;
1469
1470 /* Delay if requested at end of transfer */
1471 if (message->state == STATE_RUNNING) {
1472 previous =
1473 list_entry(transfer->transfer_list.prev,
1474 struct spi_transfer, transfer_list);
1475 if (previous->delay_usecs)
1476 udelay(previous->delay_usecs);
1477 if (previous->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001478 pl022_cs_control(pl022, SSP_CHIP_SELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001479 } else {
1480 /* STATE_START */
1481 message->state = STATE_RUNNING;
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +05301482 if (!pl022->next_msg_cs_active)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001483 pl022_cs_control(pl022, SSP_CHIP_SELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001484 }
1485
1486 /* Configuration Changing Per Transfer */
1487 if (set_up_next_transfer(pl022, transfer)) {
1488 /* Error path */
1489 message->state = STATE_ERROR;
1490 break;
1491 }
1492 /* Flush FIFOs and enable SSP */
1493 flush(pl022);
1494 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1495 SSP_CR1(pl022->virtbase));
1496
Linus Walleij556f4ae2010-05-05 09:28:15 +00001497 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
Magnus Templinga18c2662011-05-19 18:05:34 +02001498
1499 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1500 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1501 time = jiffies;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001502 readwriter(pl022);
Magnus Templinga18c2662011-05-19 18:05:34 +02001503 if (time_after(time, timeout)) {
1504 dev_warn(&pl022->adev->dev,
1505 "%s: timeout!\n", __func__);
1506 message->state = STATE_ERROR;
1507 goto out;
1508 }
Linus Walleij521999b2011-05-19 20:01:25 +02001509 cpu_relax();
Magnus Templinga18c2662011-05-19 18:05:34 +02001510 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001511
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001512 /* Update total byte transferred */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001513 message->actual_length += pl022->cur_transfer->len;
1514 if (pl022->cur_transfer->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001515 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001516 /* Move to next transfer */
1517 message->state = next_transfer(pl022);
1518 }
Magnus Templinga18c2662011-05-19 18:05:34 +02001519out:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001520 /* Handle end of message */
1521 if (message->state == STATE_DONE)
1522 message->status = 0;
1523 else
1524 message->status = -EIO;
1525
1526 giveback(pl022);
1527 return;
1528}
1529
Linus Walleijffbbdd212012-02-22 10:05:38 +01001530static int pl022_transfer_one_message(struct spi_master *master,
1531 struct spi_message *msg)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001532{
Linus Walleijffbbdd212012-02-22 10:05:38 +01001533 struct pl022 *pl022 = spi_master_get_devdata(master);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001534
1535 /* Initial message state */
Linus Walleijffbbdd212012-02-22 10:05:38 +01001536 pl022->cur_msg = msg;
1537 msg->state = STATE_START;
1538
1539 pl022->cur_transfer = list_entry(msg->transfers.next,
1540 struct spi_transfer, transfer_list);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001541
1542 /* Setup the SPI using the per chip configuration */
Linus Walleijffbbdd212012-02-22 10:05:38 +01001543 pl022->cur_chip = spi_get_ctldata(msg->spi);
Roland Stiggef6f46de2012-08-22 15:49:17 +02001544 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
Chris Blaird4b6af22011-11-04 07:43:41 +00001545
Linus Walleijb43d65f2009-06-09 08:11:42 +01001546 restore_state(pl022);
1547 flush(pl022);
1548
1549 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1550 do_polling_transfer(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001551 else
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001552 do_interrupt_dma_transfer(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001553
1554 return 0;
1555}
1556
Linus Walleijffbbdd212012-02-22 10:05:38 +01001557static int pl022_unprepare_transfer_hardware(struct spi_master *master)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001558{
Linus Walleijffbbdd212012-02-22 10:05:38 +01001559 struct pl022 *pl022 = spi_master_get_devdata(master);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001560
Linus Walleijffbbdd212012-02-22 10:05:38 +01001561 /* nothing more to do - disable spi/ssp and power off */
1562 writew((readw(SSP_CR1(pl022->virtbase)) &
1563 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +01001564
Linus Walleijb43d65f2009-06-09 08:11:42 +01001565 return 0;
1566}
1567
1568static int verify_controller_parameters(struct pl022 *pl022,
Linus Walleijf9d629c2010-10-01 13:33:13 +02001569 struct pl022_config_chip const *chip_info)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001570{
Linus Walleijb43d65f2009-06-09 08:11:42 +01001571 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1572 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001573 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001574 "interface is configured incorrectly\n");
1575 return -EINVAL;
1576 }
1577 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1578 (!pl022->vendor->unidir)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001579 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001580 "unidirectional mode not supported in this "
1581 "hardware version\n");
1582 return -EINVAL;
1583 }
1584 if ((chip_info->hierarchy != SSP_MASTER)
1585 && (chip_info->hierarchy != SSP_SLAVE)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001586 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001587 "hierarchy is configured incorrectly\n");
1588 return -EINVAL;
1589 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001590 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1591 && (chip_info->com_mode != DMA_TRANSFER)
1592 && (chip_info->com_mode != POLLING_TRANSFER)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001593 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001594 "Communication mode is configured incorrectly\n");
1595 return -EINVAL;
1596 }
Linus Walleij78b2b912011-06-16 10:14:46 +02001597 switch (chip_info->rx_lev_trig) {
1598 case SSP_RX_1_OR_MORE_ELEM:
1599 case SSP_RX_4_OR_MORE_ELEM:
1600 case SSP_RX_8_OR_MORE_ELEM:
1601 /* These are always OK, all variants can handle this */
1602 break;
1603 case SSP_RX_16_OR_MORE_ELEM:
1604 if (pl022->vendor->fifodepth < 16) {
1605 dev_err(&pl022->adev->dev,
1606 "RX FIFO Trigger Level is configured incorrectly\n");
1607 return -EINVAL;
1608 }
1609 break;
1610 case SSP_RX_32_OR_MORE_ELEM:
1611 if (pl022->vendor->fifodepth < 32) {
1612 dev_err(&pl022->adev->dev,
1613 "RX FIFO Trigger Level is configured incorrectly\n");
1614 return -EINVAL;
1615 }
1616 break;
1617 default:
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001618 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001619 "RX FIFO Trigger Level is configured incorrectly\n");
1620 return -EINVAL;
1621 }
Linus Walleij78b2b912011-06-16 10:14:46 +02001622 switch (chip_info->tx_lev_trig) {
1623 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1624 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1625 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1626 /* These are always OK, all variants can handle this */
1627 break;
1628 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1629 if (pl022->vendor->fifodepth < 16) {
1630 dev_err(&pl022->adev->dev,
1631 "TX FIFO Trigger Level is configured incorrectly\n");
1632 return -EINVAL;
1633 }
1634 break;
1635 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1636 if (pl022->vendor->fifodepth < 32) {
1637 dev_err(&pl022->adev->dev,
1638 "TX FIFO Trigger Level is configured incorrectly\n");
1639 return -EINVAL;
1640 }
1641 break;
1642 default:
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001643 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001644 "TX FIFO Trigger Level is configured incorrectly\n");
1645 return -EINVAL;
1646 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001647 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1648 if ((chip_info->ctrl_len < SSP_BITS_4)
1649 || (chip_info->ctrl_len > SSP_BITS_32)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001650 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001651 "CTRL LEN is configured incorrectly\n");
1652 return -EINVAL;
1653 }
1654 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1655 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001656 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001657 "Wait State is configured incorrectly\n");
1658 return -EINVAL;
1659 }
Linus Walleij556f4ae2010-05-05 09:28:15 +00001660 /* Half duplex is only available in the ST Micro version */
1661 if (pl022->vendor->extended_cr) {
1662 if ((chip_info->duplex !=
1663 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1664 && (chip_info->duplex !=
Julia Lawall4a4fd472010-09-29 17:31:30 +09001665 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001666 dev_err(&pl022->adev->dev,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001667 "Microwire duplex mode is configured incorrectly\n");
1668 return -EINVAL;
Julia Lawall4a4fd472010-09-29 17:31:30 +09001669 }
Linus Walleij556f4ae2010-05-05 09:28:15 +00001670 } else {
1671 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001672 dev_err(&pl022->adev->dev,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001673 "Microwire half duplex mode requested,"
1674 " but this is only available in the"
1675 " ST version of PL022\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001676 return -EINVAL;
1677 }
1678 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001679 return 0;
1680}
1681
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301682static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1683{
1684 return rate / (cpsdvsr * (1 + scr));
1685}
1686
1687static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1688 ssp_clock_params * clk_freq)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001689{
1690 /* Lets calculate the frequency parameters */
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301691 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1692 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1693 best_scr = 0, tmp, found = 0;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001694
1695 rate = clk_get_rate(pl022->clk);
1696 /* cpsdvscr = 2 & scr 0 */
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301697 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001698 /* cpsdvsr = 254 & scr = 255 */
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301699 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001700
Viresh Kumarea505bc2012-04-19 11:48:15 +05301701 if (freq > max_tclk)
1702 dev_warn(&pl022->adev->dev,
1703 "Max speed that can be programmed is %d Hz, you requested %d\n",
1704 max_tclk, freq);
1705
1706 if (freq < min_tclk) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001707 dev_err(&pl022->adev->dev,
Viresh Kumarea505bc2012-04-19 11:48:15 +05301708 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1709 freq, min_tclk);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001710 return -EINVAL;
1711 }
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301712
1713 /*
1714 * best_freq will give closest possible available rate (<= requested
1715 * freq) for all values of scr & cpsdvsr.
1716 */
1717 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1718 while (scr <= SCR_MAX) {
1719 tmp = spi_rate(rate, cpsdvsr, scr);
1720
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301721 if (tmp > freq) {
1722 /* we need lower freq */
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301723 scr++;
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301724 continue;
1725 }
1726
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301727 /*
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301728 * If found exact value, mark found and break.
1729 * If found more closer value, update and break.
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301730 */
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301731 if (tmp > best_freq) {
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301732 best_freq = tmp;
1733 best_cpsdvsr = cpsdvsr;
1734 best_scr = scr;
1735
1736 if (tmp == freq)
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301737 found = 1;
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301738 }
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301739 /*
1740 * increased scr will give lower rates, which are not
1741 * required
1742 */
1743 break;
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301744 }
1745 cpsdvsr += 2;
1746 scr = SCR_MIN;
1747 }
1748
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301749 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1750 freq);
1751
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301752 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1753 clk_freq->scr = (u8) (best_scr & 0xFF);
1754 dev_dbg(&pl022->adev->dev,
1755 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1756 freq, best_freq);
1757 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1758 clk_freq->cpsdvsr, clk_freq->scr);
1759
Linus Walleijb43d65f2009-06-09 08:11:42 +01001760 return 0;
1761}
1762
Linus Walleijf9d629c2010-10-01 13:33:13 +02001763/*
1764 * A piece of default chip info unless the platform
1765 * supplies it.
1766 */
1767static const struct pl022_config_chip pl022_default_chip_info = {
1768 .com_mode = POLLING_TRANSFER,
1769 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1770 .hierarchy = SSP_SLAVE,
1771 .slave_tx_disable = DO_NOT_DRIVE_TX,
1772 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1773 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1774 .ctrl_len = SSP_BITS_8,
1775 .wait_state = SSP_MWIRE_WAIT_ZERO,
1776 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1777 .cs_control = null_cs_control,
1778};
1779
Linus Walleijb43d65f2009-06-09 08:11:42 +01001780/**
Linus Walleijb43d65f2009-06-09 08:11:42 +01001781 * pl022_setup - setup function registered to SPI master framework
1782 * @spi: spi device which is requesting setup
1783 *
1784 * This function is registered to the SPI framework for this SPI master
1785 * controller. If it is the first time when setup is called by this device,
1786 * this function will initialize the runtime state for this chip and save
1787 * the same in the device structure. Else it will update the runtime info
1788 * with the updated chip info. Nothing is really being written to the
1789 * controller hardware here, that is not done until the actual transfer
1790 * commence.
1791 */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001792static int pl022_setup(struct spi_device *spi)
1793{
Linus Walleijf9d629c2010-10-01 13:33:13 +02001794 struct pl022_config_chip const *chip_info;
Roland Stigge6d3952a2012-08-22 15:49:18 +02001795 struct pl022_config_chip chip_info_dt;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001796 struct chip_data *chip;
Jonas Aabergc4a47842011-02-28 16:42:41 +01001797 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
Linus Walleijb43d65f2009-06-09 08:11:42 +01001798 int status = 0;
1799 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001800 unsigned int bits = spi->bits_per_word;
1801 u32 tmp;
Roland Stigge6d3952a2012-08-22 15:49:18 +02001802 struct device_node *np = spi->dev.of_node;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001803
1804 if (!spi->max_speed_hz)
1805 return -EINVAL;
1806
1807 /* Get controller_state if one is supplied */
1808 chip = spi_get_ctldata(spi);
1809
1810 if (chip == NULL) {
1811 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1812 if (!chip) {
1813 dev_err(&spi->dev,
1814 "cannot allocate controller state\n");
1815 return -ENOMEM;
1816 }
1817 dev_dbg(&spi->dev,
1818 "allocated memory for controller's runtime state\n");
1819 }
1820
1821 /* Get controller data if one is supplied */
1822 chip_info = spi->controller_data;
1823
1824 if (chip_info == NULL) {
Roland Stigge6d3952a2012-08-22 15:49:18 +02001825 if (np) {
1826 chip_info_dt = pl022_default_chip_info;
1827
1828 chip_info_dt.hierarchy = SSP_MASTER;
1829 of_property_read_u32(np, "pl022,interface",
1830 &chip_info_dt.iface);
1831 of_property_read_u32(np, "pl022,com-mode",
1832 &chip_info_dt.com_mode);
1833 of_property_read_u32(np, "pl022,rx-level-trig",
1834 &chip_info_dt.rx_lev_trig);
1835 of_property_read_u32(np, "pl022,tx-level-trig",
1836 &chip_info_dt.tx_lev_trig);
1837 of_property_read_u32(np, "pl022,ctrl-len",
1838 &chip_info_dt.ctrl_len);
1839 of_property_read_u32(np, "pl022,wait-state",
1840 &chip_info_dt.wait_state);
1841 of_property_read_u32(np, "pl022,duplex",
1842 &chip_info_dt.duplex);
1843
1844 chip_info = &chip_info_dt;
1845 } else {
1846 chip_info = &pl022_default_chip_info;
1847 /* spi_board_info.controller_data not is supplied */
1848 dev_dbg(&spi->dev,
1849 "using default controller_data settings\n");
1850 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001851 } else
Linus Walleijb43d65f2009-06-09 08:11:42 +01001852 dev_dbg(&spi->dev,
1853 "using user supplied controller_data settings\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001854
1855 /*
1856 * We can override with custom divisors, else we use the board
1857 * frequency setting
1858 */
1859 if ((0 == chip_info->clk_freq.cpsdvsr)
1860 && (0 == chip_info->clk_freq.scr)) {
1861 status = calculate_effective_freq(pl022,
1862 spi->max_speed_hz,
Linus Walleijf9d629c2010-10-01 13:33:13 +02001863 &clk_freq);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001864 if (status < 0)
1865 goto err_config_params;
1866 } else {
Linus Walleijf9d629c2010-10-01 13:33:13 +02001867 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1868 if ((clk_freq.cpsdvsr % 2) != 0)
1869 clk_freq.cpsdvsr =
1870 clk_freq.cpsdvsr - 1;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001871 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001872 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1873 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
Virupax Sadashivpetimathe3f88ae2011-06-13 16:23:46 +05301874 status = -EINVAL;
Linus Walleijf9d629c2010-10-01 13:33:13 +02001875 dev_err(&spi->dev,
1876 "cpsdvsr is configured incorrectly\n");
1877 goto err_config_params;
1878 }
1879
Linus Walleijb43d65f2009-06-09 08:11:42 +01001880 status = verify_controller_parameters(pl022, chip_info);
1881 if (status) {
1882 dev_err(&spi->dev, "controller data is incorrect");
1883 goto err_config_params;
1884 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001885
Linus Walleij083be3f2011-06-16 10:14:28 +02001886 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1887 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1888
Linus Walleijb43d65f2009-06-09 08:11:42 +01001889 /* Now set controller state based on controller data */
1890 chip->xfer_type = chip_info->com_mode;
Linus Walleijf9d629c2010-10-01 13:33:13 +02001891 if (!chip_info->cs_control) {
1892 chip->cs_control = null_cs_control;
Roland Stiggef6f46de2012-08-22 15:49:17 +02001893 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1894 dev_warn(&spi->dev,
1895 "invalid chip select\n");
Linus Walleijf9d629c2010-10-01 13:33:13 +02001896 } else
1897 chip->cs_control = chip_info->cs_control;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001898
Vinit Shenoyeb798c62012-04-17 12:40:13 +05301899 /* Check bits per word with vendor specific range */
1900 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001901 status = -ENOTSUPP;
Vinit Shenoyeb798c62012-04-17 12:40:13 +05301902 dev_err(&spi->dev, "illegal data size for this controller!\n");
1903 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1904 pl022->vendor->max_bpw);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001905 goto err_config_params;
1906 } else if (bits <= 8) {
1907 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001908 chip->n_bytes = 1;
1909 chip->read = READING_U8;
1910 chip->write = WRITING_U8;
Kevin Wellsbde435a2010-09-16 06:18:50 -07001911 } else if (bits <= 16) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001912 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1913 chip->n_bytes = 2;
1914 chip->read = READING_U16;
1915 chip->write = WRITING_U16;
1916 } else {
Vinit Shenoyeb798c62012-04-17 12:40:13 +05301917 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1918 chip->n_bytes = 4;
1919 chip->read = READING_U32;
1920 chip->write = WRITING_U32;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001921 }
1922
1923 /* Now Initialize all register settings required for this chip */
1924 chip->cr0 = 0;
1925 chip->cr1 = 0;
1926 chip->dmacr = 0;
1927 chip->cpsr = 0;
1928 if ((chip_info->com_mode == DMA_TRANSFER)
1929 && ((pl022->master_info)->enable_dma)) {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001930 chip->enable_dma = true;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001931 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001932 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1933 SSP_DMACR_MASK_RXDMAE, 0);
1934 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1935 SSP_DMACR_MASK_TXDMAE, 1);
1936 } else {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001937 chip->enable_dma = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001938 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1939 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1940 SSP_DMACR_MASK_RXDMAE, 0);
1941 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1942 SSP_DMACR_MASK_TXDMAE, 1);
1943 }
1944
Linus Walleijf9d629c2010-10-01 13:33:13 +02001945 chip->cpsr = clk_freq.cpsdvsr;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001946
Linus Walleij556f4ae2010-05-05 09:28:15 +00001947 /* Special setup for the ST micro extended control registers */
1948 if (pl022->vendor->extended_cr) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001949 u32 etx;
1950
Linus Walleij781c7b12010-05-07 08:40:53 +00001951 if (pl022->vendor->pl023) {
1952 /* These bits are only in the PL023 */
1953 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1954 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1955 } else {
1956 /* These bits are in the PL022 but not PL023 */
1957 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1958 SSP_CR0_MASK_HALFDUP_ST, 5);
1959 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1960 SSP_CR0_MASK_CSS_ST, 16);
1961 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1962 SSP_CR0_MASK_FRF_ST, 21);
1963 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1964 SSP_CR1_MASK_MWAIT_ST, 6);
1965 }
Kevin Wellsbde435a2010-09-16 06:18:50 -07001966 SSP_WRITE_BITS(chip->cr0, bits - 1,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001967 SSP_CR0_MASK_DSS_ST, 0);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001968
1969 if (spi->mode & SPI_LSB_FIRST) {
1970 tmp = SSP_RX_LSB;
1971 etx = SSP_TX_LSB;
1972 } else {
1973 tmp = SSP_RX_MSB;
1974 etx = SSP_TX_MSB;
1975 }
1976 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1977 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
Linus Walleij556f4ae2010-05-05 09:28:15 +00001978 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1979 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1980 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1981 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1982 } else {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001983 SSP_WRITE_BITS(chip->cr0, bits - 1,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001984 SSP_CR0_MASK_DSS, 0);
1985 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1986 SSP_CR0_MASK_FRF, 4);
1987 }
Kevin Wellsbde435a2010-09-16 06:18:50 -07001988
Linus Walleij556f4ae2010-05-05 09:28:15 +00001989 /* Stuff that is common for all versions */
Kevin Wellsbde435a2010-09-16 06:18:50 -07001990 if (spi->mode & SPI_CPOL)
1991 tmp = SSP_CLK_POL_IDLE_HIGH;
1992 else
1993 tmp = SSP_CLK_POL_IDLE_LOW;
1994 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1995
1996 if (spi->mode & SPI_CPHA)
1997 tmp = SSP_CLK_SECOND_EDGE;
1998 else
1999 tmp = SSP_CLK_FIRST_EDGE;
2000 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2001
Linus Walleijf9d629c2010-10-01 13:33:13 +02002002 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
Linus Walleij781c7b12010-05-07 08:40:53 +00002003 /* Loopback is available on all versions except PL023 */
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002004 if (pl022->vendor->loopback) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07002005 if (spi->mode & SPI_LOOP)
2006 tmp = LOOPBACK_ENABLED;
2007 else
2008 tmp = LOOPBACK_DISABLED;
2009 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2010 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01002011 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2012 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
Viresh Kumarf1e45f82011-08-10 14:20:54 +05302013 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2014 3);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002015
2016 /* Save controller_state */
2017 spi_set_ctldata(spi, chip);
2018 return status;
2019 err_config_params:
Kevin Wellsbde435a2010-09-16 06:18:50 -07002020 spi_set_ctldata(spi, NULL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002021 kfree(chip);
2022 return status;
2023}
2024
2025/**
2026 * pl022_cleanup - cleanup function registered to SPI master framework
2027 * @spi: spi device which is requesting cleanup
2028 *
2029 * This function is registered to the SPI framework for this SPI master
2030 * controller. It will free the runtime state of chip.
2031 */
2032static void pl022_cleanup(struct spi_device *spi)
2033{
2034 struct chip_data *chip = spi_get_ctldata(spi);
2035
2036 spi_set_ctldata(spi, NULL);
2037 kfree(chip);
2038}
2039
Roland Stigge39a6ac12012-09-18 15:53:53 +02002040static struct pl022_ssp_controller *
2041pl022_platform_data_dt_get(struct device *dev)
2042{
2043 struct device_node *np = dev->of_node;
2044 struct pl022_ssp_controller *pd;
2045 u32 tmp;
2046
2047 if (!np) {
2048 dev_err(dev, "no dt node defined\n");
2049 return NULL;
2050 }
2051
2052 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
2053 if (!pd) {
2054 dev_err(dev, "cannot allocate platform data memory\n");
2055 return NULL;
2056 }
2057
2058 pd->bus_id = -1;
Linus Walleijdbd897b2013-05-23 19:46:40 +02002059 pd->enable_dma = 1;
Roland Stigge39a6ac12012-09-18 15:53:53 +02002060 of_property_read_u32(np, "num-cs", &tmp);
2061 pd->num_chipselect = tmp;
2062 of_property_read_u32(np, "pl022,autosuspend-delay",
2063 &pd->autosuspend_delay);
2064 pd->rt = of_property_read_bool(np, "pl022,rt");
2065
2066 return pd;
2067}
2068
Grant Likelyfd4a3192012-12-07 16:57:14 +00002069static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
Linus Walleijb43d65f2009-06-09 08:11:42 +01002070{
2071 struct device *dev = &adev->dev;
Jingoo Han8074cf02013-07-30 16:58:59 +09002072 struct pl022_ssp_controller *platform_info =
2073 dev_get_platdata(&adev->dev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002074 struct spi_master *master;
2075 struct pl022 *pl022 = NULL; /*Data for this driver */
Roland Stigge6d3952a2012-08-22 15:49:18 +02002076 struct device_node *np = adev->dev.of_node;
2077 int status = 0, i, num_cs;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002078
2079 dev_info(&adev->dev,
2080 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
Roland Stigge39a6ac12012-09-18 15:53:53 +02002081 if (!platform_info && IS_ENABLED(CONFIG_OF))
2082 platform_info = pl022_platform_data_dt_get(dev);
2083
2084 if (!platform_info) {
2085 dev_err(dev, "probe: no platform data defined\n");
Linus Walleijaeef9912012-09-26 16:48:36 +02002086 return -ENODEV;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002087 }
2088
Roland Stigge6d3952a2012-08-22 15:49:18 +02002089 if (platform_info->num_chipselect) {
2090 num_cs = platform_info->num_chipselect;
Roland Stigge6d3952a2012-08-22 15:49:18 +02002091 } else {
Roland Stigge39a6ac12012-09-18 15:53:53 +02002092 dev_err(dev, "probe: no chip select defined\n");
Linus Walleijaeef9912012-09-26 16:48:36 +02002093 return -ENODEV;
Roland Stigge6d3952a2012-08-22 15:49:18 +02002094 }
2095
Linus Walleijb43d65f2009-06-09 08:11:42 +01002096 /* Allocate master with space for data */
Roland Stiggeb4b84822012-09-03 10:14:29 +02002097 master = spi_alloc_master(dev, sizeof(struct pl022));
Linus Walleijb43d65f2009-06-09 08:11:42 +01002098 if (master == NULL) {
2099 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
Linus Walleijaeef9912012-09-26 16:48:36 +02002100 return -ENOMEM;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002101 }
2102
2103 pl022 = spi_master_get_devdata(master);
2104 pl022->master = master;
2105 pl022->master_info = platform_info;
2106 pl022->adev = adev;
2107 pl022->vendor = id->data;
Roland Stiggeb4b84822012-09-03 10:14:29 +02002108 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2109 GFP_KERNEL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002110
2111 /*
2112 * Bus Number Which has been Assigned to this SSP controller
2113 * on this board
2114 */
2115 master->bus_num = platform_info->bus_id;
Roland Stigge6d3952a2012-08-22 15:49:18 +02002116 master->num_chipselect = num_cs;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002117 master->cleanup = pl022_cleanup;
2118 master->setup = pl022_setup;
Mark Brown29b6e902013-07-28 15:35:08 +01002119 master->auto_runtime_pm = true;
Linus Walleijffbbdd212012-02-22 10:05:38 +01002120 master->transfer_one_message = pl022_transfer_one_message;
2121 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
2122 master->rt = platform_info->rt;
Roland Stigge6d3952a2012-08-22 15:49:18 +02002123 master->dev.of_node = dev->of_node;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002124
Roland Stigge6d3952a2012-08-22 15:49:18 +02002125 if (platform_info->num_chipselect && platform_info->chipselects) {
2126 for (i = 0; i < num_cs; i++)
Roland Stiggef6f46de2012-08-22 15:49:17 +02002127 pl022->chipselects[i] = platform_info->chipselects[i];
Roland Stigge6d3952a2012-08-22 15:49:18 +02002128 } else if (IS_ENABLED(CONFIG_OF)) {
2129 for (i = 0; i < num_cs; i++) {
2130 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
2131
2132 if (cs_gpio == -EPROBE_DEFER) {
2133 status = -EPROBE_DEFER;
2134 goto err_no_gpio;
2135 }
2136
2137 pl022->chipselects[i] = cs_gpio;
2138
2139 if (gpio_is_valid(cs_gpio)) {
Linus Walleijaeef9912012-09-26 16:48:36 +02002140 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
Roland Stigge6d3952a2012-08-22 15:49:18 +02002141 dev_err(&adev->dev,
2142 "could not request %d gpio\n",
2143 cs_gpio);
2144 else if (gpio_direction_output(cs_gpio, 1))
2145 dev_err(&adev->dev,
2146 "could set gpio %d as output\n",
2147 cs_gpio);
2148 }
2149 }
2150 }
Roland Stiggef6f46de2012-08-22 15:49:17 +02002151
Kevin Wellsbde435a2010-09-16 06:18:50 -07002152 /*
2153 * Supports mode 0-3, loopback, and active low CS. Transfers are
2154 * always MS bit first on the original pl022.
2155 */
2156 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2157 if (pl022->vendor->extended_cr)
2158 master->mode_bits |= SPI_LSB_FIRST;
2159
Linus Walleijb43d65f2009-06-09 08:11:42 +01002160 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2161
2162 status = amba_request_regions(adev, NULL);
2163 if (status)
2164 goto err_no_ioregion;
2165
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002166 pl022->phybase = adev->res.start;
Linus Walleijaeef9912012-09-26 16:48:36 +02002167 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2168 resource_size(&adev->res));
Linus Walleijb43d65f2009-06-09 08:11:42 +01002169 if (pl022->virtbase == NULL) {
2170 status = -ENOMEM;
2171 goto err_no_ioremap;
2172 }
Jingoo Han2c067502013-10-11 18:29:58 +09002173 dev_info(&adev->dev, "mapped registers from %pa to %p\n",
2174 &adev->res.start, pl022->virtbase);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002175
Linus Walleijaeef9912012-09-26 16:48:36 +02002176 pl022->clk = devm_clk_get(&adev->dev, NULL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002177 if (IS_ERR(pl022->clk)) {
2178 status = PTR_ERR(pl022->clk);
2179 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2180 goto err_no_clk;
2181 }
Russell King7ff6bcf2011-09-22 14:27:11 +01002182
Ulf Hansson6cac1672014-02-04 16:58:50 +01002183 status = clk_prepare_enable(pl022->clk);
Ulf Hansson71e63e72011-11-04 08:10:09 +01002184 if (status) {
2185 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2186 goto err_no_clk_en;
2187 }
2188
Linus Walleijffbbdd212012-02-22 10:05:38 +01002189 /* Initialize transfer pump */
2190 tasklet_init(&pl022->pump_transfers, pump_transfers,
2191 (unsigned long)pl022);
2192
Linus Walleijb43d65f2009-06-09 08:11:42 +01002193 /* Disable SSP */
Linus Walleijb43d65f2009-06-09 08:11:42 +01002194 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2195 SSP_CR1(pl022->virtbase));
2196 load_ssp_default_config(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002197
Linus Walleijaeef9912012-09-26 16:48:36 +02002198 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
2199 0, "pl022", pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002200 if (status < 0) {
2201 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2202 goto err_no_irq;
2203 }
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002204
Arnd Bergmanndc715452013-01-28 16:24:37 +00002205 /* Get DMA channels, try autoconfiguration first */
2206 status = pl022_dma_autoprobe(pl022);
2207
2208 /* If that failed, use channels from platform_info */
2209 if (status == 0)
2210 platform_info->enable_dma = 1;
2211 else if (platform_info->enable_dma) {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002212 status = pl022_dma_probe(pl022);
2213 if (status != 0)
Viresh Kumar43c64012011-05-16 09:40:10 +05302214 platform_info->enable_dma = 0;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002215 }
2216
Linus Walleijb43d65f2009-06-09 08:11:42 +01002217 /* Register with the SPI framework */
2218 amba_set_drvdata(adev, pl022);
Jingoo Han35794a72013-09-24 13:44:59 +09002219 status = devm_spi_register_master(&adev->dev, master);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002220 if (status != 0) {
2221 dev_err(&adev->dev,
2222 "probe - problem registering spi master\n");
2223 goto err_spi_register;
2224 }
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002225 dev_dbg(dev, "probe succeeded\n");
Russell King92b97f02011-08-14 09:13:48 +01002226
2227 /* let runtime pm put suspend */
Chris Blair53e4ace2011-11-08 08:54:46 +00002228 if (platform_info->autosuspend_delay > 0) {
2229 dev_info(&adev->dev,
2230 "will use autosuspend for runtime pm, delay %dms\n",
2231 platform_info->autosuspend_delay);
2232 pm_runtime_set_autosuspend_delay(dev,
2233 platform_info->autosuspend_delay);
2234 pm_runtime_use_autosuspend(dev);
Chris Blair53e4ace2011-11-08 08:54:46 +00002235 }
Ulf Hansson0df34992012-10-17 14:27:08 +02002236 pm_runtime_put(dev);
2237
Linus Walleijb43d65f2009-06-09 08:11:42 +01002238 return 0;
2239
2240 err_spi_register:
Viresh Kumar3e3ea712011-08-10 14:20:58 +05302241 if (platform_info->enable_dma)
2242 pl022_dma_remove(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002243 err_no_irq:
Ulf Hansson6cac1672014-02-04 16:58:50 +01002244 clk_disable_unprepare(pl022->clk);
Ulf Hansson71e63e72011-11-04 08:10:09 +01002245 err_no_clk_en:
Linus Walleijb43d65f2009-06-09 08:11:42 +01002246 err_no_clk:
Linus Walleijb43d65f2009-06-09 08:11:42 +01002247 err_no_ioremap:
2248 amba_release_regions(adev);
2249 err_no_ioregion:
Roland Stigge6d3952a2012-08-22 15:49:18 +02002250 err_no_gpio:
Linus Walleijb43d65f2009-06-09 08:11:42 +01002251 spi_master_put(master);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002252 return status;
2253}
2254
Grant Likelyfd4a3192012-12-07 16:57:14 +00002255static int
Linus Walleijb43d65f2009-06-09 08:11:42 +01002256pl022_remove(struct amba_device *adev)
2257{
2258 struct pl022 *pl022 = amba_get_drvdata(adev);
Linus Walleij50658b62011-08-02 11:29:24 +02002259
Linus Walleijb43d65f2009-06-09 08:11:42 +01002260 if (!pl022)
2261 return 0;
2262
Russell King92b97f02011-08-14 09:13:48 +01002263 /*
2264 * undo pm_runtime_put() in probe. I assume that we're not
2265 * accessing the primecell here.
2266 */
2267 pm_runtime_get_noresume(&adev->dev);
2268
Linus Walleijb43d65f2009-06-09 08:11:42 +01002269 load_ssp_default_config(pl022);
Viresh Kumar3e3ea712011-08-10 14:20:58 +05302270 if (pl022->master_info->enable_dma)
2271 pl022_dma_remove(pl022);
2272
Ulf Hansson6cac1672014-02-04 16:58:50 +01002273 clk_disable_unprepare(pl022->clk);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002274 amba_release_regions(adev);
2275 tasklet_disable(&pl022->pump_transfers);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002276 return 0;
2277}
2278
Ulf Hansson84a5dc42014-03-01 11:56:07 +01002279#ifdef CONFIG_PM_SLEEP
Peter Hüwe6cfa6272011-09-05 21:07:23 +01002280static int pl022_suspend(struct device *dev)
Linus Walleijb43d65f2009-06-09 08:11:42 +01002281{
Russell King92b97f02011-08-14 09:13:48 +01002282 struct pl022 *pl022 = dev_get_drvdata(dev);
Linus Walleijffbbdd212012-02-22 10:05:38 +01002283 int ret;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002284
Linus Walleijffbbdd212012-02-22 10:05:38 +01002285 ret = spi_master_suspend(pl022->master);
2286 if (ret) {
2287 dev_warn(dev, "cannot suspend master\n");
2288 return ret;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002289 }
Ulf Hansson4964a262012-10-17 14:27:16 +02002290
Ulf Hansson84a5dc42014-03-01 11:56:07 +01002291 ret = pm_runtime_force_suspend(dev);
2292 if (ret) {
2293 spi_master_resume(pl022->master);
2294 return ret;
2295 }
2296
2297 pinctrl_pm_select_sleep_state(dev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002298
Peter Hüwe6cfa6272011-09-05 21:07:23 +01002299 dev_dbg(dev, "suspended\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01002300 return 0;
2301}
2302
Russell King92b97f02011-08-14 09:13:48 +01002303static int pl022_resume(struct device *dev)
Linus Walleijb43d65f2009-06-09 08:11:42 +01002304{
Russell King92b97f02011-08-14 09:13:48 +01002305 struct pl022 *pl022 = dev_get_drvdata(dev);
Linus Walleijffbbdd212012-02-22 10:05:38 +01002306 int ret;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002307
Ulf Hansson84a5dc42014-03-01 11:56:07 +01002308 ret = pm_runtime_force_resume(dev);
2309 if (ret)
2310 dev_err(dev, "problem resuming\n");
Linus Walleijada7aec2012-09-26 18:06:22 +02002311
Linus Walleijb43d65f2009-06-09 08:11:42 +01002312 /* Start the queue running */
Linus Walleijffbbdd212012-02-22 10:05:38 +01002313 ret = spi_master_resume(pl022->master);
2314 if (ret)
2315 dev_err(dev, "problem starting queue (%d)\n", ret);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002316 else
Russell King92b97f02011-08-14 09:13:48 +01002317 dev_dbg(dev, "resumed\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01002318
Linus Walleijffbbdd212012-02-22 10:05:38 +01002319 return ret;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002320}
Ulf Hansson84a5dc42014-03-01 11:56:07 +01002321#endif
Linus Walleijb43d65f2009-06-09 08:11:42 +01002322
Ulf Hansson736198b2014-03-01 11:56:06 +01002323#ifdef CONFIG_PM
Russell King92b97f02011-08-14 09:13:48 +01002324static int pl022_runtime_suspend(struct device *dev)
2325{
2326 struct pl022 *pl022 = dev_get_drvdata(dev);
2327
Ulf Hansson84a5dc42014-03-01 11:56:07 +01002328 clk_disable_unprepare(pl022->clk);
2329 pinctrl_pm_select_idle_state(dev);
2330
Russell King92b97f02011-08-14 09:13:48 +01002331 return 0;
2332}
2333
2334static int pl022_runtime_resume(struct device *dev)
2335{
2336 struct pl022 *pl022 = dev_get_drvdata(dev);
Patrice Chotard4f5e1b32012-09-19 14:23:46 +02002337
Ulf Hansson84a5dc42014-03-01 11:56:07 +01002338 pinctrl_pm_select_default_state(dev);
2339 clk_prepare_enable(pl022->clk);
2340
Russell King92b97f02011-08-14 09:13:48 +01002341 return 0;
2342}
2343#endif
2344
2345static const struct dev_pm_ops pl022_dev_pm_ops = {
2346 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
Ulf Hansson736198b2014-03-01 11:56:06 +01002347 SET_PM_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
Russell King92b97f02011-08-14 09:13:48 +01002348};
2349
Linus Walleijb43d65f2009-06-09 08:11:42 +01002350static struct vendor_data vendor_arm = {
2351 .fifodepth = 8,
2352 .max_bpw = 16,
2353 .unidir = false,
Linus Walleij556f4ae2010-05-05 09:28:15 +00002354 .extended_cr = false,
Linus Walleij781c7b12010-05-07 08:40:53 +00002355 .pl023 = false,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002356 .loopback = true,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002357};
2358
Linus Walleijb43d65f2009-06-09 08:11:42 +01002359static struct vendor_data vendor_st = {
2360 .fifodepth = 32,
2361 .max_bpw = 32,
2362 .unidir = false,
Linus Walleij556f4ae2010-05-05 09:28:15 +00002363 .extended_cr = true,
Linus Walleij781c7b12010-05-07 08:40:53 +00002364 .pl023 = false,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002365 .loopback = true,
Linus Walleij781c7b12010-05-07 08:40:53 +00002366};
2367
2368static struct vendor_data vendor_st_pl023 = {
2369 .fifodepth = 32,
2370 .max_bpw = 32,
2371 .unidir = false,
2372 .extended_cr = true,
2373 .pl023 = true,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002374 .loopback = false,
2375};
2376
Linus Walleijb43d65f2009-06-09 08:11:42 +01002377static struct amba_id pl022_ids[] = {
2378 {
2379 /*
2380 * ARM PL022 variant, this has a 16bit wide
2381 * and 8 locations deep TX/RX FIFO
2382 */
2383 .id = 0x00041022,
2384 .mask = 0x000fffff,
2385 .data = &vendor_arm,
2386 },
2387 {
2388 /*
2389 * ST Micro derivative, this has 32bit wide
2390 * and 32 locations deep TX/RX FIFO
2391 */
Srinidhi Kasagare89e04f2009-10-05 06:13:53 +01002392 .id = 0x01080022,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002393 .mask = 0xffffffff,
2394 .data = &vendor_st,
2395 },
Linus Walleij781c7b12010-05-07 08:40:53 +00002396 {
2397 /*
2398 * ST-Ericsson derivative "PL023" (this is not
2399 * an official ARM number), this is a PL022 SSP block
2400 * stripped to SPI mode only, it has 32bit wide
2401 * and 32 locations deep TX/RX FIFO but no extended
2402 * CR0/CR1 register
2403 */
Viresh Kumarf1e45f82011-08-10 14:20:54 +05302404 .id = 0x00080023,
2405 .mask = 0xffffffff,
2406 .data = &vendor_st_pl023,
Linus Walleij781c7b12010-05-07 08:40:53 +00002407 },
Linus Walleijb43d65f2009-06-09 08:11:42 +01002408 { 0, 0 },
2409};
2410
Dave Martin7eeac712011-10-05 15:15:22 +01002411MODULE_DEVICE_TABLE(amba, pl022_ids);
2412
Linus Walleijb43d65f2009-06-09 08:11:42 +01002413static struct amba_driver pl022_driver = {
2414 .drv = {
2415 .name = "ssp-pl022",
Russell King92b97f02011-08-14 09:13:48 +01002416 .pm = &pl022_dev_pm_ops,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002417 },
2418 .id_table = pl022_ids,
2419 .probe = pl022_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00002420 .remove = pl022_remove,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002421};
2422
Linus Walleijb43d65f2009-06-09 08:11:42 +01002423static int __init pl022_init(void)
2424{
2425 return amba_driver_register(&pl022_driver);
2426}
Linus Walleij25c8e032010-09-06 11:02:12 +02002427subsys_initcall(pl022_init);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002428
2429static void __exit pl022_exit(void)
2430{
2431 amba_driver_unregister(&pl022_driver);
2432}
Linus Walleijb43d65f2009-06-09 08:11:42 +01002433module_exit(pl022_exit);
2434
2435MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2436MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2437MODULE_LICENSE("GPL");