blob: 9009456bdf4d29c6febf56b162113fa5e4bf78ef [file] [log] [blame]
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -08001/*
2 * SuperH HSPI bus driver
3 *
4 * Copyright (C) 2011 Kuninori Morimoto
5 *
6 * Based on spi-sh.c:
7 * Based on pxa2xx_spi.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 *
24 */
Kuninori Morimoto49e599b82012-03-14 02:48:05 -070025
26#include <linux/clk.h>
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -080027#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/timer.h>
30#include <linux/delay.h>
31#include <linux/list.h>
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -080032#include <linux/interrupt.h>
33#include <linux/platform_device.h>
34#include <linux/pm_runtime.h>
35#include <linux/io.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/sh_hspi.h>
38
39#define SPCR 0x00
40#define SPSR 0x04
41#define SPSCR 0x08
42#define SPTBR 0x0C
43#define SPRBR 0x10
44#define SPCR2 0x14
45
46/* SPSR */
47#define RXFL (1 << 2)
48
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -080049struct hspi_priv {
50 void __iomem *addr;
51 struct spi_master *master;
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -080052 struct device *dev;
Kuninori Morimoto49e599b82012-03-14 02:48:05 -070053 struct clk *clk;
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -080054};
55
56/*
57 * basic function
58 */
59static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
60{
61 iowrite32(val, hspi->addr + reg);
62}
63
64static u32 hspi_read(struct hspi_priv *hspi, int reg)
65{
66 return ioread32(hspi->addr + reg);
67}
68
Phil Edworthyce329302012-11-22 14:37:27 +000069static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set)
70{
71 u32 val = hspi_read(hspi, reg);
72
73 val &= ~mask;
74 val |= set & mask;
75
76 hspi_write(hspi, reg, val);
77}
78
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -080079/*
80 * transfer function
81 */
82static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
83{
84 int t = 256;
85
86 while (t--) {
87 if ((mask & hspi_read(hspi, SPSR)) == val)
88 return 0;
89
Kuninori Morimotobc2bfff2013-05-26 17:59:20 -070090 udelay(10);
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -080091 }
92
93 dev_err(hspi->dev, "timeout\n");
94 return -ETIMEDOUT;
95}
96
Kuninori Morimotoec139b62012-03-14 02:47:40 -070097/*
98 * spi master function
99 */
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700100
Phil Edworthyce329302012-11-22 14:37:27 +0000101#define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0)
102#define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1)
103static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi)
104{
105 hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6);
106}
107
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700108static void hspi_hw_setup(struct hspi_priv *hspi,
109 struct spi_message *msg,
110 struct spi_transfer *t)
111{
112 struct spi_device *spi = msg->spi;
113 struct device *dev = hspi->dev;
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700114 u32 spcr, idiv_clk;
115 u32 rate, best_rate, min, tmp;
116
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700117 /*
118 * find best IDIV/CLKCx settings
119 */
120 min = ~0;
121 best_rate = 0;
122 spcr = 0;
123 for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) {
124 rate = clk_get_rate(hspi->clk);
125
126 /* IDIV calculation */
127 if (idiv_clk & (1 << 5))
128 rate /= 128;
129 else
130 rate /= 16;
131
132 /* CLKCx calculation */
Jingoo Hana29c8ae2013-10-14 10:35:42 +0900133 rate /= (((idiv_clk & 0x1F) + 1) * 2);
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700134
135 /* save best settings */
Axel Line428a422014-03-02 23:01:50 +0800136 tmp = abs(t->speed_hz - rate);
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700137 if (tmp < min) {
138 min = tmp;
139 spcr = idiv_clk;
140 best_rate = rate;
141 }
142 }
143
144 if (spi->mode & SPI_CPHA)
145 spcr |= 1 << 7;
146 if (spi->mode & SPI_CPOL)
147 spcr |= 1 << 6;
148
Axel Line428a422014-03-02 23:01:50 +0800149 dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate);
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700150
151 hspi_write(hspi, SPCR, spcr);
152 hspi_write(hspi, SPSR, 0x0);
Phil Edworthyce329302012-11-22 14:37:27 +0000153 hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700154}
155
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700156static int hspi_transfer_one_message(struct spi_master *master,
157 struct spi_message *msg)
158{
159 struct hspi_priv *hspi = spi_master_get_devdata(master);
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800160 struct spi_transfer *t;
Kuninori Morimotobb9c5682012-03-14 02:48:25 -0700161 u32 tx;
162 u32 rx;
163 int ret, i;
Phil Edworthyce329302012-11-22 14:37:27 +0000164 unsigned int cs_change;
165 const int nsecs = 50;
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800166
167 dev_dbg(hspi->dev, "%s\n", __func__);
168
Phil Edworthyce329302012-11-22 14:37:27 +0000169 cs_change = 1;
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700170 ret = 0;
171 list_for_each_entry(t, &msg->transfers, transfer_list) {
Phil Edworthyce329302012-11-22 14:37:27 +0000172
173 if (cs_change) {
174 hspi_hw_setup(hspi, msg, t);
175 hspi_hw_cs_enable(hspi);
176 ndelay(nsecs);
177 }
178 cs_change = t->cs_change;
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700179
Kuninori Morimotobb9c5682012-03-14 02:48:25 -0700180 for (i = 0; i < t->len; i++) {
181
182 /* wait remains */
183 ret = hspi_status_check_timeout(hspi, 0x1, 0);
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700184 if (ret < 0)
Kuninori Morimotobb9c5682012-03-14 02:48:25 -0700185 break;
186
187 tx = 0;
188 if (t->tx_buf)
189 tx = (u32)((u8 *)t->tx_buf)[i];
190
191 hspi_write(hspi, SPTBR, tx);
192
Geert Uytterhoevenc6c07b42014-01-12 14:03:38 +0100193 /* wait receive */
Kuninori Morimotobb9c5682012-03-14 02:48:25 -0700194 ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700195 if (ret < 0)
Kuninori Morimotobb9c5682012-03-14 02:48:25 -0700196 break;
197
198 rx = hspi_read(hspi, SPRBR);
199 if (t->rx_buf)
200 ((u8 *)t->rx_buf)[i] = (u8)rx;
201
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700202 }
Kuninori Morimotobb9c5682012-03-14 02:48:25 -0700203
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700204 msg->actual_length += t->len;
Phil Edworthyce329302012-11-22 14:37:27 +0000205
206 if (t->delay_usecs)
207 udelay(t->delay_usecs);
208
209 if (cs_change) {
210 ndelay(nsecs);
211 hspi_hw_cs_disable(hspi);
212 ndelay(nsecs);
213 }
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700214 }
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700215
216 msg->status = ret;
Phil Edworthyce329302012-11-22 14:37:27 +0000217 if (!cs_change) {
218 ndelay(nsecs);
219 hspi_hw_cs_disable(hspi);
220 }
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700221 spi_finalize_current_message(master);
222
223 return ret;
224}
225
Grant Likelyfd4a3192012-12-07 16:57:14 +0000226static int hspi_probe(struct platform_device *pdev)
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800227{
228 struct resource *res;
229 struct spi_master *master;
230 struct hspi_priv *hspi;
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700231 struct clk *clk;
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800232 int ret;
233
234 /* get base addr */
235 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
236 if (!res) {
237 dev_err(&pdev->dev, "invalid resource\n");
238 return -EINVAL;
239 }
240
241 master = spi_alloc_master(&pdev->dev, sizeof(*hspi));
242 if (!master) {
243 dev_err(&pdev->dev, "spi_alloc_master error.\n");
244 return -ENOMEM;
245 }
246
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700247 clk = clk_get(NULL, "shyway_clk");
Cyril Roelandtd3601e52012-12-12 01:24:54 +0100248 if (IS_ERR(clk)) {
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700249 dev_err(&pdev->dev, "shyway_clk is required\n");
250 ret = -EINVAL;
251 goto error0;
252 }
253
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800254 hspi = spi_master_get_devdata(master);
Jingoo Han24b5a822013-05-23 19:20:40 +0900255 platform_set_drvdata(pdev, hspi);
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800256
257 /* init hspi */
258 hspi->master = master;
259 hspi->dev = &pdev->dev;
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700260 hspi->clk = clk;
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800261 hspi->addr = devm_ioremap(hspi->dev,
262 res->start, resource_size(res));
263 if (!hspi->addr) {
264 dev_err(&pdev->dev, "ioremap error.\n");
265 ret = -ENOMEM;
266 goto error1;
267 }
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800268
Kuninori Morimoto268d7642013-10-03 02:15:50 -0700269 pm_runtime_enable(&pdev->dev);
270
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800271 master->bus_num = pdev->id;
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800272 master->mode_bits = SPI_CPOL | SPI_CPHA;
Kuninori Morimotoe5f78252013-10-24 21:53:29 -0700273 master->dev.of_node = pdev->dev.of_node;
Mark Brown3e00a092013-07-28 15:35:36 +0100274 master->auto_runtime_pm = true;
Kuninori Morimotoec139b62012-03-14 02:47:40 -0700275 master->transfer_one_message = hspi_transfer_one_message;
Axel Lin45221932014-02-12 22:09:52 +0800276 master->bits_per_word_mask = SPI_BPW_MASK(8);
277
Jingoo Han1c43f2a2013-09-24 13:47:59 +0900278 ret = devm_spi_register_master(&pdev->dev, master);
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800279 if (ret < 0) {
280 dev_err(&pdev->dev, "spi_register_master error.\n");
Geert Uytterhoeven3abf0ed2014-03-11 10:59:10 +0100281 goto error2;
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800282 }
283
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800284 return 0;
285
Geert Uytterhoeven3abf0ed2014-03-11 10:59:10 +0100286 error2:
287 pm_runtime_disable(&pdev->dev);
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800288 error1:
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700289 clk_put(clk);
290 error0:
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800291 spi_master_put(master);
292
293 return ret;
294}
295
Grant Likelyfd4a3192012-12-07 16:57:14 +0000296static int hspi_remove(struct platform_device *pdev)
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800297{
Jingoo Han24b5a822013-05-23 19:20:40 +0900298 struct hspi_priv *hspi = platform_get_drvdata(pdev);
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800299
300 pm_runtime_disable(&pdev->dev);
301
Kuninori Morimoto49e599b82012-03-14 02:48:05 -0700302 clk_put(hspi->clk);
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800303
304 return 0;
305}
306
Kuninori Morimotoe5f78252013-10-24 21:53:29 -0700307static struct of_device_id hspi_of_match[] = {
308 { .compatible = "renesas,hspi", },
309 { /* sentinel */ }
310};
311MODULE_DEVICE_TABLE(of, hspi_of_match);
312
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800313static struct platform_driver hspi_driver = {
314 .probe = hspi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000315 .remove = hspi_remove,
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800316 .driver = {
317 .name = "sh-hspi",
318 .owner = THIS_MODULE,
Kuninori Morimotoe5f78252013-10-24 21:53:29 -0700319 .of_match_table = hspi_of_match,
Kuninori Morimotod1c8bbd2012-03-01 17:10:17 -0800320 },
321};
322module_platform_driver(hspi_driver);
323
324MODULE_DESCRIPTION("SuperH HSPI bus driver");
325MODULE_LICENSE("GPL");
326MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
Axel Lincaedb992014-01-08 18:52:40 +0800327MODULE_ALIAS("platform:sh-hspi");