Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2011 Intel Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along with |
| 14 | * this program; if not, write to the Free Software Foundation, Inc., |
| 15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 16 | * |
| 17 | * Authors: |
| 18 | * Eric Anholt <eric@anholt.net> |
| 19 | */ |
| 20 | |
| 21 | #include <linux/i2c.h> |
| 22 | #include <linux/pm_runtime.h> |
| 23 | |
| 24 | #include <drm/drmP.h> |
| 25 | #include "framebuffer.h" |
| 26 | #include "psb_drv.h" |
| 27 | #include "psb_intel_drv.h" |
| 28 | #include "psb_intel_reg.h" |
| 29 | #include "psb_intel_display.h" |
| 30 | #include "power.h" |
| 31 | #include "cdv_device.h" |
| 32 | |
| 33 | |
| 34 | struct cdv_intel_range_t { |
| 35 | int min, max; |
| 36 | }; |
| 37 | |
| 38 | struct cdv_intel_p2_t { |
| 39 | int dot_limit; |
| 40 | int p2_slow, p2_fast; |
| 41 | }; |
| 42 | |
| 43 | struct cdv_intel_clock_t { |
| 44 | /* given values */ |
| 45 | int n; |
| 46 | int m1, m2; |
| 47 | int p1, p2; |
| 48 | /* derived values */ |
| 49 | int dot; |
| 50 | int vco; |
| 51 | int m; |
| 52 | int p; |
| 53 | }; |
| 54 | |
| 55 | #define INTEL_P2_NUM 2 |
| 56 | |
| 57 | struct cdv_intel_limit_t { |
| 58 | struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1; |
| 59 | struct cdv_intel_p2_t p2; |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 60 | bool (*find_pll)(const struct cdv_intel_limit_t *, struct drm_crtc *, |
| 61 | int, int, struct cdv_intel_clock_t *); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 62 | }; |
| 63 | |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 64 | static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit, |
| 65 | struct drm_crtc *crtc, int target, int refclk, |
| 66 | struct cdv_intel_clock_t *best_clock); |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 67 | static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct drm_crtc *crtc, int target, |
| 68 | int refclk, |
| 69 | struct cdv_intel_clock_t *best_clock); |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 70 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 71 | #define CDV_LIMIT_SINGLE_LVDS_96 0 |
| 72 | #define CDV_LIMIT_SINGLE_LVDS_100 1 |
| 73 | #define CDV_LIMIT_DAC_HDMI_27 2 |
| 74 | #define CDV_LIMIT_DAC_HDMI_96 3 |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 75 | #define CDV_LIMIT_DP_27 4 |
| 76 | #define CDV_LIMIT_DP_100 5 |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 77 | |
| 78 | static const struct cdv_intel_limit_t cdv_intel_limits[] = { |
Forest Bond | 28bbda3 | 2012-08-13 16:27:09 +0000 | [diff] [blame] | 79 | { /* CDV_SINGLE_LVDS_96MHz */ |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 80 | .dot = {.min = 20000, .max = 115500}, |
| 81 | .vco = {.min = 1800000, .max = 3600000}, |
| 82 | .n = {.min = 2, .max = 6}, |
| 83 | .m = {.min = 60, .max = 160}, |
| 84 | .m1 = {.min = 0, .max = 0}, |
| 85 | .m2 = {.min = 58, .max = 158}, |
| 86 | .p = {.min = 28, .max = 140}, |
| 87 | .p1 = {.min = 2, .max = 10}, |
| 88 | .p2 = {.dot_limit = 200000, |
| 89 | .p2_slow = 14, .p2_fast = 14}, |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 90 | .find_pll = cdv_intel_find_best_PLL, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 91 | }, |
| 92 | { /* CDV_SINGLE_LVDS_100MHz */ |
| 93 | .dot = {.min = 20000, .max = 115500}, |
| 94 | .vco = {.min = 1800000, .max = 3600000}, |
| 95 | .n = {.min = 2, .max = 6}, |
| 96 | .m = {.min = 60, .max = 160}, |
| 97 | .m1 = {.min = 0, .max = 0}, |
| 98 | .m2 = {.min = 58, .max = 158}, |
| 99 | .p = {.min = 28, .max = 140}, |
| 100 | .p1 = {.min = 2, .max = 10}, |
| 101 | /* The single-channel range is 25-112Mhz, and dual-channel |
| 102 | * is 80-224Mhz. Prefer single channel as much as possible. |
| 103 | */ |
| 104 | .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 105 | .find_pll = cdv_intel_find_best_PLL, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 106 | }, |
| 107 | { /* CDV_DAC_HDMI_27MHz */ |
| 108 | .dot = {.min = 20000, .max = 400000}, |
| 109 | .vco = {.min = 1809000, .max = 3564000}, |
| 110 | .n = {.min = 1, .max = 1}, |
| 111 | .m = {.min = 67, .max = 132}, |
| 112 | .m1 = {.min = 0, .max = 0}, |
| 113 | .m2 = {.min = 65, .max = 130}, |
| 114 | .p = {.min = 5, .max = 90}, |
| 115 | .p1 = {.min = 1, .max = 9}, |
| 116 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 117 | .find_pll = cdv_intel_find_best_PLL, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 118 | }, |
| 119 | { /* CDV_DAC_HDMI_96MHz */ |
| 120 | .dot = {.min = 20000, .max = 400000}, |
| 121 | .vco = {.min = 1800000, .max = 3600000}, |
| 122 | .n = {.min = 2, .max = 6}, |
| 123 | .m = {.min = 60, .max = 160}, |
| 124 | .m1 = {.min = 0, .max = 0}, |
| 125 | .m2 = {.min = 58, .max = 158}, |
| 126 | .p = {.min = 5, .max = 100}, |
| 127 | .p1 = {.min = 1, .max = 10}, |
| 128 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 129 | .find_pll = cdv_intel_find_best_PLL, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 130 | }, |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 131 | { /* CDV_DP_27MHz */ |
| 132 | .dot = {.min = 160000, .max = 272000}, |
| 133 | .vco = {.min = 1809000, .max = 3564000}, |
| 134 | .n = {.min = 1, .max = 1}, |
| 135 | .m = {.min = 67, .max = 132}, |
| 136 | .m1 = {.min = 0, .max = 0}, |
| 137 | .m2 = {.min = 65, .max = 130}, |
| 138 | .p = {.min = 5, .max = 90}, |
| 139 | .p1 = {.min = 1, .max = 9}, |
| 140 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10}, |
| 141 | .find_pll = cdv_intel_find_dp_pll, |
| 142 | }, |
| 143 | { /* CDV_DP_100MHz */ |
| 144 | .dot = {.min = 160000, .max = 272000}, |
| 145 | .vco = {.min = 1800000, .max = 3600000}, |
| 146 | .n = {.min = 2, .max = 6}, |
| 147 | .m = {.min = 60, .max = 164}, |
| 148 | .m1 = {.min = 0, .max = 0}, |
| 149 | .m2 = {.min = 58, .max = 162}, |
| 150 | .p = {.min = 5, .max = 100}, |
| 151 | .p1 = {.min = 1, .max = 10}, |
| 152 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10}, |
| 153 | .find_pll = cdv_intel_find_dp_pll, |
| 154 | } |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 155 | }; |
| 156 | |
| 157 | #define _wait_for(COND, MS, W) ({ \ |
| 158 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ |
| 159 | int ret__ = 0; \ |
| 160 | while (!(COND)) { \ |
| 161 | if (time_after(jiffies, timeout__)) { \ |
| 162 | ret__ = -ETIMEDOUT; \ |
| 163 | break; \ |
| 164 | } \ |
| 165 | if (W && !in_dbg_master()) \ |
| 166 | msleep(W); \ |
| 167 | } \ |
| 168 | ret__; \ |
| 169 | }) |
| 170 | |
| 171 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
| 172 | |
| 173 | |
Alan Cox | 37e7b18 | 2012-08-08 13:55:03 +0000 | [diff] [blame] | 174 | int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 175 | { |
| 176 | int ret; |
| 177 | |
| 178 | ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); |
| 179 | if (ret) { |
| 180 | DRM_ERROR("timeout waiting for SB to idle before read\n"); |
| 181 | return ret; |
| 182 | } |
| 183 | |
| 184 | REG_WRITE(SB_ADDR, reg); |
| 185 | REG_WRITE(SB_PCKT, |
| 186 | SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | |
| 187 | SET_FIELD(SB_DEST_DPLL, SB_DEST) | |
| 188 | SET_FIELD(0xf, SB_BYTE_ENABLE)); |
| 189 | |
| 190 | ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); |
| 191 | if (ret) { |
| 192 | DRM_ERROR("timeout waiting for SB to idle after read\n"); |
| 193 | return ret; |
| 194 | } |
| 195 | |
| 196 | *val = REG_READ(SB_DATA); |
| 197 | |
| 198 | return 0; |
| 199 | } |
| 200 | |
Alan Cox | 37e7b18 | 2012-08-08 13:55:03 +0000 | [diff] [blame] | 201 | int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 202 | { |
| 203 | int ret; |
| 204 | static bool dpio_debug = true; |
| 205 | u32 temp; |
| 206 | |
| 207 | if (dpio_debug) { |
| 208 | if (cdv_sb_read(dev, reg, &temp) == 0) |
| 209 | DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp); |
| 210 | DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); |
| 211 | } |
| 212 | |
| 213 | ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); |
| 214 | if (ret) { |
| 215 | DRM_ERROR("timeout waiting for SB to idle before write\n"); |
| 216 | return ret; |
| 217 | } |
| 218 | |
| 219 | REG_WRITE(SB_ADDR, reg); |
| 220 | REG_WRITE(SB_DATA, val); |
| 221 | REG_WRITE(SB_PCKT, |
| 222 | SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | |
| 223 | SET_FIELD(SB_DEST_DPLL, SB_DEST) | |
| 224 | SET_FIELD(0xf, SB_BYTE_ENABLE)); |
| 225 | |
| 226 | ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); |
| 227 | if (ret) { |
| 228 | DRM_ERROR("timeout waiting for SB to idle after write\n"); |
| 229 | return ret; |
| 230 | } |
| 231 | |
| 232 | if (dpio_debug) { |
| 233 | if (cdv_sb_read(dev, reg, &temp) == 0) |
| 234 | DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp); |
| 235 | } |
| 236 | |
| 237 | return 0; |
| 238 | } |
| 239 | |
| 240 | /* Reset the DPIO configuration register. The BIOS does this at every |
| 241 | * mode set. |
| 242 | */ |
Alan Cox | 37e7b18 | 2012-08-08 13:55:03 +0000 | [diff] [blame] | 243 | void cdv_sb_reset(struct drm_device *dev) |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 244 | { |
| 245 | |
| 246 | REG_WRITE(DPIO_CFG, 0); |
| 247 | REG_READ(DPIO_CFG); |
| 248 | REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); |
| 249 | } |
| 250 | |
| 251 | /* Unlike most Intel display engines, on Cedarview the DPLL registers |
| 252 | * are behind this sideband bus. They must be programmed while the |
| 253 | * DPLL reference clock is on in the DPLL control register, but before |
| 254 | * the DPLL is enabled in the DPLL control register. |
| 255 | */ |
| 256 | static int |
| 257 | cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 258 | struct cdv_intel_clock_t *clock, bool is_lvds, u32 ddi_select) |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 259 | { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 260 | struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 261 | int pipe = psb_crtc->pipe; |
| 262 | u32 m, n_vco, p; |
| 263 | int ret = 0; |
| 264 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 265 | int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 266 | u32 ref_value; |
Alan Cox | d235e64 | 2012-04-25 14:38:07 +0100 | [diff] [blame] | 267 | u32 lane_reg, lane_value; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 268 | |
| 269 | cdv_sb_reset(dev); |
| 270 | |
Alan Cox | d235e64 | 2012-04-25 14:38:07 +0100 | [diff] [blame] | 271 | REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); |
| 272 | |
| 273 | udelay(100); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 274 | |
| 275 | /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */ |
| 276 | ref_value = 0x68A701; |
| 277 | |
| 278 | cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value); |
| 279 | |
| 280 | /* We don't know what the other fields of these regs are, so |
| 281 | * leave them in place. |
| 282 | */ |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 283 | /* |
| 284 | * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk |
| 285 | * for the pipe A/B. Display spec 1.06 has wrong definition. |
| 286 | * Correct definition is like below: |
| 287 | * |
| 288 | * refclka mean use clock from same PLL |
| 289 | * |
| 290 | * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll |
| 291 | * |
| 292 | * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA |
| 293 | * |
| 294 | */ |
| 295 | ret = cdv_sb_read(dev, ref_sfr, &ref_value); |
| 296 | if (ret) |
| 297 | return ret; |
| 298 | ref_value &= ~(REF_CLK_MASK); |
| 299 | |
| 300 | /* use DPLL_A for pipeB on CRT/HDMI */ |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 301 | if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) { |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 302 | DRM_DEBUG_KMS("use DPLLA for pipe B\n"); |
| 303 | ref_value |= REF_CLK_DPLLA; |
| 304 | } else { |
| 305 | DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); |
| 306 | ref_value |= REF_CLK_DPLL; |
| 307 | } |
| 308 | ret = cdv_sb_write(dev, ref_sfr, ref_value); |
| 309 | if (ret) |
| 310 | return ret; |
| 311 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 312 | ret = cdv_sb_read(dev, SB_M(pipe), &m); |
| 313 | if (ret) |
| 314 | return ret; |
| 315 | m &= ~SB_M_DIVIDER_MASK; |
| 316 | m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); |
| 317 | ret = cdv_sb_write(dev, SB_M(pipe), m); |
| 318 | if (ret) |
| 319 | return ret; |
| 320 | |
| 321 | ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco); |
| 322 | if (ret) |
| 323 | return ret; |
| 324 | |
| 325 | /* Follow the BIOS to program the N_DIVIDER REG */ |
| 326 | n_vco &= 0xFFFF; |
| 327 | n_vco |= 0x107; |
| 328 | n_vco &= ~(SB_N_VCO_SEL_MASK | |
| 329 | SB_N_DIVIDER_MASK | |
| 330 | SB_N_CB_TUNE_MASK); |
| 331 | |
| 332 | n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); |
| 333 | |
| 334 | if (clock->vco < 2250000) { |
| 335 | n_vco |= (2 << SB_N_CB_TUNE_SHIFT); |
| 336 | n_vco |= (0 << SB_N_VCO_SEL_SHIFT); |
| 337 | } else if (clock->vco < 2750000) { |
| 338 | n_vco |= (1 << SB_N_CB_TUNE_SHIFT); |
| 339 | n_vco |= (1 << SB_N_VCO_SEL_SHIFT); |
| 340 | } else if (clock->vco < 3300000) { |
| 341 | n_vco |= (0 << SB_N_CB_TUNE_SHIFT); |
| 342 | n_vco |= (2 << SB_N_VCO_SEL_SHIFT); |
| 343 | } else { |
| 344 | n_vco |= (0 << SB_N_CB_TUNE_SHIFT); |
| 345 | n_vco |= (3 << SB_N_VCO_SEL_SHIFT); |
| 346 | } |
| 347 | |
| 348 | ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco); |
| 349 | if (ret) |
| 350 | return ret; |
| 351 | |
| 352 | ret = cdv_sb_read(dev, SB_P(pipe), &p); |
| 353 | if (ret) |
| 354 | return ret; |
| 355 | p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK); |
| 356 | p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); |
| 357 | switch (clock->p2) { |
| 358 | case 5: |
| 359 | p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); |
| 360 | break; |
| 361 | case 10: |
| 362 | p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); |
| 363 | break; |
| 364 | case 14: |
| 365 | p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); |
| 366 | break; |
| 367 | case 7: |
| 368 | p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); |
| 369 | break; |
| 370 | default: |
| 371 | DRM_ERROR("Bad P2 clock: %d\n", clock->p2); |
| 372 | return -EINVAL; |
| 373 | } |
| 374 | ret = cdv_sb_write(dev, SB_P(pipe), p); |
| 375 | if (ret) |
| 376 | return ret; |
| 377 | |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 378 | if (ddi_select) { |
| 379 | if ((ddi_select & DDI_MASK) == DDI0_SELECT) { |
| 380 | lane_reg = PSB_LANE0; |
| 381 | cdv_sb_read(dev, lane_reg, &lane_value); |
| 382 | lane_value &= ~(LANE_PLL_MASK); |
| 383 | lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); |
| 384 | cdv_sb_write(dev, lane_reg, lane_value); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 385 | |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 386 | lane_reg = PSB_LANE1; |
| 387 | cdv_sb_read(dev, lane_reg, &lane_value); |
| 388 | lane_value &= ~(LANE_PLL_MASK); |
| 389 | lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); |
| 390 | cdv_sb_write(dev, lane_reg, lane_value); |
| 391 | } else { |
| 392 | lane_reg = PSB_LANE2; |
| 393 | cdv_sb_read(dev, lane_reg, &lane_value); |
| 394 | lane_value &= ~(LANE_PLL_MASK); |
| 395 | lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); |
| 396 | cdv_sb_write(dev, lane_reg, lane_value); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 397 | |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 398 | lane_reg = PSB_LANE3; |
| 399 | cdv_sb_read(dev, lane_reg, &lane_value); |
| 400 | lane_value &= ~(LANE_PLL_MASK); |
| 401 | lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); |
| 402 | cdv_sb_write(dev, lane_reg, lane_value); |
| 403 | } |
| 404 | } |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | /* |
Patrik Jakobsson | a12d6a0 | 2011-12-19 21:41:22 +0000 | [diff] [blame] | 409 | * Returns whether any encoder on the specified pipe is of the specified type |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 410 | */ |
Kirill A. Shutemov | 657da16 | 2012-03-08 16:10:23 +0000 | [diff] [blame] | 411 | static bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type) |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 412 | { |
| 413 | struct drm_device *dev = crtc->dev; |
| 414 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 415 | struct drm_connector *l_entry; |
| 416 | |
| 417 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { |
| 418 | if (l_entry->encoder && l_entry->encoder->crtc == crtc) { |
Patrik Jakobsson | a12d6a0 | 2011-12-19 21:41:22 +0000 | [diff] [blame] | 419 | struct psb_intel_encoder *psb_intel_encoder = |
| 420 | psb_intel_attached_encoder(l_entry); |
| 421 | if (psb_intel_encoder->type == type) |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 422 | return true; |
| 423 | } |
| 424 | } |
| 425 | return false; |
| 426 | } |
| 427 | |
| 428 | static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc, |
| 429 | int refclk) |
| 430 | { |
| 431 | const struct cdv_intel_limit_t *limit; |
| 432 | if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
| 433 | /* |
| 434 | * Now only single-channel LVDS is supported on CDV. If it is |
| 435 | * incorrect, please add the dual-channel LVDS. |
| 436 | */ |
| 437 | if (refclk == 96000) |
| 438 | limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96]; |
| 439 | else |
| 440 | limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100]; |
Zhao Yakui | d112a81 | 2012-08-08 13:55:55 +0000 | [diff] [blame] | 441 | } else if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
| 442 | psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 443 | if (refclk == 27000) |
| 444 | limit = &cdv_intel_limits[CDV_LIMIT_DP_27]; |
| 445 | else |
| 446 | limit = &cdv_intel_limits[CDV_LIMIT_DP_100]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 447 | } else { |
| 448 | if (refclk == 27000) |
| 449 | limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27]; |
| 450 | else |
| 451 | limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96]; |
| 452 | } |
| 453 | return limit; |
| 454 | } |
| 455 | |
| 456 | /* m1 is reserved as 0 in CDV, n is a ring counter */ |
| 457 | static void cdv_intel_clock(struct drm_device *dev, |
| 458 | int refclk, struct cdv_intel_clock_t *clock) |
| 459 | { |
| 460 | clock->m = clock->m2 + 2; |
| 461 | clock->p = clock->p1 * clock->p2; |
| 462 | clock->vco = (refclk * clock->m) / clock->n; |
| 463 | clock->dot = clock->vco / clock->p; |
| 464 | } |
| 465 | |
| 466 | |
| 467 | #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } |
| 468 | static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc, |
| 469 | const struct cdv_intel_limit_t *limit, |
| 470 | struct cdv_intel_clock_t *clock) |
| 471 | { |
| 472 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
| 473 | INTELPllInvalid("p1 out of range\n"); |
| 474 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 475 | INTELPllInvalid("p out of range\n"); |
| 476 | /* unnecessary to check the range of m(m1/M2)/n again */ |
| 477 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
| 478 | INTELPllInvalid("vco out of range\n"); |
| 479 | /* XXX: We may need to be checking "Dot clock" |
| 480 | * depending on the multiplier, connector, etc., |
| 481 | * rather than just a single range. |
| 482 | */ |
| 483 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
| 484 | INTELPllInvalid("dot out of range\n"); |
| 485 | |
| 486 | return true; |
| 487 | } |
| 488 | |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 489 | static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit, |
| 490 | struct drm_crtc *crtc, int target, int refclk, |
| 491 | struct cdv_intel_clock_t *best_clock) |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 492 | { |
| 493 | struct drm_device *dev = crtc->dev; |
| 494 | struct cdv_intel_clock_t clock; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 495 | int err = target; |
| 496 | |
| 497 | |
| 498 | if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
| 499 | (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { |
| 500 | /* |
| 501 | * For LVDS, if the panel is on, just rely on its current |
| 502 | * settings for dual-channel. We haven't figured out how to |
| 503 | * reliably set up different single/dual channel state, if we |
| 504 | * even can. |
| 505 | */ |
| 506 | if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == |
| 507 | LVDS_CLKB_POWER_UP) |
| 508 | clock.p2 = limit->p2.p2_fast; |
| 509 | else |
| 510 | clock.p2 = limit->p2.p2_slow; |
| 511 | } else { |
| 512 | if (target < limit->p2.dot_limit) |
| 513 | clock.p2 = limit->p2.p2_slow; |
| 514 | else |
| 515 | clock.p2 = limit->p2.p2_fast; |
| 516 | } |
| 517 | |
| 518 | memset(best_clock, 0, sizeof(*best_clock)); |
| 519 | clock.m1 = 0; |
| 520 | /* m1 is reserved as 0 in CDV, n is a ring counter. |
| 521 | So skip the m1 loop */ |
| 522 | for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) { |
| 523 | for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; |
| 524 | clock.m2++) { |
| 525 | for (clock.p1 = limit->p1.min; |
| 526 | clock.p1 <= limit->p1.max; |
| 527 | clock.p1++) { |
| 528 | int this_err; |
| 529 | |
| 530 | cdv_intel_clock(dev, refclk, &clock); |
| 531 | |
| 532 | if (!cdv_intel_PLL_is_valid(crtc, |
| 533 | limit, &clock)) |
| 534 | continue; |
| 535 | |
| 536 | this_err = abs(clock.dot - target); |
| 537 | if (this_err < err) { |
| 538 | *best_clock = clock; |
| 539 | err = this_err; |
| 540 | } |
| 541 | } |
| 542 | } |
| 543 | } |
| 544 | |
| 545 | return err != target; |
| 546 | } |
| 547 | |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 548 | static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct drm_crtc *crtc, int target, |
| 549 | int refclk, |
| 550 | struct cdv_intel_clock_t *best_clock) |
| 551 | { |
| 552 | struct cdv_intel_clock_t clock; |
| 553 | if (refclk == 27000) { |
| 554 | if (target < 200000) { |
| 555 | clock.p1 = 2; |
| 556 | clock.p2 = 10; |
| 557 | clock.n = 1; |
| 558 | clock.m1 = 0; |
| 559 | clock.m2 = 118; |
| 560 | } else { |
| 561 | clock.p1 = 1; |
| 562 | clock.p2 = 10; |
| 563 | clock.n = 1; |
| 564 | clock.m1 = 0; |
| 565 | clock.m2 = 98; |
| 566 | } |
| 567 | } else if (refclk == 100000) { |
| 568 | if (target < 200000) { |
| 569 | clock.p1 = 2; |
| 570 | clock.p2 = 10; |
| 571 | clock.n = 5; |
| 572 | clock.m1 = 0; |
| 573 | clock.m2 = 160; |
| 574 | } else { |
| 575 | clock.p1 = 1; |
| 576 | clock.p2 = 10; |
| 577 | clock.n = 5; |
| 578 | clock.m1 = 0; |
| 579 | clock.m2 = 133; |
| 580 | } |
| 581 | } else |
| 582 | return false; |
| 583 | clock.m = clock.m2 + 2; |
| 584 | clock.p = clock.p1 * clock.p2; |
| 585 | clock.vco = (refclk * clock.m) / clock.n; |
| 586 | clock.dot = clock.vco / clock.p; |
| 587 | memcpy(best_clock, &clock, sizeof(struct cdv_intel_clock_t)); |
| 588 | return true; |
| 589 | } |
| 590 | |
Kirill A. Shutemov | 657da16 | 2012-03-08 16:10:23 +0000 | [diff] [blame] | 591 | static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 592 | int x, int y, struct drm_framebuffer *old_fb) |
| 593 | { |
| 594 | struct drm_device *dev = crtc->dev; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 595 | struct drm_psb_private *dev_priv = dev->dev_private; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 596 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 597 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); |
| 598 | int pipe = psb_intel_crtc->pipe; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 599 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 600 | unsigned long start, offset; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 601 | u32 dspcntr; |
| 602 | int ret = 0; |
| 603 | |
| 604 | if (!gma_power_begin(dev, true)) |
| 605 | return 0; |
| 606 | |
| 607 | /* no fb bound */ |
| 608 | if (!crtc->fb) { |
| 609 | dev_err(dev->dev, "No FB bound\n"); |
| 610 | goto psb_intel_pipe_cleaner; |
| 611 | } |
| 612 | |
| 613 | |
| 614 | /* We are displaying this buffer, make sure it is actually loaded |
| 615 | into the GTT */ |
| 616 | ret = psb_gtt_pin(psbfb->gtt); |
| 617 | if (ret < 0) |
| 618 | goto psb_intel_pipe_set_base_exit; |
| 619 | start = psbfb->gtt->offset; |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 620 | offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 621 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 622 | REG_WRITE(map->stride, crtc->fb->pitches[0]); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 623 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 624 | dspcntr = REG_READ(map->cntr); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 625 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
| 626 | |
| 627 | switch (crtc->fb->bits_per_pixel) { |
| 628 | case 8: |
| 629 | dspcntr |= DISPPLANE_8BPP; |
| 630 | break; |
| 631 | case 16: |
| 632 | if (crtc->fb->depth == 15) |
| 633 | dspcntr |= DISPPLANE_15_16BPP; |
| 634 | else |
| 635 | dspcntr |= DISPPLANE_16BPP; |
| 636 | break; |
| 637 | case 24: |
| 638 | case 32: |
| 639 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; |
| 640 | break; |
| 641 | default: |
| 642 | dev_err(dev->dev, "Unknown color depth\n"); |
| 643 | ret = -EINVAL; |
| 644 | goto psb_intel_pipe_set_base_exit; |
| 645 | } |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 646 | REG_WRITE(map->cntr, dspcntr); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 647 | |
| 648 | dev_dbg(dev->dev, |
| 649 | "Writing base %08lX %08lX %d %d\n", start, offset, x, y); |
| 650 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 651 | REG_WRITE(map->base, offset); |
| 652 | REG_READ(map->base); |
| 653 | REG_WRITE(map->surf, start); |
| 654 | REG_READ(map->surf); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 655 | |
| 656 | psb_intel_pipe_cleaner: |
| 657 | /* If there was a previous display we can now unpin it */ |
| 658 | if (old_fb) |
| 659 | psb_gtt_unpin(to_psb_fb(old_fb)->gtt); |
| 660 | |
| 661 | psb_intel_pipe_set_base_exit: |
| 662 | gma_power_end(dev); |
| 663 | return ret; |
| 664 | } |
| 665 | |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 666 | #define FIFO_PIPEA (1 << 0) |
| 667 | #define FIFO_PIPEB (1 << 1) |
| 668 | |
| 669 | static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe) |
| 670 | { |
| 671 | struct drm_crtc *crtc; |
| 672 | struct drm_psb_private *dev_priv = dev->dev_private; |
| 673 | struct psb_intel_crtc *psb_intel_crtc = NULL; |
| 674 | |
| 675 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
| 676 | psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 677 | |
| 678 | if (crtc->fb == NULL || !psb_intel_crtc->active) |
| 679 | return false; |
| 680 | return true; |
| 681 | } |
| 682 | |
| 683 | static bool cdv_intel_single_pipe_active (struct drm_device *dev) |
| 684 | { |
| 685 | uint32_t pipe_enabled = 0; |
| 686 | |
| 687 | if (cdv_intel_pipe_enabled(dev, 0)) |
| 688 | pipe_enabled |= FIFO_PIPEA; |
| 689 | |
| 690 | if (cdv_intel_pipe_enabled(dev, 1)) |
| 691 | pipe_enabled |= FIFO_PIPEB; |
| 692 | |
| 693 | |
| 694 | DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled); |
| 695 | |
| 696 | if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB) |
| 697 | return true; |
| 698 | else |
| 699 | return false; |
| 700 | } |
| 701 | |
| 702 | static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc) |
| 703 | { |
| 704 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 705 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 706 | struct drm_connector *connector; |
| 707 | |
| 708 | if (psb_intel_crtc->pipe != 1) |
| 709 | return false; |
| 710 | |
| 711 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 712 | struct psb_intel_encoder *psb_intel_encoder = |
| 713 | psb_intel_attached_encoder(connector); |
| 714 | |
| 715 | if (!connector->encoder |
| 716 | || connector->encoder->crtc != crtc) |
| 717 | continue; |
| 718 | |
| 719 | if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS) |
| 720 | return true; |
| 721 | } |
| 722 | |
| 723 | return false; |
| 724 | } |
| 725 | |
| 726 | static void cdv_intel_disable_self_refresh (struct drm_device *dev) |
| 727 | { |
| 728 | if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { |
| 729 | |
| 730 | /* Disable self-refresh before adjust WM */ |
| 731 | REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); |
| 732 | REG_READ(FW_BLC_SELF); |
| 733 | |
| 734 | cdv_intel_wait_for_vblank(dev); |
| 735 | |
| 736 | /* Cedarview workaround to write ovelay plane, which force to leave |
| 737 | * MAX_FIFO state. |
| 738 | */ |
| 739 | REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); |
| 740 | REG_READ(OV_OVADD); |
| 741 | |
| 742 | cdv_intel_wait_for_vblank(dev); |
| 743 | } |
| 744 | |
| 745 | } |
| 746 | |
| 747 | static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc) |
| 748 | { |
| 749 | |
| 750 | if (cdv_intel_single_pipe_active(dev)) { |
| 751 | u32 fw; |
| 752 | |
| 753 | fw = REG_READ(DSPFW1); |
| 754 | fw &= ~DSP_FIFO_SR_WM_MASK; |
| 755 | fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT); |
| 756 | fw &= ~CURSOR_B_FIFO_WM_MASK; |
| 757 | fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT); |
| 758 | REG_WRITE(DSPFW1, fw); |
| 759 | |
| 760 | fw = REG_READ(DSPFW2); |
| 761 | fw &= ~CURSOR_A_FIFO_WM_MASK; |
| 762 | fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT); |
| 763 | fw &= ~DSP_PLANE_C_FIFO_WM_MASK; |
| 764 | fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT); |
| 765 | REG_WRITE(DSPFW2, fw); |
| 766 | |
| 767 | REG_WRITE(DSPFW3, 0x36000000); |
| 768 | |
| 769 | /* ignore FW4 */ |
| 770 | |
| 771 | if (is_pipeb_lvds(dev, crtc)) { |
| 772 | REG_WRITE(DSPFW5, 0x00040330); |
| 773 | } else { |
| 774 | fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) | |
| 775 | (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) | |
| 776 | (3 << CURSOR_B_FIFO_WM1_SHIFT) | |
| 777 | (4 << CURSOR_FIFO_SR_WM1_SHIFT); |
| 778 | REG_WRITE(DSPFW5, fw); |
| 779 | } |
| 780 | |
| 781 | REG_WRITE(DSPFW6, 0x10); |
| 782 | |
| 783 | cdv_intel_wait_for_vblank(dev); |
| 784 | |
| 785 | /* enable self-refresh for single pipe active */ |
| 786 | REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
| 787 | REG_READ(FW_BLC_SELF); |
| 788 | cdv_intel_wait_for_vblank(dev); |
| 789 | |
| 790 | } else { |
| 791 | |
| 792 | /* HW team suggested values... */ |
| 793 | REG_WRITE(DSPFW1, 0x3f880808); |
| 794 | REG_WRITE(DSPFW2, 0x0b020202); |
| 795 | REG_WRITE(DSPFW3, 0x24000000); |
| 796 | REG_WRITE(DSPFW4, 0x08030202); |
| 797 | REG_WRITE(DSPFW5, 0x01010101); |
| 798 | REG_WRITE(DSPFW6, 0x1d0); |
| 799 | |
| 800 | cdv_intel_wait_for_vblank(dev); |
| 801 | |
| 802 | cdv_intel_disable_self_refresh(dev); |
| 803 | |
| 804 | } |
| 805 | } |
| 806 | |
| 807 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
| 808 | static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) |
| 809 | { |
| 810 | struct drm_device *dev = crtc->dev; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 811 | struct drm_psb_private *dev_priv = dev->dev_private; |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 812 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 813 | int palreg = PALETTE_A; |
| 814 | int i; |
| 815 | |
| 816 | /* The clocks have to be on to load the palette. */ |
| 817 | if (!crtc->enabled) |
| 818 | return; |
| 819 | |
| 820 | switch (psb_intel_crtc->pipe) { |
| 821 | case 0: |
| 822 | break; |
| 823 | case 1: |
| 824 | palreg = PALETTE_B; |
| 825 | break; |
| 826 | case 2: |
| 827 | palreg = PALETTE_C; |
| 828 | break; |
| 829 | default: |
| 830 | dev_err(dev->dev, "Illegal Pipe Number.\n"); |
| 831 | return; |
| 832 | } |
| 833 | |
| 834 | if (gma_power_begin(dev, false)) { |
| 835 | for (i = 0; i < 256; i++) { |
| 836 | REG_WRITE(palreg + 4 * i, |
| 837 | ((psb_intel_crtc->lut_r[i] + |
| 838 | psb_intel_crtc->lut_adj[i]) << 16) | |
| 839 | ((psb_intel_crtc->lut_g[i] + |
| 840 | psb_intel_crtc->lut_adj[i]) << 8) | |
| 841 | (psb_intel_crtc->lut_b[i] + |
| 842 | psb_intel_crtc->lut_adj[i])); |
| 843 | } |
| 844 | gma_power_end(dev); |
| 845 | } else { |
| 846 | for (i = 0; i < 256; i++) { |
Alan Cox | 6256304 | 2012-05-11 11:30:16 +0100 | [diff] [blame] | 847 | dev_priv->regs.pipe[0].palette[i] = |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 848 | ((psb_intel_crtc->lut_r[i] + |
| 849 | psb_intel_crtc->lut_adj[i]) << 16) | |
| 850 | ((psb_intel_crtc->lut_g[i] + |
| 851 | psb_intel_crtc->lut_adj[i]) << 8) | |
| 852 | (psb_intel_crtc->lut_b[i] + |
| 853 | psb_intel_crtc->lut_adj[i]); |
| 854 | } |
| 855 | |
| 856 | } |
| 857 | } |
| 858 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 859 | /** |
| 860 | * Sets the power management mode of the pipe and plane. |
| 861 | * |
| 862 | * This code should probably grow support for turning the cursor off and back |
| 863 | * on appropriately at the same time as we're turning the pipe off/on. |
| 864 | */ |
| 865 | static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 866 | { |
| 867 | struct drm_device *dev = crtc->dev; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 868 | struct drm_psb_private *dev_priv = dev->dev_private; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 869 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 870 | int pipe = psb_intel_crtc->pipe; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 871 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 872 | u32 temp; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 873 | |
| 874 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
| 875 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. |
| 876 | */ |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 877 | cdv_intel_disable_self_refresh(dev); |
| 878 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 879 | switch (mode) { |
| 880 | case DRM_MODE_DPMS_ON: |
| 881 | case DRM_MODE_DPMS_STANDBY: |
| 882 | case DRM_MODE_DPMS_SUSPEND: |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 883 | if (psb_intel_crtc->active) |
Zhao Yakui | 25e9dc6 | 2012-08-08 13:53:15 +0000 | [diff] [blame] | 884 | break; |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 885 | |
| 886 | psb_intel_crtc->active = true; |
| 887 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 888 | /* Enable the DPLL */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 889 | temp = REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 890 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 891 | REG_WRITE(map->dpll, temp); |
| 892 | REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 893 | /* Wait for the clocks to stabilize. */ |
| 894 | udelay(150); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 895 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); |
| 896 | REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 897 | /* Wait for the clocks to stabilize. */ |
| 898 | udelay(150); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 899 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); |
| 900 | REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 901 | /* Wait for the clocks to stabilize. */ |
| 902 | udelay(150); |
| 903 | } |
| 904 | |
| 905 | /* Jim Bish - switch plan and pipe per scott */ |
| 906 | /* Enable the plane */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 907 | temp = REG_READ(map->cntr); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 908 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 909 | REG_WRITE(map->cntr, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 910 | temp | DISPLAY_PLANE_ENABLE); |
| 911 | /* Flush the plane changes */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 912 | REG_WRITE(map->base, REG_READ(map->base)); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 913 | } |
| 914 | |
| 915 | udelay(150); |
| 916 | |
| 917 | /* Enable the pipe */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 918 | temp = REG_READ(map->conf); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 919 | if ((temp & PIPEACONF_ENABLE) == 0) |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 920 | REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 921 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 922 | temp = REG_READ(map->status); |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 923 | temp &= ~(0xFFFF); |
| 924 | temp |= PIPE_FIFO_UNDERRUN; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 925 | REG_WRITE(map->status, temp); |
| 926 | REG_READ(map->status); |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 927 | |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 928 | cdv_intel_crtc_load_lut(crtc); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 929 | |
| 930 | /* Give the overlay scaler a chance to enable |
| 931 | * if it's on this pipe */ |
| 932 | /* psb_intel_crtc_dpms_video(crtc, true); TODO */ |
| 933 | break; |
| 934 | case DRM_MODE_DPMS_OFF: |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 935 | if (!psb_intel_crtc->active) |
Zhao Yakui | 25e9dc6 | 2012-08-08 13:53:15 +0000 | [diff] [blame] | 936 | break; |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 937 | |
| 938 | psb_intel_crtc->active = false; |
| 939 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 940 | /* Give the overlay scaler a chance to disable |
| 941 | * if it's on this pipe */ |
| 942 | /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ |
| 943 | |
| 944 | /* Disable the VGA plane that we never use */ |
| 945 | REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); |
| 946 | |
| 947 | /* Jim Bish - changed pipe/plane here as well. */ |
| 948 | |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 949 | drm_vblank_off(dev, pipe); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 950 | /* Wait for vblank for the disable to take effect */ |
| 951 | cdv_intel_wait_for_vblank(dev); |
| 952 | |
| 953 | /* Next, disable display pipes */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 954 | temp = REG_READ(map->conf); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 955 | if ((temp & PIPEACONF_ENABLE) != 0) { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 956 | REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); |
| 957 | REG_READ(map->conf); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 958 | } |
| 959 | |
| 960 | /* Wait for vblank for the disable to take effect. */ |
| 961 | cdv_intel_wait_for_vblank(dev); |
| 962 | |
| 963 | udelay(150); |
| 964 | |
| 965 | /* Disable display plane */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 966 | temp = REG_READ(map->cntr); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 967 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 968 | REG_WRITE(map->cntr, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 969 | temp & ~DISPLAY_PLANE_ENABLE); |
| 970 | /* Flush the plane changes */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 971 | REG_WRITE(map->base, REG_READ(map->base)); |
| 972 | REG_READ(map->base); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 973 | } |
| 974 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 975 | temp = REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 976 | if ((temp & DPLL_VCO_ENABLE) != 0) { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 977 | REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); |
| 978 | REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 979 | } |
| 980 | |
| 981 | /* Wait for the clocks to turn off. */ |
| 982 | udelay(150); |
| 983 | break; |
| 984 | } |
Zhao Yakui | 25e9dc6 | 2012-08-08 13:53:15 +0000 | [diff] [blame] | 985 | cdv_intel_update_watermark(dev, crtc); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 986 | /*Set FIFO Watermarks*/ |
| 987 | REG_WRITE(DSPARB, 0x3F3E); |
| 988 | } |
| 989 | |
| 990 | static void cdv_intel_crtc_prepare(struct drm_crtc *crtc) |
| 991 | { |
| 992 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 993 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); |
| 994 | } |
| 995 | |
| 996 | static void cdv_intel_crtc_commit(struct drm_crtc *crtc) |
| 997 | { |
| 998 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| 999 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); |
| 1000 | } |
| 1001 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1002 | static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 1003 | const struct drm_display_mode *mode, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1004 | struct drm_display_mode *adjusted_mode) |
| 1005 | { |
| 1006 | return true; |
| 1007 | } |
| 1008 | |
| 1009 | |
| 1010 | /** |
| 1011 | * Return the pipe currently connected to the panel fitter, |
| 1012 | * or -1 if the panel fitter is not present or not in use |
| 1013 | */ |
| 1014 | static int cdv_intel_panel_fitter_pipe(struct drm_device *dev) |
| 1015 | { |
| 1016 | u32 pfit_control; |
| 1017 | |
| 1018 | pfit_control = REG_READ(PFIT_CONTROL); |
| 1019 | |
| 1020 | /* See if the panel fitter is in use */ |
| 1021 | if ((pfit_control & PFIT_ENABLE) == 0) |
| 1022 | return -1; |
| 1023 | return (pfit_control >> 29) & 0x3; |
| 1024 | } |
| 1025 | |
| 1026 | static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, |
| 1027 | struct drm_display_mode *mode, |
| 1028 | struct drm_display_mode *adjusted_mode, |
| 1029 | int x, int y, |
| 1030 | struct drm_framebuffer *old_fb) |
| 1031 | { |
| 1032 | struct drm_device *dev = crtc->dev; |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 1033 | struct drm_psb_private *dev_priv = dev->dev_private; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1034 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1035 | int pipe = psb_intel_crtc->pipe; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1036 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1037 | int refclk; |
| 1038 | struct cdv_intel_clock_t clock; |
| 1039 | u32 dpll = 0, dspcntr, pipeconf; |
Kirill A. Shutemov | 0313c0d | 2012-03-08 16:10:10 +0000 | [diff] [blame] | 1040 | bool ok; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1041 | bool is_crt = false, is_lvds = false, is_tv = false; |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 1042 | bool is_hdmi = false, is_dp = false; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1043 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 1044 | struct drm_connector *connector; |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 1045 | const struct cdv_intel_limit_t *limit; |
| 1046 | u32 ddi_select = 0; |
Zhao Yakui | d112a81 | 2012-08-08 13:55:55 +0000 | [diff] [blame] | 1047 | bool is_edp = false; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1048 | |
| 1049 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
Patrik Jakobsson | a12d6a0 | 2011-12-19 21:41:22 +0000 | [diff] [blame] | 1050 | struct psb_intel_encoder *psb_intel_encoder = |
| 1051 | psb_intel_attached_encoder(connector); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1052 | |
| 1053 | if (!connector->encoder |
| 1054 | || connector->encoder->crtc != crtc) |
| 1055 | continue; |
| 1056 | |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 1057 | ddi_select = psb_intel_encoder->ddi_select; |
Patrik Jakobsson | a12d6a0 | 2011-12-19 21:41:22 +0000 | [diff] [blame] | 1058 | switch (psb_intel_encoder->type) { |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1059 | case INTEL_OUTPUT_LVDS: |
| 1060 | is_lvds = true; |
| 1061 | break; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1062 | case INTEL_OUTPUT_TVOUT: |
| 1063 | is_tv = true; |
| 1064 | break; |
| 1065 | case INTEL_OUTPUT_ANALOG: |
| 1066 | is_crt = true; |
| 1067 | break; |
| 1068 | case INTEL_OUTPUT_HDMI: |
| 1069 | is_hdmi = true; |
| 1070 | break; |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 1071 | case INTEL_OUTPUT_DISPLAYPORT: |
| 1072 | is_dp = true; |
| 1073 | break; |
Zhao Yakui | d112a81 | 2012-08-08 13:55:55 +0000 | [diff] [blame] | 1074 | case INTEL_OUTPUT_EDP: |
| 1075 | is_edp = true; |
| 1076 | break; |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 1077 | default: |
| 1078 | DRM_ERROR("invalid output type.\n"); |
| 1079 | return 0; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1080 | } |
| 1081 | } |
| 1082 | |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 1083 | if (dev_priv->dplla_96mhz) |
| 1084 | /* low-end sku, 96/100 mhz */ |
| 1085 | refclk = 96000; |
| 1086 | else |
| 1087 | /* high-end sku, 27/100 mhz */ |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1088 | refclk = 27000; |
Zhao Yakui | d112a81 | 2012-08-08 13:55:55 +0000 | [diff] [blame] | 1089 | if (is_dp || is_edp) { |
| 1090 | /* |
| 1091 | * Based on the spec the low-end SKU has only CRT/LVDS. So it is |
| 1092 | * unnecessary to consider it for DP/eDP. |
| 1093 | * On the high-end SKU, it will use the 27/100M reference clk |
| 1094 | * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise |
| 1095 | * it will be 27MHz. From the VBIOS code it seems that the pipe A choose |
| 1096 | * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. |
| 1097 | */ |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 1098 | if (pipe == 0) |
| 1099 | refclk = 27000; |
| 1100 | else |
| 1101 | refclk = 100000; |
| 1102 | } |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1103 | |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 1104 | if (is_lvds && dev_priv->lvds_use_ssc) { |
| 1105 | refclk = dev_priv->lvds_ssc_freq * 1000; |
| 1106 | DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); |
| 1107 | } |
| 1108 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1109 | drm_mode_debug_printmodeline(adjusted_mode); |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 1110 | |
| 1111 | limit = cdv_intel_limit(crtc, refclk); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1112 | |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 1113 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1114 | &clock); |
| 1115 | if (!ok) { |
| 1116 | dev_err(dev->dev, "Couldn't find PLL settings for mode!\n"); |
| 1117 | return 0; |
| 1118 | } |
| 1119 | |
| 1120 | dpll = DPLL_VGA_MODE_DIS; |
| 1121 | if (is_tv) { |
| 1122 | /* XXX: just matching BIOS for now */ |
| 1123 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
| 1124 | dpll |= 3; |
| 1125 | } |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 1126 | /* dpll |= PLL_REF_INPUT_DREFCLK; */ |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1127 | |
Alan Cox | f76c0dd | 2012-08-22 12:00:28 +0000 | [diff] [blame] | 1128 | if (is_dp || is_edp) { |
| 1129 | cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); |
Alan Cox | 220801b | 2012-08-08 13:54:41 +0000 | [diff] [blame] | 1130 | } else { |
| 1131 | REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0); |
| 1132 | REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0); |
| 1133 | REG_WRITE(PIPE_DP_LINK_M(pipe), 0); |
| 1134 | REG_WRITE(PIPE_DP_LINK_N(pipe), 0); |
| 1135 | } |
| 1136 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1137 | dpll |= DPLL_SYNCLOCK_ENABLE; |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 1138 | /* if (is_lvds) |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1139 | dpll |= DPLLB_MODE_LVDS; |
| 1140 | else |
Alan Cox | acd7ef9 | 2012-04-25 14:36:48 +0100 | [diff] [blame] | 1141 | dpll |= DPLLB_MODE_DAC_SERIAL; */ |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1142 | /* dpll |= (2 << 11); */ |
| 1143 | |
| 1144 | /* setup pipeconf */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1145 | pipeconf = REG_READ(map->conf); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1146 | |
Zhao Yakui | d112a81 | 2012-08-08 13:55:55 +0000 | [diff] [blame] | 1147 | pipeconf &= ~(PIPE_BPC_MASK); |
| 1148 | if (is_edp) { |
| 1149 | switch (dev_priv->edp.bpp) { |
| 1150 | case 24: |
| 1151 | pipeconf |= PIPE_8BPC; |
| 1152 | break; |
| 1153 | case 18: |
| 1154 | pipeconf |= PIPE_6BPC; |
| 1155 | break; |
| 1156 | case 30: |
| 1157 | pipeconf |= PIPE_10BPC; |
| 1158 | break; |
| 1159 | default: |
| 1160 | pipeconf |= PIPE_8BPC; |
| 1161 | break; |
| 1162 | } |
| 1163 | } else if (is_lvds) { |
| 1164 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
| 1165 | if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
| 1166 | pipeconf |= PIPE_8BPC; |
| 1167 | else |
| 1168 | pipeconf |= PIPE_6BPC; |
| 1169 | } else |
| 1170 | pipeconf |= PIPE_8BPC; |
| 1171 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1172 | /* Set up the display plane register */ |
| 1173 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
| 1174 | |
| 1175 | if (pipe == 0) |
| 1176 | dspcntr |= DISPPLANE_SEL_PIPE_A; |
| 1177 | else |
| 1178 | dspcntr |= DISPPLANE_SEL_PIPE_B; |
| 1179 | |
| 1180 | dspcntr |= DISPLAY_PLANE_ENABLE; |
| 1181 | pipeconf |= PIPEACONF_ENABLE; |
| 1182 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1183 | REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); |
| 1184 | REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1185 | |
Zhao Yakui | d667609 | 2012-08-08 13:53:48 +0000 | [diff] [blame] | 1186 | cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1187 | |
| 1188 | udelay(150); |
| 1189 | |
| 1190 | |
| 1191 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
| 1192 | * This is an exception to the general rule that mode_set doesn't turn |
| 1193 | * things on. |
| 1194 | */ |
| 1195 | if (is_lvds) { |
| 1196 | u32 lvds = REG_READ(LVDS); |
| 1197 | |
| 1198 | lvds |= |
| 1199 | LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | |
| 1200 | LVDS_PIPEB_SELECT; |
| 1201 | /* Set the B0-B3 data pairs corresponding to |
| 1202 | * whether we're going to |
| 1203 | * set the DPLLs for dual-channel mode or not. |
| 1204 | */ |
| 1205 | if (clock.p2 == 7) |
| 1206 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
| 1207 | else |
| 1208 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
| 1209 | |
| 1210 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) |
| 1211 | * appropriately here, but we need to look more |
| 1212 | * thoroughly into how panels behave in the two modes. |
| 1213 | */ |
| 1214 | |
| 1215 | REG_WRITE(LVDS, lvds); |
| 1216 | REG_READ(LVDS); |
| 1217 | } |
| 1218 | |
| 1219 | dpll |= DPLL_VCO_ENABLE; |
| 1220 | |
| 1221 | /* Disable the panel fitter if it was on our pipe */ |
| 1222 | if (cdv_intel_panel_fitter_pipe(dev) == pipe) |
| 1223 | REG_WRITE(PFIT_CONTROL, 0); |
| 1224 | |
| 1225 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
| 1226 | drm_mode_debug_printmodeline(mode); |
| 1227 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1228 | REG_WRITE(map->dpll, |
| 1229 | (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); |
| 1230 | REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1231 | /* Wait for the clocks to stabilize. */ |
| 1232 | udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */ |
| 1233 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1234 | if (!(REG_READ(map->dpll) & DPLL_LOCK)) { |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1235 | dev_err(dev->dev, "Failed to get DPLL lock\n"); |
| 1236 | return -EBUSY; |
| 1237 | } |
| 1238 | |
| 1239 | { |
| 1240 | int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1241 | REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1242 | } |
| 1243 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1244 | REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1245 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1246 | REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1247 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1248 | REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1249 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1250 | REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1251 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1252 | REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1253 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1254 | REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1255 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 1256 | /* pipesrc and dspsize control the size that is scaled from, |
| 1257 | * which should always be the user's requested size. |
| 1258 | */ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1259 | REG_WRITE(map->size, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1260 | ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1261 | REG_WRITE(map->pos, 0); |
| 1262 | REG_WRITE(map->src, |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1263 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1264 | REG_WRITE(map->conf, pipeconf); |
| 1265 | REG_READ(map->conf); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1266 | |
| 1267 | cdv_intel_wait_for_vblank(dev); |
| 1268 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1269 | REG_WRITE(map->cntr, dspcntr); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1270 | |
| 1271 | /* Flush the plane changes */ |
| 1272 | { |
| 1273 | struct drm_crtc_helper_funcs *crtc_funcs = |
| 1274 | crtc->helper_private; |
| 1275 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); |
| 1276 | } |
| 1277 | |
| 1278 | cdv_intel_wait_for_vblank(dev); |
| 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1283 | |
| 1284 | /** |
| 1285 | * Save HW states of giving crtc |
| 1286 | */ |
| 1287 | static void cdv_intel_crtc_save(struct drm_crtc *crtc) |
| 1288 | { |
| 1289 | struct drm_device *dev = crtc->dev; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1290 | struct drm_psb_private *dev_priv = dev->dev_private; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1291 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1292 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1293 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1294 | uint32_t paletteReg; |
| 1295 | int i; |
| 1296 | |
| 1297 | if (!crtc_state) { |
| 1298 | dev_dbg(dev->dev, "No CRTC state found\n"); |
| 1299 | return; |
| 1300 | } |
| 1301 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1302 | crtc_state->saveDSPCNTR = REG_READ(map->cntr); |
| 1303 | crtc_state->savePIPECONF = REG_READ(map->conf); |
| 1304 | crtc_state->savePIPESRC = REG_READ(map->src); |
| 1305 | crtc_state->saveFP0 = REG_READ(map->fp0); |
| 1306 | crtc_state->saveFP1 = REG_READ(map->fp1); |
| 1307 | crtc_state->saveDPLL = REG_READ(map->dpll); |
| 1308 | crtc_state->saveHTOTAL = REG_READ(map->htotal); |
| 1309 | crtc_state->saveHBLANK = REG_READ(map->hblank); |
| 1310 | crtc_state->saveHSYNC = REG_READ(map->hsync); |
| 1311 | crtc_state->saveVTOTAL = REG_READ(map->vtotal); |
| 1312 | crtc_state->saveVBLANK = REG_READ(map->vblank); |
| 1313 | crtc_state->saveVSYNC = REG_READ(map->vsync); |
| 1314 | crtc_state->saveDSPSTRIDE = REG_READ(map->stride); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1315 | |
| 1316 | /*NOTE: DSPSIZE DSPPOS only for psb*/ |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1317 | crtc_state->saveDSPSIZE = REG_READ(map->size); |
| 1318 | crtc_state->saveDSPPOS = REG_READ(map->pos); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1319 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1320 | crtc_state->saveDSPBASE = REG_READ(map->base); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1321 | |
| 1322 | DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", |
| 1323 | crtc_state->saveDSPCNTR, |
| 1324 | crtc_state->savePIPECONF, |
| 1325 | crtc_state->savePIPESRC, |
| 1326 | crtc_state->saveFP0, |
| 1327 | crtc_state->saveFP1, |
| 1328 | crtc_state->saveDPLL, |
| 1329 | crtc_state->saveHTOTAL, |
| 1330 | crtc_state->saveHBLANK, |
| 1331 | crtc_state->saveHSYNC, |
| 1332 | crtc_state->saveVTOTAL, |
| 1333 | crtc_state->saveVBLANK, |
| 1334 | crtc_state->saveVSYNC, |
| 1335 | crtc_state->saveDSPSTRIDE, |
| 1336 | crtc_state->saveDSPSIZE, |
| 1337 | crtc_state->saveDSPPOS, |
| 1338 | crtc_state->saveDSPBASE |
| 1339 | ); |
| 1340 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1341 | paletteReg = map->palette; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1342 | for (i = 0; i < 256; ++i) |
| 1343 | crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); |
| 1344 | } |
| 1345 | |
| 1346 | /** |
| 1347 | * Restore HW states of giving crtc |
| 1348 | */ |
| 1349 | static void cdv_intel_crtc_restore(struct drm_crtc *crtc) |
| 1350 | { |
| 1351 | struct drm_device *dev = crtc->dev; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1352 | struct drm_psb_private *dev_priv = dev->dev_private; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1353 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1354 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1355 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1356 | uint32_t paletteReg; |
| 1357 | int i; |
| 1358 | |
| 1359 | if (!crtc_state) { |
| 1360 | dev_dbg(dev->dev, "No crtc state\n"); |
| 1361 | return; |
| 1362 | } |
| 1363 | |
| 1364 | DRM_DEBUG( |
| 1365 | "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1366 | REG_READ(map->cntr), |
| 1367 | REG_READ(map->conf), |
| 1368 | REG_READ(map->src), |
| 1369 | REG_READ(map->fp0), |
| 1370 | REG_READ(map->fp1), |
| 1371 | REG_READ(map->dpll), |
| 1372 | REG_READ(map->htotal), |
| 1373 | REG_READ(map->hblank), |
| 1374 | REG_READ(map->hsync), |
| 1375 | REG_READ(map->vtotal), |
| 1376 | REG_READ(map->vblank), |
| 1377 | REG_READ(map->vsync), |
| 1378 | REG_READ(map->stride), |
| 1379 | REG_READ(map->size), |
| 1380 | REG_READ(map->pos), |
| 1381 | REG_READ(map->base) |
| 1382 | ); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1383 | |
| 1384 | DRM_DEBUG( |
| 1385 | "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", |
| 1386 | crtc_state->saveDSPCNTR, |
| 1387 | crtc_state->savePIPECONF, |
| 1388 | crtc_state->savePIPESRC, |
| 1389 | crtc_state->saveFP0, |
| 1390 | crtc_state->saveFP1, |
| 1391 | crtc_state->saveDPLL, |
| 1392 | crtc_state->saveHTOTAL, |
| 1393 | crtc_state->saveHBLANK, |
| 1394 | crtc_state->saveHSYNC, |
| 1395 | crtc_state->saveVTOTAL, |
| 1396 | crtc_state->saveVBLANK, |
| 1397 | crtc_state->saveVSYNC, |
| 1398 | crtc_state->saveDSPSTRIDE, |
| 1399 | crtc_state->saveDSPSIZE, |
| 1400 | crtc_state->saveDSPPOS, |
| 1401 | crtc_state->saveDSPBASE |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1402 | ); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1403 | |
| 1404 | |
| 1405 | if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1406 | REG_WRITE(map->dpll, |
| 1407 | crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); |
| 1408 | REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1409 | DRM_DEBUG("write dpll: %x\n", |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1410 | REG_READ(map->dpll)); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1411 | udelay(150); |
| 1412 | } |
| 1413 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1414 | REG_WRITE(map->fp0, crtc_state->saveFP0); |
| 1415 | REG_READ(map->fp0); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1416 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1417 | REG_WRITE(map->fp1, crtc_state->saveFP1); |
| 1418 | REG_READ(map->fp1); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1419 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1420 | REG_WRITE(map->dpll, crtc_state->saveDPLL); |
| 1421 | REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1422 | udelay(150); |
| 1423 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1424 | REG_WRITE(map->htotal, crtc_state->saveHTOTAL); |
| 1425 | REG_WRITE(map->hblank, crtc_state->saveHBLANK); |
| 1426 | REG_WRITE(map->hsync, crtc_state->saveHSYNC); |
| 1427 | REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); |
| 1428 | REG_WRITE(map->vblank, crtc_state->saveVBLANK); |
| 1429 | REG_WRITE(map->vsync, crtc_state->saveVSYNC); |
| 1430 | REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1431 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1432 | REG_WRITE(map->size, crtc_state->saveDSPSIZE); |
| 1433 | REG_WRITE(map->pos, crtc_state->saveDSPPOS); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1434 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1435 | REG_WRITE(map->src, crtc_state->savePIPESRC); |
| 1436 | REG_WRITE(map->base, crtc_state->saveDSPBASE); |
| 1437 | REG_WRITE(map->conf, crtc_state->savePIPECONF); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1438 | |
| 1439 | cdv_intel_wait_for_vblank(dev); |
| 1440 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1441 | REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); |
| 1442 | REG_WRITE(map->base, crtc_state->saveDSPBASE); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1443 | |
| 1444 | cdv_intel_wait_for_vblank(dev); |
| 1445 | |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1446 | paletteReg = map->palette; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1447 | for (i = 0; i < 256; ++i) |
| 1448 | REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); |
| 1449 | } |
| 1450 | |
| 1451 | static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc, |
| 1452 | struct drm_file *file_priv, |
| 1453 | uint32_t handle, |
| 1454 | uint32_t width, uint32_t height) |
| 1455 | { |
| 1456 | struct drm_device *dev = crtc->dev; |
| 1457 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1458 | int pipe = psb_intel_crtc->pipe; |
| 1459 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; |
| 1460 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; |
| 1461 | uint32_t temp; |
| 1462 | size_t addr = 0; |
| 1463 | struct gtt_range *gt; |
| 1464 | struct drm_gem_object *obj; |
| 1465 | int ret; |
| 1466 | |
| 1467 | /* if we want to turn of the cursor ignore width and height */ |
| 1468 | if (!handle) { |
| 1469 | /* turn off the cursor */ |
| 1470 | temp = CURSOR_MODE_DISABLE; |
| 1471 | |
| 1472 | if (gma_power_begin(dev, false)) { |
| 1473 | REG_WRITE(control, temp); |
| 1474 | REG_WRITE(base, 0); |
| 1475 | gma_power_end(dev); |
| 1476 | } |
| 1477 | |
| 1478 | /* unpin the old GEM object */ |
| 1479 | if (psb_intel_crtc->cursor_obj) { |
| 1480 | gt = container_of(psb_intel_crtc->cursor_obj, |
| 1481 | struct gtt_range, gem); |
| 1482 | psb_gtt_unpin(gt); |
| 1483 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); |
| 1484 | psb_intel_crtc->cursor_obj = NULL; |
| 1485 | } |
| 1486 | |
| 1487 | return 0; |
| 1488 | } |
| 1489 | |
| 1490 | /* Currently we only support 64x64 cursors */ |
| 1491 | if (width != 64 || height != 64) { |
| 1492 | dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); |
| 1493 | return -EINVAL; |
| 1494 | } |
| 1495 | |
| 1496 | obj = drm_gem_object_lookup(dev, file_priv, handle); |
| 1497 | if (!obj) |
| 1498 | return -ENOENT; |
| 1499 | |
| 1500 | if (obj->size < width * height * 4) { |
| 1501 | dev_dbg(dev->dev, "buffer is to small\n"); |
| 1502 | return -ENOMEM; |
| 1503 | } |
| 1504 | |
| 1505 | gt = container_of(obj, struct gtt_range, gem); |
| 1506 | |
| 1507 | /* Pin the memory into the GTT */ |
| 1508 | ret = psb_gtt_pin(gt); |
| 1509 | if (ret) { |
| 1510 | dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); |
| 1511 | return ret; |
| 1512 | } |
| 1513 | |
| 1514 | addr = gt->offset; /* Or resource.start ??? */ |
| 1515 | |
| 1516 | psb_intel_crtc->cursor_addr = addr; |
| 1517 | |
| 1518 | temp = 0; |
| 1519 | /* set the pipe for the cursor */ |
| 1520 | temp |= (pipe << 28); |
| 1521 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; |
| 1522 | |
| 1523 | if (gma_power_begin(dev, false)) { |
| 1524 | REG_WRITE(control, temp); |
| 1525 | REG_WRITE(base, addr); |
| 1526 | gma_power_end(dev); |
| 1527 | } |
| 1528 | |
| 1529 | /* unpin the old GEM object */ |
| 1530 | if (psb_intel_crtc->cursor_obj) { |
| 1531 | gt = container_of(psb_intel_crtc->cursor_obj, |
| 1532 | struct gtt_range, gem); |
| 1533 | psb_gtt_unpin(gt); |
| 1534 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); |
| 1535 | psb_intel_crtc->cursor_obj = obj; |
| 1536 | } |
| 1537 | return 0; |
| 1538 | } |
| 1539 | |
| 1540 | static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 1541 | { |
| 1542 | struct drm_device *dev = crtc->dev; |
| 1543 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1544 | int pipe = psb_intel_crtc->pipe; |
| 1545 | uint32_t temp = 0; |
| 1546 | uint32_t adder; |
| 1547 | |
| 1548 | |
| 1549 | if (x < 0) { |
| 1550 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); |
| 1551 | x = -x; |
| 1552 | } |
| 1553 | if (y < 0) { |
| 1554 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); |
| 1555 | y = -y; |
| 1556 | } |
| 1557 | |
| 1558 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); |
| 1559 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); |
| 1560 | |
| 1561 | adder = psb_intel_crtc->cursor_addr; |
| 1562 | |
| 1563 | if (gma_power_begin(dev, false)) { |
| 1564 | REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); |
| 1565 | REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); |
| 1566 | gma_power_end(dev); |
| 1567 | } |
| 1568 | return 0; |
| 1569 | } |
| 1570 | |
| 1571 | static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, |
| 1572 | u16 *green, u16 *blue, uint32_t start, uint32_t size) |
| 1573 | { |
| 1574 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1575 | int i; |
| 1576 | int end = (start + size > 256) ? 256 : start + size; |
| 1577 | |
| 1578 | for (i = start; i < end; i++) { |
| 1579 | psb_intel_crtc->lut_r[i] = red[i] >> 8; |
| 1580 | psb_intel_crtc->lut_g[i] = green[i] >> 8; |
| 1581 | psb_intel_crtc->lut_b[i] = blue[i] >> 8; |
| 1582 | } |
| 1583 | |
| 1584 | cdv_intel_crtc_load_lut(crtc); |
| 1585 | } |
| 1586 | |
| 1587 | static int cdv_crtc_set_config(struct drm_mode_set *set) |
| 1588 | { |
| 1589 | int ret = 0; |
| 1590 | struct drm_device *dev = set->crtc->dev; |
| 1591 | struct drm_psb_private *dev_priv = dev->dev_private; |
| 1592 | |
| 1593 | if (!dev_priv->rpm_enabled) |
| 1594 | return drm_crtc_helper_set_config(set); |
| 1595 | |
| 1596 | pm_runtime_forbid(&dev->pdev->dev); |
| 1597 | |
| 1598 | ret = drm_crtc_helper_set_config(set); |
| 1599 | |
| 1600 | pm_runtime_allow(&dev->pdev->dev); |
| 1601 | |
| 1602 | return ret; |
| 1603 | } |
| 1604 | |
| 1605 | /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ |
| 1606 | |
| 1607 | /* FIXME: why are we using this, should it be cdv_ in this tree ? */ |
| 1608 | |
| 1609 | static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock) |
| 1610 | { |
| 1611 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
| 1612 | clock->p = clock->p1 * clock->p2; |
| 1613 | clock->vco = refclk * clock->m / (clock->n + 2); |
| 1614 | clock->dot = clock->vco / clock->p; |
| 1615 | } |
| 1616 | |
| 1617 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 1618 | static int cdv_intel_crtc_clock_get(struct drm_device *dev, |
| 1619 | struct drm_crtc *crtc) |
| 1620 | { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1621 | struct drm_psb_private *dev_priv = dev->dev_private; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1622 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1623 | int pipe = psb_intel_crtc->pipe; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1624 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1625 | u32 dpll; |
| 1626 | u32 fp; |
| 1627 | struct cdv_intel_clock_t clock; |
| 1628 | bool is_lvds; |
Alan Cox | 6256304 | 2012-05-11 11:30:16 +0100 | [diff] [blame] | 1629 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1630 | |
| 1631 | if (gma_power_begin(dev, false)) { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1632 | dpll = REG_READ(map->dpll); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1633 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1634 | fp = REG_READ(map->fp0); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1635 | else |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1636 | fp = REG_READ(map->fp1); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1637 | is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); |
| 1638 | gma_power_end(dev); |
| 1639 | } else { |
Alan Cox | 6256304 | 2012-05-11 11:30:16 +0100 | [diff] [blame] | 1640 | dpll = p->dpll; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1641 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
Alan Cox | 6256304 | 2012-05-11 11:30:16 +0100 | [diff] [blame] | 1642 | fp = p->fp0; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1643 | else |
Alan Cox | 6256304 | 2012-05-11 11:30:16 +0100 | [diff] [blame] | 1644 | fp = p->fp1; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1645 | |
Alan Cox | 648a8e3 | 2012-03-08 16:00:31 +0000 | [diff] [blame] | 1646 | is_lvds = (pipe == 1) && |
Alan Cox | c6265ff | 2012-03-08 16:02:05 +0000 | [diff] [blame] | 1647 | (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1648 | } |
| 1649 | |
| 1650 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; |
| 1651 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; |
| 1652 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; |
| 1653 | |
| 1654 | if (is_lvds) { |
| 1655 | clock.p1 = |
| 1656 | ffs((dpll & |
| 1657 | DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> |
| 1658 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
| 1659 | if (clock.p1 == 0) { |
| 1660 | clock.p1 = 4; |
| 1661 | dev_err(dev->dev, "PLL %d\n", dpll); |
| 1662 | } |
| 1663 | clock.p2 = 14; |
| 1664 | |
| 1665 | if ((dpll & PLL_REF_INPUT_MASK) == |
| 1666 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { |
| 1667 | /* XXX: might not be 66MHz */ |
| 1668 | i8xx_clock(66000, &clock); |
| 1669 | } else |
| 1670 | i8xx_clock(48000, &clock); |
| 1671 | } else { |
| 1672 | if (dpll & PLL_P1_DIVIDE_BY_TWO) |
| 1673 | clock.p1 = 2; |
| 1674 | else { |
| 1675 | clock.p1 = |
| 1676 | ((dpll & |
| 1677 | DPLL_FPA01_P1_POST_DIV_MASK_I830) >> |
| 1678 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; |
| 1679 | } |
| 1680 | if (dpll & PLL_P2_DIVIDE_BY_4) |
| 1681 | clock.p2 = 4; |
| 1682 | else |
| 1683 | clock.p2 = 2; |
| 1684 | |
| 1685 | i8xx_clock(48000, &clock); |
| 1686 | } |
| 1687 | |
| 1688 | /* XXX: It would be nice to validate the clocks, but we can't reuse |
| 1689 | * i830PllIsValid() because it relies on the xf86_config connector |
| 1690 | * configuration being accurate, which it isn't necessarily. |
| 1691 | */ |
| 1692 | |
| 1693 | return clock.dot; |
| 1694 | } |
| 1695 | |
| 1696 | /** Returns the currently programmed mode of the given pipe. */ |
| 1697 | struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, |
| 1698 | struct drm_crtc *crtc) |
| 1699 | { |
| 1700 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1701 | int pipe = psb_intel_crtc->pipe; |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1702 | struct drm_psb_private *dev_priv = dev->dev_private; |
| 1703 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; |
| 1704 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1705 | struct drm_display_mode *mode; |
| 1706 | int htot; |
| 1707 | int hsync; |
| 1708 | int vtot; |
| 1709 | int vsync; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1710 | |
| 1711 | if (gma_power_begin(dev, false)) { |
Alan Cox | 213a843 | 2012-05-11 11:31:22 +0100 | [diff] [blame] | 1712 | htot = REG_READ(map->htotal); |
| 1713 | hsync = REG_READ(map->hsync); |
| 1714 | vtot = REG_READ(map->vtotal); |
| 1715 | vsync = REG_READ(map->vsync); |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1716 | gma_power_end(dev); |
| 1717 | } else { |
Alan Cox | 6256304 | 2012-05-11 11:30:16 +0100 | [diff] [blame] | 1718 | htot = p->htotal; |
| 1719 | hsync = p->hsync; |
| 1720 | vtot = p->vtotal; |
| 1721 | vsync = p->vsync; |
Alan Cox | 6a227d5 | 2011-11-03 18:22:37 +0000 | [diff] [blame] | 1722 | } |
| 1723 | |
| 1724 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); |
| 1725 | if (!mode) |
| 1726 | return NULL; |
| 1727 | |
| 1728 | mode->clock = cdv_intel_crtc_clock_get(dev, crtc); |
| 1729 | mode->hdisplay = (htot & 0xffff) + 1; |
| 1730 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; |
| 1731 | mode->hsync_start = (hsync & 0xffff) + 1; |
| 1732 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; |
| 1733 | mode->vdisplay = (vtot & 0xffff) + 1; |
| 1734 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; |
| 1735 | mode->vsync_start = (vsync & 0xffff) + 1; |
| 1736 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; |
| 1737 | |
| 1738 | drm_mode_set_name(mode); |
| 1739 | drm_mode_set_crtcinfo(mode, 0); |
| 1740 | |
| 1741 | return mode; |
| 1742 | } |
| 1743 | |
| 1744 | static void cdv_intel_crtc_destroy(struct drm_crtc *crtc) |
| 1745 | { |
| 1746 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
| 1747 | |
| 1748 | kfree(psb_intel_crtc->crtc_state); |
| 1749 | drm_crtc_cleanup(crtc); |
| 1750 | kfree(psb_intel_crtc); |
| 1751 | } |
| 1752 | |
| 1753 | const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { |
| 1754 | .dpms = cdv_intel_crtc_dpms, |
| 1755 | .mode_fixup = cdv_intel_crtc_mode_fixup, |
| 1756 | .mode_set = cdv_intel_crtc_mode_set, |
| 1757 | .mode_set_base = cdv_intel_pipe_set_base, |
| 1758 | .prepare = cdv_intel_crtc_prepare, |
| 1759 | .commit = cdv_intel_crtc_commit, |
| 1760 | }; |
| 1761 | |
| 1762 | const struct drm_crtc_funcs cdv_intel_crtc_funcs = { |
| 1763 | .save = cdv_intel_crtc_save, |
| 1764 | .restore = cdv_intel_crtc_restore, |
| 1765 | .cursor_set = cdv_intel_crtc_cursor_set, |
| 1766 | .cursor_move = cdv_intel_crtc_cursor_move, |
| 1767 | .gamma_set = cdv_intel_crtc_gamma_set, |
| 1768 | .set_config = cdv_crtc_set_config, |
| 1769 | .destroy = cdv_intel_crtc_destroy, |
| 1770 | }; |