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Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020034#include <drm/drmP.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/radeon_drm.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020036#include "radeon.h"
Dave Airlie99ee7fa2010-11-23 11:47:49 +100037#include "radeon_trace.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020038
Jerome Glisse771fe6b2009-06-05 14:42:42 +020039
40int radeon_ttm_init(struct radeon_device *rdev);
41void radeon_ttm_fini(struct radeon_device *rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +010042static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020043
44/*
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
47 */
48
Jerome Glisse721604a2012-01-05 22:11:05 -050049void radeon_bo_clear_va(struct radeon_bo *bo)
50{
51 struct radeon_bo_va *bo_va, *tmp;
52
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
Christian Könige971bd52012-09-11 16:10:04 +020055 radeon_vm_bo_rmv(bo->rdev, bo_va);
Jerome Glisse721604a2012-01-05 22:11:05 -050056 }
57}
58
Jerome Glisse4c788672009-11-20 14:29:23 +010059static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020060{
Jerome Glisse4c788672009-11-20 14:29:23 +010061 struct radeon_bo *bo;
62
63 bo = container_of(tbo, struct radeon_bo, tbo);
64 mutex_lock(&bo->rdev->gem.mutex);
65 list_del_init(&bo->list);
66 mutex_unlock(&bo->rdev->gem.mutex);
67 radeon_bo_clear_surface_reg(bo);
Jerome Glisse721604a2012-01-05 22:11:05 -050068 radeon_bo_clear_va(bo);
Daniel Vetter441921d2011-02-18 17:59:16 +010069 drm_gem_object_release(&bo->gem_base);
Jerome Glisse4c788672009-11-20 14:29:23 +010070 kfree(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020071}
72
Jerome Glissed03d8582009-12-14 21:02:09 +010073bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
74{
75 if (bo->destroy == &radeon_ttm_bo_destroy)
76 return true;
77 return false;
78}
79
Jerome Glisse312ea8d2009-12-07 15:52:58 +010080void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
81{
82 u32 c = 0;
83
84 rbo->placement.fpfn = 0;
Jerome Glisse93225b02010-12-03 16:38:19 -050085 rbo->placement.lpfn = 0;
Jerome Glisse312ea8d2009-12-07 15:52:58 +010086 rbo->placement.placement = rbo->placements;
Alex Deucher20707872013-01-17 13:10:50 -050087 rbo->placement.busy_placement = rbo->placements;
Jerome Glisse312ea8d2009-12-07 15:52:58 +010088 if (domain & RADEON_GEM_DOMAIN_VRAM)
89 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
90 TTM_PL_FLAG_VRAM;
Jerome Glisse0d0b3e72012-11-28 13:47:55 -050091 if (domain & RADEON_GEM_DOMAIN_GTT) {
92 if (rbo->rdev->flags & RADEON_IS_AGP) {
93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
94 } else {
95 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
96 }
97 }
98 if (domain & RADEON_GEM_DOMAIN_CPU) {
99 if (rbo->rdev->flags & RADEON_IS_AGP) {
Dave Airliedd54fee72012-12-14 21:04:46 +1000100 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
Jerome Glisse0d0b3e72012-11-28 13:47:55 -0500101 } else {
Dave Airliedd54fee72012-12-14 21:04:46 +1000102 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
Jerome Glisse0d0b3e72012-11-28 13:47:55 -0500103 }
104 }
Jerome Glisse9fb03e62009-12-11 15:13:22 +0100105 if (!c)
106 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100107 rbo->placement.num_placement = c;
108 rbo->placement.num_busy_placement = c;
109}
110
Daniel Vetter441921d2011-02-18 17:59:16 +0100111int radeon_bo_create(struct radeon_device *rdev,
Alex Deucher268b2512010-11-17 19:00:26 -0500112 unsigned long size, int byte_align, bool kernel, u32 domain,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400113 struct sg_table *sg, struct radeon_bo **bo_ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200114{
Jerome Glisse4c788672009-11-20 14:29:23 +0100115 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200116 enum ttm_bo_type type;
Jerome Glisse93225b02010-12-03 16:38:19 -0500117 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
Jerome Glisse57de4ba2011-11-11 15:42:57 -0500118 size_t acc_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200119 int r;
120
Daniel Vetter441921d2011-02-18 17:59:16 +0100121 size = ALIGN(size, PAGE_SIZE);
122
Ilija Hadzic949c4a32012-05-15 16:40:10 -0400123 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200124 if (kernel) {
125 type = ttm_bo_type_kernel;
Alex Deucher40f5cf92012-05-10 18:33:13 -0400126 } else if (sg) {
127 type = ttm_bo_type_sg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200128 } else {
129 type = ttm_bo_type_device;
130 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100131 *bo_ptr = NULL;
Michel Dänzer2b66b502010-11-09 11:50:05 +0100132
Jerome Glisse57de4ba2011-11-11 15:42:57 -0500133 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
134 sizeof(struct radeon_bo));
135
Jerome Glisse4c788672009-11-20 14:29:23 +0100136 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
137 if (bo == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200138 return -ENOMEM;
Daniel Vetter441921d2011-02-18 17:59:16 +0100139 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
140 if (unlikely(r)) {
141 kfree(bo);
142 return r;
143 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100144 bo->rdev = rdev;
Daniel Vetter7e4d15d2011-02-18 17:59:17 +0100145 bo->gem_base.driver_private = NULL;
Jerome Glisse4c788672009-11-20 14:29:23 +0100146 bo->surface_reg = -1;
147 INIT_LIST_HEAD(&bo->list);
Jerome Glisse721604a2012-01-05 22:11:05 -0500148 INIT_LIST_HEAD(&bo->va);
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100149 radeon_ttm_placement_from_domain(bo, domain);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100150 /* Kernel allocation are uninterruptible */
Christian Königdb7fce32012-05-11 14:57:18 +0200151 down_read(&rdev->pm.mclk_lock);
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100152 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
Marcin Slusarz0b91c4a2012-11-06 21:49:51 +0000153 &bo->placement, page_align, !kernel, NULL,
Alex Deucher40f5cf92012-05-10 18:33:13 -0400154 acc_size, sg, &radeon_ttm_bo_destroy);
Christian Königdb7fce32012-05-11 14:57:18 +0200155 up_read(&rdev->pm.mclk_lock);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200156 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200157 return r;
158 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100159 *bo_ptr = bo;
Daniel Vetter441921d2011-02-18 17:59:16 +0100160
Dave Airlie99ee7fa2010-11-23 11:47:49 +1000161 trace_radeon_bo_create(bo);
Daniel Vetter441921d2011-02-18 17:59:16 +0100162
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163 return 0;
164}
165
Jerome Glisse4c788672009-11-20 14:29:23 +0100166int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200167{
Jerome Glisse4c788672009-11-20 14:29:23 +0100168 bool is_iomem;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200169 int r;
170
Jerome Glisse4c788672009-11-20 14:29:23 +0100171 if (bo->kptr) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200172 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100173 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200174 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200175 return 0;
176 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100177 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200178 if (r) {
179 return r;
180 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100181 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200182 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100183 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200184 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100185 radeon_bo_check_tiling(bo, 0, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200186 return 0;
187}
188
Jerome Glisse4c788672009-11-20 14:29:23 +0100189void radeon_bo_kunmap(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190{
Jerome Glisse4c788672009-11-20 14:29:23 +0100191 if (bo->kptr == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200192 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100193 bo->kptr = NULL;
194 radeon_bo_check_tiling(bo, 0, 0);
195 ttm_bo_kunmap(&bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200196}
197
Jerome Glisse4c788672009-11-20 14:29:23 +0100198void radeon_bo_unref(struct radeon_bo **bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200199{
Jerome Glisse4c788672009-11-20 14:29:23 +0100200 struct ttm_buffer_object *tbo;
Dave Airlief4b7fb92010-04-29 18:37:59 +1000201 struct radeon_device *rdev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200202
Jerome Glisse4c788672009-11-20 14:29:23 +0100203 if ((*bo) == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200204 return;
Dave Airlief4b7fb92010-04-29 18:37:59 +1000205 rdev = (*bo)->rdev;
Jerome Glisse4c788672009-11-20 14:29:23 +0100206 tbo = &((*bo)->tbo);
Christian Königdb7fce32012-05-11 14:57:18 +0200207 down_read(&rdev->pm.mclk_lock);
Jerome Glisse4c788672009-11-20 14:29:23 +0100208 ttm_bo_unref(&tbo);
Christian Königdb7fce32012-05-11 14:57:18 +0200209 up_read(&rdev->pm.mclk_lock);
Jerome Glisse4c788672009-11-20 14:29:23 +0100210 if (tbo == NULL)
211 *bo = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200212}
213
Michel Dänzerc4353012012-03-14 17:12:41 +0100214int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
215 u64 *gpu_addr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200216{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100217 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200218
Jerome Glisse4c788672009-11-20 14:29:23 +0100219 if (bo->pin_count) {
220 bo->pin_count++;
221 if (gpu_addr)
222 *gpu_addr = radeon_bo_gpu_offset(bo);
Michel Dänzerd9366222012-03-28 08:52:32 +0200223
224 if (max_offset != 0) {
225 u64 domain_start;
226
227 if (domain == RADEON_GEM_DOMAIN_VRAM)
228 domain_start = bo->rdev->mc.vram_start;
229 else
230 domain_start = bo->rdev->mc.gtt_start;
Michel Dänzere199fd42012-03-29 16:47:43 +0200231 WARN_ON_ONCE(max_offset <
232 (radeon_bo_gpu_offset(bo) - domain_start));
Michel Dänzerd9366222012-03-28 08:52:32 +0200233 }
234
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200235 return 0;
236 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100237 radeon_ttm_placement_from_domain(bo, domain);
Michel Dänzer3ca82da2010-03-26 19:18:55 +0000238 if (domain == RADEON_GEM_DOMAIN_VRAM) {
239 /* force to pin into visible video ram */
240 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
241 }
Michel Dänzerc4353012012-03-14 17:12:41 +0100242 if (max_offset) {
243 u64 lpfn = max_offset >> PAGE_SHIFT;
244
245 if (!bo->placement.lpfn)
246 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
247
248 if (lpfn < bo->placement.lpfn)
249 bo->placement.lpfn = lpfn;
250 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100251 for (i = 0; i < bo->placement.num_placement; i++)
252 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000253 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
Jerome Glisse4c788672009-11-20 14:29:23 +0100254 if (likely(r == 0)) {
255 bo->pin_count = 1;
256 if (gpu_addr != NULL)
257 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200258 }
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100259 if (unlikely(r != 0))
Jerome Glisse4c788672009-11-20 14:29:23 +0100260 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200261 return r;
262}
263
Michel Dänzerc4353012012-03-14 17:12:41 +0100264int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
265{
266 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
267}
268
Jerome Glisse4c788672009-11-20 14:29:23 +0100269int radeon_bo_unpin(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200270{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100271 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200272
Jerome Glisse4c788672009-11-20 14:29:23 +0100273 if (!bo->pin_count) {
274 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
275 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200276 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100277 bo->pin_count--;
278 if (bo->pin_count)
279 return 0;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100280 for (i = 0; i < bo->placement.num_placement; i++)
281 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000282 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100283 if (unlikely(r != 0))
Jerome Glisse4c788672009-11-20 14:29:23 +0100284 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100285 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200286}
287
Jerome Glisse4c788672009-11-20 14:29:23 +0100288int radeon_bo_evict_vram(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200289{
Dave Airlied796d842010-01-25 13:08:08 +1000290 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
291 if (0 && (rdev->flags & RADEON_IS_IGP)) {
Alex Deucher06b64762010-01-05 11:27:29 -0500292 if (rdev->mc.igp_sideport_enabled == false)
293 /* Useless to evict on IGP chips */
294 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200295 }
296 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
297}
298
Jerome Glisse4c788672009-11-20 14:29:23 +0100299void radeon_bo_force_delete(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200300{
Jerome Glisse4c788672009-11-20 14:29:23 +0100301 struct radeon_bo *bo, *n;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200302
303 if (list_empty(&rdev->gem.objects)) {
304 return;
305 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100306 dev_err(rdev->dev, "Userspace still has active objects !\n");
307 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200308 mutex_lock(&rdev->ddev->struct_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100309 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
Daniel Vetter31c36032011-02-18 17:59:18 +0100310 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
311 *((unsigned long *)&bo->gem_base.refcount));
Jerome Glisse4c788672009-11-20 14:29:23 +0100312 mutex_lock(&bo->rdev->gem.mutex);
313 list_del_init(&bo->list);
314 mutex_unlock(&bo->rdev->gem.mutex);
Dave Airlie91132d62011-03-01 13:40:06 +1000315 /* this should unref the ttm bo */
Daniel Vetter31c36032011-02-18 17:59:18 +0100316 drm_gem_object_unreference(&bo->gem_base);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200317 mutex_unlock(&rdev->ddev->struct_mutex);
318 }
319}
320
Jerome Glisse4c788672009-11-20 14:29:23 +0100321int radeon_bo_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200322{
Jerome Glissea4d68272009-09-11 13:00:43 +0200323 /* Add an MTRR for the VRAM */
324 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
325 MTRR_TYPE_WRCOMB, 1);
326 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
327 rdev->mc.mc_vram_size >> 20,
328 (unsigned long long)rdev->mc.aper_size >> 20);
329 DRM_INFO("RAM width %dbits %cDR\n",
330 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200331 return radeon_ttm_init(rdev);
332}
333
Jerome Glisse4c788672009-11-20 14:29:23 +0100334void radeon_bo_fini(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200335{
336 radeon_ttm_fini(rdev);
337}
338
Jerome Glisse4c788672009-11-20 14:29:23 +0100339void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
340 struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200341{
342 if (lobj->wdomain) {
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000343 list_add(&lobj->tv.head, head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200344 } else {
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000345 list_add_tail(&lobj->tv.head, head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200346 }
347}
348
Jerome Glisse6cb8e1f2010-02-15 21:36:33 +0100349int radeon_bo_list_validate(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200350{
Jerome Glisse4c788672009-11-20 14:29:23 +0100351 struct radeon_bo_list *lobj;
352 struct radeon_bo *bo;
Alex Deucher20707872013-01-17 13:10:50 -0500353 u32 domain;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200354 int r;
355
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000356 r = ttm_eu_reserve_buffers(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200357 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200358 return r;
359 }
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000360 list_for_each_entry(lobj, head, tv.head) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100361 bo = lobj->bo;
362 if (!bo->pin_count) {
Alex Deucher20707872013-01-17 13:10:50 -0500363 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
364
365 retry:
366 radeon_ttm_placement_from_domain(bo, domain);
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100367 r = ttm_bo_validate(&bo->tbo, &bo->placement,
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000368 true, false);
Michel Dänzere3765732010-07-08 12:43:28 +1000369 if (unlikely(r)) {
Alex Deucher20707872013-01-17 13:10:50 -0500370 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
371 domain |= RADEON_GEM_DOMAIN_GTT;
372 goto retry;
373 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200374 return r;
Michel Dänzere3765732010-07-08 12:43:28 +1000375 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200376 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100377 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
378 lobj->tiling_flags = bo->tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200379 }
380 return 0;
381}
382
Jerome Glisse4c788672009-11-20 14:29:23 +0100383int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200384 struct vm_area_struct *vma)
385{
Jerome Glisse4c788672009-11-20 14:29:23 +0100386 return ttm_fbdev_mmap(vma, &bo->tbo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200387}
388
Dave Airlie550e2d92009-12-09 14:15:38 +1000389int radeon_bo_get_surface_reg(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200390{
Jerome Glisse4c788672009-11-20 14:29:23 +0100391 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000392 struct radeon_surface_reg *reg;
Jerome Glisse4c788672009-11-20 14:29:23 +0100393 struct radeon_bo *old_object;
Dave Airliee024e112009-06-24 09:48:08 +1000394 int steal;
395 int i;
396
Maarten Lankhorst0a46fb52012-10-12 14:59:17 +0000397 BUG_ON(!radeon_bo_is_reserved(bo));
Jerome Glisse4c788672009-11-20 14:29:23 +0100398
399 if (!bo->tiling_flags)
Dave Airliee024e112009-06-24 09:48:08 +1000400 return 0;
401
Jerome Glisse4c788672009-11-20 14:29:23 +0100402 if (bo->surface_reg >= 0) {
403 reg = &rdev->surface_regs[bo->surface_reg];
404 i = bo->surface_reg;
Dave Airliee024e112009-06-24 09:48:08 +1000405 goto out;
406 }
407
408 steal = -1;
409 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
410
411 reg = &rdev->surface_regs[i];
Jerome Glisse4c788672009-11-20 14:29:23 +0100412 if (!reg->bo)
Dave Airliee024e112009-06-24 09:48:08 +1000413 break;
414
Jerome Glisse4c788672009-11-20 14:29:23 +0100415 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000416 if (old_object->pin_count == 0)
417 steal = i;
418 }
419
420 /* if we are all out */
421 if (i == RADEON_GEM_MAX_SURFACES) {
422 if (steal == -1)
423 return -ENOMEM;
424 /* find someone with a surface reg and nuke their BO */
425 reg = &rdev->surface_regs[steal];
Jerome Glisse4c788672009-11-20 14:29:23 +0100426 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000427 /* blow away the mapping */
428 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
Jerome Glisse4c788672009-11-20 14:29:23 +0100429 ttm_bo_unmap_virtual(&old_object->tbo);
Dave Airliee024e112009-06-24 09:48:08 +1000430 old_object->surface_reg = -1;
431 i = steal;
432 }
433
Jerome Glisse4c788672009-11-20 14:29:23 +0100434 bo->surface_reg = i;
435 reg->bo = bo;
Dave Airliee024e112009-06-24 09:48:08 +1000436
437out:
Jerome Glisse4c788672009-11-20 14:29:23 +0100438 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
Ben Skeggsd961db72010-08-05 10:48:18 +1000439 bo->tbo.mem.start << PAGE_SHIFT,
Jerome Glisse4c788672009-11-20 14:29:23 +0100440 bo->tbo.num_pages << PAGE_SHIFT);
Dave Airliee024e112009-06-24 09:48:08 +1000441 return 0;
442}
443
Jerome Glisse4c788672009-11-20 14:29:23 +0100444static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000445{
Jerome Glisse4c788672009-11-20 14:29:23 +0100446 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000447 struct radeon_surface_reg *reg;
448
Jerome Glisse4c788672009-11-20 14:29:23 +0100449 if (bo->surface_reg == -1)
Dave Airliee024e112009-06-24 09:48:08 +1000450 return;
451
Jerome Glisse4c788672009-11-20 14:29:23 +0100452 reg = &rdev->surface_regs[bo->surface_reg];
453 radeon_clear_surface_reg(rdev, bo->surface_reg);
Dave Airliee024e112009-06-24 09:48:08 +1000454
Jerome Glisse4c788672009-11-20 14:29:23 +0100455 reg->bo = NULL;
456 bo->surface_reg = -1;
Dave Airliee024e112009-06-24 09:48:08 +1000457}
458
Jerome Glisse4c788672009-11-20 14:29:23 +0100459int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
460 uint32_t tiling_flags, uint32_t pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000461{
Jerome Glisse285484e2011-12-16 17:03:42 -0500462 struct radeon_device *rdev = bo->rdev;
Jerome Glisse4c788672009-11-20 14:29:23 +0100463 int r;
464
Jerome Glisse285484e2011-12-16 17:03:42 -0500465 if (rdev->family >= CHIP_CEDAR) {
466 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
467
468 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
469 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
470 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
471 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
472 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
473 switch (bankw) {
474 case 0:
475 case 1:
476 case 2:
477 case 4:
478 case 8:
479 break;
480 default:
481 return -EINVAL;
482 }
483 switch (bankh) {
484 case 0:
485 case 1:
486 case 2:
487 case 4:
488 case 8:
489 break;
490 default:
491 return -EINVAL;
492 }
493 switch (mtaspect) {
494 case 0:
495 case 1:
496 case 2:
497 case 4:
498 case 8:
499 break;
500 default:
501 return -EINVAL;
502 }
503 if (tilesplit > 6) {
504 return -EINVAL;
505 }
506 if (stilesplit > 6) {
507 return -EINVAL;
508 }
509 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100510 r = radeon_bo_reserve(bo, false);
511 if (unlikely(r != 0))
512 return r;
513 bo->tiling_flags = tiling_flags;
514 bo->pitch = pitch;
515 radeon_bo_unreserve(bo);
516 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000517}
518
Jerome Glisse4c788672009-11-20 14:29:23 +0100519void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
520 uint32_t *tiling_flags,
521 uint32_t *pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000522{
Maarten Lankhorst0a46fb52012-10-12 14:59:17 +0000523 BUG_ON(!radeon_bo_is_reserved(bo));
Dave Airliee024e112009-06-24 09:48:08 +1000524 if (tiling_flags)
Jerome Glisse4c788672009-11-20 14:29:23 +0100525 *tiling_flags = bo->tiling_flags;
Dave Airliee024e112009-06-24 09:48:08 +1000526 if (pitch)
Jerome Glisse4c788672009-11-20 14:29:23 +0100527 *pitch = bo->pitch;
Dave Airliee024e112009-06-24 09:48:08 +1000528}
529
Jerome Glisse4c788672009-11-20 14:29:23 +0100530int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
531 bool force_drop)
Dave Airliee024e112009-06-24 09:48:08 +1000532{
Maarten Lankhorst6ed9ccb2012-11-28 11:25:40 +0000533 BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);
Jerome Glisse4c788672009-11-20 14:29:23 +0100534
535 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
Dave Airliee024e112009-06-24 09:48:08 +1000536 return 0;
537
538 if (force_drop) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100539 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000540 return 0;
541 }
542
Jerome Glisse4c788672009-11-20 14:29:23 +0100543 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
Dave Airliee024e112009-06-24 09:48:08 +1000544 if (!has_moved)
545 return 0;
546
Jerome Glisse4c788672009-11-20 14:29:23 +0100547 if (bo->surface_reg >= 0)
548 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000549 return 0;
550 }
551
Jerome Glisse4c788672009-11-20 14:29:23 +0100552 if ((bo->surface_reg >= 0) && !has_moved)
Dave Airliee024e112009-06-24 09:48:08 +1000553 return 0;
554
Jerome Glisse4c788672009-11-20 14:29:23 +0100555 return radeon_bo_get_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000556}
557
558void radeon_bo_move_notify(struct ttm_buffer_object *bo,
Jerome Glissed03d8582009-12-14 21:02:09 +0100559 struct ttm_mem_reg *mem)
Dave Airliee024e112009-06-24 09:48:08 +1000560{
Jerome Glissed03d8582009-12-14 21:02:09 +0100561 struct radeon_bo *rbo;
562 if (!radeon_ttm_bo_is_radeon_bo(bo))
563 return;
564 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100565 radeon_bo_check_tiling(rbo, 0, 1);
Jerome Glisse721604a2012-01-05 22:11:05 -0500566 radeon_vm_bo_invalidate(rbo->rdev, rbo);
Dave Airliee024e112009-06-24 09:48:08 +1000567}
568
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200569int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000570{
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200571 struct radeon_device *rdev;
Jerome Glissed03d8582009-12-14 21:02:09 +0100572 struct radeon_bo *rbo;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200573 unsigned long offset, size;
574 int r;
575
Jerome Glissed03d8582009-12-14 21:02:09 +0100576 if (!radeon_ttm_bo_is_radeon_bo(bo))
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200577 return 0;
Jerome Glissed03d8582009-12-14 21:02:09 +0100578 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100579 radeon_bo_check_tiling(rbo, 0, 0);
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200580 rdev = rbo->rdev;
581 if (bo->mem.mem_type == TTM_PL_VRAM) {
582 size = bo->mem.num_pages << PAGE_SHIFT;
Ben Skeggsd961db72010-08-05 10:48:18 +1000583 offset = bo->mem.start << PAGE_SHIFT;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200584 if ((offset + size) > rdev->mc.visible_vram_size) {
585 /* hurrah the memory is not visible ! */
586 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
587 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000588 r = ttm_bo_validate(bo, &rbo->placement, false, false);
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200589 if (unlikely(r != 0))
590 return r;
Ben Skeggsd961db72010-08-05 10:48:18 +1000591 offset = bo->mem.start << PAGE_SHIFT;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200592 /* this should not happen */
593 if ((offset + size) > rdev->mc.visible_vram_size)
594 return -EINVAL;
595 }
596 }
597 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000598}
Andi Kleence580fa2011-10-13 16:08:47 -0700599
Dave Airlie83f30d02011-10-27 18:15:10 +0200600int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
Andi Kleence580fa2011-10-13 16:08:47 -0700601{
602 int r;
603
604 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
605 if (unlikely(r != 0))
606 return r;
607 spin_lock(&bo->tbo.bdev->fence_lock);
608 if (mem_type)
609 *mem_type = bo->tbo.mem.mem_type;
610 if (bo->tbo.sync_obj)
Dave Airlie1717c0e2011-10-27 18:28:37 +0200611 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
Andi Kleence580fa2011-10-13 16:08:47 -0700612 spin_unlock(&bo->tbo.bdev->fence_lock);
613 ttm_bo_unreserve(&bo->tbo);
614 return r;
615}
616
617
618/**
619 * radeon_bo_reserve - reserve bo
620 * @bo: bo structure
Christian Königd63dfed2012-09-11 16:10:01 +0200621 * @no_intr: don't return -ERESTARTSYS on pending signal
Andi Kleence580fa2011-10-13 16:08:47 -0700622 *
623 * Returns:
Andi Kleence580fa2011-10-13 16:08:47 -0700624 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
625 * a signal. Release all buffer reservations and return to user-space.
626 */
Christian Königd63dfed2012-09-11 16:10:01 +0200627int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
Andi Kleence580fa2011-10-13 16:08:47 -0700628{
629 int r;
630
Christian Königd63dfed2012-09-11 16:10:01 +0200631 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
Andi Kleence580fa2011-10-13 16:08:47 -0700632 if (unlikely(r != 0)) {
633 if (r != -ERESTARTSYS)
634 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
635 return r;
636 }
637 return 0;
638}