blob: c76151b56568ee241e345fe779d3454df0179add [file] [log] [blame]
Thomas Bogendoerferc066a322006-12-28 18:22:32 +01001#include <linux/types.h>
2#include <linux/interrupt.h>
David Howellsca4d3e672010-10-07 14:08:54 +01003#include <linux/irq.h>
Ralf Baechle631330f2009-06-19 14:05:26 +01004#include <linux/smp.h>
Thomas Bogendoerferc066a322006-12-28 18:22:32 +01005#include <linux/time.h>
Thomas Bogendoerferc9294022007-11-01 11:36:42 +01006#include <linux/clockchips.h>
Thomas Bogendoerferc066a322006-12-28 18:22:32 +01007
Ralf Baechled865bea2007-10-11 23:46:10 +01008#include <asm/i8253.h>
Thomas Bogendoerferc066a322006-12-28 18:22:32 +01009#include <asm/sni.h>
10#include <asm/time.h>
Ralf Baechle4b550482007-10-11 23:46:08 +010011#include <asm-generic/rtc.h>
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010012
13#define SNI_CLOCK_TICK_RATE 3686400
14#define SNI_COUNTER2_DIV 64
15#define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
16
Ralf Baechle84953b32007-10-26 14:36:10 +010017static void a20r_set_mode(enum clock_event_mode mode,
18 struct clock_event_device *evt)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010019{
Ralf Baechle84953b32007-10-26 14:36:10 +010020 switch (mode) {
21 case CLOCK_EVT_MODE_PERIODIC:
22 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34;
23 wmb();
24 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV;
25 wmb();
26 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8;
27 wmb();
28
29 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4;
30 wmb();
31 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV;
32 wmb();
33 *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8;
34 wmb();
35
36 break;
37 case CLOCK_EVT_MODE_ONESHOT:
38 case CLOCK_EVT_MODE_UNUSED:
39 case CLOCK_EVT_MODE_SHUTDOWN:
40 break;
41 case CLOCK_EVT_MODE_RESUME:
42 break;
43 }
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010044}
45
Ralf Baechle84953b32007-10-26 14:36:10 +010046static struct clock_event_device a20r_clockevent_device = {
47 .name = "a20r-timer",
48 .features = CLOCK_EVT_FEAT_PERIODIC,
49
50 /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
51
52 .rating = 300,
53 .irq = SNI_A20R_IRQ_TIMER,
54 .set_mode = a20r_set_mode,
55};
56
57static irqreturn_t a20r_interrupt(int irq, void *dev_id)
58{
59 struct clock_event_device *cd = dev_id;
60
61 *(volatile u8 *)A20R_PT_TIM0_ACK = 0;
62 wmb();
63
64 cd->event_handler(cd);
65
66 return IRQ_HANDLED;
67}
68
69static struct irqaction a20r_irqaction = {
70 .handler = a20r_interrupt,
Wu Zhangjinf45e5182009-10-08 21:17:54 +080071 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
Ralf Baechle84953b32007-10-26 14:36:10 +010072 .name = "a20r-timer",
73};
74
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010075/*
76 * a20r platform uses 2 counters to divide the input frequency.
77 * Counter 2 output is connected to Counter 0 & 1 input.
78 */
Ralf Baechle84953b32007-10-26 14:36:10 +010079static void __init sni_a20r_timer_setup(void)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010080{
Ralf Baechle84953b32007-10-26 14:36:10 +010081 struct clock_event_device *cd = &a20r_clockevent_device;
82 struct irqaction *action = &a20r_irqaction;
83 unsigned int cpu = smp_processor_id();
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010084
Rusty Russell320ab2b2008-12-13 21:20:26 +103085 cd->cpumask = cpumask_of(cpu);
Thomas Bogendoerferc9294022007-11-01 11:36:42 +010086 clockevents_register_device(cd);
Ralf Baechle84953b32007-10-26 14:36:10 +010087 action->dev_id = cd;
88 setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010089}
90
91#define SNI_8254_TICK_RATE 1193182UL
92
93#define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255)
94
95static __init unsigned long dosample(void)
96{
97 u32 ct0, ct1;
98 volatile u8 msb, lsb;
99
100 /* Start the counter. */
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100101 outb_p(0x34, 0x43);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100102 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100103 outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100104
105 /* Get initial counter invariant */
106 ct0 = read_c0_count();
107
108 /* Latch and spin until top byte of counter0 is zero */
109 do {
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100110 outb(0x00, 0x43);
111 lsb = inb(0x40);
112 msb = inb(0x40);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100113 ct1 = read_c0_count();
114 } while (msb);
115
116 /* Stop the counter. */
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100117 outb(0x38, 0x43);
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100118 /*
119 * Return the difference, this is how far the r4k counter increments
120 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
121 * clock (= 1000000 / HZ / 2).
122 */
123 /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
124 return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
125}
126
127/*
128 * Here we need to calibrate the cycle counter to at least be close.
129 */
Ralf Baechle4b550482007-10-11 23:46:08 +0100130void __init plat_time_init(void)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100131{
132 unsigned long r4k_ticks[3];
133 unsigned long r4k_tick;
134
135 /*
136 * Figure out the r4k offset, the algorithm is very simple and works in
137 * _all_ cases as long as the 8254 counter register itself works ok (as
138 * an interrupt driving timer it does not because of bug, this is why
139 * we are using the onchip r4k counter/compare register to serve this
140 * purpose, but for r4k_offset calculation it will work ok for us).
141 * There are other very complicated ways of performing this calculation
142 * but this one works just fine so I am not going to futz around. ;-)
143 */
144 printk(KERN_INFO "Calibrating system timer... ");
145 dosample(); /* Prime cache. */
146 dosample(); /* Prime cache. */
147 /* Zero is NOT an option. */
148 do {
149 r4k_ticks[0] = dosample();
150 } while (!r4k_ticks[0]);
151 do {
152 r4k_ticks[1] = dosample();
153 } while (!r4k_ticks[1]);
154
155 if (r4k_ticks[0] != r4k_ticks[1]) {
156 printk("warning: timer counts differ, retrying... ");
157 r4k_ticks[2] = dosample();
158 if (r4k_ticks[2] == r4k_ticks[0]
159 || r4k_ticks[2] == r4k_ticks[1])
160 r4k_tick = r4k_ticks[2];
161 else {
162 printk("disagreement, using average... ");
163 r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
164 + r4k_ticks[2]) / 3;
165 }
166 } else
167 r4k_tick = r4k_ticks[0];
168
169 printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
170 (int) (r4k_tick / (500000 / HZ)),
171 (int) (r4k_tick % (500000 / HZ)));
172
173 mips_hpt_frequency = r4k_tick * HZ;
Ralf Baechled865bea2007-10-11 23:46:10 +0100174
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100175 switch (sni_brd_type) {
176 case SNI_BRD_10:
177 case SNI_BRD_10NEW:
178 case SNI_BRD_TOWER_OASIC:
179 case SNI_BRD_MINITOWER:
Ralf Baechle84953b32007-10-26 14:36:10 +0100180 sni_a20r_timer_setup();
181 break;
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100182 }
Thomas Bogendoerfer231a35d2008-01-04 23:31:07 +0100183 setup_pit_timer();
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100184}
Ralf Baechle4b550482007-10-11 23:46:08 +0100185
Martin Schwidefskyd4f587c2009-08-14 15:47:31 +0200186void read_persistent_clock(struct timespec *ts)
Ralf Baechle4b550482007-10-11 23:46:08 +0100187{
Martin Schwidefskyd4f587c2009-08-14 15:47:31 +0200188 ts->tv_sec = -1;
189 ts->tv_nsec = 0;
Ralf Baechle4b550482007-10-11 23:46:08 +0100190}