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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * NCR 5380 defines
3 *
4 * Copyright 1993, Drew Eckhardt
5 * Visionary Computing
6 * (Unix consulting and custom programming)
7 * drew@colorado.edu
8 * +1 (303) 666-5836
9 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 * For more information, please consult
11 *
12 * NCR 5380 Family
13 * SCSI Protocol Controller
14 * Databook
15 * NCR Microelectronics
16 * 1635 Aeroplaza Drive
17 * Colorado Springs, CO 80916
18 * 1+ (719) 578-3400
19 * 1+ (800) 334-5454
20 */
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#ifndef NCR5380_H
23#define NCR5380_H
24
25#include <linux/interrupt.h>
Boaz Harrosh28424d32007-09-10 22:37:45 +030026#include <scsi/scsi_eh.h>
Boaz Harrosh28424d32007-09-10 22:37:45 +030027
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#define NDEBUG_ARBITRATION 0x1
29#define NDEBUG_AUTOSENSE 0x2
30#define NDEBUG_DMA 0x4
31#define NDEBUG_HANDSHAKE 0x8
32#define NDEBUG_INFORMATION 0x10
33#define NDEBUG_INIT 0x20
34#define NDEBUG_INTR 0x40
35#define NDEBUG_LINKED 0x80
36#define NDEBUG_MAIN 0x100
37#define NDEBUG_NO_DATAOUT 0x200
38#define NDEBUG_NO_WRITE 0x400
39#define NDEBUG_PIO 0x800
40#define NDEBUG_PSEUDO_DMA 0x1000
41#define NDEBUG_QUEUES 0x2000
42#define NDEBUG_RESELECTION 0x4000
43#define NDEBUG_SELECTION 0x8000
44#define NDEBUG_USLEEP 0x10000
45#define NDEBUG_LAST_BYTE_SENT 0x20000
46#define NDEBUG_RESTART_SELECT 0x40000
47#define NDEBUG_EXTENDED 0x80000
48#define NDEBUG_C400_PREAD 0x100000
49#define NDEBUG_C400_PWRITE 0x200000
50#define NDEBUG_LISTS 0x400000
Finn Thain9829e522014-03-18 11:42:21 +110051#define NDEBUG_ABORT 0x800000
52#define NDEBUG_TAGS 0x1000000
53#define NDEBUG_MERGING 0x2000000
Linus Torvalds1da177e2005-04-16 15:20:36 -070054
55#define NDEBUG_ANY 0xFFFFFFFFUL
56
57/*
58 * The contents of the OUTPUT DATA register are asserted on the bus when
59 * either arbitration is occurring or the phase-indicating signals (
60 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
61 * bit in the INITIATOR COMMAND register is set.
62 */
63
64#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
65#define CURRENT_SCSI_DATA_REG 0 /* ro same */
66
67#define INITIATOR_COMMAND_REG 1 /* rw */
68#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
69#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
70#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
71#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
72#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
73#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
74#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
75#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
76#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
77#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
78
79#ifdef DIFFERENTIAL
80#define ICR_BASE ICR_DIFF_ENABLE
81#else
82#define ICR_BASE 0
83#endif
84
85#define MODE_REG 2
86/*
87 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
88 * transfer, causing the chip to hog the bus. You probably don't want
89 * this.
90 */
91#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
92#define MR_TARGET 0x40 /* rw target mode */
93#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
94#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
95#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
96#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
97#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
98#define MR_ARBITRATE 0x01 /* rw start arbitration */
99
100#ifdef PARITY
101#define MR_BASE MR_ENABLE_PAR_CHECK
102#else
103#define MR_BASE 0
104#endif
105
106#define TARGET_COMMAND_REG 3
107#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
108#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
109#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
110#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
111#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
112
113#define STATUS_REG 4 /* ro */
114/*
115 * Note : a set bit indicates an active signal, driven by us or another
116 * device.
117 */
118#define SR_RST 0x80
119#define SR_BSY 0x40
120#define SR_REQ 0x20
121#define SR_MSG 0x10
122#define SR_CD 0x08
123#define SR_IO 0x04
124#define SR_SEL 0x02
125#define SR_DBP 0x01
126
127/*
128 * Setting a bit in this register will cause an interrupt to be generated when
129 * BSY is false and SEL true and this bit is asserted on the bus.
130 */
131#define SELECT_ENABLE_REG 4 /* wo */
132
133#define BUS_AND_STATUS_REG 5 /* ro */
134#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
135#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
136#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
137#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
138#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
139#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
140#define BASR_ATN 0x02 /* ro BUS status */
141#define BASR_ACK 0x01 /* ro BUS status */
142
143/* Write any value to this register to start a DMA send */
144#define START_DMA_SEND_REG 5 /* wo */
145
146/*
147 * Used in DMA transfer mode, data is latched from the SCSI bus on
148 * the falling edge of REQ (ini) or ACK (tgt)
149 */
150#define INPUT_DATA_REG 6 /* ro */
151
152/* Write any value to this register to start a DMA receive */
153#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
154
155/* Read this register to clear interrupt conditions */
156#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
157
158/* Write any value to this register to start an ini mode DMA receive */
159#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
160
161#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
162
163#define CSR_RESET 0x80 /* wo Resets 53c400 */
164#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
165#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
166#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
167#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
168#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
169#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
170#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
171#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
172
173#if 0
174#define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
175#else
176#define CSR_BASE CSR_53C80_INTR
177#endif
178
179/* Number of 128-byte blocks to be transferred */
180#define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
181
182/* Resume transfer after disconnect */
183#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
184
185/* Access to host buffer stack */
186#define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
187
188
189/* Note : PHASE_* macros are based on the values of the STATUS register */
190#define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
191
192#define PHASE_DATAOUT 0
193#define PHASE_DATAIN SR_IO
194#define PHASE_CMDOUT SR_CD
195#define PHASE_STATIN (SR_CD | SR_IO)
196#define PHASE_MSGOUT (SR_MSG | SR_CD)
197#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
198#define PHASE_UNKNOWN 0xff
199
200/*
201 * Convert status register phase to something we can use to set phase in
202 * the target register so we can get phase mismatch interrupts on DMA
203 * transfers.
204 */
205
206#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
207
208/*
209 * The internal should_disconnect() function returns these based on the
210 * expected length of a disconnect if a device supports disconnect/
211 * reconnect.
212 */
213
214#define DISCONNECT_NONE 0
215#define DISCONNECT_TIME_TO_DATA 1
216#define DISCONNECT_LONG 2
217
218/*
Finn Thain76f13b92014-11-12 16:11:53 +1100219 * "Special" value for the (unsigned char) command tag, to indicate
220 * I_T_L nexus instead of I_T_L_Q.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 */
222
Finn Thain76f13b92014-11-12 16:11:53 +1100223#define TAG_NONE 0xff
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224
225/*
226 * These are "special" values for the irq and dma_channel fields of the
227 * Scsi_Host structure
228 */
229
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230#define DMA_NONE 255
231#define IRQ_AUTO 254
232#define DMA_AUTO 254
233#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
234
Finn Thain22f5f102014-11-12 16:11:56 +1100235#ifndef NO_IRQ
236#define NO_IRQ 0
237#endif
238
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239#define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
240#define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
241#define FLAG_NCR53C400 4 /* NCR53c400 */
242#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
243#define FLAG_DTC3181E 16 /* DTC3181E */
Finn Thainef1081c2014-11-12 16:12:14 +1100244#define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */
Finn Thainca513fc2014-11-12 16:12:19 +1100245#define FLAG_TAGGED_QUEUING 64 /* as X3T9.2 spelled it */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246
247#ifndef ASM
248struct NCR5380_hostdata {
249 NCR5380_implementation_fields; /* implementation specific */
250 struct Scsi_Host *host; /* Host backpointer */
251 unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
252 unsigned char targets_present; /* targets we have connected
253 to, so we can call a select
254 failure a retryable condition */
255 volatile unsigned char busy[8]; /* index = target, bit = lun */
256#if defined(REAL_DMA) || defined(REAL_DMA_POLL)
257 volatile int dma_len; /* requested length of DMA */
258#endif
259 volatile unsigned char last_message; /* last message OUT */
Finn Thain710ddd02014-11-12 16:12:02 +1100260 volatile struct scsi_cmnd *connected; /* currently connected command */
261 volatile struct scsi_cmnd *issue_queue; /* waiting to be issued */
262 volatile struct scsi_cmnd *disconnected_queue; /* waiting for reconnect */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263 volatile int restart_select; /* we have disconnected,
264 used to restart
265 NCR5380_select() */
266 volatile unsigned aborted:1; /* flag, says aborted */
267 int flags;
268 unsigned long time_expires; /* in jiffies, set prior to sleeping */
269 int select_time; /* timer in select for target response */
Finn Thain710ddd02014-11-12 16:12:02 +1100270 volatile struct scsi_cmnd *selecting;
David Howellsc4028952006-11-22 14:57:56 +0000271 struct delayed_work coroutine; /* our co-routine */
Boaz Harrosh28424d32007-09-10 22:37:45 +0300272 struct scsi_eh_save ses;
Finn Thain8c325132014-11-12 16:11:58 +1100273 char info[256];
Finn Thainef1081c2014-11-12 16:12:14 +1100274 int read_overruns; /* number of bytes to cut from a
275 * transfer to handle chip overruns */
276 int retain_dma_intr;
Finn Thaina9c2dc42014-11-12 16:11:59 +1100277#ifdef PSEUDO_DMA
278 unsigned spin_max_r;
279 unsigned spin_max_w;
280#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281};
282
283#ifdef __KERNEL__
284
Finn Thain9829e522014-03-18 11:42:21 +1100285#ifndef NDEBUG
286#define NDEBUG (0)
287#endif
288
Finn Thain16b9d872014-05-29 00:43:43 +1000289#define dprintk(flg, fmt, ...) \
Finn Thaind61c5422014-11-12 16:11:47 +1100290 do { if ((NDEBUG) & (flg)) \
291 printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
Finn Thain16b9d872014-05-29 00:43:43 +1000292
Finn Thain9829e522014-03-18 11:42:21 +1100293#if NDEBUG
Finn Thain9829e522014-03-18 11:42:21 +1100294#define NCR5380_dprint(flg, arg) \
295 do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
296#define NCR5380_dprint_phase(flg, arg) \
297 do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
298static void NCR5380_print_phase(struct Scsi_Host *instance);
299static void NCR5380_print(struct Scsi_Host *instance);
300#else
Finn Thain52a6a1c2014-03-18 11:42:18 +1100301#define NCR5380_dprint(flg, arg) do {} while (0)
302#define NCR5380_dprint_phase(flg, arg) do {} while (0)
Finn Thain9829e522014-03-18 11:42:21 +1100303#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
305#if defined(AUTOPROBE_IRQ)
306static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
307#endif
308static int NCR5380_init(struct Scsi_Host *instance, int flags);
309static void NCR5380_exit(struct Scsi_Host *instance);
310static void NCR5380_information_transfer(struct Scsi_Host *instance);
311#ifndef DONT_USE_INTR
David Howells7d12e782006-10-05 14:55:46 +0100312static irqreturn_t NCR5380_intr(int irq, void *dev_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313#endif
David Howellsc4028952006-11-22 14:57:56 +0000314static void NCR5380_main(struct work_struct *work);
Finn Thain8c325132014-11-12 16:11:58 +1100315static const char *NCR5380_info(struct Scsi_Host *instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316static void NCR5380_reselect(struct Scsi_Host *instance);
Finn Thain710ddd02014-11-12 16:12:02 +1100317static int NCR5380_select(struct Scsi_Host *instance, struct scsi_cmnd *cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
319static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
320#endif
321static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
322
323#if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
324
325#if defined(i386) || defined(__alpha__)
326
327/**
328 * NCR5380_pc_dma_setup - setup ISA DMA
329 * @instance: adapter to set up
330 * @ptr: block to transfer (virtual address)
331 * @count: number of bytes to transfer
332 * @mode: DMA controller mode to use
333 *
334 * Program the DMA controller ready to perform an ISA DMA transfer
335 * on this chip.
336 *
337 * Locks: takes and releases the ISA DMA lock.
338 */
339
340static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
341{
342 unsigned limit;
343 unsigned long bus_addr = virt_to_bus(ptr);
344 unsigned long flags;
345
346 if (instance->dma_channel <= 3) {
347 if (count > 65536)
348 count = 65536;
349 limit = 65536 - (bus_addr & 0xFFFF);
350 } else {
351 if (count > 65536 * 2)
352 count = 65536 * 2;
353 limit = 65536 * 2 - (bus_addr & 0x1FFFF);
354 }
355
356 if (count > limit)
357 count = limit;
358
359 if ((count & 1) || (bus_addr & 1))
360 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
361
362 flags=claim_dma_lock();
363 disable_dma(instance->dma_channel);
364 clear_dma_ff(instance->dma_channel);
365 set_dma_addr(instance->dma_channel, bus_addr);
366 set_dma_count(instance->dma_channel, count);
367 set_dma_mode(instance->dma_channel, mode);
368 enable_dma(instance->dma_channel);
369 release_dma_lock(flags);
370
371 return count;
372}
373
374/**
375 * NCR5380_pc_dma_write_setup - setup ISA DMA write
376 * @instance: adapter to set up
377 * @ptr: block to transfer (virtual address)
378 * @count: number of bytes to transfer
379 *
380 * Program the DMA controller ready to perform an ISA DMA write to the
381 * SCSI controller.
382 *
383 * Locks: called routines take and release the ISA DMA lock.
384 */
385
386static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
387{
388 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
389}
390
391/**
392 * NCR5380_pc_dma_read_setup - setup ISA DMA read
393 * @instance: adapter to set up
394 * @ptr: block to transfer (virtual address)
395 * @count: number of bytes to transfer
396 *
397 * Program the DMA controller ready to perform an ISA DMA read from the
398 * SCSI controller.
399 *
400 * Locks: called routines take and release the ISA DMA lock.
401 */
402
403static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
404{
405 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
406}
407
408/**
409 * NCR5380_pc_dma_residual - return bytes left
410 * @instance: adapter
411 *
412 * Reports the number of bytes left over after the DMA was terminated.
413 *
414 * Locks: takes and releases the ISA DMA lock.
415 */
416
417static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
418{
419 unsigned long flags;
420 int tmp;
421
422 flags = claim_dma_lock();
423 clear_dma_ff(instance->dma_channel);
424 tmp = get_dma_residue(instance->dma_channel);
425 release_dma_lock(flags);
426
427 return tmp;
428}
429#endif /* defined(i386) || defined(__alpha__) */
430#endif /* defined(REAL_DMA) */
431#endif /* __KERNEL__ */
432#endif /* ndef ASM */
433#endif /* NCR5380_H */