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Mark Lordedea3ab2005-10-10 17:53:58 -04001/*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
Tejun Heo8c3d3d42013-05-14 11:09:50 -07004 * Maintained by: Tejun Heo <tj@kernel.org>
Mark Lordedea3ab2005-10-10 17:53:58 -04005 *
6 * Copyright 2005 Mark Lord
7 *
Jeff Garzik68399bb2005-10-11 01:44:14 -04008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
Mark Lordedea3ab2005-10-10 17:53:58 -040012 *
Jeff Garzik68399bb2005-10-11 01:44:14 -040013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
Mark Lordedea3ab2005-10-10 17:53:58 -040026 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090037#include <linux/gfp.h>
Mark Lordedea3ab2005-10-10 17:53:58 -040038#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/blkdev.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Mark Lordedea3ab2005-10-10 17:53:58 -040044#include <scsi/scsi_host.h>
Mark Lordedea3ab2005-10-10 17:53:58 -040045#include <linux/libata.h>
46
47#define DRV_NAME "pdc_adma"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040048#define DRV_VERSION "1.0"
Mark Lordedea3ab2005-10-10 17:53:58 -040049
50/* macro to calculate base address for ATA regs */
Jeff Garzik5796d1c2007-10-26 00:03:37 -040051#define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
Mark Lordedea3ab2005-10-10 17:53:58 -040052
53/* macro to calculate base address for ADMA regs */
Jeff Garzik5796d1c2007-10-26 00:03:37 -040054#define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
Tejun Heo0d5ff562007-02-01 15:06:36 +090055
Tejun Heo5d728822007-04-17 23:44:08 +090056/* macro to obtain addresses from ata_port */
57#define ADMA_PORT_REGS(ap) \
58 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
Mark Lordedea3ab2005-10-10 17:53:58 -040059
60enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090061 ADMA_MMIO_BAR = 4,
62
Mark Lordedea3ab2005-10-10 17:53:58 -040063 ADMA_PORTS = 2,
64 ADMA_CPB_BYTES = 40,
65 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
66 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
67
68 ADMA_DMA_BOUNDARY = 0xffffffff,
69
70 /* global register offsets */
71 ADMA_MODE_LOCK = 0x00c7,
72
73 /* per-channel register offsets */
74 ADMA_CONTROL = 0x0000, /* ADMA control */
75 ADMA_STATUS = 0x0002, /* ADMA status */
76 ADMA_CPB_COUNT = 0x0004, /* CPB count */
77 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
78 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
79 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
80 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
81 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
82
83 /* ADMA_CONTROL register bits */
84 aNIEN = (1 << 8), /* irq mask: 1==masked */
85 aGO = (1 << 7), /* packet trigger ("Go!") */
86 aRSTADM = (1 << 5), /* ADMA logic reset */
Mark Lordedea3ab2005-10-10 17:53:58 -040087 aPIOMD4 = 0x0003, /* PIO mode 4 */
88
89 /* ADMA_STATUS register bits */
90 aPSD = (1 << 6),
91 aUIRQ = (1 << 4),
92 aPERR = (1 << 0),
93
94 /* CPB bits */
95 cDONE = (1 << 0),
Jeff Garzik640fdb52007-08-03 11:10:07 -040096 cATERR = (1 << 3),
97
Mark Lordedea3ab2005-10-10 17:53:58 -040098 cVLD = (1 << 0),
99 cDAT = (1 << 2),
100 cIEN = (1 << 3),
101
102 /* PRD bits */
103 pORD = (1 << 4),
104 pDIRO = (1 << 5),
105 pEND = (1 << 7),
106
107 /* ATA register flags */
108 rIGN = (1 << 5),
109 rEND = (1 << 7),
110
111 /* ATA register addresses */
112 ADMA_REGS_CONTROL = 0x0e,
113 ADMA_REGS_SECTOR_COUNT = 0x12,
114 ADMA_REGS_LBA_LOW = 0x13,
115 ADMA_REGS_LBA_MID = 0x14,
116 ADMA_REGS_LBA_HIGH = 0x15,
117 ADMA_REGS_DEVICE = 0x16,
118 ADMA_REGS_COMMAND = 0x17,
119
120 /* PCI device IDs */
121 board_1841_idx = 0, /* ADMA 2-port controller */
122};
123
124typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
125
126struct adma_port_priv {
127 u8 *pkt;
128 dma_addr_t pkt_dma;
129 adma_state_t state;
130};
131
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400132static int adma_ata_init_one(struct pci_dev *pdev,
Mark Lordedea3ab2005-10-10 17:53:58 -0400133 const struct pci_device_id *ent);
Mark Lordedea3ab2005-10-10 17:53:58 -0400134static int adma_port_start(struct ata_port *ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400135static void adma_port_stop(struct ata_port *ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400136static void adma_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900137static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
Mark Lordedea3ab2005-10-10 17:53:58 -0400138static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
Jeff Garzik640fdb52007-08-03 11:10:07 -0400139static void adma_freeze(struct ata_port *ap);
140static void adma_thaw(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900141static int adma_prereset(struct ata_link *link, unsigned long deadline);
Mark Lordedea3ab2005-10-10 17:53:58 -0400142
Jeff Garzik193515d2005-11-07 00:59:37 -0500143static struct scsi_host_template adma_ata_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900144 ATA_BASE_SHT(DRV_NAME),
Jeff Garzik49de0ac2007-05-26 18:20:51 -0400145 .sg_tablesize = LIBATA_MAX_PRD,
146 .dma_boundary = ADMA_DMA_BOUNDARY,
Mark Lordedea3ab2005-10-10 17:53:58 -0400147};
148
Tejun Heo029cfd62008-03-25 12:22:49 +0900149static struct ata_port_operations adma_ata_ops = {
Tejun Heob0316b12008-03-25 21:35:30 +0900150 .inherits = &ata_sff_port_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +0900151
Alan Coxc96f1732009-03-24 10:23:46 +0000152 .lost_interrupt = ATA_OP_NULL,
153
Tejun Heo029cfd62008-03-25 12:22:49 +0900154 .check_atapi_dma = adma_check_atapi_dma,
Mark Lordedea3ab2005-10-10 17:53:58 -0400155 .qc_prep = adma_qc_prep,
156 .qc_issue = adma_qc_issue,
Tejun Heo029cfd62008-03-25 12:22:49 +0900157
Jeff Garzik640fdb52007-08-03 11:10:07 -0400158 .freeze = adma_freeze,
159 .thaw = adma_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900160 .prereset = adma_prereset,
Tejun Heo029cfd62008-03-25 12:22:49 +0900161
Mark Lordedea3ab2005-10-10 17:53:58 -0400162 .port_start = adma_port_start,
163 .port_stop = adma_port_stop,
Mark Lordedea3ab2005-10-10 17:53:58 -0400164};
165
166static struct ata_port_info adma_port_info[] = {
167 /* board_1841_idx */
168 {
Sergei Shtylyov9cbe0562011-02-04 22:05:48 +0300169 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100170 .pio_mask = ATA_PIO4_ONLY,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400171 .udma_mask = ATA_UDMA4,
Mark Lordedea3ab2005-10-10 17:53:58 -0400172 .port_ops = &adma_ata_ops,
173 },
174};
175
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500176static const struct pci_device_id adma_ata_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400177 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
Mark Lordedea3ab2005-10-10 17:53:58 -0400178
179 { } /* terminate list */
180};
181
182static struct pci_driver adma_ata_pci_driver = {
183 .name = DRV_NAME,
184 .id_table = adma_ata_pci_tbl,
185 .probe = adma_ata_init_one,
186 .remove = ata_pci_remove_one,
187};
188
189static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
190{
191 return 1; /* ATAPI DMA not yet supported */
192}
193
Tejun Heo5d728822007-04-17 23:44:08 +0900194static void adma_reset_engine(struct ata_port *ap)
Mark Lordedea3ab2005-10-10 17:53:58 -0400195{
Tejun Heo5d728822007-04-17 23:44:08 +0900196 void __iomem *chan = ADMA_PORT_REGS(ap);
197
Mark Lordedea3ab2005-10-10 17:53:58 -0400198 /* reset ADMA to idle state */
199 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
200 udelay(2);
201 writew(aPIOMD4, chan + ADMA_CONTROL);
202 udelay(2);
203}
204
205static void adma_reinit_engine(struct ata_port *ap)
206{
207 struct adma_port_priv *pp = ap->private_data;
Tejun Heo5d728822007-04-17 23:44:08 +0900208 void __iomem *chan = ADMA_PORT_REGS(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400209
210 /* mask/clear ATA interrupts */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900211 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
Tejun Heo9363c382008-04-07 22:47:16 +0900212 ata_sff_check_status(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400213
214 /* reset the ADMA engine */
Tejun Heo5d728822007-04-17 23:44:08 +0900215 adma_reset_engine(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400216
217 /* set in-FIFO threshold to 0x100 */
218 writew(0x100, chan + ADMA_FIFO_IN);
219
220 /* set CPB pointer */
221 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
222
223 /* set out-FIFO threshold to 0x100 */
224 writew(0x100, chan + ADMA_FIFO_OUT);
225
226 /* set CPB count */
227 writew(1, chan + ADMA_CPB_COUNT);
228
229 /* read/discard ADMA status */
230 readb(chan + ADMA_STATUS);
231}
232
233static inline void adma_enter_reg_mode(struct ata_port *ap)
234{
Tejun Heo5d728822007-04-17 23:44:08 +0900235 void __iomem *chan = ADMA_PORT_REGS(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400236
237 writew(aPIOMD4, chan + ADMA_CONTROL);
238 readb(chan + ADMA_STATUS); /* flush */
239}
240
Jeff Garzik640fdb52007-08-03 11:10:07 -0400241static void adma_freeze(struct ata_port *ap)
Mark Lordedea3ab2005-10-10 17:53:58 -0400242{
Jeff Garzik640fdb52007-08-03 11:10:07 -0400243 void __iomem *chan = ADMA_PORT_REGS(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400244
Jeff Garzik640fdb52007-08-03 11:10:07 -0400245 /* mask/clear ATA interrupts */
246 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
Tejun Heo9363c382008-04-07 22:47:16 +0900247 ata_sff_check_status(ap);
Jeff Garzik640fdb52007-08-03 11:10:07 -0400248
249 /* reset ADMA to idle state */
250 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
251 udelay(2);
252 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
253 udelay(2);
Mark Lordedea3ab2005-10-10 17:53:58 -0400254}
255
Jeff Garzik640fdb52007-08-03 11:10:07 -0400256static void adma_thaw(struct ata_port *ap)
257{
258 adma_reinit_engine(ap);
259}
260
Tejun Heo02607312007-08-06 18:36:23 +0900261static int adma_prereset(struct ata_link *link, unsigned long deadline)
Mark Lordedea3ab2005-10-10 17:53:58 -0400262{
Tejun Heo02607312007-08-06 18:36:23 +0900263 struct ata_port *ap = link->ap;
Mark Lordedea3ab2005-10-10 17:53:58 -0400264 struct adma_port_priv *pp = ap->private_data;
265
266 if (pp->state != adma_state_idle) /* healthy paranoia */
267 pp->state = adma_state_mmio;
268 adma_reinit_engine(ap);
Jeff Garzik640fdb52007-08-03 11:10:07 -0400269
Tejun Heo9363c382008-04-07 22:47:16 +0900270 return ata_sff_prereset(link, deadline);
Jeff Garzik640fdb52007-08-03 11:10:07 -0400271}
272
Mark Lordedea3ab2005-10-10 17:53:58 -0400273static int adma_fill_sg(struct ata_queued_cmd *qc)
274{
Jeff Garzik972c26b2005-10-18 22:14:54 -0400275 struct scatterlist *sg;
Mark Lordedea3ab2005-10-10 17:53:58 -0400276 struct ata_port *ap = qc->ap;
277 struct adma_port_priv *pp = ap->private_data;
Jeff Garzik3be6cbd2007-10-18 16:21:18 -0400278 u8 *buf = pp->pkt, *last_buf = NULL;
Jeff Garzik972c26b2005-10-18 22:14:54 -0400279 int i = (2 + buf[3]) * 8;
Mark Lordedea3ab2005-10-10 17:53:58 -0400280 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
Tejun Heoff2aeb12007-12-05 16:43:11 +0900281 unsigned int si;
Mark Lordedea3ab2005-10-10 17:53:58 -0400282
Tejun Heoff2aeb12007-12-05 16:43:11 +0900283 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Mark Lordedea3ab2005-10-10 17:53:58 -0400284 u32 addr;
285 u32 len;
286
287 addr = (u32)sg_dma_address(sg);
288 *(__le32 *)(buf + i) = cpu_to_le32(addr);
289 i += 4;
290
291 len = sg_dma_len(sg) >> 3;
292 *(__le32 *)(buf + i) = cpu_to_le32(len);
293 i += 4;
294
Jeff Garzik3be6cbd2007-10-18 16:21:18 -0400295 last_buf = &buf[i];
Mark Lordedea3ab2005-10-10 17:53:58 -0400296 buf[i++] = pFLAGS;
297 buf[i++] = qc->dev->dma_mode & 0xf;
298 buf[i++] = 0; /* pPKLW */
299 buf[i++] = 0; /* reserved */
300
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400301 *(__le32 *)(buf + i) =
302 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
Mark Lordedea3ab2005-10-10 17:53:58 -0400303 i += 4;
304
Alan Coxdb7f44d2006-03-21 15:54:24 +0000305 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
Mark Lordedea3ab2005-10-10 17:53:58 -0400306 (unsigned long)addr, len);
307 }
Jeff Garzik3be6cbd2007-10-18 16:21:18 -0400308
309 if (likely(last_buf))
310 *last_buf |= pEND;
311
Mark Lordedea3ab2005-10-10 17:53:58 -0400312 return i;
313}
314
315static void adma_qc_prep(struct ata_queued_cmd *qc)
316{
317 struct adma_port_priv *pp = qc->ap->private_data;
318 u8 *buf = pp->pkt;
319 u32 pkt_dma = (u32)pp->pkt_dma;
320 int i = 0;
321
322 VPRINTK("ENTER\n");
323
324 adma_enter_reg_mode(qc->ap);
Tejun Heof47451c2010-05-10 21:41:40 +0200325 if (qc->tf.protocol != ATA_PROT_DMA)
Mark Lordedea3ab2005-10-10 17:53:58 -0400326 return;
Mark Lordedea3ab2005-10-10 17:53:58 -0400327
328 buf[i++] = 0; /* Response flags */
329 buf[i++] = 0; /* reserved */
330 buf[i++] = cVLD | cDAT | cIEN;
331 i++; /* cLEN, gets filled in below */
332
333 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
334 i += 4; /* cNCPB */
335 i += 4; /* cPRD, gets filled in below */
336
337 buf[i++] = 0; /* reserved */
338 buf[i++] = 0; /* reserved */
339 buf[i++] = 0; /* reserved */
340 buf[i++] = 0; /* reserved */
341
342 /* ATA registers; must be a multiple of 4 */
343 buf[i++] = qc->tf.device;
344 buf[i++] = ADMA_REGS_DEVICE;
345 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
346 buf[i++] = qc->tf.hob_nsect;
347 buf[i++] = ADMA_REGS_SECTOR_COUNT;
348 buf[i++] = qc->tf.hob_lbal;
349 buf[i++] = ADMA_REGS_LBA_LOW;
350 buf[i++] = qc->tf.hob_lbam;
351 buf[i++] = ADMA_REGS_LBA_MID;
352 buf[i++] = qc->tf.hob_lbah;
353 buf[i++] = ADMA_REGS_LBA_HIGH;
354 }
355 buf[i++] = qc->tf.nsect;
356 buf[i++] = ADMA_REGS_SECTOR_COUNT;
357 buf[i++] = qc->tf.lbal;
358 buf[i++] = ADMA_REGS_LBA_LOW;
359 buf[i++] = qc->tf.lbam;
360 buf[i++] = ADMA_REGS_LBA_MID;
361 buf[i++] = qc->tf.lbah;
362 buf[i++] = ADMA_REGS_LBA_HIGH;
363 buf[i++] = 0;
364 buf[i++] = ADMA_REGS_CONTROL;
365 buf[i++] = rIGN;
366 buf[i++] = 0;
367 buf[i++] = qc->tf.command;
368 buf[i++] = ADMA_REGS_COMMAND | rEND;
369
370 buf[3] = (i >> 3) - 2; /* cLEN */
371 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
372
373 i = adma_fill_sg(qc);
374 wmb(); /* flush PRDs and pkt to memory */
375#if 0
376 /* dump out CPB + PRDs for debug */
377 {
378 int j, len = 0;
379 static char obuf[2048];
380 for (j = 0; j < i; ++j) {
381 len += sprintf(obuf+len, "%02x ", buf[j]);
382 if ((j & 7) == 7) {
383 printk("%s\n", obuf);
384 len = 0;
385 }
386 }
387 if (len)
388 printk("%s\n", obuf);
389 }
390#endif
391}
392
393static inline void adma_packet_start(struct ata_queued_cmd *qc)
394{
395 struct ata_port *ap = qc->ap;
Tejun Heo5d728822007-04-17 23:44:08 +0900396 void __iomem *chan = ADMA_PORT_REGS(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400397
398 VPRINTK("ENTER, ap %p\n", ap);
399
400 /* fire up the ADMA engine */
Jeff Garzik68399bb2005-10-11 01:44:14 -0400401 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
Mark Lordedea3ab2005-10-10 17:53:58 -0400402}
403
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900404static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
Mark Lordedea3ab2005-10-10 17:53:58 -0400405{
406 struct adma_port_priv *pp = qc->ap->private_data;
407
408 switch (qc->tf.protocol) {
409 case ATA_PROT_DMA:
410 pp->state = adma_state_pkt;
411 adma_packet_start(qc);
412 return 0;
413
Tejun Heo0dc36882007-12-18 16:34:43 -0500414 case ATAPI_PROT_DMA:
Mark Lordedea3ab2005-10-10 17:53:58 -0400415 BUG();
416 break;
417
418 default:
419 break;
420 }
421
422 pp->state = adma_state_mmio;
Tejun Heo9363c382008-04-07 22:47:16 +0900423 return ata_sff_qc_issue(qc);
Mark Lordedea3ab2005-10-10 17:53:58 -0400424}
425
Jeff Garzikcca39742006-08-24 03:19:22 -0400426static inline unsigned int adma_intr_pkt(struct ata_host *host)
Mark Lordedea3ab2005-10-10 17:53:58 -0400427{
428 unsigned int handled = 0, port_no;
Mark Lordedea3ab2005-10-10 17:53:58 -0400429
Jeff Garzikcca39742006-08-24 03:19:22 -0400430 for (port_no = 0; port_no < host->n_ports; ++port_no) {
431 struct ata_port *ap = host->ports[port_no];
Mark Lordedea3ab2005-10-10 17:53:58 -0400432 struct adma_port_priv *pp;
433 struct ata_queued_cmd *qc;
Tejun Heo5d728822007-04-17 23:44:08 +0900434 void __iomem *chan = ADMA_PORT_REGS(ap);
Jeff Garzika7dac442005-10-30 04:44:42 -0500435 u8 status = readb(chan + ADMA_STATUS);
Mark Lordedea3ab2005-10-10 17:53:58 -0400436
437 if (status == 0)
438 continue;
439 handled = 1;
440 adma_enter_reg_mode(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400441 pp = ap->private_data;
442 if (!pp || pp->state != adma_state_pkt)
443 continue;
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900444 qc = ata_qc_from_tag(ap, ap->link.active_tag);
Jeff Garzik94ec1ef2005-10-30 02:15:08 -0500445 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
Jeff Garzik640fdb52007-08-03 11:10:07 -0400446 if (status & aPERR)
447 qc->err_mask |= AC_ERR_HOST_BUS;
448 else if ((status & (aPSD | aUIRQ)))
Albert Leea22e2eb2005-12-05 15:38:02 +0800449 qc->err_mask |= AC_ERR_OTHER;
Jeff Garzik640fdb52007-08-03 11:10:07 -0400450
451 if (pp->pkt[0] & cATERR)
452 qc->err_mask |= AC_ERR_DEV;
Jeff Garzika21a84a2005-10-28 15:43:16 -0400453 else if (pp->pkt[0] != cDONE)
Albert Leea22e2eb2005-12-05 15:38:02 +0800454 qc->err_mask |= AC_ERR_OTHER;
Jeff Garzika7dac442005-10-30 04:44:42 -0500455
Jeff Garzik640fdb52007-08-03 11:10:07 -0400456 if (!qc->err_mask)
457 ata_qc_complete(qc);
458 else {
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900459 struct ata_eh_info *ehi = &ap->link.eh_info;
Jeff Garzik640fdb52007-08-03 11:10:07 -0400460 ata_ehi_clear_desc(ehi);
461 ata_ehi_push_desc(ehi,
462 "ADMA-status 0x%02X", status);
463 ata_ehi_push_desc(ehi,
464 "pkt[0] 0x%02X", pp->pkt[0]);
465
466 if (qc->err_mask == AC_ERR_DEV)
467 ata_port_abort(ap);
468 else
469 ata_port_freeze(ap);
470 }
Jeff Garzika21a84a2005-10-28 15:43:16 -0400471 }
Mark Lordedea3ab2005-10-10 17:53:58 -0400472 }
473 return handled;
474}
475
Jeff Garzikcca39742006-08-24 03:19:22 -0400476static inline unsigned int adma_intr_mmio(struct ata_host *host)
Mark Lordedea3ab2005-10-10 17:53:58 -0400477{
478 unsigned int handled = 0, port_no;
479
Jeff Garzikcca39742006-08-24 03:19:22 -0400480 for (port_no = 0; port_no < host->n_ports; ++port_no) {
Tejun Heo3e4ec342010-05-10 21:41:30 +0200481 struct ata_port *ap = host->ports[port_no];
482 struct adma_port_priv *pp = ap->private_data;
483 struct ata_queued_cmd *qc;
484
485 if (!pp || pp->state != adma_state_mmio)
486 continue;
487 qc = ata_qc_from_tag(ap, ap->link.active_tag);
488 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
489
490 /* check main status, clearing INTRQ */
491 u8 status = ata_sff_check_status(ap);
492 if ((status & ATA_BUSY))
Mark Lordedea3ab2005-10-10 17:53:58 -0400493 continue;
Tejun Heo3e4ec342010-05-10 21:41:30 +0200494 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
495 ap->print_id, qc->tf.protocol, status);
Mark Lordedea3ab2005-10-10 17:53:58 -0400496
Tejun Heo3e4ec342010-05-10 21:41:30 +0200497 /* complete taskfile transaction */
498 pp->state = adma_state_idle;
499 qc->err_mask |= ac_err_mask(status);
500 if (!qc->err_mask)
501 ata_qc_complete(qc);
502 else {
503 struct ata_eh_info *ehi = &ap->link.eh_info;
504 ata_ehi_clear_desc(ehi);
505 ata_ehi_push_desc(ehi, "status 0x%02X", status);
Jeff Garzik9bec2e32006-08-31 00:02:15 -0400506
Tejun Heo3e4ec342010-05-10 21:41:30 +0200507 if (qc->err_mask == AC_ERR_DEV)
508 ata_port_abort(ap);
509 else
510 ata_port_freeze(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400511 }
Tejun Heo3e4ec342010-05-10 21:41:30 +0200512 handled = 1;
Mark Lordedea3ab2005-10-10 17:53:58 -0400513 }
514 }
515 return handled;
516}
517
David Howells7d12e782006-10-05 14:55:46 +0100518static irqreturn_t adma_intr(int irq, void *dev_instance)
Mark Lordedea3ab2005-10-10 17:53:58 -0400519{
Jeff Garzikcca39742006-08-24 03:19:22 -0400520 struct ata_host *host = dev_instance;
Mark Lordedea3ab2005-10-10 17:53:58 -0400521 unsigned int handled = 0;
522
523 VPRINTK("ENTER\n");
524
Jeff Garzikcca39742006-08-24 03:19:22 -0400525 spin_lock(&host->lock);
526 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
527 spin_unlock(&host->lock);
Mark Lordedea3ab2005-10-10 17:53:58 -0400528
529 VPRINTK("EXIT\n");
530
531 return IRQ_RETVAL(handled);
532}
533
Tejun Heo0d5ff562007-02-01 15:06:36 +0900534static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
Mark Lordedea3ab2005-10-10 17:53:58 -0400535{
536 port->cmd_addr =
537 port->data_addr = base + 0x000;
538 port->error_addr =
539 port->feature_addr = base + 0x004;
540 port->nsect_addr = base + 0x008;
541 port->lbal_addr = base + 0x00c;
542 port->lbam_addr = base + 0x010;
543 port->lbah_addr = base + 0x014;
544 port->device_addr = base + 0x018;
545 port->status_addr =
546 port->command_addr = base + 0x01c;
547 port->altstatus_addr =
548 port->ctl_addr = base + 0x038;
549}
550
551static int adma_port_start(struct ata_port *ap)
552{
Jeff Garzikcca39742006-08-24 03:19:22 -0400553 struct device *dev = ap->host->dev;
Mark Lordedea3ab2005-10-10 17:53:58 -0400554 struct adma_port_priv *pp;
Mark Lordedea3ab2005-10-10 17:53:58 -0400555
Mark Lordedea3ab2005-10-10 17:53:58 -0400556 adma_enter_reg_mode(ap);
Tejun Heo24dc5f32007-01-20 16:00:28 +0900557 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Mark Lordedea3ab2005-10-10 17:53:58 -0400558 if (!pp)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900559 return -ENOMEM;
560 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
561 GFP_KERNEL);
Mark Lordedea3ab2005-10-10 17:53:58 -0400562 if (!pp->pkt)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900563 return -ENOMEM;
Mark Lordedea3ab2005-10-10 17:53:58 -0400564 /* paranoia? */
565 if ((pp->pkt_dma & 7) != 0) {
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400566 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
Mark Lordedea3ab2005-10-10 17:53:58 -0400567 (u32)pp->pkt_dma);
Tejun Heo24dc5f32007-01-20 16:00:28 +0900568 return -ENOMEM;
Mark Lordedea3ab2005-10-10 17:53:58 -0400569 }
570 memset(pp->pkt, 0, ADMA_PKT_BYTES);
571 ap->private_data = pp;
572 adma_reinit_engine(ap);
573 return 0;
Mark Lordedea3ab2005-10-10 17:53:58 -0400574}
575
576static void adma_port_stop(struct ata_port *ap)
577{
Tejun Heo5d728822007-04-17 23:44:08 +0900578 adma_reset_engine(ap);
Mark Lordedea3ab2005-10-10 17:53:58 -0400579}
580
Tejun Heo5d728822007-04-17 23:44:08 +0900581static void adma_host_init(struct ata_host *host, unsigned int chip_id)
Mark Lordedea3ab2005-10-10 17:53:58 -0400582{
583 unsigned int port_no;
Mark Lordedea3ab2005-10-10 17:53:58 -0400584
585 /* enable/lock aGO operation */
Tejun Heo5d728822007-04-17 23:44:08 +0900586 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
Mark Lordedea3ab2005-10-10 17:53:58 -0400587
588 /* reset the ADMA logic */
589 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
Tejun Heo5d728822007-04-17 23:44:08 +0900590 adma_reset_engine(host->ports[port_no]);
Mark Lordedea3ab2005-10-10 17:53:58 -0400591}
592
593static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
594{
595 int rc;
596
Yang Hongyang284901a2009-04-06 19:01:15 -0700597 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Mark Lordedea3ab2005-10-10 17:53:58 -0400598 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700599 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
Mark Lordedea3ab2005-10-10 17:53:58 -0400600 return rc;
601 }
Yang Hongyang284901a2009-04-06 19:01:15 -0700602 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Mark Lordedea3ab2005-10-10 17:53:58 -0400603 if (rc) {
Joe Perchesa44fec12011-04-15 15:51:58 -0700604 dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
Mark Lordedea3ab2005-10-10 17:53:58 -0400605 return rc;
606 }
607 return 0;
608}
609
610static int adma_ata_init_one(struct pci_dev *pdev,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900611 const struct pci_device_id *ent)
Mark Lordedea3ab2005-10-10 17:53:58 -0400612{
Mark Lordedea3ab2005-10-10 17:53:58 -0400613 unsigned int board_idx = (unsigned int) ent->driver_data;
Tejun Heo5d728822007-04-17 23:44:08 +0900614 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
615 struct ata_host *host;
616 void __iomem *mmio_base;
Mark Lordedea3ab2005-10-10 17:53:58 -0400617 int rc, port_no;
618
Joe Perches06296a12011-04-15 15:52:00 -0700619 ata_print_version_once(&pdev->dev, DRV_VERSION);
Mark Lordedea3ab2005-10-10 17:53:58 -0400620
Tejun Heo5d728822007-04-17 23:44:08 +0900621 /* alloc host */
622 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
623 if (!host)
624 return -ENOMEM;
625
626 /* acquire resources and fill host */
Tejun Heo24dc5f32007-01-20 16:00:28 +0900627 rc = pcim_enable_device(pdev);
Mark Lordedea3ab2005-10-10 17:53:58 -0400628 if (rc)
629 return rc;
630
Tejun Heo24dc5f32007-01-20 16:00:28 +0900631 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
632 return -ENODEV;
Mark Lordedea3ab2005-10-10 17:53:58 -0400633
Tejun Heo0d5ff562007-02-01 15:06:36 +0900634 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
635 if (rc)
636 return rc;
Tejun Heo5d728822007-04-17 23:44:08 +0900637 host->iomap = pcim_iomap_table(pdev);
638 mmio_base = host->iomap[ADMA_MMIO_BAR];
Mark Lordedea3ab2005-10-10 17:53:58 -0400639
640 rc = adma_set_dma_masks(pdev, mmio_base);
641 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900642 return rc;
Mark Lordedea3ab2005-10-10 17:53:58 -0400643
Tejun Heocbcdd872007-08-18 13:14:55 +0900644 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
645 struct ata_port *ap = host->ports[port_no];
646 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
647 unsigned int offset = port_base - mmio_base;
648
649 adma_ata_setup_port(&ap->ioaddr, port_base);
650
651 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
652 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
653 }
Mark Lordedea3ab2005-10-10 17:53:58 -0400654
655 /* initialize adapter */
Tejun Heo5d728822007-04-17 23:44:08 +0900656 adma_host_init(host, board_idx);
Mark Lordedea3ab2005-10-10 17:53:58 -0400657
Tejun Heo5d728822007-04-17 23:44:08 +0900658 pci_set_master(pdev);
659 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
660 &adma_ata_sht);
Mark Lordedea3ab2005-10-10 17:53:58 -0400661}
662
Axel Lin2fc75da2012-04-19 13:43:05 +0800663module_pci_driver(adma_ata_pci_driver);
Mark Lordedea3ab2005-10-10 17:53:58 -0400664
665MODULE_AUTHOR("Mark Lord");
666MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
667MODULE_LICENSE("GPL");
668MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
669MODULE_VERSION(DRV_VERSION);