Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1 | /* |
| 2 | * EDMA3 support for DaVinci |
| 3 | * |
| 4 | * Copyright (C) 2006-2009 Texas Instruments. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | */ |
| 20 | #include <linux/kernel.h> |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 21 | #include <linux/init.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/platform_device.h> |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 25 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 26 | #include <linux/slab.h> |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 27 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 28 | #include <mach/edma.h> |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 29 | |
| 30 | /* Offsets matching "struct edmacc_param" */ |
| 31 | #define PARM_OPT 0x00 |
| 32 | #define PARM_SRC 0x04 |
| 33 | #define PARM_A_B_CNT 0x08 |
| 34 | #define PARM_DST 0x0c |
| 35 | #define PARM_SRC_DST_BIDX 0x10 |
| 36 | #define PARM_LINK_BCNTRLD 0x14 |
| 37 | #define PARM_SRC_DST_CIDX 0x18 |
| 38 | #define PARM_CCNT 0x1c |
| 39 | |
| 40 | #define PARM_SIZE 0x20 |
| 41 | |
| 42 | /* Offsets for EDMA CC global channel registers and their shadows */ |
| 43 | #define SH_ER 0x00 /* 64 bits */ |
| 44 | #define SH_ECR 0x08 /* 64 bits */ |
| 45 | #define SH_ESR 0x10 /* 64 bits */ |
| 46 | #define SH_CER 0x18 /* 64 bits */ |
| 47 | #define SH_EER 0x20 /* 64 bits */ |
| 48 | #define SH_EECR 0x28 /* 64 bits */ |
| 49 | #define SH_EESR 0x30 /* 64 bits */ |
| 50 | #define SH_SER 0x38 /* 64 bits */ |
| 51 | #define SH_SECR 0x40 /* 64 bits */ |
| 52 | #define SH_IER 0x50 /* 64 bits */ |
| 53 | #define SH_IECR 0x58 /* 64 bits */ |
| 54 | #define SH_IESR 0x60 /* 64 bits */ |
| 55 | #define SH_IPR 0x68 /* 64 bits */ |
| 56 | #define SH_ICR 0x70 /* 64 bits */ |
| 57 | #define SH_IEVAL 0x78 |
| 58 | #define SH_QER 0x80 |
| 59 | #define SH_QEER 0x84 |
| 60 | #define SH_QEECR 0x88 |
| 61 | #define SH_QEESR 0x8c |
| 62 | #define SH_QSER 0x90 |
| 63 | #define SH_QSECR 0x94 |
| 64 | #define SH_SIZE 0x200 |
| 65 | |
| 66 | /* Offsets for EDMA CC global registers */ |
| 67 | #define EDMA_REV 0x0000 |
| 68 | #define EDMA_CCCFG 0x0004 |
| 69 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ |
| 70 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ |
| 71 | #define EDMA_QDMAQNUM 0x0260 |
| 72 | #define EDMA_QUETCMAP 0x0280 |
| 73 | #define EDMA_QUEPRI 0x0284 |
| 74 | #define EDMA_EMR 0x0300 /* 64 bits */ |
| 75 | #define EDMA_EMCR 0x0308 /* 64 bits */ |
| 76 | #define EDMA_QEMR 0x0310 |
| 77 | #define EDMA_QEMCR 0x0314 |
| 78 | #define EDMA_CCERR 0x0318 |
| 79 | #define EDMA_CCERRCLR 0x031c |
| 80 | #define EDMA_EEVAL 0x0320 |
| 81 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ |
| 82 | #define EDMA_QRAE 0x0380 /* 4 registers */ |
| 83 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ |
| 84 | #define EDMA_QSTAT 0x0600 /* 2 registers */ |
| 85 | #define EDMA_QWMTHRA 0x0620 |
| 86 | #define EDMA_QWMTHRB 0x0624 |
| 87 | #define EDMA_CCSTAT 0x0640 |
| 88 | |
| 89 | #define EDMA_M 0x1000 /* global channel registers */ |
| 90 | #define EDMA_ECR 0x1008 |
| 91 | #define EDMA_ECRH 0x100C |
| 92 | #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ |
| 93 | #define EDMA_PARM 0x4000 /* 128 param entries */ |
| 94 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 95 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
| 96 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 97 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ |
| 98 | #define CHMAP_EXIST BIT(24) |
| 99 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 100 | #define EDMA_MAX_DMACH 64 |
| 101 | #define EDMA_MAX_PARAMENTRY 512 |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 102 | |
| 103 | /*****************************************************************************/ |
| 104 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 105 | static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 106 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 107 | static inline unsigned int edma_read(unsigned ctlr, int offset) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 108 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 109 | return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 110 | } |
| 111 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 112 | static inline void edma_write(unsigned ctlr, int offset, int val) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 113 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 114 | __raw_writel(val, edmacc_regs_base[ctlr] + offset); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 115 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 116 | static inline void edma_modify(unsigned ctlr, int offset, unsigned and, |
| 117 | unsigned or) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 118 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 119 | unsigned val = edma_read(ctlr, offset); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 120 | val &= and; |
| 121 | val |= or; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 122 | edma_write(ctlr, offset, val); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 123 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 124 | static inline void edma_and(unsigned ctlr, int offset, unsigned and) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 125 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 126 | unsigned val = edma_read(ctlr, offset); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 127 | val &= and; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 128 | edma_write(ctlr, offset, val); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 129 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 130 | static inline void edma_or(unsigned ctlr, int offset, unsigned or) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 131 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 132 | unsigned val = edma_read(ctlr, offset); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 133 | val |= or; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 134 | edma_write(ctlr, offset, val); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 135 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 136 | static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 137 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 138 | return edma_read(ctlr, offset + (i << 2)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 139 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 140 | static inline void edma_write_array(unsigned ctlr, int offset, int i, |
| 141 | unsigned val) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 142 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 143 | edma_write(ctlr, offset + (i << 2), val); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 144 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 145 | static inline void edma_modify_array(unsigned ctlr, int offset, int i, |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 146 | unsigned and, unsigned or) |
| 147 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 148 | edma_modify(ctlr, offset + (i << 2), and, or); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 149 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 150 | static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 151 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 152 | edma_or(ctlr, offset + (i << 2), or); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 153 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 154 | static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, |
| 155 | unsigned or) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 156 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 157 | edma_or(ctlr, offset + ((i*2 + j) << 2), or); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 158 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 159 | static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, |
| 160 | unsigned val) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 161 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 162 | edma_write(ctlr, offset + ((i*2 + j) << 2), val); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 163 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 164 | static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 165 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 166 | return edma_read(ctlr, EDMA_SHADOW0 + offset); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 167 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 168 | static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, |
| 169 | int i) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 170 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 171 | return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 172 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 173 | static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 174 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 175 | edma_write(ctlr, EDMA_SHADOW0 + offset, val); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 176 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 177 | static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, |
| 178 | unsigned val) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 179 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 180 | edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 181 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 182 | static inline unsigned int edma_parm_read(unsigned ctlr, int offset, |
| 183 | int param_no) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 184 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 185 | return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 186 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 187 | static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, |
| 188 | unsigned val) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 189 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 190 | edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 191 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 192 | static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 193 | unsigned and, unsigned or) |
| 194 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 195 | edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 196 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 197 | static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, |
| 198 | unsigned and) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 199 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 200 | edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 201 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 202 | static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, |
| 203 | unsigned or) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 204 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 205 | edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 206 | } |
| 207 | |
Rajashekhara, Sudhakar | 90bd4e6 | 2010-06-29 11:35:13 +0530 | [diff] [blame] | 208 | static inline void set_bits(int offset, int len, unsigned long *p) |
| 209 | { |
| 210 | for (; len > 0; len--) |
| 211 | set_bit(offset + (len - 1), p); |
| 212 | } |
| 213 | |
| 214 | static inline void clear_bits(int offset, int len, unsigned long *p) |
| 215 | { |
| 216 | for (; len > 0; len--) |
| 217 | clear_bit(offset + (len - 1), p); |
| 218 | } |
| 219 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 220 | /*****************************************************************************/ |
| 221 | |
| 222 | /* actual number of DMA channels and slots on this silicon */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 223 | struct edma { |
| 224 | /* how many dma resources of each type */ |
| 225 | unsigned num_channels; |
| 226 | unsigned num_region; |
| 227 | unsigned num_slots; |
| 228 | unsigned num_tc; |
| 229 | unsigned num_cc; |
Sandeep Paulraj | a0f0202 | 2009-07-27 09:57:07 -0400 | [diff] [blame] | 230 | enum dma_event_q default_queue; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 231 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 232 | /* list of channels with no even trigger; terminated by "-1" */ |
| 233 | const s8 *noevent; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 234 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 235 | /* The edma_inuse bit for each PaRAM slot is clear unless the |
| 236 | * channel is in use ... by ARM or DSP, for QDMA, or whatever. |
| 237 | */ |
| 238 | DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 239 | |
Sudhakar Rajashekhara | f900d55 | 2010-01-06 17:29:49 +0530 | [diff] [blame] | 240 | /* The edma_unused bit for each channel is clear unless |
| 241 | * it is not being used on this platform. It uses a bit |
| 242 | * of SOC-specific initialization code. |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 243 | */ |
Sudhakar Rajashekhara | f900d55 | 2010-01-06 17:29:49 +0530 | [diff] [blame] | 244 | DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 245 | |
| 246 | unsigned irq_res_start; |
| 247 | unsigned irq_res_end; |
| 248 | |
| 249 | struct dma_interrupt_data { |
| 250 | void (*callback)(unsigned channel, unsigned short ch_status, |
| 251 | void *data); |
| 252 | void *data; |
| 253 | } intr_data[EDMA_MAX_DMACH]; |
| 254 | }; |
| 255 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 256 | static struct edma *edma_cc[EDMA_MAX_CC]; |
Sudhakar Rajashekhara | 2d51750 | 2010-01-06 17:28:44 +0530 | [diff] [blame] | 257 | static int arch_num_cc; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 258 | |
| 259 | /* dummy param set used to (re)initialize parameter RAM slots */ |
| 260 | static const struct edmacc_param dummy_paramset = { |
| 261 | .link_bcntrld = 0xffff, |
| 262 | .ccnt = 1, |
| 263 | }; |
| 264 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 265 | /*****************************************************************************/ |
| 266 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 267 | static void map_dmach_queue(unsigned ctlr, unsigned ch_no, |
| 268 | enum dma_event_q queue_no) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 269 | { |
| 270 | int bit = (ch_no & 0x7) * 4; |
| 271 | |
| 272 | /* default to low priority queue */ |
| 273 | if (queue_no == EVENTQ_DEFAULT) |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 274 | queue_no = edma_cc[ctlr]->default_queue; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 275 | |
| 276 | queue_no &= 7; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 277 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 278 | ~(0x7 << bit), queue_no << bit); |
| 279 | } |
| 280 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 281 | static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 282 | { |
| 283 | int bit = queue_no * 4; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 284 | edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 285 | } |
| 286 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 287 | static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, |
| 288 | int priority) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 289 | { |
| 290 | int bit = queue_no * 4; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 291 | edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), |
| 292 | ((priority & 0x7) << bit)); |
| 293 | } |
| 294 | |
| 295 | /** |
| 296 | * map_dmach_param - Maps channel number to param entry number |
| 297 | * |
| 298 | * This maps the dma channel number to param entry numberter. In |
| 299 | * other words using the DMA channel mapping registers a param entry |
| 300 | * can be mapped to any channel |
| 301 | * |
| 302 | * Callers are responsible for ensuring the channel mapping logic is |
| 303 | * included in that particular EDMA variant (Eg : dm646x) |
| 304 | * |
| 305 | */ |
| 306 | static void __init map_dmach_param(unsigned ctlr) |
| 307 | { |
| 308 | int i; |
| 309 | for (i = 0; i < EDMA_MAX_DMACH; i++) |
| 310 | edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 311 | } |
| 312 | |
| 313 | static inline void |
| 314 | setup_dma_interrupt(unsigned lch, |
| 315 | void (*callback)(unsigned channel, u16 ch_status, void *data), |
| 316 | void *data) |
| 317 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 318 | unsigned ctlr; |
| 319 | |
| 320 | ctlr = EDMA_CTLR(lch); |
| 321 | lch = EDMA_CHAN_SLOT(lch); |
| 322 | |
Sekhar Nori | 243bc65 | 2010-05-04 14:11:36 +0530 | [diff] [blame] | 323 | if (!callback) |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 324 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 325 | BIT(lch & 0x1f)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 326 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 327 | edma_cc[ctlr]->intr_data[lch].callback = callback; |
| 328 | edma_cc[ctlr]->intr_data[lch].data = data; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 329 | |
| 330 | if (callback) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 331 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 332 | BIT(lch & 0x1f)); |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 333 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 334 | BIT(lch & 0x1f)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 335 | } |
| 336 | } |
| 337 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 338 | static int irq2ctlr(int irq) |
| 339 | { |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 340 | if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 341 | return 0; |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 342 | else if (irq >= edma_cc[1]->irq_res_start && |
| 343 | irq <= edma_cc[1]->irq_res_end) |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 344 | return 1; |
| 345 | |
| 346 | return -1; |
| 347 | } |
| 348 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 349 | /****************************************************************************** |
| 350 | * |
| 351 | * DMA interrupt handler |
| 352 | * |
| 353 | *****************************************************************************/ |
| 354 | static irqreturn_t dma_irq_handler(int irq, void *data) |
| 355 | { |
Kulikov Vasiliy | 93fe23d | 2010-07-17 19:19:07 +0400 | [diff] [blame] | 356 | int ctlr; |
Sebastian Andrzej Siewior | bcd59b0 | 2012-02-09 13:28:26 +0100 | [diff] [blame] | 357 | u32 sh_ier; |
| 358 | u32 sh_ipr; |
| 359 | u32 bank; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 360 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 361 | ctlr = irq2ctlr(irq); |
Kulikov Vasiliy | 93fe23d | 2010-07-17 19:19:07 +0400 | [diff] [blame] | 362 | if (ctlr < 0) |
| 363 | return IRQ_NONE; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 364 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 365 | dev_dbg(data, "dma_irq_handler\n"); |
| 366 | |
Sebastian Andrzej Siewior | bcd59b0 | 2012-02-09 13:28:26 +0100 | [diff] [blame] | 367 | sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0); |
| 368 | if (!sh_ipr) { |
| 369 | sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1); |
| 370 | if (!sh_ipr) |
| 371 | return IRQ_NONE; |
| 372 | sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1); |
| 373 | bank = 1; |
| 374 | } else { |
| 375 | sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0); |
| 376 | bank = 0; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 377 | } |
Sebastian Andrzej Siewior | bcd59b0 | 2012-02-09 13:28:26 +0100 | [diff] [blame] | 378 | |
| 379 | do { |
| 380 | u32 slot; |
| 381 | u32 channel; |
| 382 | |
| 383 | dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr); |
| 384 | |
| 385 | slot = __ffs(sh_ipr); |
| 386 | sh_ipr &= ~(BIT(slot)); |
| 387 | |
| 388 | if (sh_ier & BIT(slot)) { |
| 389 | channel = (bank << 5) | slot; |
| 390 | /* Clear the corresponding IPR bits */ |
| 391 | edma_shadow0_write_array(ctlr, SH_ICR, bank, |
| 392 | BIT(slot)); |
| 393 | if (edma_cc[ctlr]->intr_data[channel].callback) |
| 394 | edma_cc[ctlr]->intr_data[channel].callback( |
| 395 | channel, DMA_COMPLETE, |
| 396 | edma_cc[ctlr]->intr_data[channel].data); |
| 397 | } |
| 398 | } while (sh_ipr); |
| 399 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 400 | edma_shadow0_write(ctlr, SH_IEVAL, 1); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 401 | return IRQ_HANDLED; |
| 402 | } |
| 403 | |
| 404 | /****************************************************************************** |
| 405 | * |
| 406 | * DMA error interrupt handler |
| 407 | * |
| 408 | *****************************************************************************/ |
| 409 | static irqreturn_t dma_ccerr_handler(int irq, void *data) |
| 410 | { |
| 411 | int i; |
Kulikov Vasiliy | 93fe23d | 2010-07-17 19:19:07 +0400 | [diff] [blame] | 412 | int ctlr; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 413 | unsigned int cnt = 0; |
| 414 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 415 | ctlr = irq2ctlr(irq); |
Kulikov Vasiliy | 93fe23d | 2010-07-17 19:19:07 +0400 | [diff] [blame] | 416 | if (ctlr < 0) |
| 417 | return IRQ_NONE; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 418 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 419 | dev_dbg(data, "dma_ccerr_handler\n"); |
| 420 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 421 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
| 422 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && |
| 423 | (edma_read(ctlr, EDMA_QEMR) == 0) && |
| 424 | (edma_read(ctlr, EDMA_CCERR) == 0)) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 425 | return IRQ_NONE; |
| 426 | |
| 427 | while (1) { |
| 428 | int j = -1; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 429 | if (edma_read_array(ctlr, EDMA_EMR, 0)) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 430 | j = 0; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 431 | else if (edma_read_array(ctlr, EDMA_EMR, 1)) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 432 | j = 1; |
| 433 | if (j >= 0) { |
| 434 | dev_dbg(data, "EMR%d %08x\n", j, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 435 | edma_read_array(ctlr, EDMA_EMR, j)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 436 | for (i = 0; i < 32; i++) { |
| 437 | int k = (j << 5) + i; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 438 | if (edma_read_array(ctlr, EDMA_EMR, j) & |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 439 | BIT(i)) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 440 | /* Clear the corresponding EMR bits */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 441 | edma_write_array(ctlr, EDMA_EMCR, j, |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 442 | BIT(i)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 443 | /* Clear any SER */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 444 | edma_shadow0_write_array(ctlr, SH_SECR, |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 445 | j, BIT(i)); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 446 | if (edma_cc[ctlr]->intr_data[k]. |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 447 | callback) { |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 448 | edma_cc[ctlr]->intr_data[k]. |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 449 | callback(k, |
| 450 | DMA_CC_ERROR, |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 451 | edma_cc[ctlr]->intr_data |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 452 | [k].data); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 453 | } |
| 454 | } |
| 455 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 456 | } else if (edma_read(ctlr, EDMA_QEMR)) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 457 | dev_dbg(data, "QEMR %02x\n", |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 458 | edma_read(ctlr, EDMA_QEMR)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 459 | for (i = 0; i < 8; i++) { |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 460 | if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 461 | /* Clear the corresponding IPR bits */ |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 462 | edma_write(ctlr, EDMA_QEMCR, BIT(i)); |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 463 | edma_shadow0_write(ctlr, SH_QSECR, |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 464 | BIT(i)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 465 | |
| 466 | /* NOTE: not reported!! */ |
| 467 | } |
| 468 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 469 | } else if (edma_read(ctlr, EDMA_CCERR)) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 470 | dev_dbg(data, "CCERR %08x\n", |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 471 | edma_read(ctlr, EDMA_CCERR)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 472 | /* FIXME: CCERR.BIT(16) ignored! much better |
| 473 | * to just write CCERRCLR with CCERR value... |
| 474 | */ |
| 475 | for (i = 0; i < 8; i++) { |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 476 | if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 477 | /* Clear the corresponding IPR bits */ |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 478 | edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 479 | |
| 480 | /* NOTE: not reported!! */ |
| 481 | } |
| 482 | } |
| 483 | } |
Sekhar Nori | a6374f5 | 2010-05-10 12:41:19 +0530 | [diff] [blame] | 484 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
| 485 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && |
| 486 | (edma_read(ctlr, EDMA_QEMR) == 0) && |
| 487 | (edma_read(ctlr, EDMA_CCERR) == 0)) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 488 | break; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 489 | cnt++; |
| 490 | if (cnt > 10) |
| 491 | break; |
| 492 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 493 | edma_write(ctlr, EDMA_EEVAL, 1); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 494 | return IRQ_HANDLED; |
| 495 | } |
| 496 | |
| 497 | /****************************************************************************** |
| 498 | * |
| 499 | * Transfer controller error interrupt handlers |
| 500 | * |
| 501 | *****************************************************************************/ |
| 502 | |
| 503 | #define tc_errs_handled false /* disabled as long as they're NOPs */ |
| 504 | |
| 505 | static irqreturn_t dma_tc0err_handler(int irq, void *data) |
| 506 | { |
| 507 | dev_dbg(data, "dma_tc0err_handler\n"); |
| 508 | return IRQ_HANDLED; |
| 509 | } |
| 510 | |
| 511 | static irqreturn_t dma_tc1err_handler(int irq, void *data) |
| 512 | { |
| 513 | dev_dbg(data, "dma_tc1err_handler\n"); |
| 514 | return IRQ_HANDLED; |
| 515 | } |
| 516 | |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 517 | static int reserve_contiguous_slots(int ctlr, unsigned int id, |
| 518 | unsigned int num_slots, |
| 519 | unsigned int start_slot) |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 520 | { |
| 521 | int i, j; |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 522 | unsigned int count = num_slots; |
| 523 | int stop_slot = start_slot; |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 524 | DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 525 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 526 | for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 527 | j = EDMA_CHAN_SLOT(i); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 528 | if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 529 | /* Record our current beginning slot */ |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 530 | if (count == num_slots) |
| 531 | stop_slot = i; |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 532 | |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 533 | count--; |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 534 | set_bit(j, tmp_inuse); |
| 535 | |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 536 | if (count == 0) |
| 537 | break; |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 538 | } else { |
| 539 | clear_bit(j, tmp_inuse); |
| 540 | |
| 541 | if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 542 | stop_slot = i; |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 543 | break; |
Sekhar Nori | 243bc65 | 2010-05-04 14:11:36 +0530 | [diff] [blame] | 544 | } else { |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 545 | count = num_slots; |
Sekhar Nori | 243bc65 | 2010-05-04 14:11:36 +0530 | [diff] [blame] | 546 | } |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 547 | } |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 548 | } |
| 549 | |
| 550 | /* |
| 551 | * We have to clear any bits that we set |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 552 | * if we run out parameter RAM slots, i.e we do find a set |
| 553 | * of contiguous parameter RAM slots but do not find the exact number |
| 554 | * requested as we may reach the total number of parameter RAM slots |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 555 | */ |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 556 | if (i == edma_cc[ctlr]->num_slots) |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 557 | stop_slot = i; |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 558 | |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 559 | for (j = start_slot; j < stop_slot; j++) |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 560 | if (test_bit(j, tmp_inuse)) |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 561 | clear_bit(j, edma_cc[ctlr]->edma_inuse); |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 562 | |
Sandeep Paulraj | cc93fc3 | 2009-09-20 13:47:03 -0400 | [diff] [blame] | 563 | if (count) |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 564 | return -EBUSY; |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 565 | |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 566 | for (j = i - num_slots + 1; j <= i; ++j) |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 567 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), |
| 568 | &dummy_paramset, PARM_SIZE); |
| 569 | |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 570 | return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 571 | } |
| 572 | |
Sudhakar Rajashekhara | f900d55 | 2010-01-06 17:29:49 +0530 | [diff] [blame] | 573 | static int prepare_unused_channel_list(struct device *dev, void *data) |
| 574 | { |
| 575 | struct platform_device *pdev = to_platform_device(dev); |
| 576 | int i, ctlr; |
| 577 | |
| 578 | for (i = 0; i < pdev->num_resources; i++) { |
| 579 | if ((pdev->resource[i].flags & IORESOURCE_DMA) && |
| 580 | (int)pdev->resource[i].start >= 0) { |
| 581 | ctlr = EDMA_CTLR(pdev->resource[i].start); |
| 582 | clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 583 | edma_cc[ctlr]->edma_unused); |
Sudhakar Rajashekhara | f900d55 | 2010-01-06 17:29:49 +0530 | [diff] [blame] | 584 | } |
| 585 | } |
| 586 | |
| 587 | return 0; |
| 588 | } |
| 589 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 590 | /*-----------------------------------------------------------------------*/ |
| 591 | |
Sudhakar Rajashekhara | f900d55 | 2010-01-06 17:29:49 +0530 | [diff] [blame] | 592 | static bool unused_chan_list_done; |
| 593 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 594 | /* Resource alloc/free: dma channels, parameter RAM slots */ |
| 595 | |
| 596 | /** |
| 597 | * edma_alloc_channel - allocate DMA channel and paired parameter RAM |
| 598 | * @channel: specific channel to allocate; negative for "any unmapped channel" |
| 599 | * @callback: optional; to be issued on DMA completion or errors |
| 600 | * @data: passed to callback |
| 601 | * @eventq_no: an EVENTQ_* constant, used to choose which Transfer |
| 602 | * Controller (TC) executes requests using this channel. Use |
| 603 | * EVENTQ_DEFAULT unless you really need a high priority queue. |
| 604 | * |
| 605 | * This allocates a DMA channel and its associated parameter RAM slot. |
| 606 | * The parameter RAM is initialized to hold a dummy transfer. |
| 607 | * |
| 608 | * Normal use is to pass a specific channel number as @channel, to make |
| 609 | * use of hardware events mapped to that channel. When the channel will |
| 610 | * be used only for software triggering or event chaining, channels not |
| 611 | * mapped to hardware events (or mapped to unused events) are preferable. |
| 612 | * |
| 613 | * DMA transfers start from a channel using edma_start(), or by |
| 614 | * chaining. When the transfer described in that channel's parameter RAM |
| 615 | * slot completes, that slot's data may be reloaded through a link. |
| 616 | * |
| 617 | * DMA errors are only reported to the @callback associated with the |
| 618 | * channel driving that transfer, but transfer completion callbacks can |
| 619 | * be sent to another channel under control of the TCC field in |
| 620 | * the option word of the transfer's parameter RAM set. Drivers must not |
| 621 | * use DMA transfer completion callbacks for channels they did not allocate. |
| 622 | * (The same applies to TCC codes used in transfer chaining.) |
| 623 | * |
| 624 | * Returns the number of the channel, else negative errno. |
| 625 | */ |
| 626 | int edma_alloc_channel(int channel, |
| 627 | void (*callback)(unsigned channel, u16 ch_status, void *data), |
| 628 | void *data, |
| 629 | enum dma_event_q eventq_no) |
| 630 | { |
Sudhakar Rajashekhara | 447f18f | 2010-01-06 17:29:11 +0530 | [diff] [blame] | 631 | unsigned i, done = 0, ctlr = 0; |
Sudhakar Rajashekhara | f900d55 | 2010-01-06 17:29:49 +0530 | [diff] [blame] | 632 | int ret = 0; |
| 633 | |
| 634 | if (!unused_chan_list_done) { |
| 635 | /* |
| 636 | * Scan all the platform devices to find out the EDMA channels |
| 637 | * used and clear them in the unused list, making the rest |
| 638 | * available for ARM usage. |
| 639 | */ |
| 640 | ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, |
| 641 | prepare_unused_channel_list); |
| 642 | if (ret < 0) |
| 643 | return ret; |
| 644 | |
| 645 | unused_chan_list_done = true; |
| 646 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 647 | |
| 648 | if (channel >= 0) { |
| 649 | ctlr = EDMA_CTLR(channel); |
| 650 | channel = EDMA_CHAN_SLOT(channel); |
| 651 | } |
| 652 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 653 | if (channel < 0) { |
Sudhakar Rajashekhara | 2d51750 | 2010-01-06 17:28:44 +0530 | [diff] [blame] | 654 | for (i = 0; i < arch_num_cc; i++) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 655 | channel = 0; |
| 656 | for (;;) { |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 657 | channel = find_next_bit(edma_cc[i]->edma_unused, |
| 658 | edma_cc[i]->num_channels, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 659 | channel); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 660 | if (channel == edma_cc[i]->num_channels) |
Sudhakar Rajashekhara | 447f18f | 2010-01-06 17:29:11 +0530 | [diff] [blame] | 661 | break; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 662 | if (!test_and_set_bit(channel, |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 663 | edma_cc[i]->edma_inuse)) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 664 | done = 1; |
| 665 | ctlr = i; |
| 666 | break; |
| 667 | } |
| 668 | channel++; |
| 669 | } |
| 670 | if (done) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 671 | break; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 672 | } |
Sudhakar Rajashekhara | 447f18f | 2010-01-06 17:29:11 +0530 | [diff] [blame] | 673 | if (!done) |
| 674 | return -ENOMEM; |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 675 | } else if (channel >= edma_cc[ctlr]->num_channels) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 676 | return -EINVAL; |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 677 | } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 678 | return -EBUSY; |
| 679 | } |
| 680 | |
| 681 | /* ensure access through shadow region 0 */ |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 682 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 683 | |
| 684 | /* ensure no events are pending */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 685 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); |
| 686 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 687 | &dummy_paramset, PARM_SIZE); |
| 688 | |
| 689 | if (callback) |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 690 | setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), |
| 691 | callback, data); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 692 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 693 | map_dmach_queue(ctlr, channel, eventq_no); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 694 | |
Sudhakar Rajashekhara | 0e6cb8d | 2010-01-06 17:28:36 +0530 | [diff] [blame] | 695 | return EDMA_CTLR_CHAN(ctlr, channel); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 696 | } |
| 697 | EXPORT_SYMBOL(edma_alloc_channel); |
| 698 | |
| 699 | |
| 700 | /** |
| 701 | * edma_free_channel - deallocate DMA channel |
| 702 | * @channel: dma channel returned from edma_alloc_channel() |
| 703 | * |
| 704 | * This deallocates the DMA channel and associated parameter RAM slot |
| 705 | * allocated by edma_alloc_channel(). |
| 706 | * |
| 707 | * Callers are responsible for ensuring the channel is inactive, and |
| 708 | * will not be reactivated by linking, chaining, or software calls to |
| 709 | * edma_start(). |
| 710 | */ |
| 711 | void edma_free_channel(unsigned channel) |
| 712 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 713 | unsigned ctlr; |
| 714 | |
| 715 | ctlr = EDMA_CTLR(channel); |
| 716 | channel = EDMA_CHAN_SLOT(channel); |
| 717 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 718 | if (channel >= edma_cc[ctlr]->num_channels) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 719 | return; |
| 720 | |
| 721 | setup_dma_interrupt(channel, NULL, NULL); |
| 722 | /* REVISIT should probably take out of shadow region 0 */ |
| 723 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 724 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 725 | &dummy_paramset, PARM_SIZE); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 726 | clear_bit(channel, edma_cc[ctlr]->edma_inuse); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 727 | } |
| 728 | EXPORT_SYMBOL(edma_free_channel); |
| 729 | |
| 730 | /** |
| 731 | * edma_alloc_slot - allocate DMA parameter RAM |
| 732 | * @slot: specific slot to allocate; negative for "any unused slot" |
| 733 | * |
| 734 | * This allocates a parameter RAM slot, initializing it to hold a |
| 735 | * dummy transfer. Slots allocated using this routine have not been |
| 736 | * mapped to a hardware DMA channel, and will normally be used by |
| 737 | * linking to them from a slot associated with a DMA channel. |
| 738 | * |
| 739 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific |
| 740 | * slots may be allocated on behalf of DSP firmware. |
| 741 | * |
| 742 | * Returns the number of the slot, else negative errno. |
| 743 | */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 744 | int edma_alloc_slot(unsigned ctlr, int slot) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 745 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 746 | if (slot >= 0) |
| 747 | slot = EDMA_CHAN_SLOT(slot); |
| 748 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 749 | if (slot < 0) { |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 750 | slot = edma_cc[ctlr]->num_channels; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 751 | for (;;) { |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 752 | slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, |
| 753 | edma_cc[ctlr]->num_slots, slot); |
| 754 | if (slot == edma_cc[ctlr]->num_slots) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 755 | return -ENOMEM; |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 756 | if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 757 | break; |
| 758 | } |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 759 | } else if (slot < edma_cc[ctlr]->num_channels || |
| 760 | slot >= edma_cc[ctlr]->num_slots) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 761 | return -EINVAL; |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 762 | } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 763 | return -EBUSY; |
| 764 | } |
| 765 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 766 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 767 | &dummy_paramset, PARM_SIZE); |
| 768 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 769 | return EDMA_CTLR_CHAN(ctlr, slot); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 770 | } |
| 771 | EXPORT_SYMBOL(edma_alloc_slot); |
| 772 | |
| 773 | /** |
| 774 | * edma_free_slot - deallocate DMA parameter RAM |
| 775 | * @slot: parameter RAM slot returned from edma_alloc_slot() |
| 776 | * |
| 777 | * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). |
| 778 | * Callers are responsible for ensuring the slot is inactive, and will |
| 779 | * not be activated. |
| 780 | */ |
| 781 | void edma_free_slot(unsigned slot) |
| 782 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 783 | unsigned ctlr; |
| 784 | |
| 785 | ctlr = EDMA_CTLR(slot); |
| 786 | slot = EDMA_CHAN_SLOT(slot); |
| 787 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 788 | if (slot < edma_cc[ctlr]->num_channels || |
| 789 | slot >= edma_cc[ctlr]->num_slots) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 790 | return; |
| 791 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 792 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 793 | &dummy_paramset, PARM_SIZE); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 794 | clear_bit(slot, edma_cc[ctlr]->edma_inuse); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 795 | } |
| 796 | EXPORT_SYMBOL(edma_free_slot); |
| 797 | |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 798 | |
| 799 | /** |
| 800 | * edma_alloc_cont_slots- alloc contiguous parameter RAM slots |
| 801 | * The API will return the starting point of a set of |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 802 | * contiguous parameter RAM slots that have been requested |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 803 | * |
| 804 | * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT |
| 805 | * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 806 | * @count: number of contiguous Paramter RAM slots |
| 807 | * @slot - the start value of Parameter RAM slot that should be passed if id |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 808 | * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT |
| 809 | * |
| 810 | * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 811 | * contiguous Parameter RAM slots from parameter RAM 64 in the case of |
| 812 | * DaVinci SOCs and 32 in the case of DA8xx SOCs. |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 813 | * |
| 814 | * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 815 | * set of contiguous parameter RAM slots from the "slot" that is passed as an |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 816 | * argument to the API. |
| 817 | * |
| 818 | * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 819 | * starts looking for a set of contiguous parameter RAMs from the "slot" |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 820 | * that is passed as an argument to the API. On failure the API will try to |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 821 | * find a set of contiguous Parameter RAM slots from the remaining Parameter |
| 822 | * RAM slots |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 823 | */ |
| 824 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) |
| 825 | { |
| 826 | /* |
| 827 | * The start slot requested should be greater than |
| 828 | * the number of channels and lesser than the total number |
| 829 | * of slots |
| 830 | */ |
Sandeep Paulraj | 6b0cf4e | 2009-09-16 18:17:43 -0400 | [diff] [blame] | 831 | if ((id != EDMA_CONT_PARAMS_ANY) && |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 832 | (slot < edma_cc[ctlr]->num_channels || |
| 833 | slot >= edma_cc[ctlr]->num_slots)) |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 834 | return -EINVAL; |
| 835 | |
| 836 | /* |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 837 | * The number of parameter RAM slots requested cannot be less than 1 |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 838 | * and cannot be more than the number of slots minus the number of |
| 839 | * channels |
| 840 | */ |
| 841 | if (count < 1 || count > |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 842 | (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 843 | return -EINVAL; |
| 844 | |
| 845 | switch (id) { |
| 846 | case EDMA_CONT_PARAMS_ANY: |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 847 | return reserve_contiguous_slots(ctlr, id, count, |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 848 | edma_cc[ctlr]->num_channels); |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 849 | case EDMA_CONT_PARAMS_FIXED_EXACT: |
| 850 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 851 | return reserve_contiguous_slots(ctlr, id, count, slot); |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 852 | default: |
| 853 | return -EINVAL; |
| 854 | } |
| 855 | |
| 856 | } |
| 857 | EXPORT_SYMBOL(edma_alloc_cont_slots); |
| 858 | |
| 859 | /** |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 860 | * edma_free_cont_slots - deallocate DMA parameter RAM slots |
| 861 | * @slot: first parameter RAM of a set of parameter RAM slots to be freed |
| 862 | * @count: the number of contiguous parameter RAM slots to be freed |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 863 | * |
| 864 | * This deallocates the parameter RAM slots allocated by |
| 865 | * edma_alloc_cont_slots. |
| 866 | * Callers/applications need to keep track of sets of contiguous |
Sandeep Paulraj | 134ce22 | 2009-09-20 14:06:33 -0400 | [diff] [blame] | 867 | * parameter RAM slots that have been allocated using the edma_alloc_cont_slots |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 868 | * API. |
| 869 | * Callers are responsible for ensuring the slots are inactive, and will |
| 870 | * not be activated. |
| 871 | */ |
| 872 | int edma_free_cont_slots(unsigned slot, int count) |
| 873 | { |
Sandeep Paulraj | 51c99e0 | 2009-09-16 18:09:59 -0400 | [diff] [blame] | 874 | unsigned ctlr, slot_to_free; |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 875 | int i; |
| 876 | |
| 877 | ctlr = EDMA_CTLR(slot); |
| 878 | slot = EDMA_CHAN_SLOT(slot); |
| 879 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 880 | if (slot < edma_cc[ctlr]->num_channels || |
| 881 | slot >= edma_cc[ctlr]->num_slots || |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 882 | count < 1) |
| 883 | return -EINVAL; |
| 884 | |
| 885 | for (i = slot; i < slot + count; ++i) { |
| 886 | ctlr = EDMA_CTLR(i); |
Sandeep Paulraj | 51c99e0 | 2009-09-16 18:09:59 -0400 | [diff] [blame] | 887 | slot_to_free = EDMA_CHAN_SLOT(i); |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 888 | |
Sandeep Paulraj | 51c99e0 | 2009-09-16 18:09:59 -0400 | [diff] [blame] | 889 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 890 | &dummy_paramset, PARM_SIZE); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 891 | clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); |
Sandeep Paulraj | 213765d | 2009-07-27 15:10:36 -0400 | [diff] [blame] | 892 | } |
| 893 | |
| 894 | return 0; |
| 895 | } |
| 896 | EXPORT_SYMBOL(edma_free_cont_slots); |
| 897 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 898 | /*-----------------------------------------------------------------------*/ |
| 899 | |
| 900 | /* Parameter RAM operations (i) -- read/write partial slots */ |
| 901 | |
| 902 | /** |
| 903 | * edma_set_src - set initial DMA source address in parameter RAM slot |
| 904 | * @slot: parameter RAM slot being configured |
| 905 | * @src_port: physical address of source (memory, controller FIFO, etc) |
| 906 | * @addressMode: INCR, except in very rare cases |
| 907 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the |
| 908 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) |
| 909 | * |
| 910 | * Note that the source address is modified during the DMA transfer |
| 911 | * according to edma_set_src_index(). |
| 912 | */ |
| 913 | void edma_set_src(unsigned slot, dma_addr_t src_port, |
| 914 | enum address_mode mode, enum fifo_width width) |
| 915 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 916 | unsigned ctlr; |
| 917 | |
| 918 | ctlr = EDMA_CTLR(slot); |
| 919 | slot = EDMA_CHAN_SLOT(slot); |
| 920 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 921 | if (slot < edma_cc[ctlr]->num_slots) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 922 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 923 | |
| 924 | if (mode) { |
| 925 | /* set SAM and program FWID */ |
| 926 | i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); |
| 927 | } else { |
| 928 | /* clear SAM */ |
| 929 | i &= ~SAM; |
| 930 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 931 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 932 | |
| 933 | /* set the source port address |
| 934 | in source register of param structure */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 935 | edma_parm_write(ctlr, PARM_SRC, slot, src_port); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 936 | } |
| 937 | } |
| 938 | EXPORT_SYMBOL(edma_set_src); |
| 939 | |
| 940 | /** |
| 941 | * edma_set_dest - set initial DMA destination address in parameter RAM slot |
| 942 | * @slot: parameter RAM slot being configured |
| 943 | * @dest_port: physical address of destination (memory, controller FIFO, etc) |
| 944 | * @addressMode: INCR, except in very rare cases |
| 945 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the |
| 946 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) |
| 947 | * |
| 948 | * Note that the destination address is modified during the DMA transfer |
| 949 | * according to edma_set_dest_index(). |
| 950 | */ |
| 951 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, |
| 952 | enum address_mode mode, enum fifo_width width) |
| 953 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 954 | unsigned ctlr; |
| 955 | |
| 956 | ctlr = EDMA_CTLR(slot); |
| 957 | slot = EDMA_CHAN_SLOT(slot); |
| 958 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 959 | if (slot < edma_cc[ctlr]->num_slots) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 960 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 961 | |
| 962 | if (mode) { |
| 963 | /* set DAM and program FWID */ |
| 964 | i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); |
| 965 | } else { |
| 966 | /* clear DAM */ |
| 967 | i &= ~DAM; |
| 968 | } |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 969 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 970 | /* set the destination port address |
| 971 | in dest register of param structure */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 972 | edma_parm_write(ctlr, PARM_DST, slot, dest_port); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 973 | } |
| 974 | } |
| 975 | EXPORT_SYMBOL(edma_set_dest); |
| 976 | |
| 977 | /** |
| 978 | * edma_get_position - returns the current transfer points |
| 979 | * @slot: parameter RAM slot being examined |
| 980 | * @src: pointer to source port position |
| 981 | * @dst: pointer to destination port position |
| 982 | * |
| 983 | * Returns current source and destination addresses for a particular |
| 984 | * parameter RAM slot. Its channel should not be active when this is called. |
| 985 | */ |
| 986 | void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) |
| 987 | { |
| 988 | struct edmacc_param temp; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 989 | unsigned ctlr; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 990 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 991 | ctlr = EDMA_CTLR(slot); |
| 992 | slot = EDMA_CHAN_SLOT(slot); |
| 993 | |
| 994 | edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 995 | if (src != NULL) |
| 996 | *src = temp.src; |
| 997 | if (dst != NULL) |
| 998 | *dst = temp.dst; |
| 999 | } |
| 1000 | EXPORT_SYMBOL(edma_get_position); |
| 1001 | |
| 1002 | /** |
| 1003 | * edma_set_src_index - configure DMA source address indexing |
| 1004 | * @slot: parameter RAM slot being configured |
| 1005 | * @src_bidx: byte offset between source arrays in a frame |
| 1006 | * @src_cidx: byte offset between source frames in a block |
| 1007 | * |
| 1008 | * Offsets are specified to support either contiguous or discontiguous |
| 1009 | * memory transfers, or repeated access to a hardware register, as needed. |
| 1010 | * When accessing hardware registers, both offsets are normally zero. |
| 1011 | */ |
| 1012 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) |
| 1013 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1014 | unsigned ctlr; |
| 1015 | |
| 1016 | ctlr = EDMA_CTLR(slot); |
| 1017 | slot = EDMA_CHAN_SLOT(slot); |
| 1018 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1019 | if (slot < edma_cc[ctlr]->num_slots) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1020 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1021 | 0xffff0000, src_bidx); |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1022 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1023 | 0xffff0000, src_cidx); |
| 1024 | } |
| 1025 | } |
| 1026 | EXPORT_SYMBOL(edma_set_src_index); |
| 1027 | |
| 1028 | /** |
| 1029 | * edma_set_dest_index - configure DMA destination address indexing |
| 1030 | * @slot: parameter RAM slot being configured |
| 1031 | * @dest_bidx: byte offset between destination arrays in a frame |
| 1032 | * @dest_cidx: byte offset between destination frames in a block |
| 1033 | * |
| 1034 | * Offsets are specified to support either contiguous or discontiguous |
| 1035 | * memory transfers, or repeated access to a hardware register, as needed. |
| 1036 | * When accessing hardware registers, both offsets are normally zero. |
| 1037 | */ |
| 1038 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) |
| 1039 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1040 | unsigned ctlr; |
| 1041 | |
| 1042 | ctlr = EDMA_CTLR(slot); |
| 1043 | slot = EDMA_CHAN_SLOT(slot); |
| 1044 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1045 | if (slot < edma_cc[ctlr]->num_slots) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1046 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1047 | 0x0000ffff, dest_bidx << 16); |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1048 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1049 | 0x0000ffff, dest_cidx << 16); |
| 1050 | } |
| 1051 | } |
| 1052 | EXPORT_SYMBOL(edma_set_dest_index); |
| 1053 | |
| 1054 | /** |
| 1055 | * edma_set_transfer_params - configure DMA transfer parameters |
| 1056 | * @slot: parameter RAM slot being configured |
| 1057 | * @acnt: how many bytes per array (at least one) |
| 1058 | * @bcnt: how many arrays per frame (at least one) |
| 1059 | * @ccnt: how many frames per block (at least one) |
| 1060 | * @bcnt_rld: used only for A-Synchronized transfers; this specifies |
| 1061 | * the value to reload into bcnt when it decrements to zero |
| 1062 | * @sync_mode: ASYNC or ABSYNC |
| 1063 | * |
| 1064 | * See the EDMA3 documentation to understand how to configure and link |
| 1065 | * transfers using the fields in PaRAM slots. If you are not doing it |
| 1066 | * all at once with edma_write_slot(), you will use this routine |
| 1067 | * plus two calls each for source and destination, setting the initial |
| 1068 | * address and saying how to index that address. |
| 1069 | * |
| 1070 | * An example of an A-Synchronized transfer is a serial link using a |
| 1071 | * single word shift register. In that case, @acnt would be equal to |
| 1072 | * that word size; the serial controller issues a DMA synchronization |
| 1073 | * event to transfer each word, and memory access by the DMA transfer |
| 1074 | * controller will be word-at-a-time. |
| 1075 | * |
| 1076 | * An example of an AB-Synchronized transfer is a device using a FIFO. |
| 1077 | * In that case, @acnt equals the FIFO width and @bcnt equals its depth. |
| 1078 | * The controller with the FIFO issues DMA synchronization events when |
| 1079 | * the FIFO threshold is reached, and the DMA transfer controller will |
| 1080 | * transfer one frame to (or from) the FIFO. It will probably use |
| 1081 | * efficient burst modes to access memory. |
| 1082 | */ |
| 1083 | void edma_set_transfer_params(unsigned slot, |
| 1084 | u16 acnt, u16 bcnt, u16 ccnt, |
| 1085 | u16 bcnt_rld, enum sync_dimension sync_mode) |
| 1086 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1087 | unsigned ctlr; |
| 1088 | |
| 1089 | ctlr = EDMA_CTLR(slot); |
| 1090 | slot = EDMA_CHAN_SLOT(slot); |
| 1091 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1092 | if (slot < edma_cc[ctlr]->num_slots) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1093 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1094 | 0x0000ffff, bcnt_rld << 16); |
| 1095 | if (sync_mode == ASYNC) |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1096 | edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1097 | else |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1098 | edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1099 | /* Set the acount, bcount, ccount registers */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1100 | edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); |
| 1101 | edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1102 | } |
| 1103 | } |
| 1104 | EXPORT_SYMBOL(edma_set_transfer_params); |
| 1105 | |
| 1106 | /** |
| 1107 | * edma_link - link one parameter RAM slot to another |
| 1108 | * @from: parameter RAM slot originating the link |
| 1109 | * @to: parameter RAM slot which is the link target |
| 1110 | * |
| 1111 | * The originating slot should not be part of any active DMA transfer. |
| 1112 | */ |
| 1113 | void edma_link(unsigned from, unsigned to) |
| 1114 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1115 | unsigned ctlr_from, ctlr_to; |
| 1116 | |
| 1117 | ctlr_from = EDMA_CTLR(from); |
| 1118 | from = EDMA_CHAN_SLOT(from); |
| 1119 | ctlr_to = EDMA_CTLR(to); |
| 1120 | to = EDMA_CHAN_SLOT(to); |
| 1121 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1122 | if (from >= edma_cc[ctlr_from]->num_slots) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1123 | return; |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1124 | if (to >= edma_cc[ctlr_to]->num_slots) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1125 | return; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1126 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, |
| 1127 | PARM_OFFSET(to)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1128 | } |
| 1129 | EXPORT_SYMBOL(edma_link); |
| 1130 | |
| 1131 | /** |
| 1132 | * edma_unlink - cut link from one parameter RAM slot |
| 1133 | * @from: parameter RAM slot originating the link |
| 1134 | * |
| 1135 | * The originating slot should not be part of any active DMA transfer. |
| 1136 | * Its link is set to 0xffff. |
| 1137 | */ |
| 1138 | void edma_unlink(unsigned from) |
| 1139 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1140 | unsigned ctlr; |
| 1141 | |
| 1142 | ctlr = EDMA_CTLR(from); |
| 1143 | from = EDMA_CHAN_SLOT(from); |
| 1144 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1145 | if (from >= edma_cc[ctlr]->num_slots) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1146 | return; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1147 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1148 | } |
| 1149 | EXPORT_SYMBOL(edma_unlink); |
| 1150 | |
| 1151 | /*-----------------------------------------------------------------------*/ |
| 1152 | |
| 1153 | /* Parameter RAM operations (ii) -- read/write whole parameter sets */ |
| 1154 | |
| 1155 | /** |
| 1156 | * edma_write_slot - write parameter RAM data for slot |
| 1157 | * @slot: number of parameter RAM slot being modified |
| 1158 | * @param: data to be written into parameter RAM slot |
| 1159 | * |
| 1160 | * Use this to assign all parameters of a transfer at once. This |
| 1161 | * allows more efficient setup of transfers than issuing multiple |
| 1162 | * calls to set up those parameters in small pieces, and provides |
| 1163 | * complete control over all transfer options. |
| 1164 | */ |
| 1165 | void edma_write_slot(unsigned slot, const struct edmacc_param *param) |
| 1166 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1167 | unsigned ctlr; |
| 1168 | |
| 1169 | ctlr = EDMA_CTLR(slot); |
| 1170 | slot = EDMA_CHAN_SLOT(slot); |
| 1171 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1172 | if (slot >= edma_cc[ctlr]->num_slots) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1173 | return; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1174 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, |
| 1175 | PARM_SIZE); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1176 | } |
| 1177 | EXPORT_SYMBOL(edma_write_slot); |
| 1178 | |
| 1179 | /** |
| 1180 | * edma_read_slot - read parameter RAM data from slot |
| 1181 | * @slot: number of parameter RAM slot being copied |
| 1182 | * @param: where to store copy of parameter RAM data |
| 1183 | * |
| 1184 | * Use this to read data from a parameter RAM slot, perhaps to |
| 1185 | * save them as a template for later reuse. |
| 1186 | */ |
| 1187 | void edma_read_slot(unsigned slot, struct edmacc_param *param) |
| 1188 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1189 | unsigned ctlr; |
| 1190 | |
| 1191 | ctlr = EDMA_CTLR(slot); |
| 1192 | slot = EDMA_CHAN_SLOT(slot); |
| 1193 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1194 | if (slot >= edma_cc[ctlr]->num_slots) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1195 | return; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1196 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
| 1197 | PARM_SIZE); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1198 | } |
| 1199 | EXPORT_SYMBOL(edma_read_slot); |
| 1200 | |
| 1201 | /*-----------------------------------------------------------------------*/ |
| 1202 | |
| 1203 | /* Various EDMA channel control operations */ |
| 1204 | |
| 1205 | /** |
| 1206 | * edma_pause - pause dma on a channel |
| 1207 | * @channel: on which edma_start() has been called |
| 1208 | * |
| 1209 | * This temporarily disables EDMA hardware events on the specified channel, |
| 1210 | * preventing them from triggering new transfers on its behalf |
| 1211 | */ |
| 1212 | void edma_pause(unsigned channel) |
| 1213 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1214 | unsigned ctlr; |
| 1215 | |
| 1216 | ctlr = EDMA_CTLR(channel); |
| 1217 | channel = EDMA_CHAN_SLOT(channel); |
| 1218 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1219 | if (channel < edma_cc[ctlr]->num_channels) { |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 1220 | unsigned int mask = BIT(channel & 0x1f); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1221 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1222 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1223 | } |
| 1224 | } |
| 1225 | EXPORT_SYMBOL(edma_pause); |
| 1226 | |
| 1227 | /** |
| 1228 | * edma_resume - resumes dma on a paused channel |
| 1229 | * @channel: on which edma_pause() has been called |
| 1230 | * |
| 1231 | * This re-enables EDMA hardware events on the specified channel. |
| 1232 | */ |
| 1233 | void edma_resume(unsigned channel) |
| 1234 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1235 | unsigned ctlr; |
| 1236 | |
| 1237 | ctlr = EDMA_CTLR(channel); |
| 1238 | channel = EDMA_CHAN_SLOT(channel); |
| 1239 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1240 | if (channel < edma_cc[ctlr]->num_channels) { |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 1241 | unsigned int mask = BIT(channel & 0x1f); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1242 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1243 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1244 | } |
| 1245 | } |
| 1246 | EXPORT_SYMBOL(edma_resume); |
| 1247 | |
| 1248 | /** |
| 1249 | * edma_start - start dma on a channel |
| 1250 | * @channel: channel being activated |
| 1251 | * |
| 1252 | * Channels with event associations will be triggered by their hardware |
| 1253 | * events, and channels without such associations will be triggered by |
| 1254 | * software. (At this writing there is no interface for using software |
| 1255 | * triggers except with channels that don't support hardware triggers.) |
| 1256 | * |
| 1257 | * Returns zero on success, else negative errno. |
| 1258 | */ |
| 1259 | int edma_start(unsigned channel) |
| 1260 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1261 | unsigned ctlr; |
| 1262 | |
| 1263 | ctlr = EDMA_CTLR(channel); |
| 1264 | channel = EDMA_CHAN_SLOT(channel); |
| 1265 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1266 | if (channel < edma_cc[ctlr]->num_channels) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1267 | int j = channel >> 5; |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 1268 | unsigned int mask = BIT(channel & 0x1f); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1269 | |
| 1270 | /* EDMA channels without event association */ |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1271 | if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1272 | pr_debug("EDMA: ESR%d %08x\n", j, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1273 | edma_shadow0_read_array(ctlr, SH_ESR, j)); |
| 1274 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1275 | return 0; |
| 1276 | } |
| 1277 | |
| 1278 | /* EDMA channel with event association */ |
| 1279 | pr_debug("EDMA: ER%d %08x\n", j, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1280 | edma_shadow0_read_array(ctlr, SH_ER, j)); |
Brian Niebuhr | bb17ef1 | 2010-03-09 16:48:03 -0600 | [diff] [blame] | 1281 | /* Clear any pending event or error */ |
| 1282 | edma_write_array(ctlr, EDMA_ECR, j, mask); |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1283 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1284 | /* Clear any SER */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1285 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
| 1286 | edma_shadow0_write_array(ctlr, SH_EESR, j, mask); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1287 | pr_debug("EDMA: EER%d %08x\n", j, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1288 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1289 | return 0; |
| 1290 | } |
| 1291 | |
| 1292 | return -EINVAL; |
| 1293 | } |
| 1294 | EXPORT_SYMBOL(edma_start); |
| 1295 | |
| 1296 | /** |
| 1297 | * edma_stop - stops dma on the channel passed |
| 1298 | * @channel: channel being deactivated |
| 1299 | * |
| 1300 | * When @lch is a channel, any active transfer is paused and |
| 1301 | * all pending hardware events are cleared. The current transfer |
| 1302 | * may not be resumed, and the channel's Parameter RAM should be |
| 1303 | * reinitialized before being reused. |
| 1304 | */ |
| 1305 | void edma_stop(unsigned channel) |
| 1306 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1307 | unsigned ctlr; |
| 1308 | |
| 1309 | ctlr = EDMA_CTLR(channel); |
| 1310 | channel = EDMA_CHAN_SLOT(channel); |
| 1311 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1312 | if (channel < edma_cc[ctlr]->num_channels) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1313 | int j = channel >> 5; |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 1314 | unsigned int mask = BIT(channel & 0x1f); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1315 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1316 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); |
| 1317 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); |
| 1318 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
| 1319 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1320 | |
| 1321 | pr_debug("EDMA: EER%d %08x\n", j, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1322 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1323 | |
| 1324 | /* REVISIT: consider guarding against inappropriate event |
| 1325 | * chaining by overwriting with dummy_paramset. |
| 1326 | */ |
| 1327 | } |
| 1328 | } |
| 1329 | EXPORT_SYMBOL(edma_stop); |
| 1330 | |
| 1331 | /****************************************************************************** |
| 1332 | * |
| 1333 | * It cleans ParamEntry qand bring back EDMA to initial state if media has |
| 1334 | * been removed before EDMA has finished.It is usedful for removable media. |
| 1335 | * Arguments: |
| 1336 | * ch_no - channel no |
| 1337 | * |
| 1338 | * Return: zero on success, or corresponding error no on failure |
| 1339 | * |
| 1340 | * FIXME this should not be needed ... edma_stop() should suffice. |
| 1341 | * |
| 1342 | *****************************************************************************/ |
| 1343 | |
| 1344 | void edma_clean_channel(unsigned channel) |
| 1345 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1346 | unsigned ctlr; |
| 1347 | |
| 1348 | ctlr = EDMA_CTLR(channel); |
| 1349 | channel = EDMA_CHAN_SLOT(channel); |
| 1350 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1351 | if (channel < edma_cc[ctlr]->num_channels) { |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1352 | int j = (channel >> 5); |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 1353 | unsigned int mask = BIT(channel & 0x1f); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1354 | |
| 1355 | pr_debug("EDMA: EMR%d %08x\n", j, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1356 | edma_read_array(ctlr, EDMA_EMR, j)); |
| 1357 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1358 | /* Clear the corresponding EMR bits */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1359 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1360 | /* Clear any SER */ |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1361 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 1362 | edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1363 | } |
| 1364 | } |
| 1365 | EXPORT_SYMBOL(edma_clean_channel); |
| 1366 | |
| 1367 | /* |
| 1368 | * edma_clear_event - clear an outstanding event on the DMA channel |
| 1369 | * Arguments: |
| 1370 | * channel - channel number |
| 1371 | */ |
| 1372 | void edma_clear_event(unsigned channel) |
| 1373 | { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1374 | unsigned ctlr; |
| 1375 | |
| 1376 | ctlr = EDMA_CTLR(channel); |
| 1377 | channel = EDMA_CHAN_SLOT(channel); |
| 1378 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1379 | if (channel >= edma_cc[ctlr]->num_channels) |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1380 | return; |
| 1381 | if (channel < 32) |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 1382 | edma_write(ctlr, EDMA_ECR, BIT(channel)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1383 | else |
Sekhar Nori | d78a949 | 2010-05-10 12:41:18 +0530 | [diff] [blame] | 1384 | edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1385 | } |
| 1386 | EXPORT_SYMBOL(edma_clear_event); |
| 1387 | |
| 1388 | /*-----------------------------------------------------------------------*/ |
| 1389 | |
| 1390 | static int __init edma_probe(struct platform_device *pdev) |
| 1391 | { |
Sekhar Nori | bc3ac9f | 2010-06-29 11:35:12 +0530 | [diff] [blame] | 1392 | struct edma_soc_info **info = pdev->dev.platform_data; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1393 | const s8 (*queue_priority_mapping)[2]; |
| 1394 | const s8 (*queue_tc_mapping)[2]; |
Rajashekhara, Sudhakar | 90bd4e6 | 2010-06-29 11:35:13 +0530 | [diff] [blame] | 1395 | int i, j, off, ln, found = 0; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1396 | int status = -1; |
Rajashekhara, Sudhakar | 90bd4e6 | 2010-06-29 11:35:13 +0530 | [diff] [blame] | 1397 | const s16 (*rsv_chans)[2]; |
| 1398 | const s16 (*rsv_slots)[2]; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1399 | int irq[EDMA_MAX_CC] = {0, 0}; |
| 1400 | int err_irq[EDMA_MAX_CC] = {0, 0}; |
| 1401 | struct resource *r[EDMA_MAX_CC] = {NULL}; |
| 1402 | resource_size_t len[EDMA_MAX_CC]; |
| 1403 | char res_name[10]; |
| 1404 | char irq_name[10]; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1405 | |
| 1406 | if (!info) |
| 1407 | return -ENODEV; |
| 1408 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1409 | for (j = 0; j < EDMA_MAX_CC; j++) { |
| 1410 | sprintf(res_name, "edma_cc%d", j); |
| 1411 | r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1412 | res_name); |
Sekhar Nori | bc3ac9f | 2010-06-29 11:35:12 +0530 | [diff] [blame] | 1413 | if (!r[j] || !info[j]) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1414 | if (found) |
| 1415 | break; |
| 1416 | else |
| 1417 | return -ENODEV; |
Sekhar Nori | 243bc65 | 2010-05-04 14:11:36 +0530 | [diff] [blame] | 1418 | } else { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1419 | found = 1; |
Sekhar Nori | 243bc65 | 2010-05-04 14:11:36 +0530 | [diff] [blame] | 1420 | } |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1421 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1422 | len[j] = resource_size(r[j]); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1423 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1424 | r[j] = request_mem_region(r[j]->start, len[j], |
| 1425 | dev_name(&pdev->dev)); |
| 1426 | if (!r[j]) { |
| 1427 | status = -EBUSY; |
| 1428 | goto fail1; |
| 1429 | } |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1430 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1431 | edmacc_regs_base[j] = ioremap(r[j]->start, len[j]); |
| 1432 | if (!edmacc_regs_base[j]) { |
| 1433 | status = -EBUSY; |
| 1434 | goto fail1; |
| 1435 | } |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1436 | |
Thomas Meyer | 902532d | 2011-08-06 13:26:13 +0200 | [diff] [blame] | 1437 | edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1438 | if (!edma_cc[j]) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1439 | status = -ENOMEM; |
| 1440 | goto fail1; |
| 1441 | } |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1442 | |
Sekhar Nori | bc3ac9f | 2010-06-29 11:35:12 +0530 | [diff] [blame] | 1443 | edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1444 | EDMA_MAX_DMACH); |
Sekhar Nori | bc3ac9f | 2010-06-29 11:35:12 +0530 | [diff] [blame] | 1445 | edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot, |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1446 | EDMA_MAX_PARAMENTRY); |
Sekhar Nori | bc3ac9f | 2010-06-29 11:35:12 +0530 | [diff] [blame] | 1447 | edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc, |
| 1448 | EDMA_MAX_CC); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1449 | |
Sekhar Nori | bc3ac9f | 2010-06-29 11:35:12 +0530 | [diff] [blame] | 1450 | edma_cc[j]->default_queue = info[j]->default_queue; |
Sandeep Paulraj | a0f0202 | 2009-07-27 09:57:07 -0400 | [diff] [blame] | 1451 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1452 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", |
| 1453 | edmacc_regs_base[j]); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1454 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1455 | for (i = 0; i < edma_cc[j]->num_slots; i++) |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1456 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), |
| 1457 | &dummy_paramset, PARM_SIZE); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1458 | |
Sudhakar Rajashekhara | f900d55 | 2010-01-06 17:29:49 +0530 | [diff] [blame] | 1459 | /* Mark all channels as unused */ |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1460 | memset(edma_cc[j]->edma_unused, 0xff, |
| 1461 | sizeof(edma_cc[j]->edma_unused)); |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1462 | |
Rajashekhara, Sudhakar | 90bd4e6 | 2010-06-29 11:35:13 +0530 | [diff] [blame] | 1463 | if (info[j]->rsv) { |
| 1464 | |
| 1465 | /* Clear the reserved channels in unused list */ |
| 1466 | rsv_chans = info[j]->rsv->rsv_chans; |
| 1467 | if (rsv_chans) { |
| 1468 | for (i = 0; rsv_chans[i][0] != -1; i++) { |
| 1469 | off = rsv_chans[i][0]; |
| 1470 | ln = rsv_chans[i][1]; |
| 1471 | clear_bits(off, ln, |
| 1472 | edma_cc[j]->edma_unused); |
| 1473 | } |
| 1474 | } |
| 1475 | |
| 1476 | /* Set the reserved slots in inuse list */ |
| 1477 | rsv_slots = info[j]->rsv->rsv_slots; |
| 1478 | if (rsv_slots) { |
| 1479 | for (i = 0; rsv_slots[i][0] != -1; i++) { |
| 1480 | off = rsv_slots[i][0]; |
| 1481 | ln = rsv_slots[i][1]; |
| 1482 | set_bits(off, ln, |
| 1483 | edma_cc[j]->edma_inuse); |
| 1484 | } |
| 1485 | } |
| 1486 | } |
| 1487 | |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1488 | sprintf(irq_name, "edma%d", j); |
| 1489 | irq[j] = platform_get_irq_byname(pdev, irq_name); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1490 | edma_cc[j]->irq_res_start = irq[j]; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1491 | status = request_irq(irq[j], dma_irq_handler, 0, "edma", |
| 1492 | &pdev->dev); |
| 1493 | if (status < 0) { |
| 1494 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", |
| 1495 | irq[j], status); |
| 1496 | goto fail; |
| 1497 | } |
| 1498 | |
| 1499 | sprintf(irq_name, "edma%d_err", j); |
| 1500 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1501 | edma_cc[j]->irq_res_end = err_irq[j]; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1502 | status = request_irq(err_irq[j], dma_ccerr_handler, 0, |
| 1503 | "edma_error", &pdev->dev); |
| 1504 | if (status < 0) { |
| 1505 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", |
| 1506 | err_irq[j], status); |
| 1507 | goto fail; |
| 1508 | } |
| 1509 | |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1510 | for (i = 0; i < edma_cc[j]->num_channels; i++) |
Heiko Schocher | 0b7580b | 2012-01-19 08:05:21 +0100 | [diff] [blame] | 1511 | map_dmach_queue(j, i, info[j]->default_queue); |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1512 | |
Sekhar Nori | bc3ac9f | 2010-06-29 11:35:12 +0530 | [diff] [blame] | 1513 | queue_tc_mapping = info[j]->queue_tc_mapping; |
| 1514 | queue_priority_mapping = info[j]->queue_priority_mapping; |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1515 | |
| 1516 | /* Event queue to TC mapping */ |
| 1517 | for (i = 0; queue_tc_mapping[i][0] != -1; i++) |
| 1518 | map_queue_tc(j, queue_tc_mapping[i][0], |
| 1519 | queue_tc_mapping[i][1]); |
| 1520 | |
| 1521 | /* Event queue priority mapping */ |
| 1522 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) |
| 1523 | assign_priority_to_queue(j, |
| 1524 | queue_priority_mapping[i][0], |
| 1525 | queue_priority_mapping[i][1]); |
| 1526 | |
| 1527 | /* Map the channel to param entry if channel mapping logic |
| 1528 | * exist |
| 1529 | */ |
| 1530 | if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) |
| 1531 | map_dmach_param(j); |
| 1532 | |
Sekhar Nori | bc3ac9f | 2010-06-29 11:35:12 +0530 | [diff] [blame] | 1533 | for (i = 0; i < info[j]->n_region; i++) { |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1534 | edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); |
| 1535 | edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); |
| 1536 | edma_write_array(j, EDMA_QRAE, i, 0x0); |
| 1537 | } |
Sudhakar Rajashekhara | 2d51750 | 2010-01-06 17:28:44 +0530 | [diff] [blame] | 1538 | arch_num_cc++; |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1539 | } |
| 1540 | |
| 1541 | if (tc_errs_handled) { |
| 1542 | status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0, |
| 1543 | "edma_tc0", &pdev->dev); |
| 1544 | if (status < 0) { |
| 1545 | dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n", |
| 1546 | IRQ_TCERRINT0, status); |
| 1547 | return status; |
| 1548 | } |
| 1549 | status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0, |
| 1550 | "edma_tc1", &pdev->dev); |
| 1551 | if (status < 0) { |
| 1552 | dev_dbg(&pdev->dev, "request_irq %d --> %d\n", |
| 1553 | IRQ_TCERRINT, status); |
| 1554 | return status; |
| 1555 | } |
| 1556 | } |
| 1557 | |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1558 | return 0; |
| 1559 | |
| 1560 | fail: |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1561 | for (i = 0; i < EDMA_MAX_CC; i++) { |
| 1562 | if (err_irq[i]) |
| 1563 | free_irq(err_irq[i], &pdev->dev); |
| 1564 | if (irq[i]) |
| 1565 | free_irq(irq[i], &pdev->dev); |
| 1566 | } |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1567 | fail1: |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1568 | for (i = 0; i < EDMA_MAX_CC; i++) { |
| 1569 | if (r[i]) |
| 1570 | release_mem_region(r[i]->start, len[i]); |
| 1571 | if (edmacc_regs_base[i]) |
| 1572 | iounmap(edmacc_regs_base[i]); |
Sekhar Nori | 3f68b98 | 2010-05-04 14:11:35 +0530 | [diff] [blame] | 1573 | kfree(edma_cc[i]); |
Sudhakar Rajashekhara | 60902a2 | 2009-05-21 07:41:35 -0400 | [diff] [blame] | 1574 | } |
Kevin Hilman | a4768d2 | 2009-04-14 07:18:14 -0500 | [diff] [blame] | 1575 | return status; |
| 1576 | } |
| 1577 | |
| 1578 | |
| 1579 | static struct platform_driver edma_driver = { |
| 1580 | .driver.name = "edma", |
| 1581 | }; |
| 1582 | |
| 1583 | static int __init edma_init(void) |
| 1584 | { |
| 1585 | return platform_driver_probe(&edma_driver, edma_probe); |
| 1586 | } |
| 1587 | arch_initcall(edma_init); |
| 1588 | |