Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1 | /* |
| 2 | * arch/powerpc/kernel/mpic.c |
| 3 | * |
| 4 | * Driver for interrupt controllers following the OpenPIC standard, the |
| 5 | * common implementation beeing IBM's MPIC. This driver also can deal |
| 6 | * with various broken implementations of this HW. |
| 7 | * |
| 8 | * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. |
Scott Wood | 22d168c | 2011-03-24 16:43:54 -0500 | [diff] [blame] | 9 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 10 | * |
| 11 | * This file is subject to the terms and conditions of the GNU General Public |
| 12 | * License. See the file COPYING in the main directory of this archive |
| 13 | * for more details. |
| 14 | */ |
| 15 | |
| 16 | #undef DEBUG |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 17 | #undef DEBUG_IPI |
| 18 | #undef DEBUG_IRQ |
| 19 | #undef DEBUG_LOW |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 20 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 21 | #include <linux/types.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/irq.h> |
| 25 | #include <linux/smp.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/bootmem.h> |
| 28 | #include <linux/spinlock.h> |
| 29 | #include <linux/pci.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 31 | #include <linux/syscore_ops.h> |
Christian Dietrich | 7646223 | 2011-06-04 05:36:54 +0000 | [diff] [blame] | 32 | #include <linux/ratelimit.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 33 | |
| 34 | #include <asm/ptrace.h> |
| 35 | #include <asm/signal.h> |
| 36 | #include <asm/io.h> |
| 37 | #include <asm/pgtable.h> |
| 38 | #include <asm/irq.h> |
| 39 | #include <asm/machdep.h> |
| 40 | #include <asm/mpic.h> |
| 41 | #include <asm/smp.h> |
| 42 | |
Michael Ellerman | a7de7c7 | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 43 | #include "mpic.h" |
| 44 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 45 | #ifdef DEBUG |
| 46 | #define DBG(fmt...) printk(fmt) |
| 47 | #else |
| 48 | #define DBG(fmt...) |
| 49 | #endif |
| 50 | |
| 51 | static struct mpic *mpics; |
| 52 | static struct mpic *mpic_primary; |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 53 | static DEFINE_RAW_SPINLOCK(mpic_lock); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 54 | |
Paul Mackerras | c0c0d99 | 2005-10-01 13:49:08 +1000 | [diff] [blame] | 55 | #ifdef CONFIG_PPC32 /* XXX for now */ |
Andy Whitcroft | e40c7f0 | 2005-11-29 19:25:54 +0000 | [diff] [blame] | 56 | #ifdef CONFIG_IRQ_ALL_CPUS |
| 57 | #define distribute_irqs (1) |
| 58 | #else |
| 59 | #define distribute_irqs (0) |
| 60 | #endif |
Paul Mackerras | c0c0d99 | 2005-10-01 13:49:08 +1000 | [diff] [blame] | 61 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 62 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 63 | #ifdef CONFIG_MPIC_WEIRD |
| 64 | static u32 mpic_infos[][MPIC_IDX_END] = { |
| 65 | [0] = { /* Original OpenPIC compatible MPIC */ |
| 66 | MPIC_GREG_BASE, |
| 67 | MPIC_GREG_FEATURE_0, |
| 68 | MPIC_GREG_GLOBAL_CONF_0, |
| 69 | MPIC_GREG_VENDOR_ID, |
| 70 | MPIC_GREG_IPI_VECTOR_PRI_0, |
| 71 | MPIC_GREG_IPI_STRIDE, |
| 72 | MPIC_GREG_SPURIOUS, |
| 73 | MPIC_GREG_TIMER_FREQ, |
| 74 | |
| 75 | MPIC_TIMER_BASE, |
| 76 | MPIC_TIMER_STRIDE, |
| 77 | MPIC_TIMER_CURRENT_CNT, |
| 78 | MPIC_TIMER_BASE_CNT, |
| 79 | MPIC_TIMER_VECTOR_PRI, |
| 80 | MPIC_TIMER_DESTINATION, |
| 81 | |
| 82 | MPIC_CPU_BASE, |
| 83 | MPIC_CPU_STRIDE, |
| 84 | MPIC_CPU_IPI_DISPATCH_0, |
| 85 | MPIC_CPU_IPI_DISPATCH_STRIDE, |
| 86 | MPIC_CPU_CURRENT_TASK_PRI, |
| 87 | MPIC_CPU_WHOAMI, |
| 88 | MPIC_CPU_INTACK, |
| 89 | MPIC_CPU_EOI, |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 90 | MPIC_CPU_MCACK, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 91 | |
| 92 | MPIC_IRQ_BASE, |
| 93 | MPIC_IRQ_STRIDE, |
| 94 | MPIC_IRQ_VECTOR_PRI, |
| 95 | MPIC_VECPRI_VECTOR_MASK, |
| 96 | MPIC_VECPRI_POLARITY_POSITIVE, |
| 97 | MPIC_VECPRI_POLARITY_NEGATIVE, |
| 98 | MPIC_VECPRI_SENSE_LEVEL, |
| 99 | MPIC_VECPRI_SENSE_EDGE, |
| 100 | MPIC_VECPRI_POLARITY_MASK, |
| 101 | MPIC_VECPRI_SENSE_MASK, |
| 102 | MPIC_IRQ_DESTINATION |
| 103 | }, |
| 104 | [1] = { /* Tsi108/109 PIC */ |
| 105 | TSI108_GREG_BASE, |
| 106 | TSI108_GREG_FEATURE_0, |
| 107 | TSI108_GREG_GLOBAL_CONF_0, |
| 108 | TSI108_GREG_VENDOR_ID, |
| 109 | TSI108_GREG_IPI_VECTOR_PRI_0, |
| 110 | TSI108_GREG_IPI_STRIDE, |
| 111 | TSI108_GREG_SPURIOUS, |
| 112 | TSI108_GREG_TIMER_FREQ, |
| 113 | |
| 114 | TSI108_TIMER_BASE, |
| 115 | TSI108_TIMER_STRIDE, |
| 116 | TSI108_TIMER_CURRENT_CNT, |
| 117 | TSI108_TIMER_BASE_CNT, |
| 118 | TSI108_TIMER_VECTOR_PRI, |
| 119 | TSI108_TIMER_DESTINATION, |
| 120 | |
| 121 | TSI108_CPU_BASE, |
| 122 | TSI108_CPU_STRIDE, |
| 123 | TSI108_CPU_IPI_DISPATCH_0, |
| 124 | TSI108_CPU_IPI_DISPATCH_STRIDE, |
| 125 | TSI108_CPU_CURRENT_TASK_PRI, |
| 126 | TSI108_CPU_WHOAMI, |
| 127 | TSI108_CPU_INTACK, |
| 128 | TSI108_CPU_EOI, |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 129 | TSI108_CPU_MCACK, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 130 | |
| 131 | TSI108_IRQ_BASE, |
| 132 | TSI108_IRQ_STRIDE, |
| 133 | TSI108_IRQ_VECTOR_PRI, |
| 134 | TSI108_VECPRI_VECTOR_MASK, |
| 135 | TSI108_VECPRI_POLARITY_POSITIVE, |
| 136 | TSI108_VECPRI_POLARITY_NEGATIVE, |
| 137 | TSI108_VECPRI_SENSE_LEVEL, |
| 138 | TSI108_VECPRI_SENSE_EDGE, |
| 139 | TSI108_VECPRI_POLARITY_MASK, |
| 140 | TSI108_VECPRI_SENSE_MASK, |
| 141 | TSI108_IRQ_DESTINATION |
| 142 | }, |
| 143 | }; |
| 144 | |
| 145 | #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name] |
| 146 | |
| 147 | #else /* CONFIG_MPIC_WEIRD */ |
| 148 | |
| 149 | #define MPIC_INFO(name) MPIC_##name |
| 150 | |
| 151 | #endif /* CONFIG_MPIC_WEIRD */ |
| 152 | |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 153 | static inline unsigned int mpic_processor_id(struct mpic *mpic) |
| 154 | { |
| 155 | unsigned int cpu = 0; |
| 156 | |
Kyle Moffett | be8bec5 | 2011-12-02 06:28:03 +0000 | [diff] [blame] | 157 | if (!(mpic->flags & MPIC_SECONDARY)) |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 158 | cpu = hard_smp_processor_id(); |
| 159 | |
| 160 | return cpu; |
| 161 | } |
| 162 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 163 | /* |
| 164 | * Register accessor functions |
| 165 | */ |
| 166 | |
| 167 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 168 | static inline u32 _mpic_read(enum mpic_reg_type type, |
| 169 | struct mpic_reg_bank *rb, |
| 170 | unsigned int reg) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 171 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 172 | switch(type) { |
| 173 | #ifdef CONFIG_PPC_DCR |
| 174 | case mpic_access_dcr: |
Michael Ellerman | 83f34df | 2007-10-15 19:34:36 +1000 | [diff] [blame] | 175 | return dcr_read(rb->dhost, reg); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 176 | #endif |
| 177 | case mpic_access_mmio_be: |
| 178 | return in_be32(rb->base + (reg >> 2)); |
| 179 | case mpic_access_mmio_le: |
| 180 | default: |
| 181 | return in_le32(rb->base + (reg >> 2)); |
| 182 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 183 | } |
| 184 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 185 | static inline void _mpic_write(enum mpic_reg_type type, |
| 186 | struct mpic_reg_bank *rb, |
| 187 | unsigned int reg, u32 value) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 188 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 189 | switch(type) { |
| 190 | #ifdef CONFIG_PPC_DCR |
| 191 | case mpic_access_dcr: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 192 | dcr_write(rb->dhost, reg, value); |
| 193 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 194 | #endif |
| 195 | case mpic_access_mmio_be: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 196 | out_be32(rb->base + (reg >> 2), value); |
| 197 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 198 | case mpic_access_mmio_le: |
| 199 | default: |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 200 | out_le32(rb->base + (reg >> 2), value); |
| 201 | break; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 202 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) |
| 206 | { |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 207 | enum mpic_reg_type type = mpic->reg_type; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 208 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
| 209 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 210 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 211 | if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) |
| 212 | type = mpic_access_mmio_be; |
| 213 | return _mpic_read(type, &mpic->gregs, offset); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) |
| 217 | { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 218 | unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) + |
| 219 | (ipi * MPIC_INFO(GREG_IPI_STRIDE)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 220 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 221 | _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 222 | } |
| 223 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 224 | static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) |
| 225 | { |
| 226 | unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + |
| 227 | ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); |
| 228 | |
| 229 | if (tm >= 4) |
| 230 | offset += 0x1000 / 4; |
| 231 | |
| 232 | return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); |
| 233 | } |
| 234 | |
| 235 | static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) |
| 236 | { |
| 237 | unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) + |
| 238 | ((tm & 3) * MPIC_INFO(TIMER_STRIDE)); |
| 239 | |
| 240 | if (tm >= 4) |
| 241 | offset += 0x1000 / 4; |
| 242 | |
| 243 | _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); |
| 244 | } |
| 245 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 246 | static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) |
| 247 | { |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 248 | unsigned int cpu = mpic_processor_id(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 249 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 250 | return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 251 | } |
| 252 | |
| 253 | static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) |
| 254 | { |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 255 | unsigned int cpu = mpic_processor_id(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 256 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 257 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) |
| 261 | { |
| 262 | unsigned int isu = src_no >> mpic->isu_shift; |
| 263 | unsigned int idx = src_no & mpic->isu_mask; |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 264 | unsigned int val; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 265 | |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 266 | val = _mpic_read(mpic->reg_type, &mpic->isus[isu], |
| 267 | reg + (idx * MPIC_INFO(IRQ_STRIDE))); |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 268 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
| 269 | if (reg == 0) |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 270 | val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) | |
| 271 | mpic->isu_reg0_shadow[src_no]; |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 272 | #endif |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 273 | return val; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, |
| 277 | unsigned int reg, u32 value) |
| 278 | { |
| 279 | unsigned int isu = src_no >> mpic->isu_shift; |
| 280 | unsigned int idx = src_no & mpic->isu_mask; |
| 281 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 282 | _mpic_write(mpic->reg_type, &mpic->isus[isu], |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 283 | reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 284 | |
| 285 | #ifdef CONFIG_MPIC_BROKEN_REGREAD |
| 286 | if (reg == 0) |
Michael Ellerman | 11a6b29 | 2009-07-05 16:08:52 +0000 | [diff] [blame] | 287 | mpic->isu_reg0_shadow[src_no] = |
| 288 | value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY); |
Olof Johansson | 0d72ba9 | 2007-09-08 05:13:19 +1000 | [diff] [blame] | 289 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 290 | } |
| 291 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 292 | #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r)) |
| 293 | #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 294 | #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) |
| 295 | #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 296 | #define mpic_tm_read(i) _mpic_tm_read(mpic,(i)) |
| 297 | #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 298 | #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) |
| 299 | #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) |
| 300 | #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) |
| 301 | #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) |
| 302 | |
| 303 | |
| 304 | /* |
| 305 | * Low level utility functions |
| 306 | */ |
| 307 | |
| 308 | |
Becky Bruce | c51a3fdc | 2008-01-14 20:56:18 -0600 | [diff] [blame] | 309 | static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 310 | struct mpic_reg_bank *rb, unsigned int offset, |
| 311 | unsigned int size) |
| 312 | { |
| 313 | rb->base = ioremap(phys_addr + offset, size); |
| 314 | BUG_ON(rb->base == NULL); |
| 315 | } |
| 316 | |
| 317 | #ifdef CONFIG_PPC_DCR |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 318 | static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 319 | unsigned int offset, unsigned int size) |
| 320 | { |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 321 | phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0); |
Kyle Moffett | e62b760 | 2011-12-02 06:28:04 +0000 | [diff] [blame] | 322 | rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 323 | BUG_ON(!DCR_MAP_OK(rb->dhost)); |
| 324 | } |
| 325 | |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 326 | static inline void mpic_map(struct mpic *mpic, |
Benjamin Herrenschmidt | 5a2642f | 2009-06-22 16:47:59 +0000 | [diff] [blame] | 327 | phys_addr_t phys_addr, struct mpic_reg_bank *rb, |
| 328 | unsigned int offset, unsigned int size) |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 329 | { |
| 330 | if (mpic->flags & MPIC_USES_DCR) |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 331 | _mpic_map_dcr(mpic, rb, offset, size); |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 332 | else |
| 333 | _mpic_map_mmio(mpic, phys_addr, rb, offset, size); |
| 334 | } |
| 335 | #else /* CONFIG_PPC_DCR */ |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 336 | #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s) |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 337 | #endif /* !CONFIG_PPC_DCR */ |
| 338 | |
| 339 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 340 | |
| 341 | /* Check if we have one of those nice broken MPICs with a flipped endian on |
| 342 | * reads from IPI registers |
| 343 | */ |
| 344 | static void __init mpic_test_broken_ipi(struct mpic *mpic) |
| 345 | { |
| 346 | u32 r; |
| 347 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 348 | mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); |
| 349 | r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 350 | |
| 351 | if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { |
| 352 | printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); |
| 353 | mpic->flags |= MPIC_BROKEN_IPI; |
| 354 | } |
| 355 | } |
| 356 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 357 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 358 | |
| 359 | /* Test if an interrupt is sourced from HyperTransport (used on broken U3s) |
| 360 | * to force the edge setting on the MPIC and do the ack workaround. |
| 361 | */ |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 362 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 363 | { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 364 | if (source >= 128 || !mpic->fixups) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 365 | return 0; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 366 | return mpic->fixups[source].base != NULL; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 367 | } |
| 368 | |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 369 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 370 | static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 371 | { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 372 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 373 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 374 | if (fixup->applebase) { |
| 375 | unsigned int soff = (fixup->index >> 3) & ~3; |
| 376 | unsigned int mask = 1U << (fixup->index & 0x1f); |
| 377 | writel(mask, fixup->applebase + soff); |
| 378 | } else { |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 379 | raw_spin_lock(&mpic->fixup_lock); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 380 | writeb(0x11 + 2 * fixup->index, fixup->base + 2); |
| 381 | writel(fixup->data, fixup->base + 4); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 382 | raw_spin_unlock(&mpic->fixup_lock); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 383 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 384 | } |
| 385 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 386 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 387 | bool level) |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 388 | { |
| 389 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
| 390 | unsigned long flags; |
| 391 | u32 tmp; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 392 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 393 | if (fixup->base == NULL) |
| 394 | return; |
| 395 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 396 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
| 397 | source, fixup->index); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 398 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 399 | /* Enable and configure */ |
| 400 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 401 | tmp = readl(fixup->base + 4); |
| 402 | tmp &= ~(0x23U); |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 403 | if (level) |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 404 | tmp |= 0x22; |
| 405 | writel(tmp, fixup->base + 4); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 406 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 407 | |
| 408 | #ifdef CONFIG_PM |
| 409 | /* use the lowest bit inverted to the actual HW, |
| 410 | * set if this fixup was enabled, clear otherwise */ |
| 411 | mpic->save_data[source].fixup_data = tmp | 1; |
| 412 | #endif |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 413 | } |
| 414 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 415 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 416 | { |
| 417 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
| 418 | unsigned long flags; |
| 419 | u32 tmp; |
| 420 | |
| 421 | if (fixup->base == NULL) |
| 422 | return; |
| 423 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 424 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 425 | |
| 426 | /* Disable */ |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 427 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 428 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 429 | tmp = readl(fixup->base + 4); |
Segher Boessenkool | 72b1381 | 2006-02-17 11:25:42 +0100 | [diff] [blame] | 430 | tmp |= 1; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 431 | writel(tmp, fixup->base + 4); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 432 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 433 | |
| 434 | #ifdef CONFIG_PM |
| 435 | /* use the lowest bit inverted to the actual HW, |
| 436 | * set if this fixup was enabled, clear otherwise */ |
| 437 | mpic->save_data[source].fixup_data = tmp & ~1; |
| 438 | #endif |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 439 | } |
| 440 | |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 441 | #ifdef CONFIG_PCI_MSI |
| 442 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, |
| 443 | unsigned int devfn) |
| 444 | { |
| 445 | u8 __iomem *base; |
| 446 | u8 pos, flags; |
| 447 | u64 addr = 0; |
| 448 | |
| 449 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
| 450 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { |
| 451 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); |
| 452 | if (id == PCI_CAP_ID_HT) { |
| 453 | id = readb(devbase + pos + 3); |
| 454 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING) |
| 455 | break; |
| 456 | } |
| 457 | } |
| 458 | |
| 459 | if (pos == 0) |
| 460 | return; |
| 461 | |
| 462 | base = devbase + pos; |
| 463 | |
| 464 | flags = readb(base + HT_MSI_FLAGS); |
| 465 | if (!(flags & HT_MSI_FLAGS_FIXED)) { |
| 466 | addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK; |
| 467 | addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32); |
| 468 | } |
| 469 | |
Ingo Molnar | fe33332 | 2009-01-06 14:26:03 +0000 | [diff] [blame] | 470 | printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 471 | PCI_SLOT(devfn), PCI_FUNC(devfn), |
| 472 | flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr); |
| 473 | |
| 474 | if (!(flags & HT_MSI_FLAGS_ENABLE)) |
| 475 | writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS); |
| 476 | } |
| 477 | #else |
| 478 | static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, |
| 479 | unsigned int devfn) |
| 480 | { |
| 481 | return; |
| 482 | } |
| 483 | #endif |
| 484 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 485 | static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, |
| 486 | unsigned int devfn, u32 vdid) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 487 | { |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 488 | int i, irq, n; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 489 | u8 __iomem *base; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 490 | u32 tmp; |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 491 | u8 pos; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 492 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 493 | for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0; |
| 494 | pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) { |
| 495 | u8 id = readb(devbase + pos + PCI_CAP_LIST_ID); |
Brice Goglin | 46ff346 | 2006-08-31 01:55:24 -0400 | [diff] [blame] | 496 | if (id == PCI_CAP_ID_HT) { |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 497 | id = readb(devbase + pos + 3); |
Michael Ellerman | beb7cc8 | 2006-11-22 18:26:22 +1100 | [diff] [blame] | 498 | if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ) |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 499 | break; |
| 500 | } |
| 501 | } |
| 502 | if (pos == 0) |
| 503 | return; |
| 504 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 505 | base = devbase + pos; |
| 506 | writeb(0x01, base + 2); |
| 507 | n = (readl(base + 4) >> 16) & 0xff; |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 508 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 509 | printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" |
| 510 | " has %d irqs\n", |
| 511 | devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1); |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 512 | |
| 513 | for (i = 0; i <= n; i++) { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 514 | writeb(0x10 + 2 * i, base + 2); |
| 515 | tmp = readl(base + 4); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 516 | irq = (tmp >> 16) & 0xff; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 517 | DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp); |
| 518 | /* mask it , will be unmasked later */ |
| 519 | tmp |= 0x1; |
| 520 | writel(tmp, base + 4); |
| 521 | mpic->fixups[irq].index = i; |
| 522 | mpic->fixups[irq].base = base; |
| 523 | /* Apple HT PIC has a non-standard way of doing EOIs */ |
| 524 | if ((vdid & 0xffff) == 0x106b) |
| 525 | mpic->fixups[irq].applebase = devbase + 0x60; |
| 526 | else |
| 527 | mpic->fixups[irq].applebase = NULL; |
| 528 | writeb(0x11 + 2 * i, base + 2); |
| 529 | mpic->fixups[irq].data = readl(base + 4) | 0x80000000; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 530 | } |
| 531 | } |
| 532 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 533 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 534 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 535 | { |
| 536 | unsigned int devfn; |
| 537 | u8 __iomem *cfgspace; |
| 538 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 539 | printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 540 | |
| 541 | /* Allocate fixups array */ |
Anton Vorontsov | ea96025 | 2009-07-01 10:59:57 +0000 | [diff] [blame] | 542 | mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 543 | BUG_ON(mpic->fixups == NULL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 544 | |
| 545 | /* Init spinlock */ |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 546 | raw_spin_lock_init(&mpic->fixup_lock); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 547 | |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 548 | /* Map U3 config space. We assume all IO-APICs are on the primary bus |
| 549 | * so we only need to map 64kB. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 550 | */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 551 | cfgspace = ioremap(0xf2000000, 0x10000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 552 | BUG_ON(cfgspace == NULL); |
| 553 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 554 | /* Now we scan all slots. We do a very quick scan, we read the header |
| 555 | * type, vendor ID and device ID only, that's plenty enough |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 556 | */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 557 | for (devfn = 0; devfn < 0x100; devfn++) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 558 | u8 __iomem *devbase = cfgspace + (devfn << 8); |
| 559 | u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); |
| 560 | u32 l = readl(devbase + PCI_VENDOR_ID); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 561 | u16 s; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 562 | |
| 563 | DBG("devfn %x, l: %x\n", devfn, l); |
| 564 | |
| 565 | /* If no device, skip */ |
| 566 | if (l == 0xffffffff || l == 0x00000000 || |
| 567 | l == 0x0000ffff || l == 0xffff0000) |
| 568 | goto next; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 569 | /* Check if is supports capability lists */ |
| 570 | s = readw(devbase + PCI_STATUS); |
| 571 | if (!(s & PCI_STATUS_CAP_LIST)) |
| 572 | goto next; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 573 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 574 | mpic_scan_ht_pic(mpic, devbase, devfn, l); |
Michael Ellerman | 812fd1f | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 575 | mpic_scan_ht_msi(mpic, devbase, devfn); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 576 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 577 | next: |
| 578 | /* next device, if function 0 */ |
Segher Boessenkool | c4b22f2 | 2005-12-13 18:04:29 +1100 | [diff] [blame] | 579 | if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 580 | devfn += 7; |
| 581 | } |
| 582 | } |
| 583 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 584 | #else /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 585 | |
| 586 | static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) |
| 587 | { |
| 588 | return 0; |
| 589 | } |
| 590 | |
| 591 | static void __init mpic_scan_ht_pics(struct mpic *mpic) |
| 592 | { |
| 593 | } |
| 594 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 595 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 596 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 597 | /* Find an mpic associated with a given linux interrupt */ |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 598 | static struct mpic *mpic_find(unsigned int irq) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 599 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 600 | if (irq < NUM_ISA_INTERRUPTS) |
| 601 | return NULL; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 602 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 603 | return irq_get_chip_data(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 604 | } |
| 605 | |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 606 | /* Determine if the linux irq is an IPI */ |
Benjamin Herrenschmidt | 3a2b4f7 | 2012-04-19 17:29:34 +0000 | [diff] [blame] | 607 | static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src) |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 608 | { |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 609 | return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); |
| 610 | } |
| 611 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 612 | /* Determine if the linux irq is a timer */ |
Benjamin Herrenschmidt | 3a2b4f7 | 2012-04-19 17:29:34 +0000 | [diff] [blame] | 613 | static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src) |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 614 | { |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 615 | return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); |
| 616 | } |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 617 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 618 | /* Convert a cpu mask from logical to physical cpu numbers. */ |
| 619 | static inline u32 mpic_physmask(u32 cpumask) |
| 620 | { |
| 621 | int i; |
| 622 | u32 mask = 0; |
| 623 | |
Milton Miller | ebc0421 | 2011-05-10 19:28:59 +0000 | [diff] [blame] | 624 | for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 625 | mask |= (cpumask & 1) << get_hard_smp_processor_id(i); |
| 626 | return mask; |
| 627 | } |
| 628 | |
| 629 | #ifdef CONFIG_SMP |
| 630 | /* Get the mpic structure from the IPI number */ |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 631 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 632 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 633 | return irq_data_get_irq_chip_data(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 634 | } |
| 635 | #endif |
| 636 | |
| 637 | /* Get the mpic structure from the irq number */ |
| 638 | static inline struct mpic * mpic_from_irq(unsigned int irq) |
| 639 | { |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 640 | return irq_get_chip_data(irq); |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | /* Get the mpic structure from the irq data */ |
| 644 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) |
| 645 | { |
| 646 | return irq_data_get_irq_chip_data(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 647 | } |
| 648 | |
| 649 | /* Send an EOI */ |
| 650 | static inline void mpic_eoi(struct mpic *mpic) |
| 651 | { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 652 | mpic_cpu_write(MPIC_INFO(CPU_EOI), 0); |
| 653 | (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 654 | } |
| 655 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 656 | /* |
| 657 | * Linux descriptor level callbacks |
| 658 | */ |
| 659 | |
| 660 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 661 | void mpic_unmask_irq(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 662 | { |
| 663 | unsigned int loops = 100000; |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 664 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 665 | unsigned int src = irqd_to_hwirq(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 666 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 667 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 668 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 669 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
| 670 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 671 | ~MPIC_VECPRI_MASK); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 672 | /* make sure mask gets to controller before we return to user */ |
| 673 | do { |
| 674 | if (!loops--) { |
Scott Wood | 8bfc5e3 | 2011-01-17 12:10:41 +0000 | [diff] [blame] | 675 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
| 676 | __func__, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 677 | break; |
| 678 | } |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 679 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 680 | } |
| 681 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 682 | void mpic_mask_irq(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 683 | { |
| 684 | unsigned int loops = 100000; |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 685 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 686 | unsigned int src = irqd_to_hwirq(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 687 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 688 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 689 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 690 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
| 691 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 692 | MPIC_VECPRI_MASK); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 693 | |
| 694 | /* make sure mask gets to controller before we return to user */ |
| 695 | do { |
| 696 | if (!loops--) { |
Scott Wood | 8bfc5e3 | 2011-01-17 12:10:41 +0000 | [diff] [blame] | 697 | printk(KERN_ERR "%s: timeout on hwirq %u\n", |
| 698 | __func__, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 699 | break; |
| 700 | } |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 701 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 702 | } |
| 703 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 704 | void mpic_end_irq(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 705 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 706 | struct mpic *mpic = mpic_from_irq_data(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 707 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 708 | #ifdef DEBUG_IRQ |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 709 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 710 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 711 | /* We always EOI on end_irq() even for edge interrupts since that |
| 712 | * should only lower the priority, the MPIC should have properly |
| 713 | * latched another edge interrupt coming in anyway |
| 714 | */ |
| 715 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 716 | mpic_eoi(mpic); |
| 717 | } |
| 718 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 719 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 720 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 721 | static void mpic_unmask_ht_irq(struct irq_data *d) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 722 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 723 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 724 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 725 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 726 | mpic_unmask_irq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 727 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 728 | if (irqd_is_level_type(d)) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 729 | mpic_ht_end_irq(mpic, src); |
| 730 | } |
| 731 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 732 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 733 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 734 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 735 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 736 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 737 | mpic_unmask_irq(d); |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 738 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 739 | |
| 740 | return 0; |
| 741 | } |
| 742 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 743 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 744 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 745 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 746 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 747 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 748 | mpic_shutdown_ht_interrupt(mpic, src); |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 749 | mpic_mask_irq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 750 | } |
| 751 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 752 | static void mpic_end_ht_irq(struct irq_data *d) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 753 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 754 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 755 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 756 | |
| 757 | #ifdef DEBUG_IRQ |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 758 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 759 | #endif |
| 760 | /* We always EOI on end_irq() even for edge interrupts since that |
| 761 | * should only lower the priority, the MPIC should have properly |
| 762 | * latched another edge interrupt coming in anyway |
| 763 | */ |
| 764 | |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 765 | if (irqd_is_level_type(d)) |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 766 | mpic_ht_end_irq(mpic, src); |
| 767 | mpic_eoi(mpic); |
| 768 | } |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 769 | #endif /* !CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 770 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 771 | #ifdef CONFIG_SMP |
| 772 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 773 | static void mpic_unmask_ipi(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 774 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 775 | struct mpic *mpic = mpic_from_ipi(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 776 | unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 777 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 778 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 779 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
| 780 | } |
| 781 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 782 | static void mpic_mask_ipi(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 783 | { |
| 784 | /* NEVER disable an IPI... that's just plain wrong! */ |
| 785 | } |
| 786 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 787 | static void mpic_end_ipi(struct irq_data *d) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 788 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 789 | struct mpic *mpic = mpic_from_ipi(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 790 | |
| 791 | /* |
| 792 | * IPIs are marked IRQ_PER_CPU. This has the side effect of |
| 793 | * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from |
| 794 | * applying to them. We EOI them late to avoid re-entering. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 795 | */ |
| 796 | mpic_eoi(mpic); |
| 797 | } |
| 798 | |
| 799 | #endif /* CONFIG_SMP */ |
| 800 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 801 | static void mpic_unmask_tm(struct irq_data *d) |
| 802 | { |
| 803 | struct mpic *mpic = mpic_from_irq_data(d); |
| 804 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; |
| 805 | |
Dmitry Eremin-Solenikov | 77ef489 | 2011-05-30 01:56:09 +0000 | [diff] [blame] | 806 | DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 807 | mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK); |
| 808 | mpic_tm_read(src); |
| 809 | } |
| 810 | |
| 811 | static void mpic_mask_tm(struct irq_data *d) |
| 812 | { |
| 813 | struct mpic *mpic = mpic_from_irq_data(d); |
| 814 | unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; |
| 815 | |
| 816 | mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK); |
| 817 | mpic_tm_read(src); |
| 818 | } |
| 819 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 820 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
| 821 | bool force) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 822 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 823 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 824 | unsigned int src = irqd_to_hwirq(d); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 825 | |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 826 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
Yang Li | 38e1313 | 2009-12-16 20:18:11 +0000 | [diff] [blame] | 827 | int cpuid = irq_choose_cpu(cpumask); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 828 | |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 829 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
| 830 | } else { |
Milton Miller | 2a116f3 | 2011-05-10 19:29:02 +0000 | [diff] [blame] | 831 | u32 mask = cpumask_bits(cpumask)[0]; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 832 | |
Milton Miller | 2a116f3 | 2011-05-10 19:29:02 +0000 | [diff] [blame] | 833 | mask &= cpumask_bits(cpu_online_mask)[0]; |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 834 | |
| 835 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), |
Milton Miller | 2a116f3 | 2011-05-10 19:29:02 +0000 | [diff] [blame] | 836 | mpic_physmask(mask)); |
Kumar Gala | 3c10c9c | 2008-10-28 18:01:39 +0000 | [diff] [blame] | 837 | } |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 838 | |
| 839 | return 0; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 840 | } |
| 841 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 842 | static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 843 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 844 | /* Now convert sense value */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 845 | switch(type & IRQ_TYPE_SENSE_MASK) { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 846 | case IRQ_TYPE_EDGE_RISING: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 847 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
| 848 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 849 | case IRQ_TYPE_EDGE_FALLING: |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 850 | case IRQ_TYPE_EDGE_BOTH: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 851 | return MPIC_INFO(VECPRI_SENSE_EDGE) | |
| 852 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 853 | case IRQ_TYPE_LEVEL_HIGH: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 854 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
| 855 | MPIC_INFO(VECPRI_POLARITY_POSITIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 856 | case IRQ_TYPE_LEVEL_LOW: |
| 857 | default: |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 858 | return MPIC_INFO(VECPRI_SENSE_LEVEL) | |
| 859 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 860 | } |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 861 | } |
| 862 | |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 863 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 864 | { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 865 | struct mpic *mpic = mpic_from_irq_data(d); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 866 | unsigned int src = irqd_to_hwirq(d); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 867 | unsigned int vecpri, vold, vnew; |
| 868 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 869 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 870 | mpic, d->irq, src, flow_type); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 871 | |
Kyle Moffett | 5019609 | 2011-12-22 10:19:12 +0000 | [diff] [blame] | 872 | if (src >= mpic->num_sources) |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 873 | return -EINVAL; |
| 874 | |
Benjamin Herrenschmidt | 446f6d0 | 2012-04-19 17:30:57 +0000 | [diff] [blame] | 875 | vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 876 | |
Benjamin Herrenschmidt | 446f6d0 | 2012-04-19 17:30:57 +0000 | [diff] [blame] | 877 | /* We don't support "none" type */ |
| 878 | if (flow_type == IRQ_TYPE_NONE) |
| 879 | flow_type = IRQ_TYPE_DEFAULT; |
| 880 | |
| 881 | /* Default: read HW settings */ |
| 882 | if (flow_type == IRQ_TYPE_DEFAULT) { |
| 883 | switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) | |
| 884 | MPIC_INFO(VECPRI_SENSE_MASK))) { |
| 885 | case MPIC_INFO(VECPRI_SENSE_EDGE) | |
| 886 | MPIC_INFO(VECPRI_POLARITY_POSITIVE): |
| 887 | flow_type = IRQ_TYPE_EDGE_RISING; |
| 888 | break; |
| 889 | case MPIC_INFO(VECPRI_SENSE_EDGE) | |
| 890 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE): |
| 891 | flow_type = IRQ_TYPE_EDGE_FALLING; |
| 892 | break; |
| 893 | case MPIC_INFO(VECPRI_SENSE_LEVEL) | |
| 894 | MPIC_INFO(VECPRI_POLARITY_POSITIVE): |
| 895 | flow_type = IRQ_TYPE_LEVEL_HIGH; |
| 896 | break; |
| 897 | case MPIC_INFO(VECPRI_SENSE_LEVEL) | |
| 898 | MPIC_INFO(VECPRI_POLARITY_NEGATIVE): |
| 899 | flow_type = IRQ_TYPE_LEVEL_LOW; |
| 900 | break; |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | /* Apply to irq desc */ |
Thomas Gleixner | 24a3f2e | 2011-03-25 16:20:15 +0100 | [diff] [blame] | 905 | irqd_set_trigger_type(d, flow_type); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 906 | |
Benjamin Herrenschmidt | 446f6d0 | 2012-04-19 17:30:57 +0000 | [diff] [blame] | 907 | /* Apply to HW */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 908 | if (mpic_is_ht_interrupt(mpic, src)) |
| 909 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | |
| 910 | MPIC_VECPRI_SENSE_EDGE; |
| 911 | else |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 912 | vecpri = mpic_type_to_vecpri(mpic, flow_type); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 913 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 914 | vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) | |
| 915 | MPIC_INFO(VECPRI_SENSE_MASK)); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 916 | vnew |= vecpri; |
| 917 | if (vold != vnew) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 918 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 919 | |
Justin P. Mattock | e075cd7 | 2011-11-21 06:43:26 +0000 | [diff] [blame] | 920 | return IRQ_SET_MASK_OK_NOCOPY; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 921 | } |
| 922 | |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 923 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
| 924 | { |
| 925 | struct mpic *mpic = mpic_from_irq(virq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 926 | unsigned int src = virq_to_hw(virq); |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 927 | unsigned int vecpri; |
| 928 | |
| 929 | DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", |
| 930 | mpic, virq, src, vector); |
| 931 | |
Kyle Moffett | 5019609 | 2011-12-22 10:19:12 +0000 | [diff] [blame] | 932 | if (src >= mpic->num_sources) |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 933 | return; |
| 934 | |
| 935 | vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); |
| 936 | vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK); |
| 937 | vecpri |= vector; |
| 938 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
| 939 | } |
| 940 | |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 941 | void mpic_set_destination(unsigned int virq, unsigned int cpuid) |
| 942 | { |
| 943 | struct mpic *mpic = mpic_from_irq(virq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 944 | unsigned int src = virq_to_hw(virq); |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 945 | |
| 946 | DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", |
| 947 | mpic, virq, src, cpuid); |
| 948 | |
Kyle Moffett | 5019609 | 2011-12-22 10:19:12 +0000 | [diff] [blame] | 949 | if (src >= mpic->num_sources) |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 950 | return; |
| 951 | |
| 952 | mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); |
| 953 | } |
| 954 | |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 955 | static struct irq_chip mpic_irq_chip = { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 956 | .irq_mask = mpic_mask_irq, |
| 957 | .irq_unmask = mpic_unmask_irq, |
| 958 | .irq_eoi = mpic_end_irq, |
| 959 | .irq_set_type = mpic_set_irq_type, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 960 | }; |
| 961 | |
| 962 | #ifdef CONFIG_SMP |
| 963 | static struct irq_chip mpic_ipi_chip = { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 964 | .irq_mask = mpic_mask_ipi, |
| 965 | .irq_unmask = mpic_unmask_ipi, |
| 966 | .irq_eoi = mpic_end_ipi, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 967 | }; |
| 968 | #endif /* CONFIG_SMP */ |
| 969 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 970 | static struct irq_chip mpic_tm_chip = { |
| 971 | .irq_mask = mpic_mask_tm, |
| 972 | .irq_unmask = mpic_unmask_tm, |
| 973 | .irq_eoi = mpic_end_irq, |
| 974 | }; |
| 975 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 976 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 977 | static struct irq_chip mpic_irq_ht_chip = { |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 978 | .irq_startup = mpic_startup_ht_irq, |
| 979 | .irq_shutdown = mpic_shutdown_ht_irq, |
| 980 | .irq_mask = mpic_mask_irq, |
| 981 | .irq_unmask = mpic_unmask_ht_irq, |
| 982 | .irq_eoi = mpic_end_ht_irq, |
| 983 | .irq_set_type = mpic_set_irq_type, |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 984 | }; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 985 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 986 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 987 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 988 | static int mpic_host_match(struct irq_domain *h, struct device_node *node) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 989 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 990 | /* Exact match, unless mpic node is NULL */ |
Michael Ellerman | 52964f8 | 2007-08-28 18:47:54 +1000 | [diff] [blame] | 991 | return h->of_node == NULL || h->of_node == node; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 992 | } |
| 993 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 994 | static int mpic_host_map(struct irq_domain *h, unsigned int virq, |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 995 | irq_hw_number_t hw) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 996 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 997 | struct mpic *mpic = h->host_data; |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 998 | struct irq_chip *chip; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 999 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1000 | DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1001 | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1002 | if (hw == mpic->spurious_vec) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1003 | return -EINVAL; |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1004 | if (mpic->protected && test_bit(hw, mpic->protected)) |
| 1005 | return -EINVAL; |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1006 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1007 | #ifdef CONFIG_SMP |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1008 | else if (hw >= mpic->ipi_vecs[0]) { |
Kyle Moffett | be8bec5 | 2011-12-02 06:28:03 +0000 | [diff] [blame] | 1009 | WARN_ON(mpic->flags & MPIC_SECONDARY); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1010 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1011 | DBG("mpic: mapping as IPI\n"); |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 1012 | irq_set_chip_data(virq, mpic); |
| 1013 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1014 | handle_percpu_irq); |
| 1015 | return 0; |
| 1016 | } |
| 1017 | #endif /* CONFIG_SMP */ |
| 1018 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1019 | if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { |
Kyle Moffett | be8bec5 | 2011-12-02 06:28:03 +0000 | [diff] [blame] | 1020 | WARN_ON(mpic->flags & MPIC_SECONDARY); |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1021 | |
| 1022 | DBG("mpic: mapping as timer\n"); |
| 1023 | irq_set_chip_data(virq, mpic); |
| 1024 | irq_set_chip_and_handler(virq, &mpic->hc_tm, |
| 1025 | handle_fasteoi_irq); |
| 1026 | return 0; |
| 1027 | } |
| 1028 | |
Kyle Moffett | 5019609 | 2011-12-22 10:19:12 +0000 | [diff] [blame] | 1029 | if (hw >= mpic->num_sources) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1030 | return -EINVAL; |
| 1031 | |
Michael Ellerman | a7de7c7 | 2007-05-08 12:58:36 +1000 | [diff] [blame] | 1032 | mpic_msi_reserve_hwirq(mpic, hw); |
| 1033 | |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1034 | /* Default chip */ |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1035 | chip = &mpic->hc_irq; |
| 1036 | |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1037 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1038 | /* Check for HT interrupts, override vecpri */ |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1039 | if (mpic_is_ht_interrupt(mpic, hw)) |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1040 | chip = &mpic->hc_ht_irq; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1041 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1042 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1043 | DBG("mpic: mapping to irq chip @%p\n", chip); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1044 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 1045 | irq_set_chip_data(virq, mpic); |
| 1046 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1047 | |
| 1048 | /* Set default irq type */ |
Benjamin Herrenschmidt | 446f6d0 | 2012-04-19 17:30:57 +0000 | [diff] [blame] | 1049 | irq_set_irq_type(virq, IRQ_TYPE_DEFAULT); |
Benjamin Herrenschmidt | 6e99e45 | 2006-07-10 04:44:42 -0700 | [diff] [blame] | 1050 | |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1051 | /* If the MPIC was reset, then all vectors have already been |
| 1052 | * initialized. Otherwise, a per source lazy initialization |
| 1053 | * is done here. |
| 1054 | */ |
| 1055 | if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1056 | mpic_set_vector(virq, hw); |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 1057 | mpic_set_destination(virq, mpic_processor_id(mpic)); |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1058 | mpic_irq_set_priority(virq, 8); |
| 1059 | } |
| 1060 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1061 | return 0; |
| 1062 | } |
| 1063 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 1064 | static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct, |
Roman Fietze | 40d50cf | 2009-12-08 02:39:50 +0000 | [diff] [blame] | 1065 | const u32 *intspec, unsigned int intsize, |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1066 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) |
| 1067 | |
| 1068 | { |
Scott Wood | 22d168c | 2011-03-24 16:43:54 -0500 | [diff] [blame] | 1069 | struct mpic *mpic = h->host_data; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1070 | static unsigned char map_mpic_senses[4] = { |
| 1071 | IRQ_TYPE_EDGE_RISING, |
| 1072 | IRQ_TYPE_LEVEL_LOW, |
| 1073 | IRQ_TYPE_LEVEL_HIGH, |
| 1074 | IRQ_TYPE_EDGE_FALLING, |
| 1075 | }; |
| 1076 | |
| 1077 | *out_hwirq = intspec[0]; |
Scott Wood | 22d168c | 2011-03-24 16:43:54 -0500 | [diff] [blame] | 1078 | if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { |
| 1079 | /* |
| 1080 | * Freescale MPIC with extended intspec: |
| 1081 | * First two cells are as usual. Third specifies |
| 1082 | * an "interrupt type". Fourth is type-specific data. |
| 1083 | * |
| 1084 | * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt |
| 1085 | */ |
| 1086 | switch (intspec[2]) { |
| 1087 | case 0: |
| 1088 | case 1: /* no EISR/EIMR support for now, treat as shared IRQ */ |
| 1089 | break; |
| 1090 | case 2: |
| 1091 | if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) |
| 1092 | return -EINVAL; |
| 1093 | |
| 1094 | *out_hwirq = mpic->ipi_vecs[intspec[0]]; |
| 1095 | break; |
| 1096 | case 3: |
| 1097 | if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) |
| 1098 | return -EINVAL; |
| 1099 | |
| 1100 | *out_hwirq = mpic->timer_vecs[intspec[0]]; |
| 1101 | break; |
| 1102 | default: |
| 1103 | pr_debug("%s: unknown irq type %u\n", |
| 1104 | __func__, intspec[2]); |
| 1105 | return -EINVAL; |
| 1106 | } |
| 1107 | |
| 1108 | *out_flags = map_mpic_senses[intspec[1] & 3]; |
| 1109 | } else if (intsize > 1) { |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1110 | u32 mask = 0x3; |
| 1111 | |
| 1112 | /* Apple invented a new race of encoding on machines with |
| 1113 | * an HT APIC. They encode, among others, the index within |
| 1114 | * the HT APIC. We don't care about it here since thankfully, |
| 1115 | * it appears that they have the APIC already properly |
| 1116 | * configured, and thus our current fixup code that reads the |
| 1117 | * APIC config works fine. However, we still need to mask out |
| 1118 | * bits in the specifier to make sure we only get bit 0 which |
| 1119 | * is the level/edge bit (the only sense bit exposed by Apple), |
| 1120 | * as their bit 1 means something else. |
| 1121 | */ |
| 1122 | if (machine_is(powermac)) |
| 1123 | mask = 0x1; |
| 1124 | *out_flags = map_mpic_senses[intspec[1] & mask]; |
| 1125 | } else |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1126 | *out_flags = IRQ_TYPE_NONE; |
| 1127 | |
Benjamin Herrenschmidt | 06fe98e | 2006-07-10 04:44:43 -0700 | [diff] [blame] | 1128 | DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", |
| 1129 | intsize, intspec[0], intspec[1], *out_hwirq, *out_flags); |
| 1130 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1131 | return 0; |
| 1132 | } |
| 1133 | |
Kyle Moffett | 09dc34a | 2011-12-02 06:28:07 +0000 | [diff] [blame] | 1134 | /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */ |
| 1135 | static void mpic_cascade(unsigned int irq, struct irq_desc *desc) |
| 1136 | { |
| 1137 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 1138 | struct mpic *mpic = irq_desc_get_handler_data(desc); |
| 1139 | unsigned int virq; |
| 1140 | |
| 1141 | BUG_ON(!(mpic->flags & MPIC_SECONDARY)); |
| 1142 | |
| 1143 | virq = mpic_get_one_irq(mpic); |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 1144 | if (virq) |
Kyle Moffett | 09dc34a | 2011-12-02 06:28:07 +0000 | [diff] [blame] | 1145 | generic_handle_irq(virq); |
| 1146 | |
| 1147 | chip->irq_eoi(&desc->irq_data); |
| 1148 | } |
| 1149 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 1150 | static struct irq_domain_ops mpic_host_ops = { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1151 | .match = mpic_host_match, |
| 1152 | .map = mpic_host_map, |
| 1153 | .xlate = mpic_host_xlate, |
| 1154 | }; |
| 1155 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1156 | /* |
| 1157 | * Exported functions |
| 1158 | */ |
| 1159 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1160 | struct mpic * __init mpic_alloc(struct device_node *node, |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1161 | phys_addr_t phys_addr, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1162 | unsigned int flags, |
| 1163 | unsigned int isu_size, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1164 | unsigned int irq_count, |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1165 | const char *name) |
| 1166 | { |
Kyle Moffett | 5bdb6f2 | 2011-12-02 06:28:00 +0000 | [diff] [blame] | 1167 | int i, psize, intvec_top; |
| 1168 | struct mpic *mpic; |
| 1169 | u32 greg_feature; |
| 1170 | const char *vers; |
| 1171 | const u32 *psrc; |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1172 | u32 last_irq; |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1173 | |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1174 | /* Default MPIC search parameters */ |
| 1175 | static const struct of_device_id __initconst mpic_device_id[] = { |
| 1176 | { .type = "open-pic", }, |
| 1177 | { .compatible = "open-pic", }, |
| 1178 | {}, |
| 1179 | }; |
| 1180 | |
| 1181 | /* |
| 1182 | * If we were not passed a device-tree node, then perform the default |
| 1183 | * search for standardized a standardized OpenPIC. |
| 1184 | */ |
| 1185 | if (node) { |
| 1186 | node = of_node_get(node); |
| 1187 | } else { |
| 1188 | node = of_find_matching_node(NULL, mpic_device_id); |
| 1189 | if (!node) |
| 1190 | return NULL; |
| 1191 | } |
Kyle Moffett | 5bdb6f2 | 2011-12-02 06:28:00 +0000 | [diff] [blame] | 1192 | |
| 1193 | /* Pick the physical address from the device tree if unspecified */ |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1194 | if (!phys_addr) { |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1195 | /* Check if it is DCR-based */ |
| 1196 | if (of_get_property(node, "dcr-reg", NULL)) { |
| 1197 | flags |= MPIC_USES_DCR; |
| 1198 | } else { |
| 1199 | struct resource r; |
| 1200 | if (of_address_to_resource(node, 0, &r)) |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1201 | goto err_of_node_put; |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1202 | phys_addr = r.start; |
| 1203 | } |
| 1204 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1205 | |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1206 | /* Read extra device-tree properties into the flags variable */ |
| 1207 | if (of_get_property(node, "big-endian", NULL)) |
| 1208 | flags |= MPIC_BIG_ENDIAN; |
| 1209 | if (of_get_property(node, "pic-no-reset", NULL)) |
| 1210 | flags |= MPIC_NO_RESET; |
Kyle Moffett | 9ca163c | 2011-12-22 10:19:11 +0000 | [diff] [blame] | 1211 | if (of_get_property(node, "single-cpu-affinity", NULL)) |
| 1212 | flags |= MPIC_SINGLE_DEST_CPU; |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1213 | if (of_device_is_compatible(node, "fsl,mpic")) |
| 1214 | flags |= MPIC_FSL; |
| 1215 | |
Kumar Gala | 85355bb | 2009-06-18 22:01:20 +0000 | [diff] [blame] | 1216 | mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1217 | if (mpic == NULL) |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1218 | goto err_of_node_put; |
Kumar Gala | 85355bb | 2009-06-18 22:01:20 +0000 | [diff] [blame] | 1219 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1220 | mpic->name = name; |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1221 | mpic->node = node; |
Kyle Moffett | e7a9867 | 2011-12-02 06:28:01 +0000 | [diff] [blame] | 1222 | mpic->paddr = phys_addr; |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1223 | mpic->flags = flags; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1224 | |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1225 | mpic->hc_irq = mpic_irq_chip; |
Thomas Gleixner | b27df67 | 2009-11-18 23:44:21 +0000 | [diff] [blame] | 1226 | mpic->hc_irq.name = name; |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1227 | if (!(mpic->flags & MPIC_SECONDARY)) |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 1228 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1229 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1230 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
Thomas Gleixner | b27df67 | 2009-11-18 23:44:21 +0000 | [diff] [blame] | 1231 | mpic->hc_ht_irq.name = name; |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1232 | if (!(mpic->flags & MPIC_SECONDARY)) |
Lennert Buytenhek | 835c0553 | 2011-03-08 22:26:43 +0000 | [diff] [blame] | 1233 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
Michael Ellerman | 6cfef5b | 2007-04-23 18:47:08 +1000 | [diff] [blame] | 1234 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1235 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1236 | #ifdef CONFIG_SMP |
Benjamin Herrenschmidt | b9e5b4e | 2006-07-03 19:32:51 +1000 | [diff] [blame] | 1237 | mpic->hc_ipi = mpic_ipi_chip; |
Thomas Gleixner | b27df67 | 2009-11-18 23:44:21 +0000 | [diff] [blame] | 1238 | mpic->hc_ipi.name = name; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1239 | #endif /* CONFIG_SMP */ |
| 1240 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1241 | mpic->hc_tm = mpic_tm_chip; |
| 1242 | mpic->hc_tm.name = name; |
| 1243 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1244 | mpic->num_sources = 0; /* so far */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1245 | |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1246 | if (mpic->flags & MPIC_LARGE_VECTORS) |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1247 | intvec_top = 2047; |
| 1248 | else |
| 1249 | intvec_top = 255; |
| 1250 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1251 | mpic->timer_vecs[0] = intvec_top - 12; |
| 1252 | mpic->timer_vecs[1] = intvec_top - 11; |
| 1253 | mpic->timer_vecs[2] = intvec_top - 10; |
| 1254 | mpic->timer_vecs[3] = intvec_top - 9; |
| 1255 | mpic->timer_vecs[4] = intvec_top - 8; |
| 1256 | mpic->timer_vecs[5] = intvec_top - 7; |
| 1257 | mpic->timer_vecs[6] = intvec_top - 6; |
| 1258 | mpic->timer_vecs[7] = intvec_top - 5; |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1259 | mpic->ipi_vecs[0] = intvec_top - 4; |
| 1260 | mpic->ipi_vecs[1] = intvec_top - 3; |
| 1261 | mpic->ipi_vecs[2] = intvec_top - 2; |
| 1262 | mpic->ipi_vecs[3] = intvec_top - 1; |
| 1263 | mpic->spurious_vec = intvec_top; |
| 1264 | |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1265 | /* Look for protected sources */ |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1266 | psrc = of_get_property(mpic->node, "protected-sources", &psize); |
Kyle Moffett | 5bdb6f2 | 2011-12-02 06:28:00 +0000 | [diff] [blame] | 1267 | if (psrc) { |
| 1268 | /* Allocate a bitmap with one bit per interrupt */ |
| 1269 | unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1); |
| 1270 | mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL); |
| 1271 | BUG_ON(mpic->protected == NULL); |
| 1272 | for (i = 0; i < psize/sizeof(u32); i++) { |
| 1273 | if (psrc[i] > intvec_top) |
| 1274 | continue; |
| 1275 | __set_bit(psrc[i], mpic->protected); |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1276 | } |
| 1277 | } |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1278 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1279 | #ifdef CONFIG_MPIC_WEIRD |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1280 | mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)]; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1281 | #endif |
| 1282 | |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1283 | /* default register type */ |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1284 | if (mpic->flags & MPIC_BIG_ENDIAN) |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1285 | mpic->reg_type = mpic_access_mmio_be; |
| 1286 | else |
| 1287 | mpic->reg_type = mpic_access_mmio_le; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1288 | |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1289 | /* |
| 1290 | * An MPIC with a "dcr-reg" property must be accessed that way, but |
| 1291 | * only if the kernel includes DCR support. |
| 1292 | */ |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1293 | #ifdef CONFIG_PPC_DCR |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1294 | if (mpic->flags & MPIC_USES_DCR) |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1295 | mpic->reg_type = mpic_access_dcr; |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1296 | #else |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1297 | BUG_ON(mpic->flags & MPIC_USES_DCR); |
Kyle Moffett | 8bf4156 | 2011-12-02 06:27:59 +0000 | [diff] [blame] | 1298 | #endif |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1299 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1300 | /* Map the global registers */ |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1301 | mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); |
| 1302 | mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1303 | |
| 1304 | /* Reset */ |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1305 | |
| 1306 | /* When using a device-node, reset requests are only honored if the MPIC |
| 1307 | * is allowed to reset. |
| 1308 | */ |
Kyle Moffett | e55d7f7 | 2011-12-22 10:19:14 +0000 | [diff] [blame] | 1309 | if (!(mpic->flags & MPIC_NO_RESET)) { |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1310 | printk(KERN_DEBUG "mpic: Resetting\n"); |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1311 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1312 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1313 | | MPIC_GREG_GCONF_RESET); |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1314 | while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1315 | & MPIC_GREG_GCONF_RESET) |
| 1316 | mb(); |
| 1317 | } |
| 1318 | |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1319 | /* CoreInt */ |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1320 | if (mpic->flags & MPIC_ENABLE_COREINT) |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1321 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1322 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1323 | | MPIC_GREG_GCONF_COREINT); |
| 1324 | |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1325 | if (mpic->flags & MPIC_ENABLE_MCK) |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1326 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1327 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1328 | | MPIC_GREG_GCONF_MCK); |
| 1329 | |
Timur Tabi | 14b9247 | 2011-07-08 11:12:42 +0000 | [diff] [blame] | 1330 | /* |
Timur Tabi | 14b9247 | 2011-07-08 11:12:42 +0000 | [diff] [blame] | 1331 | * The MPIC driver will crash if there are more cores than we |
| 1332 | * can initialize, so we may as well catch that problem here. |
| 1333 | */ |
| 1334 | BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS); |
| 1335 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1336 | /* Map the per-CPU registers */ |
Timur Tabi | 14b9247 | 2011-07-08 11:12:42 +0000 | [diff] [blame] | 1337 | for_each_possible_cpu(i) { |
| 1338 | unsigned int cpu = get_hard_smp_processor_id(i); |
| 1339 | |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1340 | mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu], |
Timur Tabi | 14b9247 | 2011-07-08 11:12:42 +0000 | [diff] [blame] | 1341 | MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE), |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1342 | 0x1000); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1343 | } |
| 1344 | |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1345 | /* |
| 1346 | * Read feature register. For non-ISU MPICs, num sources as well. On |
| 1347 | * ISU MPICs, sources are counted as ISUs are added |
| 1348 | */ |
| 1349 | greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); |
| 1350 | |
| 1351 | /* |
| 1352 | * By default, the last source number comes from the MPIC, but the |
| 1353 | * device-tree and board support code can override it on buggy hw. |
Benjamin Herrenschmidt | fe83364 | 2012-02-22 13:50:13 +0000 | [diff] [blame] | 1354 | * If we get passed an isu_size (multi-isu MPIC) then we use that |
| 1355 | * as a default instead of the value read from the HW. |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1356 | */ |
| 1357 | last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) |
Benjamin Herrenschmidt | fe83364 | 2012-02-22 13:50:13 +0000 | [diff] [blame] | 1358 | >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT; |
| 1359 | if (isu_size) |
| 1360 | last_irq = isu_size * MPIC_MAX_ISU - 1; |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1361 | of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq); |
| 1362 | if (irq_count) |
| 1363 | last_irq = irq_count - 1; |
| 1364 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1365 | /* Initialize main ISU if none provided */ |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1366 | if (!isu_size) { |
| 1367 | isu_size = last_irq + 1; |
| 1368 | mpic->num_sources = isu_size; |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1369 | mpic_map(mpic, mpic->paddr, &mpic->isus[0], |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1370 | MPIC_INFO(IRQ_BASE), |
| 1371 | MPIC_INFO(IRQ_STRIDE) * isu_size); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1372 | } |
Kyle Moffett | c1b8d45 | 2011-12-22 10:19:13 +0000 | [diff] [blame] | 1373 | |
| 1374 | mpic->isu_size = isu_size; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1375 | mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); |
| 1376 | mpic->isu_mask = (1 << mpic->isu_shift) - 1; |
| 1377 | |
Grant Likely | a8db8cf | 2012-02-14 14:06:54 -0700 | [diff] [blame] | 1378 | mpic->irqhost = irq_domain_add_linear(mpic->node, |
Linus Torvalds | 5375871 | 2012-03-21 18:55:10 -0700 | [diff] [blame] | 1379 | last_irq + 1, |
Grant Likely | a8db8cf | 2012-02-14 14:06:54 -0700 | [diff] [blame] | 1380 | &mpic_host_ops, mpic); |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1381 | |
| 1382 | /* |
| 1383 | * FIXME: The code leaks the MPIC object and mappings here; this |
| 1384 | * is very unlikely to fail but it ought to be fixed anyways. |
| 1385 | */ |
Kumar Gala | 31207da | 2009-05-08 12:08:20 +0000 | [diff] [blame] | 1386 | if (mpic->irqhost == NULL) |
| 1387 | return NULL; |
| 1388 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1389 | /* Display version */ |
Johannes Berg | d9d1063 | 2008-02-21 20:39:01 +1100 | [diff] [blame] | 1390 | switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1391 | case 1: |
| 1392 | vers = "1.0"; |
| 1393 | break; |
| 1394 | case 2: |
| 1395 | vers = "1.2"; |
| 1396 | break; |
| 1397 | case 3: |
| 1398 | vers = "1.3"; |
| 1399 | break; |
| 1400 | default: |
| 1401 | vers = "<unknown>"; |
| 1402 | break; |
| 1403 | } |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1404 | printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," |
| 1405 | " max %d CPUs\n", |
Kyle Moffett | e7a9867 | 2011-12-02 06:28:01 +0000 | [diff] [blame] | 1406 | name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1407 | printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", |
| 1408 | mpic->isu_size, mpic->isu_shift, mpic->isu_mask); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1409 | |
| 1410 | mpic->next = mpics; |
| 1411 | mpics = mpic; |
| 1412 | |
Kyle Moffett | 3a7a717 | 2011-12-22 10:19:09 +0000 | [diff] [blame] | 1413 | if (!(mpic->flags & MPIC_SECONDARY)) { |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1414 | mpic_primary = mpic; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1415 | irq_set_default_host(mpic->irqhost); |
| 1416 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1417 | |
| 1418 | return mpic; |
Kyle Moffett | 996983b | 2011-12-02 06:28:02 +0000 | [diff] [blame] | 1419 | |
| 1420 | err_of_node_put: |
| 1421 | of_node_put(node); |
| 1422 | return NULL; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1423 | } |
| 1424 | |
| 1425 | void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, |
Benjamin Herrenschmidt | a959ff5 | 2006-11-11 17:24:56 +1100 | [diff] [blame] | 1426 | phys_addr_t paddr) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1427 | { |
| 1428 | unsigned int isu_first = isu_num * mpic->isu_size; |
| 1429 | |
| 1430 | BUG_ON(isu_num >= MPIC_MAX_ISU); |
| 1431 | |
Kyle Moffett | c51242e | 2011-12-02 06:28:06 +0000 | [diff] [blame] | 1432 | mpic_map(mpic, |
Benjamin Herrenschmidt | 5a2642f | 2009-06-22 16:47:59 +0000 | [diff] [blame] | 1433 | paddr, &mpic->isus[isu_num], 0, |
Benjamin Herrenschmidt | fbf0274 | 2006-11-11 17:24:55 +1100 | [diff] [blame] | 1434 | MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); |
Benjamin Herrenschmidt | 5a2642f | 2009-06-22 16:47:59 +0000 | [diff] [blame] | 1435 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1436 | if ((isu_first + mpic->isu_size) > mpic->num_sources) |
| 1437 | mpic->num_sources = isu_first + mpic->isu_size; |
| 1438 | } |
| 1439 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1440 | void __init mpic_init(struct mpic *mpic) |
| 1441 | { |
Kyle Moffett | 09dc34a | 2011-12-02 06:28:07 +0000 | [diff] [blame] | 1442 | int i, cpu; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1443 | |
| 1444 | BUG_ON(mpic->num_sources == 0); |
| 1445 | |
| 1446 | printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); |
| 1447 | |
| 1448 | /* Set current processor priority to max */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1449 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1450 | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1451 | /* Initialize timers to our reserved vectors and mask them for now */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1452 | for (i = 0; i < 4; i++) { |
| 1453 | mpic_write(mpic->tmregs, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1454 | i * MPIC_INFO(TIMER_STRIDE) + |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1455 | MPIC_INFO(TIMER_DESTINATION), |
| 1456 | 1 << hard_smp_processor_id()); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1457 | mpic_write(mpic->tmregs, |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1458 | i * MPIC_INFO(TIMER_STRIDE) + |
| 1459 | MPIC_INFO(TIMER_VECTOR_PRI), |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1460 | MPIC_VECPRI_MASK | |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1461 | (9 << MPIC_VECPRI_PRIORITY_SHIFT) | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1462 | (mpic->timer_vecs[0] + i)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1463 | } |
| 1464 | |
| 1465 | /* Initialize IPIs to our reserved vectors and mark them disabled for now */ |
| 1466 | mpic_test_broken_ipi(mpic); |
| 1467 | for (i = 0; i < 4; i++) { |
| 1468 | mpic_ipi_write(i, |
| 1469 | MPIC_VECPRI_MASK | |
| 1470 | (10 << MPIC_VECPRI_PRIORITY_SHIFT) | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1471 | (mpic->ipi_vecs[0] + i)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1472 | } |
| 1473 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1474 | /* Do the HT PIC fixups on U3 broken mpic */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1475 | DBG("MPIC flags: %x\n", mpic->flags); |
Kyle Moffett | be8bec5 | 2011-12-02 06:28:03 +0000 | [diff] [blame] | 1476 | if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1477 | mpic_scan_ht_pics(mpic); |
Michael Ellerman | 05af7bd | 2007-05-08 12:58:37 +1000 | [diff] [blame] | 1478 | mpic_u3msi_init(mpic); |
| 1479 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1480 | |
Olof Johansson | 38958dd | 2007-12-12 17:44:46 +1100 | [diff] [blame] | 1481 | mpic_pasemi_msi_init(mpic); |
| 1482 | |
Meador Inge | d6a2639 | 2011-03-14 10:01:07 +0000 | [diff] [blame] | 1483 | cpu = mpic_processor_id(mpic); |
Arnd Bergmann | cc353c3 | 2008-11-28 09:51:23 +0000 | [diff] [blame] | 1484 | |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1485 | if (!(mpic->flags & MPIC_NO_RESET)) { |
| 1486 | for (i = 0; i < mpic->num_sources; i++) { |
| 1487 | /* start with vector = source number, and masked */ |
| 1488 | u32 vecpri = MPIC_VECPRI_MASK | i | |
| 1489 | (8 << MPIC_VECPRI_PRIORITY_SHIFT); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1490 | |
Meador Inge | dfec220 | 2011-03-14 10:01:06 +0000 | [diff] [blame] | 1491 | /* check if protected */ |
| 1492 | if (mpic->protected && test_bit(i, mpic->protected)) |
| 1493 | continue; |
| 1494 | /* init hw */ |
| 1495 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri); |
| 1496 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu); |
| 1497 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1498 | } |
| 1499 | |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1500 | /* Init spurious vector */ |
| 1501 | mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1502 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1503 | /* Disable 8259 passthrough, if supported */ |
| 1504 | if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) |
| 1505 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1506 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1507 | | MPIC_GREG_GCONF_8259_PTHROU_DIS); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1508 | |
Olof Johansson | d87bf3b | 2007-12-27 22:16:29 -0600 | [diff] [blame] | 1509 | if (mpic->flags & MPIC_NO_BIAS) |
| 1510 | mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), |
| 1511 | mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) |
| 1512 | | MPIC_GREG_GCONF_NO_BIAS); |
| 1513 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1514 | /* Set current processor priority to 0 */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1515 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1516 | |
| 1517 | #ifdef CONFIG_PM |
| 1518 | /* allocate memory to save mpic state */ |
Anton Vorontsov | ea96025 | 2009-07-01 10:59:57 +0000 | [diff] [blame] | 1519 | mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data), |
| 1520 | GFP_KERNEL); |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1521 | BUG_ON(mpic->save_data == NULL); |
| 1522 | #endif |
Kyle Moffett | 09dc34a | 2011-12-02 06:28:07 +0000 | [diff] [blame] | 1523 | |
| 1524 | /* Check if this MPIC is chained from a parent interrupt controller */ |
| 1525 | if (mpic->flags & MPIC_SECONDARY) { |
| 1526 | int virq = irq_of_parse_and_map(mpic->node, 0); |
| 1527 | if (virq != NO_IRQ) { |
| 1528 | printk(KERN_INFO "%s: hooking up to IRQ %d\n", |
| 1529 | mpic->node->full_name, virq); |
| 1530 | irq_set_handler_data(virq, mpic); |
| 1531 | irq_set_chained_handler(virq, &mpic_cascade); |
| 1532 | } |
| 1533 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1534 | } |
| 1535 | |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1536 | void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) |
| 1537 | { |
| 1538 | u32 v; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1539 | |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1540 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
| 1541 | v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK; |
| 1542 | v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio); |
| 1543 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); |
| 1544 | } |
| 1545 | |
| 1546 | void __init mpic_set_serial_int(struct mpic *mpic, int enable) |
| 1547 | { |
Benjamin Herrenschmidt | ba1826e | 2006-07-05 15:36:15 +1000 | [diff] [blame] | 1548 | unsigned long flags; |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1549 | u32 v; |
| 1550 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1551 | raw_spin_lock_irqsave(&mpic_lock, flags); |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1552 | v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1); |
| 1553 | if (enable) |
| 1554 | v |= MPIC_GREG_GLOBAL_CONF_1_SIE; |
| 1555 | else |
| 1556 | v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE; |
| 1557 | mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1558 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
Mark A. Greer | 868ea0c | 2006-06-20 14:15:36 -0700 | [diff] [blame] | 1559 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1560 | |
| 1561 | void mpic_irq_set_priority(unsigned int irq, unsigned int pri) |
| 1562 | { |
Tony Breeds | d69a78d | 2009-04-07 18:26:54 +0000 | [diff] [blame] | 1563 | struct mpic *mpic = mpic_find(irq); |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 1564 | unsigned int src = virq_to_hw(irq); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1565 | unsigned long flags; |
| 1566 | u32 reg; |
| 1567 | |
Stephen Rothwell | 06a901c | 2008-05-21 16:24:31 +1000 | [diff] [blame] | 1568 | if (!mpic) |
| 1569 | return; |
| 1570 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1571 | raw_spin_lock_irqsave(&mpic_lock, flags); |
Benjamin Herrenschmidt | 3a2b4f7 | 2012-04-19 17:29:34 +0000 | [diff] [blame] | 1572 | if (mpic_is_ipi(mpic, src)) { |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1573 | reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 1574 | ~MPIC_VECPRI_PRIORITY_MASK; |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1575 | mpic_ipi_write(src - mpic->ipi_vecs[0], |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1576 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
Benjamin Herrenschmidt | 3a2b4f7 | 2012-04-19 17:29:34 +0000 | [diff] [blame] | 1577 | } else if (mpic_is_tm(mpic, src)) { |
Scott Wood | ea94187 | 2011-03-24 16:43:55 -0500 | [diff] [blame] | 1578 | reg = mpic_tm_read(src - mpic->timer_vecs[0]) & |
| 1579 | ~MPIC_VECPRI_PRIORITY_MASK; |
| 1580 | mpic_tm_write(src - mpic->timer_vecs[0], |
| 1581 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1582 | } else { |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1583 | reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
Benjamin Herrenschmidt | e535664 | 2005-11-18 17:18:15 +1100 | [diff] [blame] | 1584 | & ~MPIC_VECPRI_PRIORITY_MASK; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1585 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1586 | reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); |
| 1587 | } |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1588 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1589 | } |
| 1590 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1591 | void mpic_setup_this_cpu(void) |
| 1592 | { |
| 1593 | #ifdef CONFIG_SMP |
| 1594 | struct mpic *mpic = mpic_primary; |
| 1595 | unsigned long flags; |
| 1596 | u32 msk = 1 << hard_smp_processor_id(); |
| 1597 | unsigned int i; |
| 1598 | |
| 1599 | BUG_ON(mpic == NULL); |
| 1600 | |
| 1601 | DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); |
| 1602 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1603 | raw_spin_lock_irqsave(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1604 | |
| 1605 | /* let the mpic know we want intrs. default affinity is 0xffffffff |
| 1606 | * until changed via /proc. That's how it's done on x86. If we want |
| 1607 | * it differently, then we should make sure we also change the default |
Ingo Molnar | a53da52 | 2006-06-29 02:24:38 -0700 | [diff] [blame] | 1608 | * values of irq_desc[].affinity in irq.c. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1609 | */ |
| 1610 | if (distribute_irqs) { |
| 1611 | for (i = 0; i < mpic->num_sources ; i++) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1612 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1613 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1614 | } |
| 1615 | |
| 1616 | /* Set current processor priority to 0 */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1617 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1618 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1619 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1620 | #endif /* CONFIG_SMP */ |
| 1621 | } |
| 1622 | |
| 1623 | int mpic_cpu_get_priority(void) |
| 1624 | { |
| 1625 | struct mpic *mpic = mpic_primary; |
| 1626 | |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1627 | return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI)); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1628 | } |
| 1629 | |
| 1630 | void mpic_cpu_set_priority(int prio) |
| 1631 | { |
| 1632 | struct mpic *mpic = mpic_primary; |
| 1633 | |
| 1634 | prio &= MPIC_CPU_TASKPRI_MASK; |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1635 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1636 | } |
| 1637 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1638 | void mpic_teardown_this_cpu(int secondary) |
| 1639 | { |
| 1640 | struct mpic *mpic = mpic_primary; |
| 1641 | unsigned long flags; |
| 1642 | u32 msk = 1 << hard_smp_processor_id(); |
| 1643 | unsigned int i; |
| 1644 | |
| 1645 | BUG_ON(mpic == NULL); |
| 1646 | |
| 1647 | DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1648 | raw_spin_lock_irqsave(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1649 | |
| 1650 | /* let the mpic know we don't want intrs. */ |
| 1651 | for (i = 0; i < mpic->num_sources ; i++) |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1652 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1653 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1654 | |
| 1655 | /* Set current processor priority to max */ |
Zang Roy-r61911 | 7233593 | 2006-08-25 14:16:30 +1000 | [diff] [blame] | 1656 | mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); |
Valentine Barshak | 7132799 | 2008-04-03 23:09:43 +0400 | [diff] [blame] | 1657 | /* We need to EOI the IPI since not all platforms reset the MPIC |
| 1658 | * on boot and new interrupts wouldn't get delivered otherwise. |
| 1659 | */ |
| 1660 | mpic_eoi(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1661 | |
Thomas Gleixner | 203041a | 2010-02-18 02:23:18 +0000 | [diff] [blame] | 1662 | raw_spin_unlock_irqrestore(&mpic_lock, flags); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1663 | } |
| 1664 | |
| 1665 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1666 | static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1667 | { |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1668 | u32 src; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1669 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1670 | src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1671 | #ifdef DEBUG_LOW |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1672 | DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 1673 | #endif |
Josh Boyer | 5cddd2e | 2007-05-01 06:38:11 +1000 | [diff] [blame] | 1674 | if (unlikely(src == mpic->spurious_vec)) { |
| 1675 | if (mpic->flags & MPIC_SPV_EOI) |
| 1676 | mpic_eoi(mpic); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1677 | return NO_IRQ; |
Josh Boyer | 5cddd2e | 2007-05-01 06:38:11 +1000 | [diff] [blame] | 1678 | } |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1679 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
Christian Dietrich | 7646223 | 2011-06-04 05:36:54 +0000 | [diff] [blame] | 1680 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
| 1681 | mpic->name, (int)src); |
Benjamin Herrenschmidt | 7fd7218 | 2007-07-21 09:55:21 +1000 | [diff] [blame] | 1682 | mpic_eoi(mpic); |
| 1683 | return NO_IRQ; |
| 1684 | } |
| 1685 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1686 | return irq_linear_revmap(mpic->irqhost, src); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1687 | } |
| 1688 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1689 | unsigned int mpic_get_one_irq(struct mpic *mpic) |
| 1690 | { |
| 1691 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); |
| 1692 | } |
| 1693 | |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 1694 | unsigned int mpic_get_irq(void) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1695 | { |
| 1696 | struct mpic *mpic = mpic_primary; |
| 1697 | |
| 1698 | BUG_ON(mpic == NULL); |
| 1699 | |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 1700 | return mpic_get_one_irq(mpic); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1701 | } |
| 1702 | |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1703 | unsigned int mpic_get_coreint_irq(void) |
| 1704 | { |
| 1705 | #ifdef CONFIG_BOOKE |
| 1706 | struct mpic *mpic = mpic_primary; |
| 1707 | u32 src; |
| 1708 | |
| 1709 | BUG_ON(mpic == NULL); |
| 1710 | |
| 1711 | src = mfspr(SPRN_EPR); |
| 1712 | |
| 1713 | if (unlikely(src == mpic->spurious_vec)) { |
| 1714 | if (mpic->flags & MPIC_SPV_EOI) |
| 1715 | mpic_eoi(mpic); |
| 1716 | return NO_IRQ; |
| 1717 | } |
| 1718 | if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { |
Christian Dietrich | 7646223 | 2011-06-04 05:36:54 +0000 | [diff] [blame] | 1719 | printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n", |
| 1720 | mpic->name, (int)src); |
Kumar Gala | d91e4ea | 2009-01-07 15:53:29 -0600 | [diff] [blame] | 1721 | return NO_IRQ; |
| 1722 | } |
| 1723 | |
| 1724 | return irq_linear_revmap(mpic->irqhost, src); |
| 1725 | #else |
| 1726 | return NO_IRQ; |
| 1727 | #endif |
| 1728 | } |
| 1729 | |
Olof Johansson | f365355 | 2007-12-20 13:11:18 -0600 | [diff] [blame] | 1730 | unsigned int mpic_get_mcirq(void) |
| 1731 | { |
| 1732 | struct mpic *mpic = mpic_primary; |
| 1733 | |
| 1734 | BUG_ON(mpic == NULL); |
| 1735 | |
| 1736 | return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); |
| 1737 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1738 | |
| 1739 | #ifdef CONFIG_SMP |
| 1740 | void mpic_request_ipis(void) |
| 1741 | { |
| 1742 | struct mpic *mpic = mpic_primary; |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1743 | int i; |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1744 | BUG_ON(mpic == NULL); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1745 | |
Frans Pop | 8354be9 | 2010-02-06 07:47:20 +0000 | [diff] [blame] | 1746 | printk(KERN_INFO "mpic: requesting IPIs...\n"); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1747 | |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1748 | for (i = 0; i < 4; i++) { |
| 1749 | unsigned int vipi = irq_create_mapping(mpic->irqhost, |
Olof Johansson | 7df2457 | 2007-01-28 23:33:18 -0600 | [diff] [blame] | 1750 | mpic->ipi_vecs[0] + i); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1751 | if (vipi == NO_IRQ) { |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1752 | printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]); |
| 1753 | continue; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1754 | } |
Milton Miller | 78608dd | 2008-10-10 01:56:50 +0000 | [diff] [blame] | 1755 | smp_request_message_ipi(vipi, i); |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 1756 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1757 | } |
Paul Mackerras | a9c5926 | 2005-10-20 17:09:51 +1000 | [diff] [blame] | 1758 | |
Milton Miller | 3caba98 | 2011-05-10 19:29:17 +0000 | [diff] [blame] | 1759 | void smp_mpic_message_pass(int cpu, int msg) |
Benjamin Herrenschmidt | 2ef613cb | 2010-05-06 18:01:46 +1000 | [diff] [blame] | 1760 | { |
| 1761 | struct mpic *mpic = mpic_primary; |
Milton Miller | 3caba98 | 2011-05-10 19:29:17 +0000 | [diff] [blame] | 1762 | u32 physmask; |
Benjamin Herrenschmidt | 2ef613cb | 2010-05-06 18:01:46 +1000 | [diff] [blame] | 1763 | |
| 1764 | BUG_ON(mpic == NULL); |
| 1765 | |
Paul Mackerras | a9c5926 | 2005-10-20 17:09:51 +1000 | [diff] [blame] | 1766 | /* make sure we're sending something that translates to an IPI */ |
| 1767 | if ((unsigned int)msg > 3) { |
| 1768 | printk("SMP %d: smp_message_pass: unknown msg %d\n", |
| 1769 | smp_processor_id(), msg); |
| 1770 | return; |
| 1771 | } |
Milton Miller | 3caba98 | 2011-05-10 19:29:17 +0000 | [diff] [blame] | 1772 | |
| 1773 | #ifdef DEBUG_IPI |
| 1774 | DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); |
| 1775 | #endif |
| 1776 | |
| 1777 | physmask = 1 << get_hard_smp_processor_id(cpu); |
| 1778 | |
| 1779 | mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) + |
| 1780 | msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask); |
Paul Mackerras | a9c5926 | 2005-10-20 17:09:51 +1000 | [diff] [blame] | 1781 | } |
Michael Ellerman | 775aeff | 2007-02-08 18:34:04 +1100 | [diff] [blame] | 1782 | |
| 1783 | int __init smp_mpic_probe(void) |
| 1784 | { |
| 1785 | int nr_cpus; |
| 1786 | |
| 1787 | DBG("smp_mpic_probe()...\n"); |
| 1788 | |
Benjamin Herrenschmidt | 2ef613cb | 2010-05-06 18:01:46 +1000 | [diff] [blame] | 1789 | nr_cpus = cpumask_weight(cpu_possible_mask); |
Michael Ellerman | 775aeff | 2007-02-08 18:34:04 +1100 | [diff] [blame] | 1790 | |
| 1791 | DBG("nr_cpus: %d\n", nr_cpus); |
| 1792 | |
| 1793 | if (nr_cpus > 1) |
| 1794 | mpic_request_ipis(); |
| 1795 | |
| 1796 | return nr_cpus; |
| 1797 | } |
| 1798 | |
| 1799 | void __devinit smp_mpic_setup_cpu(int cpu) |
| 1800 | { |
| 1801 | mpic_setup_this_cpu(); |
| 1802 | } |
Matthew McClintock | 66953eb | 2010-06-29 09:42:26 +0000 | [diff] [blame] | 1803 | |
| 1804 | void mpic_reset_core(int cpu) |
| 1805 | { |
| 1806 | struct mpic *mpic = mpic_primary; |
| 1807 | u32 pir; |
| 1808 | int cpuid = get_hard_smp_processor_id(cpu); |
Matthew McClintock | 44f16fc | 2011-10-26 13:46:57 -0500 | [diff] [blame] | 1809 | int i; |
Matthew McClintock | 66953eb | 2010-06-29 09:42:26 +0000 | [diff] [blame] | 1810 | |
| 1811 | /* Set target bit for core reset */ |
| 1812 | pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); |
| 1813 | pir |= (1 << cpuid); |
| 1814 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); |
| 1815 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); |
| 1816 | |
| 1817 | /* Restore target bit after reset complete */ |
| 1818 | pir &= ~(1 << cpuid); |
| 1819 | mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); |
| 1820 | mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); |
Matthew McClintock | 44f16fc | 2011-10-26 13:46:57 -0500 | [diff] [blame] | 1821 | |
| 1822 | /* Perform 15 EOI on each reset core to clear pending interrupts. |
| 1823 | * This is required for FSL CoreNet based devices */ |
| 1824 | if (mpic->flags & MPIC_FSL) { |
| 1825 | for (i = 0; i < 15; i++) { |
| 1826 | _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], |
| 1827 | MPIC_CPU_EOI, 0); |
| 1828 | } |
| 1829 | } |
Matthew McClintock | 66953eb | 2010-06-29 09:42:26 +0000 | [diff] [blame] | 1830 | } |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1831 | #endif /* CONFIG_SMP */ |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1832 | |
| 1833 | #ifdef CONFIG_PM |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1834 | static void mpic_suspend_one(struct mpic *mpic) |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1835 | { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1836 | int i; |
| 1837 | |
| 1838 | for (i = 0; i < mpic->num_sources; i++) { |
| 1839 | mpic->save_data[i].vecprio = |
| 1840 | mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI)); |
| 1841 | mpic->save_data[i].dest = |
| 1842 | mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)); |
| 1843 | } |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1844 | } |
| 1845 | |
| 1846 | static int mpic_suspend(void) |
| 1847 | { |
| 1848 | struct mpic *mpic = mpics; |
| 1849 | |
| 1850 | while (mpic) { |
| 1851 | mpic_suspend_one(mpic); |
| 1852 | mpic = mpic->next; |
| 1853 | } |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1854 | |
| 1855 | return 0; |
| 1856 | } |
| 1857 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1858 | static void mpic_resume_one(struct mpic *mpic) |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1859 | { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1860 | int i; |
| 1861 | |
| 1862 | for (i = 0; i < mpic->num_sources; i++) { |
| 1863 | mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), |
| 1864 | mpic->save_data[i].vecprio); |
| 1865 | mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), |
| 1866 | mpic->save_data[i].dest); |
| 1867 | |
| 1868 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
Alastair Bridgewater | 7c9d936 | 2010-06-12 15:36:48 +0000 | [diff] [blame] | 1869 | if (mpic->fixups) { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1870 | struct mpic_irq_fixup *fixup = &mpic->fixups[i]; |
| 1871 | |
| 1872 | if (fixup->base) { |
| 1873 | /* we use the lowest bit in an inverted meaning */ |
| 1874 | if ((mpic->save_data[i].fixup_data & 1) == 0) |
| 1875 | continue; |
| 1876 | |
| 1877 | /* Enable and configure */ |
| 1878 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
| 1879 | |
| 1880 | writel(mpic->save_data[i].fixup_data & ~1, |
| 1881 | fixup->base + 4); |
| 1882 | } |
| 1883 | } |
| 1884 | #endif |
| 1885 | } /* end for loop */ |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1886 | } |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1887 | |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1888 | static void mpic_resume(void) |
| 1889 | { |
| 1890 | struct mpic *mpic = mpics; |
| 1891 | |
| 1892 | while (mpic) { |
| 1893 | mpic_resume_one(mpic); |
| 1894 | mpic = mpic->next; |
| 1895 | } |
| 1896 | } |
| 1897 | |
| 1898 | static struct syscore_ops mpic_syscore_ops = { |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1899 | .resume = mpic_resume, |
| 1900 | .suspend = mpic_suspend, |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1901 | }; |
| 1902 | |
| 1903 | static int mpic_init_sys(void) |
| 1904 | { |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1905 | register_syscore_ops(&mpic_syscore_ops); |
| 1906 | return 0; |
Johannes Berg | 3669e93 | 2007-05-02 16:33:41 +1000 | [diff] [blame] | 1907 | } |
| 1908 | |
| 1909 | device_initcall(mpic_init_sys); |
Rafael J. Wysocki | f5a592f | 2011-04-26 19:14:57 +0200 | [diff] [blame] | 1910 | #endif |