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Paul Walmsleyd8a94452009-12-08 16:21:29 -07001/*
2 * opp2420_data.c - old-style "OPP" table for OMAP2420
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
6 *
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
10 * These configurations are characterized by voltage and speed for clocks.
11 * The device is only validated for certain combinations. One way to express
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070012 * these combinations is via the 'ratios' which the clocks operate with
Paul Walmsleyd8a94452009-12-08 16:21:29 -070013 * respect to each other. These ratio sets are for a given voltage/DPLL
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070014 * setting. All configurations can be described by a DPLL setting and a ratio.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070015 *
16 * XXX Missing voltage data.
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070017 * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
Paul Walmsleyd8a94452009-12-08 16:21:29 -070018 *
19 * THe format described in this file is deprecated. Once a reasonable
20 * OPP API exists, the data in this file should be converted to use it.
21 *
22 * This is technically part of the OMAP2xxx clock code.
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070023 *
24 * Considerable work is still needed to fully support dynamic frequency
25 * changes on OMAP2xxx-series chips. Readers interested in such a
26 * project are encouraged to review the Maemo Diablo RX-34 and RX-44
27 * kernel source at:
28 * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
Paul Walmsleyd8a94452009-12-08 16:21:29 -070029 */
30
Tony Lindgren2c799ce2012-02-24 10:34:35 -080031#include <plat/hardware.h>
32
Paul Walmsleyd8a94452009-12-08 16:21:29 -070033#include "opp2xxx.h"
34#include "sdrc.h"
35#include "clock.h"
36
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070037/*
38 * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070039 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
40 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
41 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
42 *
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070043 * Filling in table based on H4 boards available. There are quite a
44 * few more rate combinations which could be defined.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070045 *
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070046 * When multiple values are defined the start up will try and choose
47 * the fastest one. If a 'fast' value is defined, then automatically,
48 * the /2 one should be included as it can be used. Generally having
49 * more than one fast set does not make sense, as static timings need
50 * to be changed to change the set. The exception is the bypass
51 * setting which is available for low power bypass.
Paul Walmsleyd8a94452009-12-08 16:21:29 -070052 *
53 * Note: This table needs to be sorted, fastest to slowest.
Paul Walmsleyca6eccb2010-01-08 15:23:15 -070054 **/
Paul Walmsleyd8a94452009-12-08 16:21:29 -070055const struct prcm_config omap2420_rate_table[] = {
56 /* PRCM I - FAST */
57 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
58 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
59 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
60 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
61 RATE_IN_242X},
62
63 /* PRCM II - FAST */
64 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
65 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
66 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
67 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
68 RATE_IN_242X},
69
70 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
71 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
72 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
73 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
74 RATE_IN_242X},
75
76 /* PRCM III - FAST */
77 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
78 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
79 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
80 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
81 RATE_IN_242X},
82
83 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
84 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
85 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
86 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
87 RATE_IN_242X},
88
89 /* PRCM II - SLOW */
90 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
91 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
92 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
93 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
94 RATE_IN_242X},
95
96 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
97 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
98 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
99 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
100 RATE_IN_242X},
101
102 /* PRCM III - SLOW */
103 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
104 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
105 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
106 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
107 RATE_IN_242X},
108
109 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
110 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
111 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
112 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
113 RATE_IN_242X},
114
115 /* PRCM-VII (boot-bypass) */
116 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
117 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
118 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
119 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
120 RATE_IN_242X},
121
122 /* PRCM-VII (boot-bypass) */
123 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
124 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
125 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
126 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
127 RATE_IN_242X},
128
129 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
130};