Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Alex Deucher <alexander.deucher@amd.com> |
| 25 | */ |
| 26 | |
| 27 | #include "drmP.h" |
| 28 | #include "drm.h" |
| 29 | #include "radeon_drm.h" |
| 30 | #include "radeon.h" |
| 31 | |
| 32 | #include "evergreend.h" |
| 33 | #include "evergreen_blit_shaders.h" |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame^] | 34 | #include "cayman_blit_shaders.h" |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 35 | |
| 36 | #define DI_PT_RECTLIST 0x11 |
| 37 | #define DI_INDEX_SIZE_16_BIT 0x0 |
| 38 | #define DI_SRC_SEL_AUTO_INDEX 0x2 |
| 39 | |
| 40 | #define FMT_8 0x1 |
| 41 | #define FMT_5_6_5 0x8 |
| 42 | #define FMT_8_8_8_8 0x1a |
| 43 | #define COLOR_8 0x1 |
| 44 | #define COLOR_5_6_5 0x8 |
| 45 | #define COLOR_8_8_8_8 0x1a |
| 46 | |
| 47 | /* emits 17 */ |
| 48 | static void |
| 49 | set_render_target(struct radeon_device *rdev, int format, |
| 50 | int w, int h, u64 gpu_addr) |
| 51 | { |
| 52 | u32 cb_color_info; |
| 53 | int pitch, slice; |
| 54 | |
| 55 | h = ALIGN(h, 8); |
| 56 | if (h < 8) |
| 57 | h = 8; |
| 58 | |
Alex Deucher | 27dcfc1 | 2011-02-10 14:51:34 -0500 | [diff] [blame] | 59 | cb_color_info = ((format << 2) | (1 << 24) | (1 << 8)); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 60 | pitch = (w / 8) - 1; |
| 61 | slice = ((w * h) / 64) - 1; |
| 62 | |
| 63 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); |
| 64 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 65 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 66 | radeon_ring_write(rdev, pitch); |
| 67 | radeon_ring_write(rdev, slice); |
| 68 | radeon_ring_write(rdev, 0); |
| 69 | radeon_ring_write(rdev, cb_color_info); |
| 70 | radeon_ring_write(rdev, (1 << 4)); |
| 71 | radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16)); |
| 72 | radeon_ring_write(rdev, 0); |
| 73 | radeon_ring_write(rdev, 0); |
| 74 | radeon_ring_write(rdev, 0); |
| 75 | radeon_ring_write(rdev, 0); |
| 76 | radeon_ring_write(rdev, 0); |
| 77 | radeon_ring_write(rdev, 0); |
| 78 | radeon_ring_write(rdev, 0); |
| 79 | radeon_ring_write(rdev, 0); |
| 80 | } |
| 81 | |
| 82 | /* emits 5dw */ |
| 83 | static void |
| 84 | cp_set_surface_sync(struct radeon_device *rdev, |
| 85 | u32 sync_type, u32 size, |
| 86 | u64 mc_addr) |
| 87 | { |
| 88 | u32 cp_coher_size; |
| 89 | |
| 90 | if (size == 0xffffffff) |
| 91 | cp_coher_size = 0xffffffff; |
| 92 | else |
| 93 | cp_coher_size = ((size + 255) >> 8); |
| 94 | |
| 95 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 96 | radeon_ring_write(rdev, sync_type); |
| 97 | radeon_ring_write(rdev, cp_coher_size); |
| 98 | radeon_ring_write(rdev, mc_addr >> 8); |
| 99 | radeon_ring_write(rdev, 10); /* poll interval */ |
| 100 | } |
| 101 | |
| 102 | /* emits 11dw + 1 surface sync = 16dw */ |
| 103 | static void |
| 104 | set_shaders(struct radeon_device *rdev) |
| 105 | { |
| 106 | u64 gpu_addr; |
| 107 | |
| 108 | /* VS */ |
| 109 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
| 110 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3)); |
| 111 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 112 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 113 | radeon_ring_write(rdev, 2); |
| 114 | radeon_ring_write(rdev, 0); |
| 115 | |
| 116 | /* PS */ |
| 117 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
| 118 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4)); |
| 119 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 120 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 121 | radeon_ring_write(rdev, 1); |
| 122 | radeon_ring_write(rdev, 0); |
| 123 | radeon_ring_write(rdev, 2); |
| 124 | |
| 125 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
| 126 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
| 127 | } |
| 128 | |
| 129 | /* emits 10 + 1 sync (5) = 15 */ |
| 130 | static void |
| 131 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
| 132 | { |
| 133 | u32 sq_vtx_constant_word2, sq_vtx_constant_word3; |
| 134 | |
| 135 | /* high addr, stride */ |
| 136 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 137 | #ifdef __BIG_ENDIAN |
| 138 | sq_vtx_constant_word2 |= (2 << 30); |
| 139 | #endif |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 140 | /* xyzw swizzles */ |
| 141 | sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12); |
| 142 | |
| 143 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); |
| 144 | radeon_ring_write(rdev, 0x580); |
| 145 | radeon_ring_write(rdev, gpu_addr & 0xffffffff); |
| 146 | radeon_ring_write(rdev, 48 - 1); /* size */ |
| 147 | radeon_ring_write(rdev, sq_vtx_constant_word2); |
| 148 | radeon_ring_write(rdev, sq_vtx_constant_word3); |
| 149 | radeon_ring_write(rdev, 0); |
| 150 | radeon_ring_write(rdev, 0); |
| 151 | radeon_ring_write(rdev, 0); |
| 152 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
| 153 | |
Alex Deucher | e719ebd | 2010-11-22 17:56:33 -0500 | [diff] [blame] | 154 | if ((rdev->family == CHIP_CEDAR) || |
Alex Deucher | ff5b856 | 2011-01-06 21:19:28 -0500 | [diff] [blame] | 155 | (rdev->family == CHIP_PALM) || |
| 156 | (rdev->family == CHIP_CAICOS)) |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 157 | cp_set_surface_sync(rdev, |
| 158 | PACKET3_TC_ACTION_ENA, 48, gpu_addr); |
| 159 | else |
| 160 | cp_set_surface_sync(rdev, |
| 161 | PACKET3_VC_ACTION_ENA, 48, gpu_addr); |
| 162 | |
| 163 | } |
| 164 | |
| 165 | /* emits 10 */ |
| 166 | static void |
| 167 | set_tex_resource(struct radeon_device *rdev, |
| 168 | int format, int w, int h, int pitch, |
| 169 | u64 gpu_addr) |
| 170 | { |
| 171 | u32 sq_tex_resource_word0, sq_tex_resource_word1; |
| 172 | u32 sq_tex_resource_word4, sq_tex_resource_word7; |
| 173 | |
| 174 | if (h < 1) |
| 175 | h = 1; |
| 176 | |
| 177 | sq_tex_resource_word0 = (1 << 0); /* 2D */ |
| 178 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) | |
| 179 | ((w - 1) << 18)); |
Alex Deucher | 27dcfc1 | 2011-02-10 14:51:34 -0500 | [diff] [blame] | 180 | sq_tex_resource_word1 = ((h - 1) << 0) | (1 << 28); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 181 | /* xyzw swizzles */ |
| 182 | sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25); |
| 183 | |
| 184 | sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30); |
| 185 | |
| 186 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); |
| 187 | radeon_ring_write(rdev, 0); |
| 188 | radeon_ring_write(rdev, sq_tex_resource_word0); |
| 189 | radeon_ring_write(rdev, sq_tex_resource_word1); |
| 190 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 191 | radeon_ring_write(rdev, gpu_addr >> 8); |
| 192 | radeon_ring_write(rdev, sq_tex_resource_word4); |
| 193 | radeon_ring_write(rdev, 0); |
| 194 | radeon_ring_write(rdev, 0); |
| 195 | radeon_ring_write(rdev, sq_tex_resource_word7); |
| 196 | } |
| 197 | |
| 198 | /* emits 12 */ |
| 199 | static void |
| 200 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
| 201 | int x2, int y2) |
| 202 | { |
Alex Deucher | ac10f81 | 2011-05-25 01:00:45 -0400 | [diff] [blame] | 203 | /* workaround some hw bugs */ |
| 204 | if (x2 == 0) |
| 205 | x1 = 1; |
| 206 | if (y2 == 0) |
| 207 | y1 = 1; |
| 208 | if (rdev->family == CHIP_CAYMAN) { |
| 209 | if ((x2 == 1) && (y2 == 1)) |
| 210 | x2 = 2; |
| 211 | } |
| 212 | |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 213 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 214 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 215 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
| 216 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 217 | |
| 218 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 219 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 220 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| 221 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 222 | |
| 223 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 224 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 225 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| 226 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| 227 | } |
| 228 | |
| 229 | /* emits 10 */ |
| 230 | static void |
| 231 | draw_auto(struct radeon_device *rdev) |
| 232 | { |
| 233 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 234 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); |
| 235 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
| 236 | |
| 237 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 238 | radeon_ring_write(rdev, |
| 239 | #ifdef __BIG_ENDIAN |
| 240 | (2 << 2) | |
| 241 | #endif |
| 242 | DI_INDEX_SIZE_16_BIT); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 243 | |
| 244 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
| 245 | radeon_ring_write(rdev, 1); |
| 246 | |
| 247 | radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
| 248 | radeon_ring_write(rdev, 3); |
| 249 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
| 250 | |
| 251 | } |
| 252 | |
Alex Deucher | 1292059 | 2011-02-02 12:37:40 -0500 | [diff] [blame] | 253 | /* emits 36 */ |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 254 | static void |
| 255 | set_default_state(struct radeon_device *rdev) |
| 256 | { |
| 257 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; |
| 258 | u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; |
| 259 | u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; |
| 260 | int num_ps_gprs, num_vs_gprs, num_temp_gprs; |
| 261 | int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs; |
| 262 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
| 263 | int num_hs_threads, num_ls_threads; |
| 264 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
| 265 | int num_hs_stack_entries, num_ls_stack_entries; |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 266 | u64 gpu_addr; |
| 267 | int dwords; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 268 | |
Alex Deucher | 2281a37 | 2010-10-21 13:31:38 -0400 | [diff] [blame] | 269 | /* set clear context state */ |
| 270 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); |
| 271 | radeon_ring_write(rdev, 0); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 272 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame^] | 273 | if (rdev->family < CHIP_CAYMAN) { |
| 274 | switch (rdev->family) { |
| 275 | case CHIP_CEDAR: |
| 276 | default: |
| 277 | num_ps_gprs = 93; |
| 278 | num_vs_gprs = 46; |
| 279 | num_temp_gprs = 4; |
| 280 | num_gs_gprs = 31; |
| 281 | num_es_gprs = 31; |
| 282 | num_hs_gprs = 23; |
| 283 | num_ls_gprs = 23; |
| 284 | num_ps_threads = 96; |
| 285 | num_vs_threads = 16; |
| 286 | num_gs_threads = 16; |
| 287 | num_es_threads = 16; |
| 288 | num_hs_threads = 16; |
| 289 | num_ls_threads = 16; |
| 290 | num_ps_stack_entries = 42; |
| 291 | num_vs_stack_entries = 42; |
| 292 | num_gs_stack_entries = 42; |
| 293 | num_es_stack_entries = 42; |
| 294 | num_hs_stack_entries = 42; |
| 295 | num_ls_stack_entries = 42; |
| 296 | break; |
| 297 | case CHIP_REDWOOD: |
| 298 | num_ps_gprs = 93; |
| 299 | num_vs_gprs = 46; |
| 300 | num_temp_gprs = 4; |
| 301 | num_gs_gprs = 31; |
| 302 | num_es_gprs = 31; |
| 303 | num_hs_gprs = 23; |
| 304 | num_ls_gprs = 23; |
| 305 | num_ps_threads = 128; |
| 306 | num_vs_threads = 20; |
| 307 | num_gs_threads = 20; |
| 308 | num_es_threads = 20; |
| 309 | num_hs_threads = 20; |
| 310 | num_ls_threads = 20; |
| 311 | num_ps_stack_entries = 42; |
| 312 | num_vs_stack_entries = 42; |
| 313 | num_gs_stack_entries = 42; |
| 314 | num_es_stack_entries = 42; |
| 315 | num_hs_stack_entries = 42; |
| 316 | num_ls_stack_entries = 42; |
| 317 | break; |
| 318 | case CHIP_JUNIPER: |
| 319 | num_ps_gprs = 93; |
| 320 | num_vs_gprs = 46; |
| 321 | num_temp_gprs = 4; |
| 322 | num_gs_gprs = 31; |
| 323 | num_es_gprs = 31; |
| 324 | num_hs_gprs = 23; |
| 325 | num_ls_gprs = 23; |
| 326 | num_ps_threads = 128; |
| 327 | num_vs_threads = 20; |
| 328 | num_gs_threads = 20; |
| 329 | num_es_threads = 20; |
| 330 | num_hs_threads = 20; |
| 331 | num_ls_threads = 20; |
| 332 | num_ps_stack_entries = 85; |
| 333 | num_vs_stack_entries = 85; |
| 334 | num_gs_stack_entries = 85; |
| 335 | num_es_stack_entries = 85; |
| 336 | num_hs_stack_entries = 85; |
| 337 | num_ls_stack_entries = 85; |
| 338 | break; |
| 339 | case CHIP_CYPRESS: |
| 340 | case CHIP_HEMLOCK: |
| 341 | num_ps_gprs = 93; |
| 342 | num_vs_gprs = 46; |
| 343 | num_temp_gprs = 4; |
| 344 | num_gs_gprs = 31; |
| 345 | num_es_gprs = 31; |
| 346 | num_hs_gprs = 23; |
| 347 | num_ls_gprs = 23; |
| 348 | num_ps_threads = 128; |
| 349 | num_vs_threads = 20; |
| 350 | num_gs_threads = 20; |
| 351 | num_es_threads = 20; |
| 352 | num_hs_threads = 20; |
| 353 | num_ls_threads = 20; |
| 354 | num_ps_stack_entries = 85; |
| 355 | num_vs_stack_entries = 85; |
| 356 | num_gs_stack_entries = 85; |
| 357 | num_es_stack_entries = 85; |
| 358 | num_hs_stack_entries = 85; |
| 359 | num_ls_stack_entries = 85; |
| 360 | break; |
| 361 | case CHIP_PALM: |
| 362 | num_ps_gprs = 93; |
| 363 | num_vs_gprs = 46; |
| 364 | num_temp_gprs = 4; |
| 365 | num_gs_gprs = 31; |
| 366 | num_es_gprs = 31; |
| 367 | num_hs_gprs = 23; |
| 368 | num_ls_gprs = 23; |
| 369 | num_ps_threads = 96; |
| 370 | num_vs_threads = 16; |
| 371 | num_gs_threads = 16; |
| 372 | num_es_threads = 16; |
| 373 | num_hs_threads = 16; |
| 374 | num_ls_threads = 16; |
| 375 | num_ps_stack_entries = 42; |
| 376 | num_vs_stack_entries = 42; |
| 377 | num_gs_stack_entries = 42; |
| 378 | num_es_stack_entries = 42; |
| 379 | num_hs_stack_entries = 42; |
| 380 | num_ls_stack_entries = 42; |
| 381 | break; |
| 382 | case CHIP_BARTS: |
| 383 | num_ps_gprs = 93; |
| 384 | num_vs_gprs = 46; |
| 385 | num_temp_gprs = 4; |
| 386 | num_gs_gprs = 31; |
| 387 | num_es_gprs = 31; |
| 388 | num_hs_gprs = 23; |
| 389 | num_ls_gprs = 23; |
| 390 | num_ps_threads = 128; |
| 391 | num_vs_threads = 20; |
| 392 | num_gs_threads = 20; |
| 393 | num_es_threads = 20; |
| 394 | num_hs_threads = 20; |
| 395 | num_ls_threads = 20; |
| 396 | num_ps_stack_entries = 85; |
| 397 | num_vs_stack_entries = 85; |
| 398 | num_gs_stack_entries = 85; |
| 399 | num_es_stack_entries = 85; |
| 400 | num_hs_stack_entries = 85; |
| 401 | num_ls_stack_entries = 85; |
| 402 | break; |
| 403 | case CHIP_TURKS: |
| 404 | num_ps_gprs = 93; |
| 405 | num_vs_gprs = 46; |
| 406 | num_temp_gprs = 4; |
| 407 | num_gs_gprs = 31; |
| 408 | num_es_gprs = 31; |
| 409 | num_hs_gprs = 23; |
| 410 | num_ls_gprs = 23; |
| 411 | num_ps_threads = 128; |
| 412 | num_vs_threads = 20; |
| 413 | num_gs_threads = 20; |
| 414 | num_es_threads = 20; |
| 415 | num_hs_threads = 20; |
| 416 | num_ls_threads = 20; |
| 417 | num_ps_stack_entries = 42; |
| 418 | num_vs_stack_entries = 42; |
| 419 | num_gs_stack_entries = 42; |
| 420 | num_es_stack_entries = 42; |
| 421 | num_hs_stack_entries = 42; |
| 422 | num_ls_stack_entries = 42; |
| 423 | break; |
| 424 | case CHIP_CAICOS: |
| 425 | num_ps_gprs = 93; |
| 426 | num_vs_gprs = 46; |
| 427 | num_temp_gprs = 4; |
| 428 | num_gs_gprs = 31; |
| 429 | num_es_gprs = 31; |
| 430 | num_hs_gprs = 23; |
| 431 | num_ls_gprs = 23; |
| 432 | num_ps_threads = 128; |
| 433 | num_vs_threads = 10; |
| 434 | num_gs_threads = 10; |
| 435 | num_es_threads = 10; |
| 436 | num_hs_threads = 10; |
| 437 | num_ls_threads = 10; |
| 438 | num_ps_stack_entries = 42; |
| 439 | num_vs_stack_entries = 42; |
| 440 | num_gs_stack_entries = 42; |
| 441 | num_es_stack_entries = 42; |
| 442 | num_hs_stack_entries = 42; |
| 443 | num_ls_stack_entries = 42; |
| 444 | break; |
| 445 | } |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 446 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame^] | 447 | if ((rdev->family == CHIP_CEDAR) || |
| 448 | (rdev->family == CHIP_PALM) || |
| 449 | (rdev->family == CHIP_CAICOS)) |
| 450 | sq_config = 0; |
| 451 | else |
| 452 | sq_config = VC_ENABLE; |
| 453 | |
| 454 | sq_config |= (EXPORT_SRC_C | |
| 455 | CS_PRIO(0) | |
| 456 | LS_PRIO(0) | |
| 457 | HS_PRIO(0) | |
| 458 | PS_PRIO(0) | |
| 459 | VS_PRIO(1) | |
| 460 | GS_PRIO(2) | |
| 461 | ES_PRIO(3)); |
| 462 | |
| 463 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
| 464 | NUM_VS_GPRS(num_vs_gprs) | |
| 465 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
| 466 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
| 467 | NUM_ES_GPRS(num_es_gprs)); |
| 468 | sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) | |
| 469 | NUM_LS_GPRS(num_ls_gprs)); |
| 470 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
| 471 | NUM_VS_THREADS(num_vs_threads) | |
| 472 | NUM_GS_THREADS(num_gs_threads) | |
| 473 | NUM_ES_THREADS(num_es_threads)); |
| 474 | sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) | |
| 475 | NUM_LS_THREADS(num_ls_threads)); |
| 476 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
| 477 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
| 478 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
| 479 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
| 480 | sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) | |
| 481 | NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); |
| 482 | |
| 483 | /* disable dyn gprs */ |
| 484 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 485 | radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); |
| 486 | radeon_ring_write(rdev, 0); |
| 487 | |
| 488 | /* SQ config */ |
| 489 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); |
| 490 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); |
| 491 | radeon_ring_write(rdev, sq_config); |
| 492 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
| 493 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
| 494 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_3); |
| 495 | radeon_ring_write(rdev, 0); |
| 496 | radeon_ring_write(rdev, 0); |
| 497 | radeon_ring_write(rdev, sq_thread_resource_mgmt); |
| 498 | radeon_ring_write(rdev, sq_thread_resource_mgmt_2); |
| 499 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
| 500 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
| 501 | radeon_ring_write(rdev, sq_stack_resource_mgmt_3); |
| 502 | } |
Alex Deucher | 2281a37 | 2010-10-21 13:31:38 -0400 | [diff] [blame] | 503 | |
| 504 | /* CONTEXT_CONTROL */ |
| 505 | radeon_ring_write(rdev, 0xc0012800); |
| 506 | radeon_ring_write(rdev, 0x80000000); |
| 507 | radeon_ring_write(rdev, 0x80000000); |
| 508 | |
| 509 | /* SQ_VTX_BASE_VTX_LOC */ |
| 510 | radeon_ring_write(rdev, 0xc0026f00); |
| 511 | radeon_ring_write(rdev, 0x00000000); |
| 512 | radeon_ring_write(rdev, 0x00000000); |
| 513 | radeon_ring_write(rdev, 0x00000000); |
| 514 | |
| 515 | /* SET_SAMPLER */ |
| 516 | radeon_ring_write(rdev, 0xc0036e00); |
| 517 | radeon_ring_write(rdev, 0x00000000); |
| 518 | radeon_ring_write(rdev, 0x00000012); |
| 519 | radeon_ring_write(rdev, 0x00000000); |
| 520 | radeon_ring_write(rdev, 0x00000000); |
| 521 | |
Alex Deucher | 1292059 | 2011-02-02 12:37:40 -0500 | [diff] [blame] | 522 | /* set to DX10/11 mode */ |
| 523 | radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0)); |
| 524 | radeon_ring_write(rdev, 1); |
| 525 | |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 526 | /* emit an IB pointing at default state */ |
| 527 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
| 528 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
| 529 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| 530 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
| 531 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
| 532 | radeon_ring_write(rdev, dwords); |
| 533 | |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 534 | } |
| 535 | |
| 536 | static inline uint32_t i2f(uint32_t input) |
| 537 | { |
| 538 | u32 result, i, exponent, fraction; |
| 539 | |
| 540 | if ((input & 0x3fff) == 0) |
| 541 | result = 0; /* 0 is a special case */ |
| 542 | else { |
| 543 | exponent = 140; /* exponent biased by 127; */ |
| 544 | fraction = (input & 0x3fff) << 10; /* cheat and only |
| 545 | handle numbers below 2^^15 */ |
| 546 | for (i = 0; i < 14; i++) { |
| 547 | if (fraction & 0x800000) |
| 548 | break; |
| 549 | else { |
| 550 | fraction = fraction << 1; /* keep |
| 551 | shifting left until top bit = 1 */ |
| 552 | exponent = exponent - 1; |
| 553 | } |
| 554 | } |
| 555 | result = exponent << 23 | (fraction & 0x7fffff); /* mask |
| 556 | off top bit; assumed 1 */ |
| 557 | } |
| 558 | return result; |
| 559 | } |
| 560 | |
| 561 | int evergreen_blit_init(struct radeon_device *rdev) |
| 562 | { |
| 563 | u32 obj_size; |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 564 | int i, r, dwords; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 565 | void *ptr; |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 566 | u32 packet2s[16]; |
| 567 | int num_packet2s = 0; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 568 | |
| 569 | /* pin copy shader into vram if already initialized */ |
| 570 | if (rdev->r600_blit.shader_obj) |
| 571 | goto done; |
| 572 | |
| 573 | mutex_init(&rdev->r600_blit.mutex); |
| 574 | rdev->r600_blit.state_offset = 0; |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 575 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame^] | 576 | if (rdev->family < CHIP_CAYMAN) |
| 577 | rdev->r600_blit.state_len = evergreen_default_size; |
| 578 | else |
| 579 | rdev->r600_blit.state_len = cayman_default_size; |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 580 | |
| 581 | dwords = rdev->r600_blit.state_len; |
| 582 | while (dwords & 0xf) { |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 583 | packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 584 | dwords++; |
| 585 | } |
| 586 | |
| 587 | obj_size = dwords * 4; |
| 588 | obj_size = ALIGN(obj_size, 256); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 589 | |
| 590 | rdev->r600_blit.vs_offset = obj_size; |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame^] | 591 | if (rdev->family < CHIP_CAYMAN) |
| 592 | obj_size += evergreen_vs_size * 4; |
| 593 | else |
| 594 | obj_size += cayman_vs_size * 4; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 595 | obj_size = ALIGN(obj_size, 256); |
| 596 | |
| 597 | rdev->r600_blit.ps_offset = obj_size; |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame^] | 598 | if (rdev->family < CHIP_CAYMAN) |
| 599 | obj_size += evergreen_ps_size * 4; |
| 600 | else |
| 601 | obj_size += cayman_ps_size * 4; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 602 | obj_size = ALIGN(obj_size, 256); |
| 603 | |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 604 | r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 605 | &rdev->r600_blit.shader_obj); |
| 606 | if (r) { |
| 607 | DRM_ERROR("evergreen failed to allocate shader\n"); |
| 608 | return r; |
| 609 | } |
| 610 | |
| 611 | DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n", |
| 612 | obj_size, |
| 613 | rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); |
| 614 | |
| 615 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| 616 | if (unlikely(r != 0)) |
| 617 | return r; |
| 618 | r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); |
| 619 | if (r) { |
| 620 | DRM_ERROR("failed to map blit object %d\n", r); |
| 621 | return r; |
| 622 | } |
| 623 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame^] | 624 | if (rdev->family < CHIP_CAYMAN) { |
| 625 | memcpy_toio(ptr + rdev->r600_blit.state_offset, |
| 626 | evergreen_default_state, rdev->r600_blit.state_len * 4); |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 627 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame^] | 628 | if (num_packet2s) |
| 629 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
| 630 | packet2s, num_packet2s * 4); |
| 631 | for (i = 0; i < evergreen_vs_size; i++) |
| 632 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); |
| 633 | for (i = 0; i < evergreen_ps_size; i++) |
| 634 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); |
| 635 | } else { |
| 636 | memcpy_toio(ptr + rdev->r600_blit.state_offset, |
| 637 | cayman_default_state, rdev->r600_blit.state_len * 4); |
| 638 | |
| 639 | if (num_packet2s) |
| 640 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
| 641 | packet2s, num_packet2s * 4); |
| 642 | for (i = 0; i < cayman_vs_size; i++) |
| 643 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]); |
| 644 | for (i = 0; i < cayman_ps_size; i++) |
| 645 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]); |
| 646 | } |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 647 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
| 648 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| 649 | |
| 650 | done: |
| 651 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| 652 | if (unlikely(r != 0)) |
| 653 | return r; |
| 654 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
| 655 | &rdev->r600_blit.shader_gpu_addr); |
| 656 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| 657 | if (r) { |
| 658 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
| 659 | return r; |
| 660 | } |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 661 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 662 | return 0; |
| 663 | } |
| 664 | |
| 665 | void evergreen_blit_fini(struct radeon_device *rdev) |
| 666 | { |
| 667 | int r; |
| 668 | |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 669 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 670 | if (rdev->r600_blit.shader_obj == NULL) |
| 671 | return; |
| 672 | /* If we can't reserve the bo, unref should be enough to destroy |
| 673 | * it when it becomes idle. |
| 674 | */ |
| 675 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| 676 | if (!r) { |
| 677 | radeon_bo_unpin(rdev->r600_blit.shader_obj); |
| 678 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| 679 | } |
| 680 | radeon_bo_unref(&rdev->r600_blit.shader_obj); |
| 681 | } |
| 682 | |
| 683 | static int evergreen_vb_ib_get(struct radeon_device *rdev) |
| 684 | { |
| 685 | int r; |
| 686 | r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); |
| 687 | if (r) { |
| 688 | DRM_ERROR("failed to get IB for vertex buffer\n"); |
| 689 | return r; |
| 690 | } |
| 691 | |
| 692 | rdev->r600_blit.vb_total = 64*1024; |
| 693 | rdev->r600_blit.vb_used = 0; |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | static void evergreen_vb_ib_put(struct radeon_device *rdev) |
| 698 | { |
| 699 | radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); |
| 700 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
| 701 | } |
| 702 | |
| 703 | int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) |
| 704 | { |
| 705 | int r; |
| 706 | int ring_size, line_size; |
| 707 | int max_size; |
| 708 | /* loops of emits + fence emit possible */ |
| 709 | int dwords_per_loop = 74, num_loops; |
| 710 | |
| 711 | r = evergreen_vb_ib_get(rdev); |
| 712 | if (r) |
| 713 | return r; |
| 714 | |
| 715 | /* 8 bpp vs 32 bpp for xfer unit */ |
| 716 | if (size_bytes & 3) |
| 717 | line_size = 8192; |
| 718 | else |
| 719 | line_size = 8192 * 4; |
| 720 | |
| 721 | max_size = 8192 * line_size; |
| 722 | |
| 723 | /* major loops cover the max size transfer */ |
| 724 | num_loops = ((size_bytes + max_size) / max_size); |
| 725 | /* minor loops cover the extra non aligned bits */ |
| 726 | num_loops += ((size_bytes % line_size) ? 1 : 0); |
| 727 | /* calculate number of loops correctly */ |
| 728 | ring_size = num_loops * dwords_per_loop; |
| 729 | /* set default + shaders */ |
Alex Deucher | 1292059 | 2011-02-02 12:37:40 -0500 | [diff] [blame] | 730 | ring_size += 52; /* shaders + def state */ |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 731 | ring_size += 10; /* fence emit for VB IB */ |
| 732 | ring_size += 5; /* done copy */ |
| 733 | ring_size += 10; /* fence emit for done copy */ |
| 734 | r = radeon_ring_lock(rdev, ring_size); |
| 735 | if (r) |
| 736 | return r; |
| 737 | |
Alex Deucher | 1292059 | 2011-02-02 12:37:40 -0500 | [diff] [blame] | 738 | set_default_state(rdev); /* 36 */ |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 739 | set_shaders(rdev); /* 16 */ |
| 740 | return 0; |
| 741 | } |
| 742 | |
| 743 | void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) |
| 744 | { |
| 745 | int r; |
| 746 | |
| 747 | if (rdev->r600_blit.vb_ib) |
| 748 | evergreen_vb_ib_put(rdev); |
| 749 | |
| 750 | if (fence) |
| 751 | r = radeon_fence_emit(rdev, fence); |
| 752 | |
| 753 | radeon_ring_unlock_commit(rdev); |
| 754 | } |
| 755 | |
| 756 | void evergreen_kms_blit_copy(struct radeon_device *rdev, |
| 757 | u64 src_gpu_addr, u64 dst_gpu_addr, |
| 758 | int size_bytes) |
| 759 | { |
| 760 | int max_bytes; |
| 761 | u64 vb_gpu_addr; |
| 762 | u32 *vb; |
| 763 | |
| 764 | DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, |
| 765 | size_bytes, rdev->r600_blit.vb_used); |
| 766 | vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); |
| 767 | if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { |
| 768 | max_bytes = 8192; |
| 769 | |
| 770 | while (size_bytes) { |
| 771 | int cur_size = size_bytes; |
| 772 | int src_x = src_gpu_addr & 255; |
| 773 | int dst_x = dst_gpu_addr & 255; |
| 774 | int h = 1; |
Alex Deucher | 2126d0a | 2010-10-06 00:13:04 -0400 | [diff] [blame] | 775 | src_gpu_addr = src_gpu_addr & ~255ULL; |
| 776 | dst_gpu_addr = dst_gpu_addr & ~255ULL; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 777 | |
| 778 | if (!src_x && !dst_x) { |
| 779 | h = (cur_size / max_bytes); |
| 780 | if (h > 8192) |
| 781 | h = 8192; |
| 782 | if (h == 0) |
| 783 | h = 1; |
| 784 | else |
| 785 | cur_size = max_bytes; |
| 786 | } else { |
| 787 | if (cur_size > max_bytes) |
| 788 | cur_size = max_bytes; |
| 789 | if (cur_size > (max_bytes - dst_x)) |
| 790 | cur_size = (max_bytes - dst_x); |
| 791 | if (cur_size > (max_bytes - src_x)) |
| 792 | cur_size = (max_bytes - src_x); |
| 793 | } |
| 794 | |
| 795 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
| 796 | WARN_ON(1); |
| 797 | } |
| 798 | |
| 799 | vb[0] = i2f(dst_x); |
| 800 | vb[1] = 0; |
| 801 | vb[2] = i2f(src_x); |
| 802 | vb[3] = 0; |
| 803 | |
| 804 | vb[4] = i2f(dst_x); |
| 805 | vb[5] = i2f(h); |
| 806 | vb[6] = i2f(src_x); |
| 807 | vb[7] = i2f(h); |
| 808 | |
| 809 | vb[8] = i2f(dst_x + cur_size); |
| 810 | vb[9] = i2f(h); |
| 811 | vb[10] = i2f(src_x + cur_size); |
| 812 | vb[11] = i2f(h); |
| 813 | |
| 814 | /* src 10 */ |
| 815 | set_tex_resource(rdev, FMT_8, |
| 816 | src_x + cur_size, h, src_x + cur_size, |
| 817 | src_gpu_addr); |
| 818 | |
| 819 | /* 5 */ |
| 820 | cp_set_surface_sync(rdev, |
| 821 | PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
| 822 | |
| 823 | |
| 824 | /* dst 17 */ |
| 825 | set_render_target(rdev, COLOR_8, |
| 826 | dst_x + cur_size, h, |
| 827 | dst_gpu_addr); |
| 828 | |
| 829 | /* scissors 12 */ |
| 830 | set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); |
| 831 | |
| 832 | /* 15 */ |
| 833 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
| 834 | set_vtx_resource(rdev, vb_gpu_addr); |
| 835 | |
| 836 | /* draw 10 */ |
| 837 | draw_auto(rdev); |
| 838 | |
| 839 | /* 5 */ |
| 840 | cp_set_surface_sync(rdev, |
| 841 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| 842 | cur_size * h, dst_gpu_addr); |
| 843 | |
| 844 | vb += 12; |
| 845 | rdev->r600_blit.vb_used += 12 * 4; |
| 846 | |
| 847 | src_gpu_addr += cur_size * h; |
| 848 | dst_gpu_addr += cur_size * h; |
| 849 | size_bytes -= cur_size * h; |
| 850 | } |
| 851 | } else { |
| 852 | max_bytes = 8192 * 4; |
| 853 | |
| 854 | while (size_bytes) { |
| 855 | int cur_size = size_bytes; |
| 856 | int src_x = (src_gpu_addr & 255); |
| 857 | int dst_x = (dst_gpu_addr & 255); |
| 858 | int h = 1; |
Alex Deucher | 2126d0a | 2010-10-06 00:13:04 -0400 | [diff] [blame] | 859 | src_gpu_addr = src_gpu_addr & ~255ULL; |
| 860 | dst_gpu_addr = dst_gpu_addr & ~255ULL; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 861 | |
| 862 | if (!src_x && !dst_x) { |
| 863 | h = (cur_size / max_bytes); |
| 864 | if (h > 8192) |
| 865 | h = 8192; |
| 866 | if (h == 0) |
| 867 | h = 1; |
| 868 | else |
| 869 | cur_size = max_bytes; |
| 870 | } else { |
| 871 | if (cur_size > max_bytes) |
| 872 | cur_size = max_bytes; |
| 873 | if (cur_size > (max_bytes - dst_x)) |
| 874 | cur_size = (max_bytes - dst_x); |
| 875 | if (cur_size > (max_bytes - src_x)) |
| 876 | cur_size = (max_bytes - src_x); |
| 877 | } |
| 878 | |
| 879 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
| 880 | WARN_ON(1); |
| 881 | } |
| 882 | |
| 883 | vb[0] = i2f(dst_x / 4); |
| 884 | vb[1] = 0; |
| 885 | vb[2] = i2f(src_x / 4); |
| 886 | vb[3] = 0; |
| 887 | |
| 888 | vb[4] = i2f(dst_x / 4); |
| 889 | vb[5] = i2f(h); |
| 890 | vb[6] = i2f(src_x / 4); |
| 891 | vb[7] = i2f(h); |
| 892 | |
| 893 | vb[8] = i2f((dst_x + cur_size) / 4); |
| 894 | vb[9] = i2f(h); |
| 895 | vb[10] = i2f((src_x + cur_size) / 4); |
| 896 | vb[11] = i2f(h); |
| 897 | |
| 898 | /* src 10 */ |
| 899 | set_tex_resource(rdev, FMT_8_8_8_8, |
| 900 | (src_x + cur_size) / 4, |
| 901 | h, (src_x + cur_size) / 4, |
| 902 | src_gpu_addr); |
| 903 | /* 5 */ |
| 904 | cp_set_surface_sync(rdev, |
| 905 | PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
| 906 | |
| 907 | /* dst 17 */ |
| 908 | set_render_target(rdev, COLOR_8_8_8_8, |
| 909 | (dst_x + cur_size) / 4, h, |
| 910 | dst_gpu_addr); |
| 911 | |
| 912 | /* scissors 12 */ |
| 913 | set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); |
| 914 | |
| 915 | /* Vertex buffer setup 15 */ |
| 916 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
| 917 | set_vtx_resource(rdev, vb_gpu_addr); |
| 918 | |
| 919 | /* draw 10 */ |
| 920 | draw_auto(rdev); |
| 921 | |
| 922 | /* 5 */ |
| 923 | cp_set_surface_sync(rdev, |
| 924 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| 925 | cur_size * h, dst_gpu_addr); |
| 926 | |
| 927 | /* 74 ring dwords per loop */ |
| 928 | vb += 12; |
| 929 | rdev->r600_blit.vb_used += 12 * 4; |
| 930 | |
| 931 | src_gpu_addr += cur_size * h; |
| 932 | dst_gpu_addr += cur_size * h; |
| 933 | size_bytes -= cur_size * h; |
| 934 | } |
| 935 | } |
| 936 | } |
| 937 | |