| Tony Prisk | cb935e7 | 2012-08-03 20:54:16 +1200 | [diff] [blame] | 1 | /* |
| 2 | * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> |
| 5 | * |
| 6 | * Licensed under GPLv2 or later |
| 7 | */ |
| 8 | |
| 9 | /include/ "skeleton.dtsi" |
| 10 | |
| 11 | / { |
| 12 | compatible = "wm,wm8650"; |
| 13 | |
| 14 | soc { |
| 15 | #address-cells = <1>; |
| 16 | #size-cells = <1>; |
| 17 | compatible = "simple-bus"; |
| 18 | ranges; |
| 19 | interrupt-parent = <&intc0>; |
| 20 | |
| 21 | intc0: interrupt-controller@d8140000 { |
| 22 | compatible = "via,vt8500-intc"; |
| 23 | interrupt-controller; |
| 24 | reg = <0xd8140000 0x10000>; |
| 25 | #interrupt-cells = <1>; |
| 26 | }; |
| 27 | |
| 28 | /* Secondary IC cascaded to intc0 */ |
| 29 | intc1: interrupt-controller@d8150000 { |
| 30 | compatible = "via,vt8500-intc"; |
| 31 | interrupt-controller; |
| 32 | #interrupt-cells = <1>; |
| 33 | reg = <0xD8150000 0x10000>; |
| 34 | interrupts = <56 57 58 59 60 61 62 63>; |
| 35 | }; |
| 36 | |
| 37 | gpio: gpio-controller@d8110000 { |
| 38 | compatible = "wm,wm8650-gpio"; |
| 39 | gpio-controller; |
| 40 | reg = <0xd8110000 0x10000>; |
| 41 | #gpio-cells = <3>; |
| 42 | }; |
| 43 | |
| 44 | pmc@d8130000 { |
| 45 | compatible = "via,vt8500-pmc"; |
| 46 | reg = <0xd8130000 0x1000>; |
| 47 | |
| 48 | clocks { |
| 49 | #address-cells = <1>; |
| 50 | #size-cells = <0>; |
| 51 | |
| 52 | ref25: ref25M { |
| 53 | #clock-cells = <0>; |
| 54 | compatible = "fixed-clock"; |
| 55 | clock-frequency = <25000000>; |
| 56 | }; |
| 57 | |
| 58 | ref24: ref24M { |
| 59 | #clock-cells = <0>; |
| 60 | compatible = "fixed-clock"; |
| 61 | clock-frequency = <24000000>; |
| 62 | }; |
| 63 | |
| 64 | plla: plla { |
| 65 | #clock-cells = <0>; |
| 66 | compatible = "wm,wm8650-pll-clock"; |
| 67 | clocks = <&ref25>; |
| 68 | reg = <0x200>; |
| 69 | }; |
| 70 | |
| 71 | pllb: pllb { |
| 72 | #clock-cells = <0>; |
| 73 | compatible = "wm,wm8650-pll-clock"; |
| 74 | clocks = <&ref25>; |
| 75 | reg = <0x204>; |
| 76 | }; |
| 77 | |
| 78 | arm: arm { |
| 79 | #clock-cells = <0>; |
| 80 | compatible = "via,vt8500-device-clock"; |
| 81 | clocks = <&plla>; |
| 82 | divisor-reg = <0x300>; |
| 83 | }; |
| 84 | |
| 85 | sdhc: sdhc { |
| 86 | #clock-cells = <0>; |
| 87 | compatible = "via,vt8500-device-clock"; |
| 88 | clocks = <&pllb>; |
| 89 | divisor-reg = <0x328>; |
| 90 | divisor-mask = <0x3f>; |
| 91 | enable-reg = <0x254>; |
| 92 | enable-bit = <18>; |
| 93 | }; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | timer@d8130100 { |
| 98 | compatible = "via,vt8500-timer"; |
| 99 | reg = <0xd8130100 0x28>; |
| 100 | interrupts = <36>; |
| 101 | }; |
| 102 | |
| 103 | ehci@d8007900 { |
| 104 | compatible = "via,vt8500-ehci"; |
| 105 | reg = <0xd8007900 0x200>; |
| 106 | interrupts = <43>; |
| 107 | }; |
| 108 | |
| 109 | uhci@d8007b00 { |
| 110 | compatible = "platform-uhci"; |
| 111 | reg = <0xd8007b00 0x200>; |
| 112 | interrupts = <43>; |
| 113 | }; |
| 114 | |
| 115 | fb@d8050800 { |
| 116 | compatible = "wm,wm8505-fb"; |
| 117 | reg = <0xd8050800 0x200>; |
| 118 | display = <&display>; |
| 119 | default-mode = <&mode0>; |
| 120 | }; |
| 121 | |
| 122 | ge_rops@d8050400 { |
| 123 | compatible = "wm,prizm-ge-rops"; |
| 124 | reg = <0xd8050400 0x100>; |
| 125 | }; |
| 126 | |
| 127 | uart@d8200000 { |
| 128 | compatible = "via,vt8500-uart"; |
| 129 | reg = <0xd8200000 0x1040>; |
| 130 | interrupts = <32>; |
| 131 | clocks = <&ref24>; |
| 132 | }; |
| 133 | |
| 134 | uart@d82b0000 { |
| 135 | compatible = "via,vt8500-uart"; |
| 136 | reg = <0xd82b0000 0x1040>; |
| 137 | interrupts = <33>; |
| 138 | clocks = <&ref24>; |
| 139 | }; |
| 140 | |
| 141 | rtc@d8100000 { |
| 142 | compatible = "via,vt8500-rtc"; |
| 143 | reg = <0xd8100000 0x10000>; |
| 144 | interrupts = <48>; |
| 145 | }; |
| 146 | }; |
| 147 | }; |