blob: 050835e39aa3569769e25e00bc18cfdeb2161b5a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* cg6.c: CGSIX (GX, GXplus, TGX) frame buffer driver
2 *
3 * Copyright (C) 2003 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
5 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 *
8 * Driver layout based loosely on tgafb.c, see that file for credits.
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/fb.h>
19#include <linux/mm.h>
20
21#include <asm/io.h>
22#include <asm/sbus.h>
23#include <asm/oplib.h>
24#include <asm/fbio.h>
25
26#include "sbuslib.h"
27
28/*
29 * Local functions.
30 */
31
32static int cg6_setcolreg(unsigned, unsigned, unsigned, unsigned,
33 unsigned, struct fb_info *);
34static int cg6_blank(int, struct fb_info *);
35
36static void cg6_imageblit(struct fb_info *, const struct fb_image *);
37static void cg6_fillrect(struct fb_info *, const struct fb_fillrect *);
38static int cg6_sync(struct fb_info *);
39static int cg6_mmap(struct fb_info *, struct file *, struct vm_area_struct *);
40static int cg6_ioctl(struct inode *, struct file *, unsigned int,
41 unsigned long, struct fb_info *);
42
43/*
44 * Frame buffer operations
45 */
46
47static struct fb_ops cg6_ops = {
48 .owner = THIS_MODULE,
49 .fb_setcolreg = cg6_setcolreg,
50 .fb_blank = cg6_blank,
51 .fb_fillrect = cg6_fillrect,
52 .fb_copyarea = cfb_copyarea,
53 .fb_imageblit = cg6_imageblit,
54 .fb_sync = cg6_sync,
55 .fb_mmap = cg6_mmap,
56 .fb_ioctl = cg6_ioctl,
Christoph Hellwig9ffb83b2005-11-12 12:11:12 -080057#ifdef CONFIG_COMPAT
58 .fb_compat_ioctl = sbusfb_compat_ioctl,
59#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070060};
61
62/* Offset of interesting structures in the OBIO space */
63/*
64 * Brooktree is the video dac and is funny to program on the cg6.
65 * (it's even funnier on the cg3)
66 * The FBC could be the frame buffer control
67 * The FHC could is the frame buffer hardware control.
68 */
69#define CG6_ROM_OFFSET 0x0UL
70#define CG6_BROOKTREE_OFFSET 0x200000UL
71#define CG6_DHC_OFFSET 0x240000UL
72#define CG6_ALT_OFFSET 0x280000UL
73#define CG6_FHC_OFFSET 0x300000UL
74#define CG6_THC_OFFSET 0x301000UL
75#define CG6_FBC_OFFSET 0x700000UL
76#define CG6_TEC_OFFSET 0x701000UL
77#define CG6_RAM_OFFSET 0x800000UL
78
79/* FHC definitions */
80#define CG6_FHC_FBID_SHIFT 24
81#define CG6_FHC_FBID_MASK 255
82#define CG6_FHC_REV_SHIFT 20
83#define CG6_FHC_REV_MASK 15
84#define CG6_FHC_FROP_DISABLE (1 << 19)
85#define CG6_FHC_ROW_DISABLE (1 << 18)
86#define CG6_FHC_SRC_DISABLE (1 << 17)
87#define CG6_FHC_DST_DISABLE (1 << 16)
88#define CG6_FHC_RESET (1 << 15)
89#define CG6_FHC_LITTLE_ENDIAN (1 << 13)
90#define CG6_FHC_RES_MASK (3 << 11)
91#define CG6_FHC_1024 (0 << 11)
92#define CG6_FHC_1152 (1 << 11)
93#define CG6_FHC_1280 (2 << 11)
94#define CG6_FHC_1600 (3 << 11)
95#define CG6_FHC_CPU_MASK (3 << 9)
96#define CG6_FHC_CPU_SPARC (0 << 9)
97#define CG6_FHC_CPU_68020 (1 << 9)
98#define CG6_FHC_CPU_386 (2 << 9)
99#define CG6_FHC_TEST (1 << 8)
100#define CG6_FHC_TEST_X_SHIFT 4
101#define CG6_FHC_TEST_X_MASK 15
102#define CG6_FHC_TEST_Y_SHIFT 0
103#define CG6_FHC_TEST_Y_MASK 15
104
105/* FBC mode definitions */
106#define CG6_FBC_BLIT_IGNORE 0x00000000
107#define CG6_FBC_BLIT_NOSRC 0x00100000
108#define CG6_FBC_BLIT_SRC 0x00200000
109#define CG6_FBC_BLIT_ILLEGAL 0x00300000
110#define CG6_FBC_BLIT_MASK 0x00300000
111
112#define CG6_FBC_VBLANK 0x00080000
113
114#define CG6_FBC_MODE_IGNORE 0x00000000
115#define CG6_FBC_MODE_COLOR8 0x00020000
116#define CG6_FBC_MODE_COLOR1 0x00040000
117#define CG6_FBC_MODE_HRMONO 0x00060000
118#define CG6_FBC_MODE_MASK 0x00060000
119
120#define CG6_FBC_DRAW_IGNORE 0x00000000
121#define CG6_FBC_DRAW_RENDER 0x00008000
122#define CG6_FBC_DRAW_PICK 0x00010000
123#define CG6_FBC_DRAW_ILLEGAL 0x00018000
124#define CG6_FBC_DRAW_MASK 0x00018000
125
126#define CG6_FBC_BWRITE0_IGNORE 0x00000000
127#define CG6_FBC_BWRITE0_ENABLE 0x00002000
128#define CG6_FBC_BWRITE0_DISABLE 0x00004000
129#define CG6_FBC_BWRITE0_ILLEGAL 0x00006000
130#define CG6_FBC_BWRITE0_MASK 0x00006000
131
132#define CG6_FBC_BWRITE1_IGNORE 0x00000000
133#define CG6_FBC_BWRITE1_ENABLE 0x00000800
134#define CG6_FBC_BWRITE1_DISABLE 0x00001000
135#define CG6_FBC_BWRITE1_ILLEGAL 0x00001800
136#define CG6_FBC_BWRITE1_MASK 0x00001800
137
138#define CG6_FBC_BREAD_IGNORE 0x00000000
139#define CG6_FBC_BREAD_0 0x00000200
140#define CG6_FBC_BREAD_1 0x00000400
141#define CG6_FBC_BREAD_ILLEGAL 0x00000600
142#define CG6_FBC_BREAD_MASK 0x00000600
143
144#define CG6_FBC_BDISP_IGNORE 0x00000000
145#define CG6_FBC_BDISP_0 0x00000080
146#define CG6_FBC_BDISP_1 0x00000100
147#define CG6_FBC_BDISP_ILLEGAL 0x00000180
148#define CG6_FBC_BDISP_MASK 0x00000180
149
150#define CG6_FBC_INDEX_MOD 0x00000040
151#define CG6_FBC_INDEX_MASK 0x00000030
152
153/* THC definitions */
154#define CG6_THC_MISC_REV_SHIFT 16
155#define CG6_THC_MISC_REV_MASK 15
156#define CG6_THC_MISC_RESET (1 << 12)
157#define CG6_THC_MISC_VIDEO (1 << 10)
158#define CG6_THC_MISC_SYNC (1 << 9)
159#define CG6_THC_MISC_VSYNC (1 << 8)
160#define CG6_THC_MISC_SYNC_ENAB (1 << 7)
161#define CG6_THC_MISC_CURS_RES (1 << 6)
162#define CG6_THC_MISC_INT_ENAB (1 << 5)
163#define CG6_THC_MISC_INT (1 << 4)
164#define CG6_THC_MISC_INIT 0x9f
165
166/* The contents are unknown */
167struct cg6_tec {
168 volatile int tec_matrix;
169 volatile int tec_clip;
170 volatile int tec_vdc;
171};
172
173struct cg6_thc {
174 uint thc_pad0[512];
175 volatile uint thc_hs; /* hsync timing */
176 volatile uint thc_hsdvs;
177 volatile uint thc_hd;
178 volatile uint thc_vs; /* vsync timing */
179 volatile uint thc_vd;
180 volatile uint thc_refresh;
181 volatile uint thc_misc;
182 uint thc_pad1[56];
183 volatile uint thc_cursxy; /* cursor x,y position (16 bits each) */
184 volatile uint thc_cursmask[32]; /* cursor mask bits */
185 volatile uint thc_cursbits[32]; /* what to show where mask enabled */
186};
187
188struct cg6_fbc {
189 u32 xxx0[1];
190 volatile u32 mode;
191 volatile u32 clip;
192 u32 xxx1[1];
193 volatile u32 s;
194 volatile u32 draw;
195 volatile u32 blit;
196 volatile u32 font;
197 u32 xxx2[24];
198 volatile u32 x0, y0, z0, color0;
199 volatile u32 x1, y1, z1, color1;
200 volatile u32 x2, y2, z2, color2;
201 volatile u32 x3, y3, z3, color3;
202 volatile u32 offx, offy;
203 u32 xxx3[2];
204 volatile u32 incx, incy;
205 u32 xxx4[2];
206 volatile u32 clipminx, clipminy;
207 u32 xxx5[2];
208 volatile u32 clipmaxx, clipmaxy;
209 u32 xxx6[2];
210 volatile u32 fg;
211 volatile u32 bg;
212 volatile u32 alu;
213 volatile u32 pm;
214 volatile u32 pixelm;
215 u32 xxx7[2];
216 volatile u32 patalign;
217 volatile u32 pattern[8];
218 u32 xxx8[432];
219 volatile u32 apointx, apointy, apointz;
220 u32 xxx9[1];
221 volatile u32 rpointx, rpointy, rpointz;
222 u32 xxx10[5];
223 volatile u32 pointr, pointg, pointb, pointa;
224 volatile u32 alinex, aliney, alinez;
225 u32 xxx11[1];
226 volatile u32 rlinex, rliney, rlinez;
227 u32 xxx12[5];
228 volatile u32 liner, lineg, lineb, linea;
229 volatile u32 atrix, atriy, atriz;
230 u32 xxx13[1];
231 volatile u32 rtrix, rtriy, rtriz;
232 u32 xxx14[5];
233 volatile u32 trir, trig, trib, tria;
234 volatile u32 aquadx, aquady, aquadz;
235 u32 xxx15[1];
236 volatile u32 rquadx, rquady, rquadz;
237 u32 xxx16[5];
238 volatile u32 quadr, quadg, quadb, quada;
239 volatile u32 arectx, arecty, arectz;
240 u32 xxx17[1];
241 volatile u32 rrectx, rrecty, rrectz;
242 u32 xxx18[5];
243 volatile u32 rectr, rectg, rectb, recta;
244};
245
246struct bt_regs {
247 volatile u32 addr;
248 volatile u32 color_map;
249 volatile u32 control;
250 volatile u32 cursor;
251};
252
253struct cg6_par {
254 spinlock_t lock;
255 struct bt_regs __iomem *bt;
256 struct cg6_fbc __iomem *fbc;
257 struct cg6_thc __iomem *thc;
258 struct cg6_tec __iomem *tec;
259 volatile u32 __iomem *fhc;
260
261 u32 flags;
262#define CG6_FLAG_BLANKED 0x00000001
263
264 unsigned long physbase;
265 unsigned long fbsize;
266
267 struct sbus_dev *sdev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268};
269
270static int cg6_sync(struct fb_info *info)
271{
272 struct cg6_par *par = (struct cg6_par *) info->par;
273 struct cg6_fbc __iomem *fbc = par->fbc;
274 int limit = 10000;
275
276 do {
277 if (!(sbus_readl(&fbc->s) & 0x10000000))
278 break;
279 udelay(10);
280 } while (--limit > 0);
281
282 return 0;
283}
284
285/**
286 * cg6_fillrect - REQUIRED function. Can use generic routines if
287 * non acclerated hardware and packed pixel based.
288 * Draws a rectangle on the screen.
289 *
290 * @info: frame buffer structure that represents a single frame buffer
291 * @rect: structure defining the rectagle and operation.
292 */
293static void cg6_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
294{
295 struct cg6_par *par = (struct cg6_par *) info->par;
296 struct cg6_fbc __iomem *fbc = par->fbc;
297 unsigned long flags;
298 s32 val;
299
300 /* XXX doesn't handle ROP_XOR */
301
302 spin_lock_irqsave(&par->lock, flags);
303 cg6_sync(info);
304 sbus_writel(rect->color, &fbc->fg);
305 sbus_writel(~(u32)0, &fbc->pixelm);
306 sbus_writel(0xea80ff00, &fbc->alu);
307 sbus_writel(0, &fbc->s);
308 sbus_writel(0, &fbc->clip);
309 sbus_writel(~(u32)0, &fbc->pm);
310 sbus_writel(rect->dy, &fbc->arecty);
311 sbus_writel(rect->dx, &fbc->arectx);
312 sbus_writel(rect->dy + rect->height, &fbc->arecty);
313 sbus_writel(rect->dx + rect->width, &fbc->arectx);
314 do {
315 val = sbus_readl(&fbc->draw);
316 } while (val < 0 && (val & 0x20000000));
317 spin_unlock_irqrestore(&par->lock, flags);
318}
319
320/**
321 * cg6_imageblit - REQUIRED function. Can use generic routines if
322 * non acclerated hardware and packed pixel based.
323 * Copies a image from system memory to the screen.
324 *
325 * @info: frame buffer structure that represents a single frame buffer
326 * @image: structure defining the image.
327 */
328static void cg6_imageblit(struct fb_info *info, const struct fb_image *image)
329{
330 struct cg6_par *par = (struct cg6_par *) info->par;
331 struct cg6_fbc __iomem *fbc = par->fbc;
332 const u8 *data = image->data;
333 unsigned long flags;
334 u32 x, y;
335 int i, width;
336
337 if (image->depth > 1) {
338 cfb_imageblit(info, image);
339 return;
340 }
341
342 spin_lock_irqsave(&par->lock, flags);
343
344 cg6_sync(info);
345
346 sbus_writel(image->fg_color, &fbc->fg);
347 sbus_writel(image->bg_color, &fbc->bg);
348 sbus_writel(0x140000, &fbc->mode);
349 sbus_writel(0xe880fc30, &fbc->alu);
350 sbus_writel(~(u32)0, &fbc->pixelm);
351 sbus_writel(0, &fbc->s);
352 sbus_writel(0, &fbc->clip);
353 sbus_writel(0xff, &fbc->pm);
354 sbus_writel(32, &fbc->incx);
355 sbus_writel(0, &fbc->incy);
356
357 x = image->dx;
358 y = image->dy;
359 for (i = 0; i < image->height; i++) {
360 width = image->width;
361
362 while (width >= 32) {
363 u32 val;
364
365 sbus_writel(y, &fbc->y0);
366 sbus_writel(x, &fbc->x0);
367 sbus_writel(x + 32 - 1, &fbc->x1);
368
369 val = ((u32)data[0] << 24) |
370 ((u32)data[1] << 16) |
371 ((u32)data[2] << 8) |
372 ((u32)data[3] << 0);
373 sbus_writel(val, &fbc->font);
374
375 data += 4;
376 x += 32;
377 width -= 32;
378 }
379 if (width) {
380 u32 val;
381
382 sbus_writel(y, &fbc->y0);
383 sbus_writel(x, &fbc->x0);
384 sbus_writel(x + width - 1, &fbc->x1);
385 if (width <= 8) {
386 val = (u32) data[0] << 24;
387 data += 1;
388 } else if (width <= 16) {
389 val = ((u32) data[0] << 24) |
390 ((u32) data[1] << 16);
391 data += 2;
392 } else {
393 val = ((u32) data[0] << 24) |
394 ((u32) data[1] << 16) |
395 ((u32) data[2] << 8);
396 data += 3;
397 }
398 sbus_writel(val, &fbc->font);
399 }
400
401 y += 1;
402 x = image->dx;
403 }
404
405 spin_unlock_irqrestore(&par->lock, flags);
406}
407
408/**
409 * cg6_setcolreg - Optional function. Sets a color register.
410 * @regno: boolean, 0 copy local, 1 get_user() function
411 * @red: frame buffer colormap structure
412 * @green: The green value which can be up to 16 bits wide
413 * @blue: The blue value which can be up to 16 bits wide.
414 * @transp: If supported the alpha value which can be up to 16 bits wide.
415 * @info: frame buffer info structure
416 */
417static int cg6_setcolreg(unsigned regno,
418 unsigned red, unsigned green, unsigned blue,
419 unsigned transp, struct fb_info *info)
420{
421 struct cg6_par *par = (struct cg6_par *) info->par;
422 struct bt_regs __iomem *bt = par->bt;
423 unsigned long flags;
424
425 if (regno >= 256)
426 return 1;
427
428 red >>= 8;
429 green >>= 8;
430 blue >>= 8;
431
432 spin_lock_irqsave(&par->lock, flags);
433
434 sbus_writel((u32)regno << 24, &bt->addr);
435 sbus_writel((u32)red << 24, &bt->color_map);
436 sbus_writel((u32)green << 24, &bt->color_map);
437 sbus_writel((u32)blue << 24, &bt->color_map);
438
439 spin_unlock_irqrestore(&par->lock, flags);
440
441 return 0;
442}
443
444/**
445 * cg6_blank - Optional function. Blanks the display.
446 * @blank_mode: the blank mode we want.
447 * @info: frame buffer structure that represents a single frame buffer
448 */
449static int
450cg6_blank(int blank, struct fb_info *info)
451{
452 struct cg6_par *par = (struct cg6_par *) info->par;
453 struct cg6_thc __iomem *thc = par->thc;
454 unsigned long flags;
455 u32 val;
456
457 spin_lock_irqsave(&par->lock, flags);
458
459 switch (blank) {
460 case FB_BLANK_UNBLANK: /* Unblanking */
461 val = sbus_readl(&thc->thc_misc);
462 val |= CG6_THC_MISC_VIDEO;
463 sbus_writel(val, &thc->thc_misc);
464 par->flags &= ~CG6_FLAG_BLANKED;
465 break;
466
467 case FB_BLANK_NORMAL: /* Normal blanking */
468 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
469 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
470 case FB_BLANK_POWERDOWN: /* Poweroff */
471 val = sbus_readl(&thc->thc_misc);
472 val &= ~CG6_THC_MISC_VIDEO;
473 sbus_writel(val, &thc->thc_misc);
474 par->flags |= CG6_FLAG_BLANKED;
475 break;
476 }
477
478 spin_unlock_irqrestore(&par->lock, flags);
479
480 return 0;
481}
482
483static struct sbus_mmap_map cg6_mmap_map[] = {
484 {
485 .voff = CG6_FBC,
486 .poff = CG6_FBC_OFFSET,
487 .size = PAGE_SIZE
488 },
489 {
490 .voff = CG6_TEC,
491 .poff = CG6_TEC_OFFSET,
492 .size = PAGE_SIZE
493 },
494 {
495 .voff = CG6_BTREGS,
496 .poff = CG6_BROOKTREE_OFFSET,
497 .size = PAGE_SIZE
498 },
499 {
500 .voff = CG6_FHC,
501 .poff = CG6_FHC_OFFSET,
502 .size = PAGE_SIZE
503 },
504 {
505 .voff = CG6_THC,
506 .poff = CG6_THC_OFFSET,
507 .size = PAGE_SIZE
508 },
509 {
510 .voff = CG6_ROM,
511 .poff = CG6_ROM_OFFSET,
512 .size = 0x10000
513 },
514 {
515 .voff = CG6_RAM,
516 .poff = CG6_RAM_OFFSET,
517 .size = SBUS_MMAP_FBSIZE(1)
518 },
519 {
520 .voff = CG6_DHC,
521 .poff = CG6_DHC_OFFSET,
522 .size = 0x40000
523 },
524 { .size = 0 }
525};
526
527static int cg6_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
528{
529 struct cg6_par *par = (struct cg6_par *)info->par;
530
531 return sbusfb_mmap_helper(cg6_mmap_map,
532 par->physbase, par->fbsize,
533 par->sdev->reg_addrs[0].which_io,
534 vma);
535}
536
537static int cg6_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
538 unsigned long arg, struct fb_info *info)
539{
540 struct cg6_par *par = (struct cg6_par *) info->par;
541
542 return sbusfb_ioctl_helper(cmd, arg, info,
543 FBTYPE_SUNFAST_COLOR, 8, par->fbsize);
544}
545
546/*
547 * Initialisation
548 */
549
550static void
551cg6_init_fix(struct fb_info *info, int linebytes)
552{
553 struct cg6_par *par = (struct cg6_par *)info->par;
554 const char *cg6_cpu_name, *cg6_card_name;
555 u32 conf;
556
557 conf = sbus_readl(par->fhc);
558 switch(conf & CG6_FHC_CPU_MASK) {
559 case CG6_FHC_CPU_SPARC:
560 cg6_cpu_name = "sparc";
561 break;
562 case CG6_FHC_CPU_68020:
563 cg6_cpu_name = "68020";
564 break;
565 default:
566 cg6_cpu_name = "i386";
567 break;
568 };
569 if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) {
570 if (par->fbsize <= 0x100000) {
571 cg6_card_name = "TGX";
572 } else {
573 cg6_card_name = "TGX+";
574 }
575 } else {
576 if (par->fbsize <= 0x100000) {
577 cg6_card_name = "GX";
578 } else {
579 cg6_card_name = "GX+";
580 }
581 }
582
583 sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name);
584 info->fix.id[sizeof(info->fix.id)-1] = 0;
585
586 info->fix.type = FB_TYPE_PACKED_PIXELS;
587 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
588
589 info->fix.line_length = linebytes;
590
591 info->fix.accel = FB_ACCEL_SUN_CGSIX;
592}
593
594/* Initialize Brooktree DAC */
595static void cg6_bt_init(struct cg6_par *par)
596{
597 struct bt_regs __iomem *bt = par->bt;
598
599 sbus_writel(0x04 << 24, &bt->addr); /* color planes */
600 sbus_writel(0xff << 24, &bt->control);
601 sbus_writel(0x05 << 24, &bt->addr);
602 sbus_writel(0x00 << 24, &bt->control);
603 sbus_writel(0x06 << 24, &bt->addr); /* overlay plane */
604 sbus_writel(0x73 << 24, &bt->control);
605 sbus_writel(0x07 << 24, &bt->addr);
606 sbus_writel(0x00 << 24, &bt->control);
607}
608
609static void cg6_chip_init(struct fb_info *info)
610{
611 struct cg6_par *par = (struct cg6_par *) info->par;
612 struct cg6_tec __iomem *tec = par->tec;
613 struct cg6_fbc __iomem *fbc = par->fbc;
David S. Miller806f7bf2005-12-12 14:41:20 -0800614 u32 rev, conf, mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 int i;
616
617 /* Turn off stuff in the Transform Engine. */
618 sbus_writel(0, &tec->tec_matrix);
619 sbus_writel(0, &tec->tec_clip);
620 sbus_writel(0, &tec->tec_vdc);
621
622 /* Take care of bugs in old revisions. */
623 rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK;
624 if (rev < 5) {
625 conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) |
626 CG6_FHC_CPU_68020 | CG6_FHC_TEST |
627 (11 << CG6_FHC_TEST_X_SHIFT) |
628 (11 << CG6_FHC_TEST_Y_SHIFT);
629 if (rev < 2)
630 conf |= CG6_FHC_DST_DISABLE;
631 sbus_writel(conf, par->fhc);
632 }
633
634 /* Set things in the FBC. Bad things appear to happen if we do
635 * back to back store/loads on the mode register, so copy it
636 * out instead. */
637 mode = sbus_readl(&fbc->mode);
638 do {
639 i = sbus_readl(&fbc->s);
640 } while (i & 0x10000000);
641 mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK |
642 CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK |
643 CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK |
644 CG6_FBC_BDISP_MASK);
645 mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 |
646 CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE |
647 CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 |
648 CG6_FBC_BDISP_0);
649 sbus_writel(mode, &fbc->mode);
650
651 sbus_writel(0, &fbc->clip);
652 sbus_writel(0, &fbc->offx);
653 sbus_writel(0, &fbc->offy);
654 sbus_writel(0, &fbc->clipminx);
655 sbus_writel(0, &fbc->clipminy);
656 sbus_writel(info->var.xres - 1, &fbc->clipmaxx);
657 sbus_writel(info->var.yres - 1, &fbc->clipmaxy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658}
659
660struct all_info {
661 struct fb_info info;
662 struct cg6_par par;
663 struct list_head list;
664};
665static LIST_HEAD(cg6_list);
666
667static void cg6_init_one(struct sbus_dev *sdev)
668{
669 struct all_info *all;
670 int linebytes;
671
672 all = kmalloc(sizeof(*all), GFP_KERNEL);
673 if (!all) {
674 printk(KERN_ERR "cg6: Cannot allocate memory.\n");
675 return;
676 }
677 memset(all, 0, sizeof(*all));
678
679 INIT_LIST_HEAD(&all->list);
680
681 spin_lock_init(&all->par.lock);
682 all->par.sdev = sdev;
683
684 all->par.physbase = sdev->reg_addrs[0].phys_addr;
685
686 sbusfb_fill_var(&all->info.var, sdev->prom_node, 8);
687 all->info.var.red.length = 8;
688 all->info.var.green.length = 8;
689 all->info.var.blue.length = 8;
690
691 linebytes = prom_getintdefault(sdev->prom_node, "linebytes",
692 all->info.var.xres);
693 all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
694 if (prom_getbool(sdev->prom_node, "dblbuf"))
695 all->par.fbsize *= 4;
696
697 all->par.fbc = sbus_ioremap(&sdev->resource[0], CG6_FBC_OFFSET,
698 4096, "cgsix fbc");
699 all->par.tec = sbus_ioremap(&sdev->resource[0], CG6_TEC_OFFSET,
700 sizeof(struct cg6_tec), "cgsix tec");
701 all->par.thc = sbus_ioremap(&sdev->resource[0], CG6_THC_OFFSET,
702 sizeof(struct cg6_thc), "cgsix thc");
703 all->par.bt = sbus_ioremap(&sdev->resource[0], CG6_BROOKTREE_OFFSET,
704 sizeof(struct bt_regs), "cgsix dac");
705 all->par.fhc = sbus_ioremap(&sdev->resource[0], CG6_FHC_OFFSET,
706 sizeof(u32), "cgsix fhc");
707
708 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT |
709 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
710 all->info.fbops = &cg6_ops;
711#ifdef CONFIG_SPARC32
712 all->info.screen_base = (char __iomem *)
713 prom_getintdefault(sdev->prom_node, "address", 0);
714#endif
715 if (!all->info.screen_base)
716 all->info.screen_base =
717 sbus_ioremap(&sdev->resource[0], CG6_RAM_OFFSET,
718 all->par.fbsize, "cgsix ram");
719 all->info.par = &all->par;
720
721 all->info.var.accel_flags = FB_ACCELF_TEXT;
722
723 cg6_bt_init(&all->par);
724 cg6_chip_init(&all->info);
725 cg6_blank(0, &all->info);
726
727 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
728 printk(KERN_ERR "cg6: Could not allocate color map.\n");
729 kfree(all);
730 return;
731 }
732
733 fb_set_cmap(&all->info.cmap, &all->info);
734 cg6_init_fix(&all->info, linebytes);
735
736 if (register_framebuffer(&all->info) < 0) {
737 printk(KERN_ERR "cg6: Could not register framebuffer.\n");
738 fb_dealloc_cmap(&all->info.cmap);
739 kfree(all);
740 return;
741 }
742
743 list_add(&all->list, &cg6_list);
744
745 printk("cg6: CGsix [%s] at %lx:%lx\n",
746 all->info.fix.id,
747 (long) sdev->reg_addrs[0].which_io,
748 (long) sdev->reg_addrs[0].phys_addr);
749}
750
751int __init cg6_init(void)
752{
753 struct sbus_bus *sbus;
754 struct sbus_dev *sdev;
755
756 if (fb_get_options("cg6fb", NULL))
757 return -ENODEV;
758
759 for_all_sbusdev(sdev, sbus) {
760 if (!strcmp(sdev->prom_name, "cgsix") ||
761 !strcmp(sdev->prom_name, "cgthree+"))
762 cg6_init_one(sdev);
763 }
764
765 return 0;
766}
767
768void __exit cg6_exit(void)
769{
770 struct list_head *pos, *tmp;
771
772 list_for_each_safe(pos, tmp, &cg6_list) {
773 struct all_info *all = list_entry(pos, typeof(*all), list);
774
775 unregister_framebuffer(&all->info);
776 fb_dealloc_cmap(&all->info.cmap);
777 kfree(all);
778 }
779}
780
781int __init
782cg6_setup(char *arg)
783{
784 /* No cmdline options yet... */
785 return 0;
786}
787
788module_init(cg6_init);
789
790#ifdef MODULE
791module_exit(cg6_exit);
792#endif
793
794MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets");
795MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
796MODULE_LICENSE("GPL");