Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> |
| 3 | * Copyright © 2004 Micron Technology Inc. |
| 4 | * Copyright © 2004 David Brownell |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/platform_device.h> |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 12 | #include <linux/dmaengine.h> |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 13 | #include <linux/dma-mapping.h> |
| 14 | #include <linux/delay.h> |
Paul Gortmaker | a0e5cc5 | 2011-07-03 15:17:31 -0400 | [diff] [blame] | 15 | #include <linux/module.h> |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 16 | #include <linux/interrupt.h> |
vimal singh | c276aca | 2009-06-27 11:07:06 +0530 | [diff] [blame] | 17 | #include <linux/jiffies.h> |
| 18 | #include <linux/sched.h> |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 19 | #include <linux/mtd/mtd.h> |
| 20 | #include <linux/mtd/nand.h> |
| 21 | #include <linux/mtd/partitions.h> |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 22 | #include <linux/omap-dma.h> |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 23 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 24 | #include <linux/slab.h> |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 25 | |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 26 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
| 27 | #include <linux/bch.h> |
| 28 | #endif |
| 29 | |
Arnd Bergmann | 2203747 | 2012-08-24 15:21:06 +0200 | [diff] [blame] | 30 | #include <linux/platform_data/mtd-nand-omap2.h> |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 31 | |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 32 | #define DRIVER_NAME "omap2-nand" |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 33 | #define OMAP_NAND_TIMEOUT_MS 5000 |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 34 | |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 35 | #define NAND_Ecc_P1e (1 << 0) |
| 36 | #define NAND_Ecc_P2e (1 << 1) |
| 37 | #define NAND_Ecc_P4e (1 << 2) |
| 38 | #define NAND_Ecc_P8e (1 << 3) |
| 39 | #define NAND_Ecc_P16e (1 << 4) |
| 40 | #define NAND_Ecc_P32e (1 << 5) |
| 41 | #define NAND_Ecc_P64e (1 << 6) |
| 42 | #define NAND_Ecc_P128e (1 << 7) |
| 43 | #define NAND_Ecc_P256e (1 << 8) |
| 44 | #define NAND_Ecc_P512e (1 << 9) |
| 45 | #define NAND_Ecc_P1024e (1 << 10) |
| 46 | #define NAND_Ecc_P2048e (1 << 11) |
| 47 | |
| 48 | #define NAND_Ecc_P1o (1 << 16) |
| 49 | #define NAND_Ecc_P2o (1 << 17) |
| 50 | #define NAND_Ecc_P4o (1 << 18) |
| 51 | #define NAND_Ecc_P8o (1 << 19) |
| 52 | #define NAND_Ecc_P16o (1 << 20) |
| 53 | #define NAND_Ecc_P32o (1 << 21) |
| 54 | #define NAND_Ecc_P64o (1 << 22) |
| 55 | #define NAND_Ecc_P128o (1 << 23) |
| 56 | #define NAND_Ecc_P256o (1 << 24) |
| 57 | #define NAND_Ecc_P512o (1 << 25) |
| 58 | #define NAND_Ecc_P1024o (1 << 26) |
| 59 | #define NAND_Ecc_P2048o (1 << 27) |
| 60 | |
| 61 | #define TF(value) (value ? 1 : 0) |
| 62 | |
| 63 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) |
| 64 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) |
| 65 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) |
| 66 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) |
| 67 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) |
| 68 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) |
| 69 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) |
| 70 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) |
| 71 | |
| 72 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) |
| 73 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) |
| 74 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) |
| 75 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) |
| 76 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) |
| 77 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) |
| 78 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) |
| 79 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) |
| 80 | |
| 81 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) |
| 82 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) |
| 83 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) |
| 84 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) |
| 85 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) |
| 86 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) |
| 87 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) |
| 88 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) |
| 89 | |
| 90 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) |
| 91 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) |
| 92 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) |
| 93 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) |
| 94 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) |
| 95 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) |
| 96 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) |
| 97 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) |
| 98 | |
| 99 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) |
| 100 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) |
| 101 | |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 102 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
| 103 | #define ECC_CONFIG_CS_SHIFT 1 |
| 104 | #define CS_MASK 0x7 |
| 105 | #define ENABLE_PREFETCH (0x1 << 7) |
| 106 | #define DMA_MPU_MODE_SHIFT 2 |
Afzal Mohammed | 2ef9f3d | 2012-10-04 19:03:06 +0530 | [diff] [blame] | 107 | #define ECCSIZE0_SHIFT 12 |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 108 | #define ECCSIZE1_SHIFT 22 |
| 109 | #define ECC1RESULTSIZE 0x1 |
| 110 | #define ECCCLEAR 0x100 |
| 111 | #define ECC1 0x1 |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 112 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
| 113 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) |
| 114 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) |
| 115 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) |
| 116 | #define STATUS_BUFF_EMPTY 0x00000001 |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 117 | |
Lokesh Vutla | d5e7c86 | 2012-10-15 14:03:51 -0700 | [diff] [blame] | 118 | #define OMAP24XX_DMA_GPMC 4 |
| 119 | |
Sukumar Ghorai | f040d33 | 2011-01-28 15:42:09 +0530 | [diff] [blame] | 120 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
| 121 | static struct nand_ecclayout omap_oobinfo; |
| 122 | /* Define some generic bad / good block scan pattern which are used |
| 123 | * while scanning a device for factory marked good / bad blocks |
| 124 | */ |
| 125 | static uint8_t scan_ff_pattern[] = { 0xff }; |
| 126 | static struct nand_bbt_descr bb_descrip_flashbased = { |
| 127 | .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, |
| 128 | .offs = 0, |
| 129 | .len = 1, |
| 130 | .pattern = scan_ff_pattern, |
| 131 | }; |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 132 | |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 133 | |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 134 | struct omap_nand_info { |
| 135 | struct nand_hw_control controller; |
| 136 | struct omap_nand_platform_data *pdata; |
| 137 | struct mtd_info mtd; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 138 | struct nand_chip nand; |
| 139 | struct platform_device *pdev; |
| 140 | |
| 141 | int gpmc_cs; |
| 142 | unsigned long phys_base; |
Afzal Mohammed | 9c4c2f8 | 2012-08-30 12:53:23 -0700 | [diff] [blame] | 143 | unsigned long mem_size; |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 144 | struct completion comp; |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 145 | struct dma_chan *dma; |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 146 | int gpmc_irq_fifo; |
| 147 | int gpmc_irq_count; |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 148 | enum { |
| 149 | OMAP_NAND_IO_READ = 0, /* read */ |
| 150 | OMAP_NAND_IO_WRITE, /* write */ |
| 151 | } iomode; |
| 152 | u_char *buf; |
| 153 | int buf_len; |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 154 | struct gpmc_nand_regs reg; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 155 | |
| 156 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
| 157 | struct bch_control *bch; |
| 158 | struct nand_ecclayout ecclayout; |
| 159 | #endif |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 160 | }; |
| 161 | |
| 162 | /** |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 163 | * omap_prefetch_enable - configures and starts prefetch transfer |
| 164 | * @cs: cs (chip select) number |
| 165 | * @fifo_th: fifo threshold to be used for read/ write |
| 166 | * @dma_mode: dma mode enable (1) or disable (0) |
| 167 | * @u32_count: number of bytes to be transferred |
| 168 | * @is_write: prefetch read(0) or write post(1) mode |
| 169 | */ |
| 170 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, |
| 171 | unsigned int u32_count, int is_write, struct omap_nand_info *info) |
| 172 | { |
| 173 | u32 val; |
| 174 | |
| 175 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) |
| 176 | return -1; |
| 177 | |
| 178 | if (readl(info->reg.gpmc_prefetch_control)) |
| 179 | return -EBUSY; |
| 180 | |
| 181 | /* Set the amount of bytes to be prefetched */ |
| 182 | writel(u32_count, info->reg.gpmc_prefetch_config2); |
| 183 | |
| 184 | /* Set dma/mpu mode, the prefetch read / post write and |
| 185 | * enable the engine. Set which cs is has requested for. |
| 186 | */ |
| 187 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | |
| 188 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | |
| 189 | (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write)); |
| 190 | writel(val, info->reg.gpmc_prefetch_config1); |
| 191 | |
| 192 | /* Start the prefetch engine */ |
| 193 | writel(0x1, info->reg.gpmc_prefetch_control); |
| 194 | |
| 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | /** |
| 199 | * omap_prefetch_reset - disables and stops the prefetch engine |
| 200 | */ |
| 201 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) |
| 202 | { |
| 203 | u32 config1; |
| 204 | |
| 205 | /* check if the same module/cs is trying to reset */ |
| 206 | config1 = readl(info->reg.gpmc_prefetch_config1); |
| 207 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) |
| 208 | return -EINVAL; |
| 209 | |
| 210 | /* Stop the PFPW engine */ |
| 211 | writel(0x0, info->reg.gpmc_prefetch_control); |
| 212 | |
| 213 | /* Reset/disable the PFPW engine */ |
| 214 | writel(0x0, info->reg.gpmc_prefetch_config1); |
| 215 | |
| 216 | return 0; |
| 217 | } |
| 218 | |
| 219 | /** |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 220 | * omap_hwcontrol - hardware specific access to control-lines |
| 221 | * @mtd: MTD device structure |
| 222 | * @cmd: command to device |
| 223 | * @ctrl: |
| 224 | * NAND_NCE: bit 0 -> don't care |
| 225 | * NAND_CLE: bit 1 -> Command Latch |
| 226 | * NAND_ALE: bit 2 -> Address Latch |
| 227 | * |
| 228 | * NOTE: boards may use different bits for these!! |
| 229 | */ |
| 230 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
| 231 | { |
| 232 | struct omap_nand_info *info = container_of(mtd, |
| 233 | struct omap_nand_info, mtd); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 234 | |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 235 | if (cmd != NAND_CMD_NONE) { |
| 236 | if (ctrl & NAND_CLE) |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 237 | writeb(cmd, info->reg.gpmc_nand_command); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 238 | |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 239 | else if (ctrl & NAND_ALE) |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 240 | writeb(cmd, info->reg.gpmc_nand_address); |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 241 | |
| 242 | else /* NAND_NCE */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 243 | writeb(cmd, info->reg.gpmc_nand_data); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 244 | } |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | /** |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 248 | * omap_read_buf8 - read data from NAND controller into buffer |
| 249 | * @mtd: MTD device structure |
| 250 | * @buf: buffer to store date |
| 251 | * @len: number of bytes to read |
| 252 | */ |
| 253 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) |
| 254 | { |
| 255 | struct nand_chip *nand = mtd->priv; |
| 256 | |
| 257 | ioread8_rep(nand->IO_ADDR_R, buf, len); |
| 258 | } |
| 259 | |
| 260 | /** |
| 261 | * omap_write_buf8 - write buffer to NAND controller |
| 262 | * @mtd: MTD device structure |
| 263 | * @buf: data buffer |
| 264 | * @len: number of bytes to write |
| 265 | */ |
| 266 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) |
| 267 | { |
| 268 | struct omap_nand_info *info = container_of(mtd, |
| 269 | struct omap_nand_info, mtd); |
| 270 | u_char *p = (u_char *)buf; |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 271 | u32 status = 0; |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 272 | |
| 273 | while (len--) { |
| 274 | iowrite8(*p++, info->nand.IO_ADDR_W); |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 275 | /* wait until buffer is available for write */ |
| 276 | do { |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 277 | status = readl(info->reg.gpmc_status) & |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 278 | STATUS_BUFF_EMPTY; |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 279 | } while (!status); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 280 | } |
| 281 | } |
| 282 | |
| 283 | /** |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 284 | * omap_read_buf16 - read data from NAND controller into buffer |
| 285 | * @mtd: MTD device structure |
| 286 | * @buf: buffer to store date |
| 287 | * @len: number of bytes to read |
| 288 | */ |
| 289 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) |
| 290 | { |
| 291 | struct nand_chip *nand = mtd->priv; |
| 292 | |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 293 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 294 | } |
| 295 | |
| 296 | /** |
| 297 | * omap_write_buf16 - write buffer to NAND controller |
| 298 | * @mtd: MTD device structure |
| 299 | * @buf: data buffer |
| 300 | * @len: number of bytes to write |
| 301 | */ |
| 302 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) |
| 303 | { |
| 304 | struct omap_nand_info *info = container_of(mtd, |
| 305 | struct omap_nand_info, mtd); |
| 306 | u16 *p = (u16 *) buf; |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 307 | u32 status = 0; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 308 | /* FIXME try bursts of writesw() or DMA ... */ |
| 309 | len >>= 1; |
| 310 | |
| 311 | while (len--) { |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 312 | iowrite16(*p++, info->nand.IO_ADDR_W); |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 313 | /* wait until buffer is available for write */ |
| 314 | do { |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 315 | status = readl(info->reg.gpmc_status) & |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 316 | STATUS_BUFF_EMPTY; |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 317 | } while (!status); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 318 | } |
| 319 | } |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 320 | |
| 321 | /** |
| 322 | * omap_read_buf_pref - read data from NAND controller into buffer |
| 323 | * @mtd: MTD device structure |
| 324 | * @buf: buffer to store date |
| 325 | * @len: number of bytes to read |
| 326 | */ |
| 327 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) |
| 328 | { |
| 329 | struct omap_nand_info *info = container_of(mtd, |
| 330 | struct omap_nand_info, mtd); |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 331 | uint32_t r_count = 0; |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 332 | int ret = 0; |
| 333 | u32 *p = (u32 *)buf; |
| 334 | |
| 335 | /* take care of subpage reads */ |
Vimal Singh | c3341d0 | 2010-01-07 12:16:26 +0530 | [diff] [blame] | 336 | if (len % 4) { |
| 337 | if (info->nand.options & NAND_BUSWIDTH_16) |
| 338 | omap_read_buf16(mtd, buf, len % 4); |
| 339 | else |
| 340 | omap_read_buf8(mtd, buf, len % 4); |
| 341 | p = (u32 *) (buf + len % 4); |
| 342 | len -= len % 4; |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 343 | } |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 344 | |
| 345 | /* configure and start prefetch transfer */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 346 | ret = omap_prefetch_enable(info->gpmc_cs, |
| 347 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 348 | if (ret) { |
| 349 | /* PFPW engine is busy, use cpu copy method */ |
| 350 | if (info->nand.options & NAND_BUSWIDTH_16) |
Kishore Kadiyala | c5d8c0c | 2011-05-11 21:17:27 +0530 | [diff] [blame] | 351 | omap_read_buf16(mtd, (u_char *)p, len); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 352 | else |
Kishore Kadiyala | c5d8c0c | 2011-05-11 21:17:27 +0530 | [diff] [blame] | 353 | omap_read_buf8(mtd, (u_char *)p, len); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 354 | } else { |
| 355 | do { |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 356 | r_count = readl(info->reg.gpmc_prefetch_status); |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 357 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 358 | r_count = r_count >> 2; |
| 359 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 360 | p += r_count; |
| 361 | len -= r_count << 2; |
| 362 | } while (len); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 363 | /* disable and stop the PFPW engine */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 364 | omap_prefetch_reset(info->gpmc_cs, info); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 365 | } |
| 366 | } |
| 367 | |
| 368 | /** |
| 369 | * omap_write_buf_pref - write buffer to NAND controller |
| 370 | * @mtd: MTD device structure |
| 371 | * @buf: data buffer |
| 372 | * @len: number of bytes to write |
| 373 | */ |
| 374 | static void omap_write_buf_pref(struct mtd_info *mtd, |
| 375 | const u_char *buf, int len) |
| 376 | { |
| 377 | struct omap_nand_info *info = container_of(mtd, |
| 378 | struct omap_nand_info, mtd); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 379 | uint32_t w_count = 0; |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 380 | int i = 0, ret = 0; |
Kishore Kadiyala | c5d8c0c | 2011-05-11 21:17:27 +0530 | [diff] [blame] | 381 | u16 *p = (u16 *)buf; |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 382 | unsigned long tim, limit; |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 383 | u32 val; |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 384 | |
| 385 | /* take care of subpage writes */ |
| 386 | if (len % 2 != 0) { |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 387 | writeb(*buf, info->nand.IO_ADDR_W); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 388 | p = (u16 *)(buf + 1); |
| 389 | len--; |
| 390 | } |
| 391 | |
| 392 | /* configure and start prefetch transfer */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 393 | ret = omap_prefetch_enable(info->gpmc_cs, |
| 394 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 395 | if (ret) { |
| 396 | /* PFPW engine is busy, use cpu copy method */ |
| 397 | if (info->nand.options & NAND_BUSWIDTH_16) |
Kishore Kadiyala | c5d8c0c | 2011-05-11 21:17:27 +0530 | [diff] [blame] | 398 | omap_write_buf16(mtd, (u_char *)p, len); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 399 | else |
Kishore Kadiyala | c5d8c0c | 2011-05-11 21:17:27 +0530 | [diff] [blame] | 400 | omap_write_buf8(mtd, (u_char *)p, len); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 401 | } else { |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 402 | while (len) { |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 403 | w_count = readl(info->reg.gpmc_prefetch_status); |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 404 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 405 | w_count = w_count >> 1; |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 406 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 407 | iowrite16(*p++, info->nand.IO_ADDR_W); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 408 | } |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 409 | /* wait for data to flushed-out before reset the prefetch */ |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 410 | tim = 0; |
| 411 | limit = (loops_per_jiffy * |
| 412 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 413 | do { |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 414 | cpu_relax(); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 415 | val = readl(info->reg.gpmc_prefetch_status); |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 416 | val = PREFETCH_STATUS_COUNT(val); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 417 | } while (val && (tim++ < limit)); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 418 | |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 419 | /* disable and stop the PFPW engine */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 420 | omap_prefetch_reset(info->gpmc_cs, info); |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 421 | } |
| 422 | } |
| 423 | |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 424 | /* |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 425 | * omap_nand_dma_callback: callback on the completion of dma transfer |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 426 | * @data: pointer to completion data structure |
| 427 | */ |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 428 | static void omap_nand_dma_callback(void *data) |
| 429 | { |
| 430 | complete((struct completion *) data); |
| 431 | } |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 432 | |
| 433 | /* |
Peter Meerwald | 4cacbe2 | 2012-07-19 13:21:04 +0200 | [diff] [blame] | 434 | * omap_nand_dma_transfer: configure and start dma transfer |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 435 | * @mtd: MTD device structure |
| 436 | * @addr: virtual address in RAM of source/destination |
| 437 | * @len: number of data bytes to be transferred |
| 438 | * @is_write: flag for read/write operation |
| 439 | */ |
| 440 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, |
| 441 | unsigned int len, int is_write) |
| 442 | { |
| 443 | struct omap_nand_info *info = container_of(mtd, |
| 444 | struct omap_nand_info, mtd); |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 445 | struct dma_async_tx_descriptor *tx; |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 446 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
| 447 | DMA_FROM_DEVICE; |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 448 | struct scatterlist sg; |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 449 | unsigned long tim, limit; |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 450 | unsigned n; |
| 451 | int ret; |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 452 | u32 val; |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 453 | |
| 454 | if (addr >= high_memory) { |
| 455 | struct page *p1; |
| 456 | |
| 457 | if (((size_t)addr & PAGE_MASK) != |
| 458 | ((size_t)(addr + len - 1) & PAGE_MASK)) |
| 459 | goto out_copy; |
| 460 | p1 = vmalloc_to_page(addr); |
| 461 | if (!p1) |
| 462 | goto out_copy; |
| 463 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); |
| 464 | } |
| 465 | |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 466 | sg_init_one(&sg, addr, len); |
| 467 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); |
| 468 | if (n == 0) { |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 469 | dev_err(&info->pdev->dev, |
| 470 | "Couldn't DMA map a %d byte buffer\n", len); |
| 471 | goto out_copy; |
| 472 | } |
| 473 | |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 474 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
| 475 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, |
| 476 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 477 | if (!tx) |
| 478 | goto out_copy_unmap; |
| 479 | |
| 480 | tx->callback = omap_nand_dma_callback; |
| 481 | tx->callback_param = &info->comp; |
| 482 | dmaengine_submit(tx); |
| 483 | |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 484 | /* configure and start prefetch transfer */ |
| 485 | ret = omap_prefetch_enable(info->gpmc_cs, |
| 486 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 487 | if (ret) |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 488 | /* PFPW engine is busy, use cpu copy method */ |
Grazvydas Ignotas | d7efe22 | 2012-04-11 04:04:34 +0300 | [diff] [blame] | 489 | goto out_copy_unmap; |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 490 | |
| 491 | init_completion(&info->comp); |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 492 | dma_async_issue_pending(info->dma); |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 493 | |
| 494 | /* setup and start DMA using dma_addr */ |
| 495 | wait_for_completion(&info->comp); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 496 | tim = 0; |
| 497 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 498 | |
| 499 | do { |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 500 | cpu_relax(); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 501 | val = readl(info->reg.gpmc_prefetch_status); |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 502 | val = PREFETCH_STATUS_COUNT(val); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 503 | } while (val && (tim++ < limit)); |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 504 | |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 505 | /* disable and stop the PFPW engine */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 506 | omap_prefetch_reset(info->gpmc_cs, info); |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 507 | |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 508 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 509 | return 0; |
| 510 | |
Grazvydas Ignotas | d7efe22 | 2012-04-11 04:04:34 +0300 | [diff] [blame] | 511 | out_copy_unmap: |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 512 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 513 | out_copy: |
| 514 | if (info->nand.options & NAND_BUSWIDTH_16) |
| 515 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) |
| 516 | : omap_write_buf16(mtd, (u_char *) addr, len); |
| 517 | else |
| 518 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) |
| 519 | : omap_write_buf8(mtd, (u_char *) addr, len); |
| 520 | return 0; |
| 521 | } |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 522 | |
| 523 | /** |
| 524 | * omap_read_buf_dma_pref - read data from NAND controller into buffer |
| 525 | * @mtd: MTD device structure |
| 526 | * @buf: buffer to store date |
| 527 | * @len: number of bytes to read |
| 528 | */ |
| 529 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) |
| 530 | { |
| 531 | if (len <= mtd->oobsize) |
| 532 | omap_read_buf_pref(mtd, buf, len); |
| 533 | else |
| 534 | /* start transfer in DMA mode */ |
| 535 | omap_nand_dma_transfer(mtd, buf, len, 0x0); |
| 536 | } |
| 537 | |
| 538 | /** |
| 539 | * omap_write_buf_dma_pref - write buffer to NAND controller |
| 540 | * @mtd: MTD device structure |
| 541 | * @buf: data buffer |
| 542 | * @len: number of bytes to write |
| 543 | */ |
| 544 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, |
| 545 | const u_char *buf, int len) |
| 546 | { |
| 547 | if (len <= mtd->oobsize) |
| 548 | omap_write_buf_pref(mtd, buf, len); |
| 549 | else |
| 550 | /* start transfer in DMA mode */ |
Vimal Singh | bdaefc4 | 2010-01-05 12:49:24 +0530 | [diff] [blame] | 551 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 552 | } |
| 553 | |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 554 | /* |
Peter Meerwald | 4cacbe2 | 2012-07-19 13:21:04 +0200 | [diff] [blame] | 555 | * omap_nand_irq - GPMC irq handler |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 556 | * @this_irq: gpmc irq number |
| 557 | * @dev: omap_nand_info structure pointer is passed here |
| 558 | */ |
| 559 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) |
| 560 | { |
| 561 | struct omap_nand_info *info = (struct omap_nand_info *) dev; |
| 562 | u32 bytes; |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 563 | |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 564 | bytes = readl(info->reg.gpmc_prefetch_status); |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 565 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 566 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
| 567 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 568 | if (this_irq == info->gpmc_irq_count) |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 569 | goto done; |
| 570 | |
| 571 | if (info->buf_len && (info->buf_len < bytes)) |
| 572 | bytes = info->buf_len; |
| 573 | else if (!info->buf_len) |
| 574 | bytes = 0; |
| 575 | iowrite32_rep(info->nand.IO_ADDR_W, |
| 576 | (u32 *)info->buf, bytes >> 2); |
| 577 | info->buf = info->buf + bytes; |
| 578 | info->buf_len -= bytes; |
| 579 | |
| 580 | } else { |
| 581 | ioread32_rep(info->nand.IO_ADDR_R, |
| 582 | (u32 *)info->buf, bytes >> 2); |
| 583 | info->buf = info->buf + bytes; |
| 584 | |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 585 | if (this_irq == info->gpmc_irq_count) |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 586 | goto done; |
| 587 | } |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 588 | |
| 589 | return IRQ_HANDLED; |
| 590 | |
| 591 | done: |
| 592 | complete(&info->comp); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 593 | |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 594 | disable_irq_nosync(info->gpmc_irq_fifo); |
| 595 | disable_irq_nosync(info->gpmc_irq_count); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 596 | |
| 597 | return IRQ_HANDLED; |
| 598 | } |
| 599 | |
| 600 | /* |
| 601 | * omap_read_buf_irq_pref - read data from NAND controller into buffer |
| 602 | * @mtd: MTD device structure |
| 603 | * @buf: buffer to store date |
| 604 | * @len: number of bytes to read |
| 605 | */ |
| 606 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) |
| 607 | { |
| 608 | struct omap_nand_info *info = container_of(mtd, |
| 609 | struct omap_nand_info, mtd); |
| 610 | int ret = 0; |
| 611 | |
| 612 | if (len <= mtd->oobsize) { |
| 613 | omap_read_buf_pref(mtd, buf, len); |
| 614 | return; |
| 615 | } |
| 616 | |
| 617 | info->iomode = OMAP_NAND_IO_READ; |
| 618 | info->buf = buf; |
| 619 | init_completion(&info->comp); |
| 620 | |
| 621 | /* configure and start prefetch transfer */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 622 | ret = omap_prefetch_enable(info->gpmc_cs, |
| 623 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 624 | if (ret) |
| 625 | /* PFPW engine is busy, use cpu copy method */ |
| 626 | goto out_copy; |
| 627 | |
| 628 | info->buf_len = len; |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 629 | |
| 630 | enable_irq(info->gpmc_irq_count); |
| 631 | enable_irq(info->gpmc_irq_fifo); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 632 | |
| 633 | /* waiting for read to complete */ |
| 634 | wait_for_completion(&info->comp); |
| 635 | |
| 636 | /* disable and stop the PFPW engine */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 637 | omap_prefetch_reset(info->gpmc_cs, info); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 638 | return; |
| 639 | |
| 640 | out_copy: |
| 641 | if (info->nand.options & NAND_BUSWIDTH_16) |
| 642 | omap_read_buf16(mtd, buf, len); |
| 643 | else |
| 644 | omap_read_buf8(mtd, buf, len); |
| 645 | } |
| 646 | |
| 647 | /* |
| 648 | * omap_write_buf_irq_pref - write buffer to NAND controller |
| 649 | * @mtd: MTD device structure |
| 650 | * @buf: data buffer |
| 651 | * @len: number of bytes to write |
| 652 | */ |
| 653 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, |
| 654 | const u_char *buf, int len) |
| 655 | { |
| 656 | struct omap_nand_info *info = container_of(mtd, |
| 657 | struct omap_nand_info, mtd); |
| 658 | int ret = 0; |
| 659 | unsigned long tim, limit; |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 660 | u32 val; |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 661 | |
| 662 | if (len <= mtd->oobsize) { |
| 663 | omap_write_buf_pref(mtd, buf, len); |
| 664 | return; |
| 665 | } |
| 666 | |
| 667 | info->iomode = OMAP_NAND_IO_WRITE; |
| 668 | info->buf = (u_char *) buf; |
| 669 | init_completion(&info->comp); |
| 670 | |
Sukumar Ghorai | 317379a | 2011-01-28 15:42:07 +0530 | [diff] [blame] | 671 | /* configure and start prefetch transfer : size=24 */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 672 | ret = omap_prefetch_enable(info->gpmc_cs, |
| 673 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 674 | if (ret) |
| 675 | /* PFPW engine is busy, use cpu copy method */ |
| 676 | goto out_copy; |
| 677 | |
| 678 | info->buf_len = len; |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 679 | |
| 680 | enable_irq(info->gpmc_irq_count); |
| 681 | enable_irq(info->gpmc_irq_fifo); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 682 | |
| 683 | /* waiting for write to complete */ |
| 684 | wait_for_completion(&info->comp); |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 685 | |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 686 | /* wait for data to flushed-out before reset the prefetch */ |
| 687 | tim = 0; |
| 688 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 689 | do { |
| 690 | val = readl(info->reg.gpmc_prefetch_status); |
Afzal Mohammed | 47f88af4 | 2012-09-29 18:20:11 +0530 | [diff] [blame] | 691 | val = PREFETCH_STATUS_COUNT(val); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 692 | cpu_relax(); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 693 | } while (val && (tim++ < limit)); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 694 | |
| 695 | /* disable and stop the PFPW engine */ |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 696 | omap_prefetch_reset(info->gpmc_cs, info); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 697 | return; |
| 698 | |
| 699 | out_copy: |
| 700 | if (info->nand.options & NAND_BUSWIDTH_16) |
| 701 | omap_write_buf16(mtd, buf, len); |
| 702 | else |
| 703 | omap_write_buf8(mtd, buf, len); |
| 704 | } |
| 705 | |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 706 | /** |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 707 | * gen_true_ecc - This function will generate true ECC value |
| 708 | * @ecc_buf: buffer to store ecc code |
| 709 | * |
| 710 | * This generated true ECC value can be used when correcting |
| 711 | * data read from NAND flash memory core |
| 712 | */ |
| 713 | static void gen_true_ecc(u8 *ecc_buf) |
| 714 | { |
| 715 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | |
| 716 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); |
| 717 | |
| 718 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | |
| 719 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); |
| 720 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | |
| 721 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); |
| 722 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | |
| 723 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); |
| 724 | } |
| 725 | |
| 726 | /** |
| 727 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data |
| 728 | * @ecc_data1: ecc code from nand spare area |
| 729 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc |
| 730 | * @page_data: page data |
| 731 | * |
| 732 | * This function compares two ECC's and indicates if there is an error. |
| 733 | * If the error can be corrected it will be corrected to the buffer. |
John Ogness | 74f1b72 | 2011-02-28 13:12:46 +0100 | [diff] [blame] | 734 | * If there is no error, %0 is returned. If there is an error but it |
| 735 | * was corrected, %1 is returned. Otherwise, %-1 is returned. |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 736 | */ |
| 737 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ |
| 738 | u8 *ecc_data2, /* read from register */ |
| 739 | u8 *page_data) |
| 740 | { |
| 741 | uint i; |
| 742 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; |
| 743 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; |
| 744 | u8 ecc_bit[24]; |
| 745 | u8 ecc_sum = 0; |
| 746 | u8 find_bit = 0; |
| 747 | uint find_byte = 0; |
| 748 | int isEccFF; |
| 749 | |
| 750 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); |
| 751 | |
| 752 | gen_true_ecc(ecc_data1); |
| 753 | gen_true_ecc(ecc_data2); |
| 754 | |
| 755 | for (i = 0; i <= 2; i++) { |
| 756 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); |
| 757 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); |
| 758 | } |
| 759 | |
| 760 | for (i = 0; i < 8; i++) { |
| 761 | tmp0_bit[i] = *ecc_data1 % 2; |
| 762 | *ecc_data1 = *ecc_data1 / 2; |
| 763 | } |
| 764 | |
| 765 | for (i = 0; i < 8; i++) { |
| 766 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; |
| 767 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; |
| 768 | } |
| 769 | |
| 770 | for (i = 0; i < 8; i++) { |
| 771 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; |
| 772 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; |
| 773 | } |
| 774 | |
| 775 | for (i = 0; i < 8; i++) { |
| 776 | comp0_bit[i] = *ecc_data2 % 2; |
| 777 | *ecc_data2 = *ecc_data2 / 2; |
| 778 | } |
| 779 | |
| 780 | for (i = 0; i < 8; i++) { |
| 781 | comp1_bit[i] = *(ecc_data2 + 1) % 2; |
| 782 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; |
| 783 | } |
| 784 | |
| 785 | for (i = 0; i < 8; i++) { |
| 786 | comp2_bit[i] = *(ecc_data2 + 2) % 2; |
| 787 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; |
| 788 | } |
| 789 | |
| 790 | for (i = 0; i < 6; i++) |
| 791 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; |
| 792 | |
| 793 | for (i = 0; i < 8; i++) |
| 794 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; |
| 795 | |
| 796 | for (i = 0; i < 8; i++) |
| 797 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; |
| 798 | |
| 799 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; |
| 800 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; |
| 801 | |
| 802 | for (i = 0; i < 24; i++) |
| 803 | ecc_sum += ecc_bit[i]; |
| 804 | |
| 805 | switch (ecc_sum) { |
| 806 | case 0: |
| 807 | /* Not reached because this function is not called if |
| 808 | * ECC values are equal |
| 809 | */ |
| 810 | return 0; |
| 811 | |
| 812 | case 1: |
| 813 | /* Uncorrectable error */ |
Brian Norris | 289c052 | 2011-07-19 10:06:09 -0700 | [diff] [blame] | 814 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 815 | return -1; |
| 816 | |
| 817 | case 11: |
| 818 | /* UN-Correctable error */ |
Brian Norris | 289c052 | 2011-07-19 10:06:09 -0700 | [diff] [blame] | 819 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 820 | return -1; |
| 821 | |
| 822 | case 12: |
| 823 | /* Correctable error */ |
| 824 | find_byte = (ecc_bit[23] << 8) + |
| 825 | (ecc_bit[21] << 7) + |
| 826 | (ecc_bit[19] << 6) + |
| 827 | (ecc_bit[17] << 5) + |
| 828 | (ecc_bit[15] << 4) + |
| 829 | (ecc_bit[13] << 3) + |
| 830 | (ecc_bit[11] << 2) + |
| 831 | (ecc_bit[9] << 1) + |
| 832 | ecc_bit[7]; |
| 833 | |
| 834 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; |
| 835 | |
Brian Norris | 0a32a10 | 2011-07-19 10:06:10 -0700 | [diff] [blame] | 836 | pr_debug("Correcting single bit ECC error at offset: " |
| 837 | "%d, bit: %d\n", find_byte, find_bit); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 838 | |
| 839 | page_data[find_byte] ^= (1 << find_bit); |
| 840 | |
John Ogness | 74f1b72 | 2011-02-28 13:12:46 +0100 | [diff] [blame] | 841 | return 1; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 842 | default: |
| 843 | if (isEccFF) { |
| 844 | if (ecc_data2[0] == 0 && |
| 845 | ecc_data2[1] == 0 && |
| 846 | ecc_data2[2] == 0) |
| 847 | return 0; |
| 848 | } |
Brian Norris | 289c052 | 2011-07-19 10:06:09 -0700 | [diff] [blame] | 849 | pr_debug("UNCORRECTED_ERROR default\n"); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 850 | return -1; |
| 851 | } |
| 852 | } |
| 853 | |
| 854 | /** |
| 855 | * omap_correct_data - Compares the ECC read with HW generated ECC |
| 856 | * @mtd: MTD device structure |
| 857 | * @dat: page data |
| 858 | * @read_ecc: ecc read from nand flash |
| 859 | * @calc_ecc: ecc read from HW ECC registers |
| 860 | * |
| 861 | * Compares the ecc read from nand spare area with ECC registers values |
John Ogness | 74f1b72 | 2011-02-28 13:12:46 +0100 | [diff] [blame] | 862 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
| 863 | * detection and correction. If there are no errors, %0 is returned. If |
| 864 | * there were errors and all of the errors were corrected, the number of |
| 865 | * corrected errors is returned. If uncorrectable errors exist, %-1 is |
| 866 | * returned. |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 867 | */ |
| 868 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, |
| 869 | u_char *read_ecc, u_char *calc_ecc) |
| 870 | { |
| 871 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 872 | mtd); |
| 873 | int blockCnt = 0, i = 0, ret = 0; |
John Ogness | 74f1b72 | 2011-02-28 13:12:46 +0100 | [diff] [blame] | 874 | int stat = 0; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 875 | |
| 876 | /* Ex NAND_ECC_HW12_2048 */ |
| 877 | if ((info->nand.ecc.mode == NAND_ECC_HW) && |
| 878 | (info->nand.ecc.size == 2048)) |
| 879 | blockCnt = 4; |
| 880 | else |
| 881 | blockCnt = 1; |
| 882 | |
| 883 | for (i = 0; i < blockCnt; i++) { |
| 884 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { |
| 885 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); |
| 886 | if (ret < 0) |
| 887 | return ret; |
John Ogness | 74f1b72 | 2011-02-28 13:12:46 +0100 | [diff] [blame] | 888 | /* keep track of the number of corrected errors */ |
| 889 | stat += ret; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 890 | } |
| 891 | read_ecc += 3; |
| 892 | calc_ecc += 3; |
| 893 | dat += 512; |
| 894 | } |
John Ogness | 74f1b72 | 2011-02-28 13:12:46 +0100 | [diff] [blame] | 895 | return stat; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 896 | } |
| 897 | |
| 898 | /** |
| 899 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. |
| 900 | * @mtd: MTD device structure |
| 901 | * @dat: The pointer to data on which ecc is computed |
| 902 | * @ecc_code: The ecc_code buffer |
| 903 | * |
| 904 | * Using noninverted ECC can be considered ugly since writing a blank |
| 905 | * page ie. padding will clear the ECC bytes. This is no problem as long |
| 906 | * nobody is trying to write data on the seemingly unused page. Reading |
| 907 | * an erased page will produce an ECC mismatch between generated and read |
| 908 | * ECC bytes that has to be dealt with separately. |
| 909 | */ |
| 910 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
| 911 | u_char *ecc_code) |
| 912 | { |
| 913 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 914 | mtd); |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 915 | u32 val; |
| 916 | |
| 917 | val = readl(info->reg.gpmc_ecc_config); |
| 918 | if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) |
| 919 | return -EINVAL; |
| 920 | |
| 921 | /* read ecc result */ |
| 922 | val = readl(info->reg.gpmc_ecc1_result); |
| 923 | *ecc_code++ = val; /* P128e, ..., P1e */ |
| 924 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ |
| 925 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ |
| 926 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); |
| 927 | |
| 928 | return 0; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 929 | } |
| 930 | |
| 931 | /** |
| 932 | * omap_enable_hwecc - This function enables the hardware ecc functionality |
| 933 | * @mtd: MTD device structure |
| 934 | * @mode: Read/Write mode |
| 935 | */ |
| 936 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) |
| 937 | { |
| 938 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 939 | mtd); |
| 940 | struct nand_chip *chip = mtd->priv; |
| 941 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 942 | u32 val; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 943 | |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 944 | /* clear ecc and enable bits */ |
| 945 | val = ECCCLEAR | ECC1; |
| 946 | writel(val, info->reg.gpmc_ecc_control); |
| 947 | |
| 948 | /* program ecc and result sizes */ |
| 949 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | |
| 950 | ECC1RESULTSIZE); |
| 951 | writel(val, info->reg.gpmc_ecc_size_config); |
| 952 | |
| 953 | switch (mode) { |
| 954 | case NAND_ECC_READ: |
| 955 | case NAND_ECC_WRITE: |
| 956 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); |
| 957 | break; |
| 958 | case NAND_ECC_READSYN: |
| 959 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); |
| 960 | break; |
| 961 | default: |
| 962 | dev_info(&info->pdev->dev, |
| 963 | "error: unrecognized Mode[%d]!\n", mode); |
| 964 | break; |
| 965 | } |
| 966 | |
| 967 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
| 968 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); |
| 969 | writel(val, info->reg.gpmc_ecc_config); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 970 | } |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 971 | |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 972 | /** |
| 973 | * omap_wait - wait until the command is done |
| 974 | * @mtd: MTD device structure |
| 975 | * @chip: NAND Chip structure |
| 976 | * |
| 977 | * Wait function is called during Program and erase operations and |
| 978 | * the way it is called from MTD layer, we should wait till the NAND |
| 979 | * chip is ready after the programming/erase operation has completed. |
| 980 | * |
| 981 | * Erase can take up to 400ms and program up to 20ms according to |
| 982 | * general NAND and SmartMedia specs |
| 983 | */ |
| 984 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) |
| 985 | { |
| 986 | struct nand_chip *this = mtd->priv; |
| 987 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 988 | mtd); |
| 989 | unsigned long timeo = jiffies; |
Ivan Djelic | a9c465f | 2012-04-17 13:11:53 +0200 | [diff] [blame] | 990 | int status, state = this->state; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 991 | |
| 992 | if (state == FL_ERASING) |
| 993 | timeo += (HZ * 400) / 1000; |
| 994 | else |
| 995 | timeo += (HZ * 20) / 1000; |
| 996 | |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 997 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 998 | while (time_before(jiffies, timeo)) { |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 999 | status = readb(info->reg.gpmc_nand_data); |
vimal singh | c276aca | 2009-06-27 11:07:06 +0530 | [diff] [blame] | 1000 | if (status & NAND_STATUS_READY) |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1001 | break; |
vimal singh | c276aca | 2009-06-27 11:07:06 +0530 | [diff] [blame] | 1002 | cond_resched(); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1003 | } |
Ivan Djelic | a9c465f | 2012-04-17 13:11:53 +0200 | [diff] [blame] | 1004 | |
Afzal Mohammed | 4ea1e4b | 2012-09-29 11:22:21 +0530 | [diff] [blame] | 1005 | status = readb(info->reg.gpmc_nand_data); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1006 | return status; |
| 1007 | } |
| 1008 | |
| 1009 | /** |
| 1010 | * omap_dev_ready - calls the platform specific dev_ready function |
| 1011 | * @mtd: MTD device structure |
| 1012 | */ |
| 1013 | static int omap_dev_ready(struct mtd_info *mtd) |
| 1014 | { |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 1015 | unsigned int val = 0; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1016 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1017 | mtd); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1018 | |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 1019 | val = readl(info->reg.gpmc_status); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1020 | |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 1021 | if ((val & 0x100) == 0x100) { |
| 1022 | return 1; |
| 1023 | } else { |
| 1024 | return 0; |
| 1025 | } |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1026 | } |
| 1027 | |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1028 | #ifdef CONFIG_MTD_NAND_OMAP_BCH |
| 1029 | |
| 1030 | /** |
| 1031 | * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction |
| 1032 | * @mtd: MTD device structure |
| 1033 | * @mode: Read/Write mode |
| 1034 | */ |
| 1035 | static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode) |
| 1036 | { |
| 1037 | int nerrors; |
Afzal Mohammed | 2ef9f3d | 2012-10-04 19:03:06 +0530 | [diff] [blame] | 1038 | unsigned int dev_width, nsectors; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1039 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1040 | mtd); |
| 1041 | struct nand_chip *chip = mtd->priv; |
Afzal Mohammed | 2ef9f3d | 2012-10-04 19:03:06 +0530 | [diff] [blame] | 1042 | u32 val; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1043 | |
| 1044 | nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4; |
| 1045 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
Afzal Mohammed | 2ef9f3d | 2012-10-04 19:03:06 +0530 | [diff] [blame] | 1046 | nsectors = 1; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1047 | /* |
| 1048 | * Program GPMC to perform correction on one 512-byte sector at a time. |
| 1049 | * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and |
| 1050 | * gives a slight (5%) performance gain (but requires additional code). |
| 1051 | */ |
Afzal Mohammed | 2ef9f3d | 2012-10-04 19:03:06 +0530 | [diff] [blame] | 1052 | |
| 1053 | writel(ECC1, info->reg.gpmc_ecc_control); |
| 1054 | |
| 1055 | /* |
| 1056 | * When using BCH, sector size is hardcoded to 512 bytes. |
| 1057 | * Here we are using wrapping mode 6 both for reading and writing, with: |
| 1058 | * size0 = 0 (no additional protected byte in spare area) |
| 1059 | * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) |
| 1060 | */ |
| 1061 | val = (32 << ECCSIZE1_SHIFT) | (0 << ECCSIZE0_SHIFT); |
| 1062 | writel(val, info->reg.gpmc_ecc_size_config); |
| 1063 | |
| 1064 | /* BCH configuration */ |
| 1065 | val = ((1 << 16) | /* enable BCH */ |
| 1066 | (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */ |
| 1067 | (0x06 << 8) | /* wrap mode = 6 */ |
| 1068 | (dev_width << 7) | /* bus width */ |
| 1069 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ |
| 1070 | (info->gpmc_cs << 1) | /* ECC CS */ |
| 1071 | (0x1)); /* enable ECC */ |
| 1072 | |
| 1073 | writel(val, info->reg.gpmc_ecc_config); |
| 1074 | |
| 1075 | /* clear ecc and enable bits */ |
| 1076 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1077 | } |
| 1078 | |
| 1079 | /** |
| 1080 | * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes |
| 1081 | * @mtd: MTD device structure |
| 1082 | * @dat: The pointer to data on which ecc is computed |
| 1083 | * @ecc_code: The ecc_code buffer |
| 1084 | */ |
| 1085 | static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat, |
| 1086 | u_char *ecc_code) |
| 1087 | { |
| 1088 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1089 | mtd); |
Afzal Mohammed | 2ef9f3d | 2012-10-04 19:03:06 +0530 | [diff] [blame] | 1090 | unsigned long nsectors, val1, val2; |
| 1091 | int i; |
| 1092 | |
| 1093 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; |
| 1094 | |
| 1095 | for (i = 0; i < nsectors; i++) { |
| 1096 | |
| 1097 | /* Read hw-computed remainder */ |
| 1098 | val1 = readl(info->reg.gpmc_bch_result0[i]); |
| 1099 | val2 = readl(info->reg.gpmc_bch_result1[i]); |
| 1100 | |
| 1101 | /* |
| 1102 | * Add constant polynomial to remainder, in order to get an ecc |
| 1103 | * sequence of 0xFFs for a buffer filled with 0xFFs; and |
| 1104 | * left-justify the resulting polynomial. |
| 1105 | */ |
| 1106 | *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF); |
| 1107 | *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF); |
| 1108 | *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF)); |
| 1109 | *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF); |
| 1110 | *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF); |
| 1111 | *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF); |
| 1112 | *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4); |
| 1113 | } |
| 1114 | |
| 1115 | return 0; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1116 | } |
| 1117 | |
| 1118 | /** |
| 1119 | * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes |
| 1120 | * @mtd: MTD device structure |
| 1121 | * @dat: The pointer to data on which ecc is computed |
| 1122 | * @ecc_code: The ecc_code buffer |
| 1123 | */ |
| 1124 | static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat, |
| 1125 | u_char *ecc_code) |
| 1126 | { |
| 1127 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1128 | mtd); |
Afzal Mohammed | 2ef9f3d | 2012-10-04 19:03:06 +0530 | [diff] [blame] | 1129 | unsigned long nsectors, val1, val2, val3, val4; |
| 1130 | int i; |
| 1131 | |
| 1132 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; |
| 1133 | |
| 1134 | for (i = 0; i < nsectors; i++) { |
| 1135 | |
| 1136 | /* Read hw-computed remainder */ |
| 1137 | val1 = readl(info->reg.gpmc_bch_result0[i]); |
| 1138 | val2 = readl(info->reg.gpmc_bch_result1[i]); |
| 1139 | val3 = readl(info->reg.gpmc_bch_result2[i]); |
| 1140 | val4 = readl(info->reg.gpmc_bch_result3[i]); |
| 1141 | |
| 1142 | /* |
| 1143 | * Add constant polynomial to remainder, in order to get an ecc |
| 1144 | * sequence of 0xFFs for a buffer filled with 0xFFs. |
| 1145 | */ |
| 1146 | *ecc_code++ = 0xef ^ (val4 & 0xFF); |
| 1147 | *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF); |
| 1148 | *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF); |
| 1149 | *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF); |
| 1150 | *ecc_code++ = 0xed ^ (val3 & 0xFF); |
| 1151 | *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF); |
| 1152 | *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF); |
| 1153 | *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF); |
| 1154 | *ecc_code++ = 0x97 ^ (val2 & 0xFF); |
| 1155 | *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF); |
| 1156 | *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF); |
| 1157 | *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF); |
| 1158 | *ecc_code++ = 0xb5 ^ (val1 & 0xFF); |
| 1159 | } |
| 1160 | |
| 1161 | return 0; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1162 | } |
| 1163 | |
| 1164 | /** |
| 1165 | * omap3_correct_data_bch - Decode received data and correct errors |
| 1166 | * @mtd: MTD device structure |
| 1167 | * @data: page data |
| 1168 | * @read_ecc: ecc read from nand flash |
| 1169 | * @calc_ecc: ecc read from HW ECC registers |
| 1170 | */ |
| 1171 | static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data, |
| 1172 | u_char *read_ecc, u_char *calc_ecc) |
| 1173 | { |
| 1174 | int i, count; |
| 1175 | /* cannot correct more than 8 errors */ |
| 1176 | unsigned int errloc[8]; |
| 1177 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1178 | mtd); |
| 1179 | |
| 1180 | count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL, |
| 1181 | errloc); |
| 1182 | if (count > 0) { |
| 1183 | /* correct errors */ |
| 1184 | for (i = 0; i < count; i++) { |
| 1185 | /* correct data only, not ecc bytes */ |
| 1186 | if (errloc[i] < 8*512) |
| 1187 | data[errloc[i]/8] ^= 1 << (errloc[i] & 7); |
| 1188 | pr_debug("corrected bitflip %u\n", errloc[i]); |
| 1189 | } |
| 1190 | } else if (count < 0) { |
| 1191 | pr_err("ecc unrecoverable error\n"); |
| 1192 | } |
| 1193 | return count; |
| 1194 | } |
| 1195 | |
| 1196 | /** |
| 1197 | * omap3_free_bch - Release BCH ecc resources |
| 1198 | * @mtd: MTD device structure |
| 1199 | */ |
| 1200 | static void omap3_free_bch(struct mtd_info *mtd) |
| 1201 | { |
| 1202 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1203 | mtd); |
| 1204 | if (info->bch) { |
| 1205 | free_bch(info->bch); |
| 1206 | info->bch = NULL; |
| 1207 | } |
| 1208 | } |
| 1209 | |
| 1210 | /** |
| 1211 | * omap3_init_bch - Initialize BCH ECC |
| 1212 | * @mtd: MTD device structure |
| 1213 | * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW) |
| 1214 | */ |
| 1215 | static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) |
| 1216 | { |
Afzal Mohammed | 2ef9f3d | 2012-10-04 19:03:06 +0530 | [diff] [blame] | 1217 | int max_errors; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1218 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1219 | mtd); |
| 1220 | #ifdef CONFIG_MTD_NAND_OMAP_BCH8 |
| 1221 | const int hw_errors = 8; |
| 1222 | #else |
| 1223 | const int hw_errors = 4; |
| 1224 | #endif |
| 1225 | info->bch = NULL; |
| 1226 | |
| 1227 | max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4; |
| 1228 | if (max_errors != hw_errors) { |
| 1229 | pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported", |
| 1230 | max_errors, hw_errors); |
| 1231 | goto fail; |
| 1232 | } |
| 1233 | |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1234 | /* software bch library is only used to detect and locate errors */ |
| 1235 | info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */); |
| 1236 | if (!info->bch) |
| 1237 | goto fail; |
| 1238 | |
| 1239 | info->nand.ecc.size = 512; |
| 1240 | info->nand.ecc.hwctl = omap3_enable_hwecc_bch; |
| 1241 | info->nand.ecc.correct = omap3_correct_data_bch; |
| 1242 | info->nand.ecc.mode = NAND_ECC_HW; |
| 1243 | |
| 1244 | /* |
| 1245 | * The number of corrected errors in an ecc block that will trigger |
| 1246 | * block scrubbing defaults to the ecc strength (4 or 8). |
| 1247 | * Set mtd->bitflip_threshold here to define a custom threshold. |
| 1248 | */ |
| 1249 | |
| 1250 | if (max_errors == 8) { |
| 1251 | info->nand.ecc.strength = 8; |
| 1252 | info->nand.ecc.bytes = 13; |
| 1253 | info->nand.ecc.calculate = omap3_calculate_ecc_bch8; |
| 1254 | } else { |
| 1255 | info->nand.ecc.strength = 4; |
| 1256 | info->nand.ecc.bytes = 7; |
| 1257 | info->nand.ecc.calculate = omap3_calculate_ecc_bch4; |
| 1258 | } |
| 1259 | |
| 1260 | pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors); |
| 1261 | return 0; |
| 1262 | fail: |
| 1263 | omap3_free_bch(mtd); |
| 1264 | return -1; |
| 1265 | } |
| 1266 | |
| 1267 | /** |
| 1268 | * omap3_init_bch_tail - Build an oob layout for BCH ECC correction. |
| 1269 | * @mtd: MTD device structure |
| 1270 | */ |
| 1271 | static int omap3_init_bch_tail(struct mtd_info *mtd) |
| 1272 | { |
| 1273 | int i, steps; |
| 1274 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1275 | mtd); |
| 1276 | struct nand_ecclayout *layout = &info->ecclayout; |
| 1277 | |
| 1278 | /* build oob layout */ |
| 1279 | steps = mtd->writesize/info->nand.ecc.size; |
| 1280 | layout->eccbytes = steps*info->nand.ecc.bytes; |
| 1281 | |
| 1282 | /* do not bother creating special oob layouts for small page devices */ |
| 1283 | if (mtd->oobsize < 64) { |
| 1284 | pr_err("BCH ecc is not supported on small page devices\n"); |
| 1285 | goto fail; |
| 1286 | } |
| 1287 | |
| 1288 | /* reserve 2 bytes for bad block marker */ |
| 1289 | if (layout->eccbytes+2 > mtd->oobsize) { |
| 1290 | pr_err("no oob layout available for oobsize %d eccbytes %u\n", |
| 1291 | mtd->oobsize, layout->eccbytes); |
| 1292 | goto fail; |
| 1293 | } |
| 1294 | |
| 1295 | /* put ecc bytes at oob tail */ |
| 1296 | for (i = 0; i < layout->eccbytes; i++) |
| 1297 | layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i; |
| 1298 | |
| 1299 | layout->oobfree[0].offset = 2; |
| 1300 | layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; |
| 1301 | info->nand.ecc.layout = layout; |
| 1302 | |
| 1303 | if (!(info->nand.options & NAND_BUSWIDTH_16)) |
| 1304 | info->nand.badblock_pattern = &bb_descrip_flashbased; |
| 1305 | return 0; |
| 1306 | fail: |
| 1307 | omap3_free_bch(mtd); |
| 1308 | return -1; |
| 1309 | } |
| 1310 | |
| 1311 | #else |
| 1312 | static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt) |
| 1313 | { |
| 1314 | pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n"); |
| 1315 | return -1; |
| 1316 | } |
| 1317 | static int omap3_init_bch_tail(struct mtd_info *mtd) |
| 1318 | { |
| 1319 | return -1; |
| 1320 | } |
| 1321 | static void omap3_free_bch(struct mtd_info *mtd) |
| 1322 | { |
| 1323 | } |
| 1324 | #endif /* CONFIG_MTD_NAND_OMAP_BCH */ |
| 1325 | |
Bill Pemberton | 06f2551 | 2012-11-19 13:23:07 -0500 | [diff] [blame] | 1326 | static int omap_nand_probe(struct platform_device *pdev) |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1327 | { |
| 1328 | struct omap_nand_info *info; |
| 1329 | struct omap_nand_platform_data *pdata; |
| 1330 | int err; |
Sukumar Ghorai | f040d33 | 2011-01-28 15:42:09 +0530 | [diff] [blame] | 1331 | int i, offset; |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 1332 | dma_cap_mask_t mask; |
| 1333 | unsigned sig; |
Afzal Mohammed | 9c4c2f8 | 2012-08-30 12:53:23 -0700 | [diff] [blame] | 1334 | struct resource *res; |
Daniel Mack | ccf04c5 | 2012-12-14 11:36:41 +0100 | [diff] [blame^] | 1335 | struct mtd_part_parser_data ppdata = {}; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1336 | |
| 1337 | pdata = pdev->dev.platform_data; |
| 1338 | if (pdata == NULL) { |
| 1339 | dev_err(&pdev->dev, "platform data missing\n"); |
| 1340 | return -ENODEV; |
| 1341 | } |
| 1342 | |
| 1343 | info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); |
| 1344 | if (!info) |
| 1345 | return -ENOMEM; |
| 1346 | |
| 1347 | platform_set_drvdata(pdev, info); |
| 1348 | |
| 1349 | spin_lock_init(&info->controller.lock); |
| 1350 | init_waitqueue_head(&info->controller.wq); |
| 1351 | |
| 1352 | info->pdev = pdev; |
| 1353 | |
| 1354 | info->gpmc_cs = pdata->cs; |
Afzal Mohammed | 65b97cf | 2012-08-30 12:53:22 -0700 | [diff] [blame] | 1355 | info->reg = pdata->reg; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1356 | |
| 1357 | info->mtd.priv = &info->nand; |
| 1358 | info->mtd.name = dev_name(&pdev->dev); |
| 1359 | info->mtd.owner = THIS_MODULE; |
| 1360 | |
Sukumar Ghorai | d5ce2b6 | 2011-01-28 15:42:03 +0530 | [diff] [blame] | 1361 | info->nand.options = pdata->devsize; |
Vimal Singh | 2f70a1e | 2010-02-15 10:03:33 -0800 | [diff] [blame] | 1362 | info->nand.options |= NAND_SKIP_BBTSCAN; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1363 | |
Afzal Mohammed | 9c4c2f8 | 2012-08-30 12:53:23 -0700 | [diff] [blame] | 1364 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1365 | if (res == NULL) { |
| 1366 | err = -EINVAL; |
| 1367 | dev_err(&pdev->dev, "error getting memory resource\n"); |
| 1368 | goto out_free_info; |
| 1369 | } |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1370 | |
Afzal Mohammed | 9c4c2f8 | 2012-08-30 12:53:23 -0700 | [diff] [blame] | 1371 | info->phys_base = res->start; |
| 1372 | info->mem_size = resource_size(res); |
| 1373 | |
| 1374 | if (!request_mem_region(info->phys_base, info->mem_size, |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1375 | pdev->dev.driver->name)) { |
| 1376 | err = -EBUSY; |
Vimal Singh | 2f70a1e | 2010-02-15 10:03:33 -0800 | [diff] [blame] | 1377 | goto out_free_info; |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1378 | } |
| 1379 | |
Afzal Mohammed | 9c4c2f8 | 2012-08-30 12:53:23 -0700 | [diff] [blame] | 1380 | info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1381 | if (!info->nand.IO_ADDR_R) { |
| 1382 | err = -ENOMEM; |
| 1383 | goto out_release_mem_region; |
| 1384 | } |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 1385 | |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1386 | info->nand.controller = &info->controller; |
| 1387 | |
| 1388 | info->nand.IO_ADDR_W = info->nand.IO_ADDR_R; |
| 1389 | info->nand.cmd_ctrl = omap_hwcontrol; |
| 1390 | |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1391 | /* |
| 1392 | * If RDY/BSY line is connected to OMAP then use the omap ready |
Peter Meerwald | 4cacbe2 | 2012-07-19 13:21:04 +0200 | [diff] [blame] | 1393 | * function and the generic nand_wait function which reads the status |
| 1394 | * register after monitoring the RDY/BSY line. Otherwise use a standard |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1395 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
| 1396 | * device and read status register until you get a failure or success |
| 1397 | */ |
| 1398 | if (pdata->dev_ready) { |
| 1399 | info->nand.dev_ready = omap_dev_ready; |
| 1400 | info->nand.chip_delay = 0; |
| 1401 | } else { |
| 1402 | info->nand.waitfunc = omap_wait; |
| 1403 | info->nand.chip_delay = 50; |
| 1404 | } |
| 1405 | |
Sukumar Ghorai | 1b0b323c | 2011-01-28 15:42:04 +0530 | [diff] [blame] | 1406 | switch (pdata->xfer_type) { |
| 1407 | case NAND_OMAP_PREFETCH_POLLED: |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 1408 | info->nand.read_buf = omap_read_buf_pref; |
| 1409 | info->nand.write_buf = omap_write_buf_pref; |
Sukumar Ghorai | 1b0b323c | 2011-01-28 15:42:04 +0530 | [diff] [blame] | 1410 | break; |
vimal singh | dfe3289 | 2009-07-13 16:29:16 +0530 | [diff] [blame] | 1411 | |
Sukumar Ghorai | 1b0b323c | 2011-01-28 15:42:04 +0530 | [diff] [blame] | 1412 | case NAND_OMAP_POLLED: |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 1413 | if (info->nand.options & NAND_BUSWIDTH_16) { |
| 1414 | info->nand.read_buf = omap_read_buf16; |
| 1415 | info->nand.write_buf = omap_write_buf16; |
| 1416 | } else { |
| 1417 | info->nand.read_buf = omap_read_buf8; |
| 1418 | info->nand.write_buf = omap_write_buf8; |
| 1419 | } |
Sukumar Ghorai | 1b0b323c | 2011-01-28 15:42:04 +0530 | [diff] [blame] | 1420 | break; |
| 1421 | |
| 1422 | case NAND_OMAP_PREFETCH_DMA: |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 1423 | dma_cap_zero(mask); |
| 1424 | dma_cap_set(DMA_SLAVE, mask); |
| 1425 | sig = OMAP24XX_DMA_GPMC; |
| 1426 | info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig); |
| 1427 | if (!info->dma) { |
Russell King | 2df41d0 | 2012-04-25 00:19:39 +0100 | [diff] [blame] | 1428 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
| 1429 | err = -ENXIO; |
| 1430 | goto out_release_mem_region; |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 1431 | } else { |
| 1432 | struct dma_slave_config cfg; |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 1433 | |
| 1434 | memset(&cfg, 0, sizeof(cfg)); |
| 1435 | cfg.src_addr = info->phys_base; |
| 1436 | cfg.dst_addr = info->phys_base; |
| 1437 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 1438 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 1439 | cfg.src_maxburst = 16; |
| 1440 | cfg.dst_maxburst = 16; |
Arnd Bergmann | d680e2c | 2012-08-04 11:05:25 +0000 | [diff] [blame] | 1441 | err = dmaengine_slave_config(info->dma, &cfg); |
| 1442 | if (err) { |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 1443 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
Arnd Bergmann | d680e2c | 2012-08-04 11:05:25 +0000 | [diff] [blame] | 1444 | err); |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 1445 | goto out_release_mem_region; |
| 1446 | } |
| 1447 | info->nand.read_buf = omap_read_buf_dma_pref; |
| 1448 | info->nand.write_buf = omap_write_buf_dma_pref; |
Sukumar Ghorai | 1b0b323c | 2011-01-28 15:42:04 +0530 | [diff] [blame] | 1449 | } |
| 1450 | break; |
| 1451 | |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 1452 | case NAND_OMAP_PREFETCH_IRQ: |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 1453 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
| 1454 | if (info->gpmc_irq_fifo <= 0) { |
| 1455 | dev_err(&pdev->dev, "error getting fifo irq\n"); |
| 1456 | err = -ENODEV; |
| 1457 | goto out_release_mem_region; |
| 1458 | } |
| 1459 | err = request_irq(info->gpmc_irq_fifo, omap_nand_irq, |
| 1460 | IRQF_SHARED, "gpmc-nand-fifo", info); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 1461 | if (err) { |
| 1462 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 1463 | info->gpmc_irq_fifo, err); |
| 1464 | info->gpmc_irq_fifo = 0; |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 1465 | goto out_release_mem_region; |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 1466 | } |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 1467 | |
| 1468 | info->gpmc_irq_count = platform_get_irq(pdev, 1); |
| 1469 | if (info->gpmc_irq_count <= 0) { |
| 1470 | dev_err(&pdev->dev, "error getting count irq\n"); |
| 1471 | err = -ENODEV; |
| 1472 | goto out_release_mem_region; |
| 1473 | } |
| 1474 | err = request_irq(info->gpmc_irq_count, omap_nand_irq, |
| 1475 | IRQF_SHARED, "gpmc-nand-count", info); |
| 1476 | if (err) { |
| 1477 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", |
| 1478 | info->gpmc_irq_count, err); |
| 1479 | info->gpmc_irq_count = 0; |
| 1480 | goto out_release_mem_region; |
| 1481 | } |
| 1482 | |
| 1483 | info->nand.read_buf = omap_read_buf_irq_pref; |
| 1484 | info->nand.write_buf = omap_write_buf_irq_pref; |
| 1485 | |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 1486 | break; |
| 1487 | |
Sukumar Ghorai | 1b0b323c | 2011-01-28 15:42:04 +0530 | [diff] [blame] | 1488 | default: |
| 1489 | dev_err(&pdev->dev, |
| 1490 | "xfer_type(%d) not supported!\n", pdata->xfer_type); |
| 1491 | err = -EINVAL; |
| 1492 | goto out_release_mem_region; |
vimal singh | 59e9c5a | 2009-07-13 16:26:24 +0530 | [diff] [blame] | 1493 | } |
Sukumar Ghorai | 1b0b323c | 2011-01-28 15:42:04 +0530 | [diff] [blame] | 1494 | |
Peter Meerwald | 4cacbe2 | 2012-07-19 13:21:04 +0200 | [diff] [blame] | 1495 | /* select the ecc type */ |
Sukumar Ghorai | f3d73f3 | 2011-01-28 15:42:08 +0530 | [diff] [blame] | 1496 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) |
| 1497 | info->nand.ecc.mode = NAND_ECC_SOFT; |
Sukumar Ghorai | f040d33 | 2011-01-28 15:42:09 +0530 | [diff] [blame] | 1498 | else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || |
| 1499 | (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { |
Sukumar Ghorai | f3d73f3 | 2011-01-28 15:42:08 +0530 | [diff] [blame] | 1500 | info->nand.ecc.bytes = 3; |
| 1501 | info->nand.ecc.size = 512; |
Mike Dunn | 6a918ba | 2012-03-11 14:21:11 -0700 | [diff] [blame] | 1502 | info->nand.ecc.strength = 1; |
Sukumar Ghorai | f3d73f3 | 2011-01-28 15:42:08 +0530 | [diff] [blame] | 1503 | info->nand.ecc.calculate = omap_calculate_ecc; |
| 1504 | info->nand.ecc.hwctl = omap_enable_hwecc; |
| 1505 | info->nand.ecc.correct = omap_correct_data; |
| 1506 | info->nand.ecc.mode = NAND_ECC_HW; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1507 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
| 1508 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { |
| 1509 | err = omap3_init_bch(&info->mtd, pdata->ecc_opt); |
| 1510 | if (err) { |
| 1511 | err = -EINVAL; |
| 1512 | goto out_release_mem_region; |
| 1513 | } |
Sukumar Ghorai | f3d73f3 | 2011-01-28 15:42:08 +0530 | [diff] [blame] | 1514 | } |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1515 | |
| 1516 | /* DIP switches on some boards change between 8 and 16 bit |
| 1517 | * bus widths for flash. Try the other width if the first try fails. |
| 1518 | */ |
Jan Weitzel | a80f1c1 | 2011-04-19 16:15:34 +0200 | [diff] [blame] | 1519 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1520 | info->nand.options ^= NAND_BUSWIDTH_16; |
Jan Weitzel | a80f1c1 | 2011-04-19 16:15:34 +0200 | [diff] [blame] | 1521 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1522 | err = -ENXIO; |
| 1523 | goto out_release_mem_region; |
| 1524 | } |
| 1525 | } |
| 1526 | |
Sukumar Ghorai | f040d33 | 2011-01-28 15:42:09 +0530 | [diff] [blame] | 1527 | /* rom code layout */ |
| 1528 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { |
| 1529 | |
| 1530 | if (info->nand.options & NAND_BUSWIDTH_16) |
| 1531 | offset = 2; |
| 1532 | else { |
| 1533 | offset = 1; |
| 1534 | info->nand.badblock_pattern = &bb_descrip_flashbased; |
| 1535 | } |
| 1536 | omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16); |
| 1537 | for (i = 0; i < omap_oobinfo.eccbytes; i++) |
| 1538 | omap_oobinfo.eccpos[i] = i+offset; |
| 1539 | |
| 1540 | omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; |
| 1541 | omap_oobinfo.oobfree->length = info->mtd.oobsize - |
| 1542 | (offset + omap_oobinfo.eccbytes); |
| 1543 | |
| 1544 | info->nand.ecc.layout = &omap_oobinfo; |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1545 | } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) || |
| 1546 | (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) { |
| 1547 | /* build OOB layout for BCH ECC correction */ |
| 1548 | err = omap3_init_bch_tail(&info->mtd); |
| 1549 | if (err) { |
| 1550 | err = -EINVAL; |
| 1551 | goto out_release_mem_region; |
| 1552 | } |
Sukumar Ghorai | f040d33 | 2011-01-28 15:42:09 +0530 | [diff] [blame] | 1553 | } |
Sukumar Ghorai | 1b0b323c | 2011-01-28 15:42:04 +0530 | [diff] [blame] | 1554 | |
Jan Weitzel | a80f1c1 | 2011-04-19 16:15:34 +0200 | [diff] [blame] | 1555 | /* second phase scan */ |
| 1556 | if (nand_scan_tail(&info->mtd)) { |
| 1557 | err = -ENXIO; |
| 1558 | goto out_release_mem_region; |
| 1559 | } |
| 1560 | |
Daniel Mack | ccf04c5 | 2012-12-14 11:36:41 +0100 | [diff] [blame^] | 1561 | ppdata.of_node = pdata->of_node; |
| 1562 | mtd_device_parse_register(&info->mtd, NULL, &ppdata, pdata->parts, |
Artem Bityutskiy | 42d7fbe | 2012-03-09 19:24:26 +0200 | [diff] [blame] | 1563 | pdata->nr_parts); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1564 | |
| 1565 | platform_set_drvdata(pdev, &info->mtd); |
| 1566 | |
| 1567 | return 0; |
| 1568 | |
| 1569 | out_release_mem_region: |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 1570 | if (info->dma) |
| 1571 | dma_release_channel(info->dma); |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 1572 | if (info->gpmc_irq_count > 0) |
| 1573 | free_irq(info->gpmc_irq_count, info); |
| 1574 | if (info->gpmc_irq_fifo > 0) |
| 1575 | free_irq(info->gpmc_irq_fifo, info); |
Afzal Mohammed | 9c4c2f8 | 2012-08-30 12:53:23 -0700 | [diff] [blame] | 1576 | release_mem_region(info->phys_base, info->mem_size); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1577 | out_free_info: |
| 1578 | kfree(info); |
| 1579 | |
| 1580 | return err; |
| 1581 | } |
| 1582 | |
| 1583 | static int omap_nand_remove(struct platform_device *pdev) |
| 1584 | { |
| 1585 | struct mtd_info *mtd = platform_get_drvdata(pdev); |
Vimal Singh | f35b6ed | 2010-01-05 16:01:08 +0530 | [diff] [blame] | 1586 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
| 1587 | mtd); |
Ivan Djelic | 0e618ef | 2012-04-30 12:17:18 +0200 | [diff] [blame] | 1588 | omap3_free_bch(&info->mtd); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1589 | |
| 1590 | platform_set_drvdata(pdev, NULL); |
Russell King | 763e735 | 2012-04-25 00:16:00 +0100 | [diff] [blame] | 1591 | if (info->dma) |
| 1592 | dma_release_channel(info->dma); |
| 1593 | |
Afzal Mohammed | 5c46845 | 2012-08-30 12:53:24 -0700 | [diff] [blame] | 1594 | if (info->gpmc_irq_count > 0) |
| 1595 | free_irq(info->gpmc_irq_count, info); |
| 1596 | if (info->gpmc_irq_fifo > 0) |
| 1597 | free_irq(info->gpmc_irq_fifo, info); |
Sukumar Ghorai | 4e07037 | 2011-01-28 15:42:06 +0530 | [diff] [blame] | 1598 | |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1599 | /* Release NAND device, its internal structures and partitions */ |
| 1600 | nand_release(&info->mtd); |
Sukumar Ghorai | 2c01946c | 2010-07-09 09:14:45 +0000 | [diff] [blame] | 1601 | iounmap(info->nand.IO_ADDR_R); |
Afzal Mohammed | 48b51d4 | 2012-09-29 11:14:47 +0530 | [diff] [blame] | 1602 | release_mem_region(info->phys_base, info->mem_size); |
Andreas Bießmann | 7d9b110 | 2012-08-31 13:35:41 +0200 | [diff] [blame] | 1603 | kfree(info); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1604 | return 0; |
| 1605 | } |
| 1606 | |
| 1607 | static struct platform_driver omap_nand_driver = { |
| 1608 | .probe = omap_nand_probe, |
| 1609 | .remove = omap_nand_remove, |
| 1610 | .driver = { |
| 1611 | .name = DRIVER_NAME, |
| 1612 | .owner = THIS_MODULE, |
| 1613 | }, |
| 1614 | }; |
| 1615 | |
Axel Lin | f99640d | 2011-11-27 20:45:03 +0800 | [diff] [blame] | 1616 | module_platform_driver(omap_nand_driver); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1617 | |
Axel Lin | c804c73 | 2011-03-07 11:04:24 +0800 | [diff] [blame] | 1618 | MODULE_ALIAS("platform:" DRIVER_NAME); |
Vimal Singh | 67ce04b | 2009-05-12 13:47:03 -0700 | [diff] [blame] | 1619 | MODULE_LICENSE("GPL"); |
| 1620 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |