Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 2 | * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. |
| 3 | * All rights reserved. |
| 4 | * Authors: Carsten Langgaard <carstenl@mips.com> |
| 5 | * Maciej W. Rozycki <macro@mips.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) |
| 8 | * |
| 9 | * This program is free software; you can distribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License (Version 2) as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along |
| 19 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 20 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 21 | * |
| 22 | * MIPS boards specific PCI support. |
| 23 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <linux/types.h> |
| 25 | #include <linux/pci.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/init.h> |
| 28 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include <asm/gt64120.h> |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 30 | |
| 31 | #include <asm/mips-boards/generic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <asm/mips-boards/bonito64.h> |
| 33 | #include <asm/mips-boards/msc01_pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | |
| 35 | static struct resource bonito64_mem_resource = { |
| 36 | .name = "Bonito PCI MEM", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | .flags = IORESOURCE_MEM, |
| 38 | }; |
| 39 | |
| 40 | static struct resource bonito64_io_resource = { |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 41 | .name = "Bonito PCI I/O", |
| 42 | .start = 0x00000000UL, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | .end = 0x000fffffUL, |
| 44 | .flags = IORESOURCE_IO, |
| 45 | }; |
| 46 | |
| 47 | static struct resource gt64120_mem_resource = { |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 48 | .name = "GT-64120 PCI MEM", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | .flags = IORESOURCE_MEM, |
| 50 | }; |
| 51 | |
| 52 | static struct resource gt64120_io_resource = { |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 53 | .name = "GT-64120 PCI I/O", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | .flags = IORESOURCE_IO, |
| 55 | }; |
| 56 | |
| 57 | static struct resource msc_mem_resource = { |
| 58 | .name = "MSC PCI MEM", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | .flags = IORESOURCE_MEM, |
| 60 | }; |
| 61 | |
| 62 | static struct resource msc_io_resource = { |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 63 | .name = "MSC PCI I/O", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | .flags = IORESOURCE_IO, |
| 65 | }; |
| 66 | |
| 67 | extern struct pci_ops bonito64_pci_ops; |
| 68 | extern struct pci_ops gt64120_pci_ops; |
| 69 | extern struct pci_ops msc_pci_ops; |
| 70 | |
| 71 | static struct pci_controller bonito64_controller = { |
| 72 | .pci_ops = &bonito64_pci_ops, |
| 73 | .io_resource = &bonito64_io_resource, |
| 74 | .mem_resource = &bonito64_mem_resource, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | .io_offset = 0x00000000UL, |
| 76 | }; |
| 77 | |
| 78 | static struct pci_controller gt64120_controller = { |
| 79 | .pci_ops = >64120_pci_ops, |
| 80 | .io_resource = >64120_io_resource, |
| 81 | .mem_resource = >64120_mem_resource, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | }; |
| 83 | |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 84 | static struct pci_controller msc_controller = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | .pci_ops = &msc_pci_ops, |
| 86 | .io_resource = &msc_io_resource, |
| 87 | .mem_resource = &msc_mem_resource, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | }; |
| 89 | |
Ralf Baechle | c83cfc9 | 2005-06-21 13:56:30 +0000 | [diff] [blame] | 90 | void __init mips_pcibios_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | { |
| 92 | struct pci_controller *controller; |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 93 | unsigned long start, end, map, start1, end1, map1, map2, map3, mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | |
| 95 | switch (mips_revision_corid) { |
| 96 | case MIPS_REVISION_CORID_QED_RM5261: |
| 97 | case MIPS_REVISION_CORID_CORE_LV: |
| 98 | case MIPS_REVISION_CORID_CORE_FPGA: |
| 99 | case MIPS_REVISION_CORID_CORE_FPGAR2: |
| 100 | /* |
| 101 | * Due to a bug in the Galileo system controller, we need |
| 102 | * to setup the PCI BAR for the Galileo internal registers. |
| 103 | * This should be done in the bios/bootprom and will be |
| 104 | * fixed in a later revision of YAMON (the MIPS boards |
| 105 | * boot prom). |
| 106 | */ |
| 107 | GT_WRITE(GT_PCI0_CFGADDR_OFS, |
| 108 | (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */ |
| 109 | (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */ |
| 110 | (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/ |
| 111 | ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/ |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 112 | GT_PCI0_CFGADDR_CONFIGEN_BIT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | |
| 114 | /* Perform the write */ |
| 115 | GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE)); |
| 116 | |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 117 | /* Set up resource ranges from the controller's registers. */ |
| 118 | start = GT_READ(GT_PCI0M0LD_OFS); |
| 119 | end = GT_READ(GT_PCI0M0HD_OFS); |
| 120 | map = GT_READ(GT_PCI0M0REMAP_OFS); |
| 121 | end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); |
| 122 | start1 = GT_READ(GT_PCI0M1LD_OFS); |
| 123 | end1 = GT_READ(GT_PCI0M1HD_OFS); |
| 124 | map1 = GT_READ(GT_PCI0M1REMAP_OFS); |
| 125 | end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK); |
| 126 | /* Cannot support multiple windows, use the wider. */ |
| 127 | if (end1 - start1 > end - start) { |
| 128 | start = start1; |
| 129 | end = end1; |
| 130 | map = map1; |
| 131 | } |
| 132 | mask = ~(start ^ end); |
| 133 | /* We don't support remapping with a discontiguous mask. */ |
| 134 | BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && |
| 135 | mask != ~((mask & -mask) - 1)); |
| 136 | gt64120_mem_resource.start = start; |
| 137 | gt64120_mem_resource.end = end; |
| 138 | gt64120_controller.mem_offset = (start & mask) - (map & mask); |
| 139 | /* Addresses are 36-bit, so do shifts in the destinations. */ |
| 140 | gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF; |
| 141 | gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF; |
| 142 | gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; |
| 143 | gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF; |
| 144 | |
| 145 | start = GT_READ(GT_PCI0IOLD_OFS); |
| 146 | end = GT_READ(GT_PCI0IOHD_OFS); |
| 147 | map = GT_READ(GT_PCI0IOREMAP_OFS); |
| 148 | end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK); |
| 149 | mask = ~(start ^ end); |
| 150 | /* We don't support remapping with a discontiguous mask. */ |
| 151 | BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) && |
| 152 | mask != ~((mask & -mask) - 1)); |
| 153 | gt64120_io_resource.start = map & mask; |
| 154 | gt64120_io_resource.end = (map & mask) | ~mask; |
| 155 | gt64120_controller.io_offset = 0; |
| 156 | /* Addresses are 36-bit, so do shifts in the destinations. */ |
| 157 | gt64120_io_resource.start <<= GT_PCI_DCRM_SHF; |
| 158 | gt64120_io_resource.end <<= GT_PCI_DCRM_SHF; |
| 159 | gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1; |
| 160 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | controller = >64120_controller; |
| 162 | break; |
| 163 | |
| 164 | case MIPS_REVISION_CORID_BONITO64: |
| 165 | case MIPS_REVISION_CORID_CORE_20K: |
| 166 | case MIPS_REVISION_CORID_CORE_EMUL_BON: |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 167 | /* Set up resource ranges from the controller's registers. */ |
| 168 | map = BONITO_PCIMAP; |
| 169 | map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >> |
| 170 | BONITO_PCIMAP_PCIMAP_LO0_SHIFT; |
| 171 | map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >> |
| 172 | BONITO_PCIMAP_PCIMAP_LO1_SHIFT; |
| 173 | map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >> |
| 174 | BONITO_PCIMAP_PCIMAP_LO2_SHIFT; |
| 175 | /* Combine as many adjacent windows as possible. */ |
| 176 | map = map1; |
| 177 | start = BONITO_PCILO0_BASE; |
| 178 | end = 1; |
| 179 | if (map3 == map2 + 1) { |
| 180 | map = map2; |
| 181 | start = BONITO_PCILO1_BASE; |
| 182 | end++; |
| 183 | } |
| 184 | if (map2 == map1 + 1) { |
| 185 | map = map1; |
| 186 | start = BONITO_PCILO0_BASE; |
| 187 | end++; |
| 188 | } |
| 189 | bonito64_mem_resource.start = start; |
| 190 | bonito64_mem_resource.end = start + |
| 191 | BONITO_PCIMAP_WINBASE(end) - 1; |
| 192 | bonito64_controller.mem_offset = start - |
| 193 | BONITO_PCIMAP_WINBASE(map); |
| 194 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | controller = &bonito64_controller; |
| 196 | break; |
| 197 | |
| 198 | case MIPS_REVISION_CORID_CORE_MSC: |
| 199 | case MIPS_REVISION_CORID_CORE_FPGA2: |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 200 | case MIPS_REVISION_CORID_CORE_FPGA3: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 202 | /* Set up resource ranges from the controller's registers. */ |
| 203 | MSC_READ(MSC01_PCI_SC2PMBASL, start); |
| 204 | MSC_READ(MSC01_PCI_SC2PMMSKL, mask); |
| 205 | MSC_READ(MSC01_PCI_SC2PMMAPL, map); |
| 206 | msc_mem_resource.start = start & mask; |
| 207 | msc_mem_resource.end = (start & mask) | ~mask; |
| 208 | msc_controller.mem_offset = (start & mask) - (map & mask); |
| 209 | |
| 210 | MSC_READ(MSC01_PCI_SC2PIOBASL, start); |
| 211 | MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); |
| 212 | MSC_READ(MSC01_PCI_SC2PIOMAPL, map); |
| 213 | msc_io_resource.start = map & mask; |
| 214 | msc_io_resource.end = (map & mask) | ~mask; |
| 215 | msc_controller.io_offset = 0; |
| 216 | ioport_resource.end = ~mask; |
| 217 | |
| 218 | /* If ranges overlap I/O takes precedence. */ |
| 219 | start = start & mask; |
| 220 | end = start | ~mask; |
| 221 | if ((start >= msc_mem_resource.start && |
| 222 | start <= msc_mem_resource.end) || |
| 223 | (end >= msc_mem_resource.start && |
| 224 | end <= msc_mem_resource.end)) { |
| 225 | /* Use the larger space. */ |
| 226 | start = max(start, msc_mem_resource.start); |
| 227 | end = min(end, msc_mem_resource.end); |
| 228 | if (start - msc_mem_resource.start >= |
| 229 | msc_mem_resource.end - end) |
| 230 | msc_mem_resource.end = start - 1; |
| 231 | else |
| 232 | msc_mem_resource.start = end + 1; |
| 233 | } |
| 234 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | controller = &msc_controller; |
| 236 | break; |
| 237 | default: |
Ralf Baechle | c83cfc9 | 2005-06-21 13:56:30 +0000 | [diff] [blame] | 238 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 239 | } |
| 240 | |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 241 | if (controller->io_resource->start < 0x00001000UL) /* FIXME */ |
| 242 | controller->io_resource->start = 0x00001000UL; |
| 243 | |
| 244 | iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | ioport_resource.end = controller->io_resource->end; |
| 246 | |
| 247 | register_pci_controller (controller); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | } |