Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. |
| 3 | * |
| 4 | * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) |
| 5 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
| 6 | * Copyright (C) 1999 - 2001 Kanoj Sarcar |
| 7 | */ |
Ralf Baechle | d3ffd08 | 2005-08-08 12:42:26 +0000 | [diff] [blame] | 8 | |
| 9 | #undef DEBUG |
| 10 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/config.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/irq.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/signal.h> |
| 16 | #include <linux/sched.h> |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/ioport.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <linux/timex.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/random.h> |
| 23 | #include <linux/smp_lock.h> |
Ralf Baechle | d3ffd08 | 2005-08-08 12:42:26 +0000 | [diff] [blame] | 24 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <linux/kernel_stat.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/bitops.h> |
| 28 | |
| 29 | #include <asm/bootinfo.h> |
| 30 | #include <asm/io.h> |
| 31 | #include <asm/mipsregs.h> |
| 32 | #include <asm/system.h> |
| 33 | |
| 34 | #include <asm/ptrace.h> |
| 35 | #include <asm/processor.h> |
| 36 | #include <asm/pci/bridge.h> |
| 37 | #include <asm/sn/addrs.h> |
| 38 | #include <asm/sn/agent.h> |
| 39 | #include <asm/sn/arch.h> |
| 40 | #include <asm/sn/hub.h> |
| 41 | #include <asm/sn/intr.h> |
| 42 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | /* |
| 44 | * Linux has a controller-independent x86 interrupt architecture. |
| 45 | * every controller has a 'controller-template', that is used |
| 46 | * by the main code to do the right thing. Each driver-visible |
| 47 | * interrupt source is transparently wired to the apropriate |
| 48 | * controller. Thus drivers need not be aware of the |
| 49 | * interrupt-controller. |
| 50 | * |
| 51 | * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, |
| 52 | * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. |
| 53 | * (IO-APICs assumed to be messaging to Pentium local-APICs) |
| 54 | * |
| 55 | * the code is designed to be easily extended with new/different |
| 56 | * interrupt controllers, without having to do assembly magic. |
| 57 | */ |
| 58 | |
| 59 | extern asmlinkage void ip27_irq(void); |
| 60 | |
| 61 | extern struct bridge_controller *irq_to_bridge[]; |
| 62 | extern int irq_to_slot[]; |
| 63 | |
| 64 | /* |
| 65 | * use these macros to get the encoded nasid and widget id |
| 66 | * from the irq value |
| 67 | */ |
| 68 | #define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)] |
| 69 | #define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i] |
| 70 | |
| 71 | static inline int alloc_level(int cpu, int irq) |
| 72 | { |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 73 | struct hub_data *hub = hub_data(cpu_to_node(cpu)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | struct slice_data *si = cpu_data[cpu].data; |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 75 | int level; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 77 | level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | if (level >= LEVELS_PER_SLICE) |
| 79 | panic("Cpu %d flooded with devices\n", cpu); |
| 80 | |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 81 | __set_bit(level, hub->irq_alloc_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | si->level_to_irq[level] = irq; |
| 83 | |
| 84 | return level; |
| 85 | } |
| 86 | |
| 87 | static inline int find_level(cpuid_t *cpunum, int irq) |
| 88 | { |
| 89 | int cpu, i; |
| 90 | |
Andrew Morton | 394e390 | 2006-03-23 03:01:05 -0800 | [diff] [blame] | 91 | for_each_online_cpu(cpu) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | struct slice_data *si = cpu_data[cpu].data; |
| 93 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++) |
| 95 | if (si->level_to_irq[i] == irq) { |
| 96 | *cpunum = cpu; |
| 97 | |
| 98 | return i; |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | panic("Could not identify cpu/level for irq %d\n", irq); |
| 103 | } |
| 104 | |
| 105 | /* |
| 106 | * Find first bit set |
| 107 | */ |
| 108 | static int ms1bit(unsigned long x) |
| 109 | { |
| 110 | int b = 0, s; |
| 111 | |
| 112 | s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s; |
| 113 | s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s; |
| 114 | s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s; |
| 115 | s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s; |
| 116 | s = 1; if (x >> 1 == 0) s = 0; b += s; |
| 117 | |
| 118 | return b; |
| 119 | } |
| 120 | |
| 121 | /* |
| 122 | * This code is unnecessarily complex, because we do SA_INTERRUPT |
| 123 | * intr enabling. Basically, once we grab the set of intrs we need |
| 124 | * to service, we must mask _all_ these interrupts; firstly, to make |
| 125 | * sure the same intr does not intr again, causing recursion that |
| 126 | * can lead to stack overflow. Secondly, we can not just mask the |
| 127 | * one intr we are do_IRQing, because the non-masked intrs in the |
| 128 | * first set might intr again, causing multiple servicings of the |
| 129 | * same intr. This effect is mostly seen for intercpu intrs. |
| 130 | * Kanoj 05.13.00 |
| 131 | */ |
| 132 | |
| 133 | void ip27_do_irq_mask0(struct pt_regs *regs) |
| 134 | { |
| 135 | int irq, swlevel; |
| 136 | hubreg_t pend0, mask0; |
| 137 | cpuid_t cpu = smp_processor_id(); |
| 138 | int pi_int_mask0 = |
| 139 | (cputoslice(cpu) == 0) ? PI_INT_MASK0_A : PI_INT_MASK0_B; |
| 140 | |
| 141 | /* copied from Irix intpend0() */ |
| 142 | pend0 = LOCAL_HUB_L(PI_INT_PEND0); |
| 143 | mask0 = LOCAL_HUB_L(pi_int_mask0); |
| 144 | |
| 145 | pend0 &= mask0; /* Pick intrs we should look at */ |
| 146 | if (!pend0) |
| 147 | return; |
| 148 | |
| 149 | swlevel = ms1bit(pend0); |
| 150 | #ifdef CONFIG_SMP |
| 151 | if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) { |
| 152 | LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ); |
| 153 | } else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) { |
| 154 | LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ); |
| 155 | } else if (pend0 & (1UL << CPU_CALL_A_IRQ)) { |
| 156 | LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ); |
| 157 | smp_call_function_interrupt(); |
| 158 | } else if (pend0 & (1UL << CPU_CALL_B_IRQ)) { |
| 159 | LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ); |
| 160 | smp_call_function_interrupt(); |
| 161 | } else |
| 162 | #endif |
| 163 | { |
| 164 | /* "map" swlevel to irq */ |
| 165 | struct slice_data *si = cpu_data[cpu].data; |
| 166 | |
| 167 | irq = si->level_to_irq[swlevel]; |
| 168 | do_IRQ(irq, regs); |
| 169 | } |
| 170 | |
| 171 | LOCAL_HUB_L(PI_INT_PEND0); |
| 172 | } |
| 173 | |
| 174 | void ip27_do_irq_mask1(struct pt_regs *regs) |
| 175 | { |
| 176 | int irq, swlevel; |
| 177 | hubreg_t pend1, mask1; |
| 178 | cpuid_t cpu = smp_processor_id(); |
| 179 | int pi_int_mask1 = (cputoslice(cpu) == 0) ? PI_INT_MASK1_A : PI_INT_MASK1_B; |
| 180 | struct slice_data *si = cpu_data[cpu].data; |
| 181 | |
| 182 | /* copied from Irix intpend0() */ |
| 183 | pend1 = LOCAL_HUB_L(PI_INT_PEND1); |
| 184 | mask1 = LOCAL_HUB_L(pi_int_mask1); |
| 185 | |
| 186 | pend1 &= mask1; /* Pick intrs we should look at */ |
| 187 | if (!pend1) |
| 188 | return; |
| 189 | |
| 190 | swlevel = ms1bit(pend1); |
| 191 | /* "map" swlevel to irq */ |
| 192 | irq = si->level_to_irq[swlevel]; |
| 193 | LOCAL_HUB_CLR_INTR(swlevel); |
| 194 | do_IRQ(irq, regs); |
| 195 | |
| 196 | LOCAL_HUB_L(PI_INT_PEND1); |
| 197 | } |
| 198 | |
| 199 | void ip27_prof_timer(struct pt_regs *regs) |
| 200 | { |
| 201 | panic("CPU %d got a profiling interrupt", smp_processor_id()); |
| 202 | } |
| 203 | |
| 204 | void ip27_hub_error(struct pt_regs *regs) |
| 205 | { |
| 206 | panic("CPU %d got a hub error interrupt", smp_processor_id()); |
| 207 | } |
| 208 | |
| 209 | static int intr_connect_level(int cpu, int bit) |
| 210 | { |
| 211 | nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); |
| 212 | struct slice_data *si = cpu_data[cpu].data; |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 213 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 215 | set_bit(bit, si->irq_enable_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 217 | local_irq_save(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | if (!cputoslice(cpu)) { |
| 219 | REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); |
| 220 | REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); |
| 221 | } else { |
| 222 | REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); |
| 223 | REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); |
| 224 | } |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 225 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | |
| 227 | return 0; |
| 228 | } |
| 229 | |
| 230 | static int intr_disconnect_level(int cpu, int bit) |
| 231 | { |
| 232 | nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); |
| 233 | struct slice_data *si = cpu_data[cpu].data; |
| 234 | |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 235 | clear_bit(bit, si->irq_enable_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | |
| 237 | if (!cputoslice(cpu)) { |
| 238 | REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); |
| 239 | REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); |
| 240 | } else { |
| 241 | REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); |
| 242 | REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); |
| 243 | } |
| 244 | |
| 245 | return 0; |
| 246 | } |
| 247 | |
| 248 | /* Startup one of the (PCI ...) IRQs routes over a bridge. */ |
| 249 | static unsigned int startup_bridge_irq(unsigned int irq) |
| 250 | { |
| 251 | struct bridge_controller *bc; |
| 252 | bridgereg_t device; |
| 253 | bridge_t *bridge; |
| 254 | int pin, swlevel; |
| 255 | cpuid_t cpu; |
| 256 | |
| 257 | pin = SLOT_FROM_PCI_IRQ(irq); |
| 258 | bc = IRQ_TO_BRIDGE(irq); |
| 259 | bridge = bc->base; |
| 260 | |
Ralf Baechle | d3ffd08 | 2005-08-08 12:42:26 +0000 | [diff] [blame] | 261 | pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", irq, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | /* |
| 263 | * "map" irq to a swlevel greater than 6 since the first 6 bits |
| 264 | * of INT_PEND0 are taken |
| 265 | */ |
| 266 | swlevel = find_level(&cpu, irq); |
| 267 | bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); |
| 268 | bridge->b_int_enable |= (1 << pin); |
| 269 | bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ |
| 270 | |
| 271 | /* |
| 272 | * Enable sending of an interrupt clear packt to the hub on a high to |
| 273 | * low transition of the interrupt pin. |
| 274 | * |
| 275 | * IRIX sets additional bits in the address which are documented as |
| 276 | * reserved in the bridge docs. |
| 277 | */ |
| 278 | bridge->b_int_mode |= (1UL << pin); |
| 279 | |
| 280 | /* |
| 281 | * We assume the bridge to have a 1:1 mapping between devices |
| 282 | * (slots) and intr pins. |
| 283 | */ |
| 284 | device = bridge->b_int_device; |
| 285 | device &= ~(7 << (pin*3)); |
| 286 | device |= (pin << (pin*3)); |
| 287 | bridge->b_int_device = device; |
| 288 | |
| 289 | bridge->b_wid_tflush; |
| 290 | |
| 291 | return 0; /* Never anything pending. */ |
| 292 | } |
| 293 | |
| 294 | /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ |
| 295 | static void shutdown_bridge_irq(unsigned int irq) |
| 296 | { |
| 297 | struct bridge_controller *bc = IRQ_TO_BRIDGE(irq); |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 298 | struct hub_data *hub = hub_data(cpu_to_node(bc->irq_cpu)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | bridge_t *bridge = bc->base; |
| 300 | struct slice_data *si = cpu_data[bc->irq_cpu].data; |
| 301 | int pin, swlevel; |
| 302 | cpuid_t cpu; |
| 303 | |
Ralf Baechle | d3ffd08 | 2005-08-08 12:42:26 +0000 | [diff] [blame] | 304 | pr_debug("bridge_shutdown: irq 0x%x\n", irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | pin = SLOT_FROM_PCI_IRQ(irq); |
| 306 | |
| 307 | /* |
| 308 | * map irq to a swlevel greater than 6 since the first 6 bits |
| 309 | * of INT_PEND0 are taken |
| 310 | */ |
| 311 | swlevel = find_level(&cpu, irq); |
| 312 | intr_disconnect_level(cpu, swlevel); |
| 313 | |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 314 | __clear_bit(swlevel, hub->irq_alloc_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | si->level_to_irq[swlevel] = -1; |
| 316 | |
| 317 | bridge->b_int_enable &= ~(1 << pin); |
| 318 | bridge->b_wid_tflush; |
| 319 | } |
| 320 | |
| 321 | static inline void enable_bridge_irq(unsigned int irq) |
| 322 | { |
| 323 | cpuid_t cpu; |
| 324 | int swlevel; |
| 325 | |
| 326 | swlevel = find_level(&cpu, irq); /* Criminal offence */ |
| 327 | intr_connect_level(cpu, swlevel); |
| 328 | } |
| 329 | |
| 330 | static inline void disable_bridge_irq(unsigned int irq) |
| 331 | { |
| 332 | cpuid_t cpu; |
| 333 | int swlevel; |
| 334 | |
| 335 | swlevel = find_level(&cpu, irq); /* Criminal offence */ |
| 336 | intr_disconnect_level(cpu, swlevel); |
| 337 | } |
| 338 | |
| 339 | static void mask_and_ack_bridge_irq(unsigned int irq) |
| 340 | { |
| 341 | disable_bridge_irq(irq); |
| 342 | } |
| 343 | |
| 344 | static void end_bridge_irq(unsigned int irq) |
| 345 | { |
| 346 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && |
| 347 | irq_desc[irq].action) |
| 348 | enable_bridge_irq(irq); |
| 349 | } |
| 350 | |
| 351 | static struct hw_interrupt_type bridge_irq_type = { |
| 352 | .typename = "bridge", |
| 353 | .startup = startup_bridge_irq, |
| 354 | .shutdown = shutdown_bridge_irq, |
| 355 | .enable = enable_bridge_irq, |
| 356 | .disable = disable_bridge_irq, |
| 357 | .ack = mask_and_ack_bridge_irq, |
| 358 | .end = end_bridge_irq, |
| 359 | }; |
| 360 | |
| 361 | static unsigned long irq_map[NR_IRQS / BITS_PER_LONG]; |
| 362 | |
| 363 | static int allocate_irqno(void) |
| 364 | { |
| 365 | int irq; |
| 366 | |
| 367 | again: |
| 368 | irq = find_first_zero_bit(irq_map, NR_IRQS); |
| 369 | |
| 370 | if (irq >= NR_IRQS) |
| 371 | return -ENOSPC; |
| 372 | |
| 373 | if (test_and_set_bit(irq, irq_map)) |
| 374 | goto again; |
| 375 | |
| 376 | return irq; |
| 377 | } |
| 378 | |
| 379 | void free_irqno(unsigned int irq) |
| 380 | { |
| 381 | clear_bit(irq, irq_map); |
| 382 | } |
| 383 | |
| 384 | void __devinit register_bridge_irq(unsigned int irq) |
| 385 | { |
| 386 | irq_desc[irq].status = IRQ_DISABLED; |
| 387 | irq_desc[irq].action = 0; |
| 388 | irq_desc[irq].depth = 1; |
| 389 | irq_desc[irq].handler = &bridge_irq_type; |
| 390 | } |
| 391 | |
| 392 | int __devinit request_bridge_irq(struct bridge_controller *bc) |
| 393 | { |
| 394 | int irq = allocate_irqno(); |
| 395 | int swlevel, cpu; |
| 396 | nasid_t nasid; |
| 397 | |
| 398 | if (irq < 0) |
| 399 | return irq; |
| 400 | |
| 401 | /* |
| 402 | * "map" irq to a swlevel greater than 6 since the first 6 bits |
| 403 | * of INT_PEND0 are taken |
| 404 | */ |
| 405 | cpu = bc->irq_cpu; |
| 406 | swlevel = alloc_level(cpu, irq); |
| 407 | if (unlikely(swlevel < 0)) { |
| 408 | free_irqno(irq); |
| 409 | |
| 410 | return -EAGAIN; |
| 411 | } |
| 412 | |
| 413 | /* Make sure it's not already pending when we connect it. */ |
| 414 | nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); |
| 415 | REMOTE_HUB_CLR_INTR(nasid, swlevel); |
| 416 | |
| 417 | intr_connect_level(cpu, swlevel); |
| 418 | |
| 419 | register_bridge_irq(irq); |
| 420 | |
| 421 | return irq; |
| 422 | } |
| 423 | |
| 424 | void __init arch_init_irq(void) |
| 425 | { |
| 426 | set_except_vector(0, ip27_irq); |
| 427 | } |
| 428 | |
| 429 | void install_ipi(void) |
| 430 | { |
| 431 | int slice = LOCAL_HUB_L(PI_CPU_NUM); |
| 432 | int cpu = smp_processor_id(); |
| 433 | struct slice_data *si = cpu_data[cpu].data; |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 434 | struct hub_data *hub = hub_data(cpu_to_node(cpu)); |
| 435 | int resched, call; |
| 436 | |
| 437 | resched = CPU_RESCHED_A_IRQ + slice; |
| 438 | __set_bit(resched, hub->irq_alloc_mask); |
| 439 | __set_bit(resched, si->irq_enable_mask); |
| 440 | LOCAL_HUB_CLR_INTR(resched); |
| 441 | |
| 442 | call = CPU_CALL_A_IRQ + slice; |
| 443 | __set_bit(call, hub->irq_alloc_mask); |
| 444 | __set_bit(call, si->irq_enable_mask); |
| 445 | LOCAL_HUB_CLR_INTR(call); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | |
| 447 | if (slice == 0) { |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 448 | LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]); |
| 449 | LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 450 | } else { |
Ralf Baechle | 4f12bfe | 2005-03-21 18:59:38 +0000 | [diff] [blame] | 451 | LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]); |
| 452 | LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | } |
| 454 | } |