Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version 2 |
| 7 | * of the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 17 | */ |
| 18 | #include <linux/config.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/linkage.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/spinlock.h> |
| 24 | #include <linux/mm.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/kernel_stat.h> |
| 27 | |
| 28 | #include <asm/errno.h> |
| 29 | #include <asm/signal.h> |
| 30 | #include <asm/system.h> |
| 31 | #include <asm/ptrace.h> |
| 32 | #include <asm/io.h> |
| 33 | |
| 34 | #include <asm/sibyte/bcm1480_regs.h> |
| 35 | #include <asm/sibyte/bcm1480_int.h> |
| 36 | #include <asm/sibyte/bcm1480_scd.h> |
| 37 | |
| 38 | #include <asm/sibyte/sb1250_uart.h> |
| 39 | #include <asm/sibyte/sb1250.h> |
| 40 | |
| 41 | /* |
| 42 | * These are the routines that handle all the low level interrupt stuff. |
| 43 | * Actions handled here are: initialization of the interrupt map, requesting of |
| 44 | * interrupt lines by handlers, dispatching if interrupts to handlers, probing |
| 45 | * for interrupt lines |
| 46 | */ |
| 47 | |
| 48 | |
| 49 | #define shutdown_bcm1480_irq disable_bcm1480_irq |
| 50 | static void end_bcm1480_irq(unsigned int irq); |
| 51 | static void enable_bcm1480_irq(unsigned int irq); |
| 52 | static void disable_bcm1480_irq(unsigned int irq); |
| 53 | static unsigned int startup_bcm1480_irq(unsigned int irq); |
| 54 | static void ack_bcm1480_irq(unsigned int irq); |
| 55 | #ifdef CONFIG_SMP |
| 56 | static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); |
| 57 | #endif |
| 58 | |
| 59 | #ifdef CONFIG_PCI |
| 60 | extern unsigned long ht_eoi_space; |
| 61 | #endif |
| 62 | |
| 63 | #ifdef CONFIG_KGDB |
| 64 | #include <asm/gdb-stub.h> |
| 65 | extern void breakpoint(void); |
| 66 | static int kgdb_irq; |
| 67 | #ifdef CONFIG_GDB_CONSOLE |
| 68 | extern void register_gdb_console(void); |
| 69 | #endif |
| 70 | |
| 71 | /* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */ |
| 72 | static int kgdb_flag = 1; |
| 73 | static int __init nokgdb(char *str) |
| 74 | { |
| 75 | kgdb_flag = 0; |
| 76 | return 1; |
| 77 | } |
| 78 | __setup("nokgdb", nokgdb); |
| 79 | |
| 80 | /* Default to UART1 */ |
| 81 | int kgdb_port = 1; |
| 82 | #ifdef CONFIG_SIBYTE_SB1250_DUART |
| 83 | extern char sb1250_duart_present[]; |
| 84 | #endif |
| 85 | #endif |
| 86 | |
| 87 | static struct hw_interrupt_type bcm1480_irq_type = { |
| 88 | .typename = "BCM1480-IMR", |
| 89 | .startup = startup_bcm1480_irq, |
| 90 | .shutdown = shutdown_bcm1480_irq, |
| 91 | .enable = enable_bcm1480_irq, |
| 92 | .disable = disable_bcm1480_irq, |
| 93 | .ack = ack_bcm1480_irq, |
| 94 | .end = end_bcm1480_irq, |
| 95 | #ifdef CONFIG_SMP |
| 96 | .set_affinity = bcm1480_set_affinity |
| 97 | #endif |
| 98 | }; |
| 99 | |
| 100 | /* Store the CPU id (not the logical number) */ |
| 101 | int bcm1480_irq_owner[BCM1480_NR_IRQS]; |
| 102 | |
| 103 | DEFINE_SPINLOCK(bcm1480_imr_lock); |
| 104 | |
| 105 | void bcm1480_mask_irq(int cpu, int irq) |
| 106 | { |
| 107 | unsigned long flags; |
| 108 | u64 cur_ints,hl_spacing; |
| 109 | |
| 110 | spin_lock_irqsave(&bcm1480_imr_lock, flags); |
| 111 | hl_spacing = 0; |
| 112 | if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { |
| 113 | hl_spacing = BCM1480_IMR_HL_SPACING; |
| 114 | irq -= BCM1480_NR_IRQS_HALF; |
| 115 | } |
| 116 | cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); |
| 117 | cur_ints |= (((u64) 1) << irq); |
| 118 | ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); |
| 119 | spin_unlock_irqrestore(&bcm1480_imr_lock, flags); |
| 120 | } |
| 121 | |
| 122 | void bcm1480_unmask_irq(int cpu, int irq) |
| 123 | { |
| 124 | unsigned long flags; |
| 125 | u64 cur_ints,hl_spacing; |
| 126 | |
| 127 | spin_lock_irqsave(&bcm1480_imr_lock, flags); |
| 128 | hl_spacing = 0; |
| 129 | if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) { |
| 130 | hl_spacing = BCM1480_IMR_HL_SPACING; |
| 131 | irq -= BCM1480_NR_IRQS_HALF; |
| 132 | } |
| 133 | cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); |
| 134 | cur_ints &= ~(((u64) 1) << irq); |
| 135 | ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing)); |
| 136 | spin_unlock_irqrestore(&bcm1480_imr_lock, flags); |
| 137 | } |
| 138 | |
| 139 | #ifdef CONFIG_SMP |
| 140 | static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask) |
| 141 | { |
Martin Michlmayr | 76e1dae | 2006-02-20 04:57:00 +0000 | [diff] [blame] | 142 | int i = 0, old_cpu, cpu, int_on, k; |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 143 | u64 cur_ints; |
| 144 | irq_desc_t *desc = irq_desc + irq; |
| 145 | unsigned long flags; |
| 146 | unsigned int irq_dirty; |
| 147 | |
| 148 | i = first_cpu(mask); |
| 149 | if (next_cpu(i, mask) <= NR_CPUS) { |
| 150 | printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq); |
| 151 | return; |
| 152 | } |
| 153 | |
| 154 | /* Convert logical CPU to physical CPU */ |
| 155 | cpu = cpu_logical_map(i); |
| 156 | |
| 157 | /* Protect against other affinity changers and IMR manipulation */ |
| 158 | spin_lock_irqsave(&desc->lock, flags); |
| 159 | spin_lock(&bcm1480_imr_lock); |
| 160 | |
| 161 | /* Swizzle each CPU's IMR (but leave the IP selection alone) */ |
| 162 | old_cpu = bcm1480_irq_owner[irq]; |
| 163 | irq_dirty = irq; |
| 164 | if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { |
| 165 | irq_dirty -= BCM1480_NR_IRQS_HALF; |
| 166 | } |
| 167 | |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 168 | for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */ |
| 169 | cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); |
| 170 | int_on = !(cur_ints & (((u64) 1) << irq_dirty)); |
| 171 | if (int_on) { |
| 172 | /* If it was on, mask it */ |
| 173 | cur_ints |= (((u64) 1) << irq_dirty); |
| 174 | ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); |
| 175 | } |
| 176 | bcm1480_irq_owner[irq] = cpu; |
| 177 | if (int_on) { |
| 178 | /* unmask for the new CPU */ |
| 179 | cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); |
| 180 | cur_ints &= ~(((u64) 1) << irq_dirty); |
| 181 | ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); |
| 182 | } |
| 183 | } |
| 184 | spin_unlock(&bcm1480_imr_lock); |
| 185 | spin_unlock_irqrestore(&desc->lock, flags); |
| 186 | } |
| 187 | #endif |
| 188 | |
| 189 | |
| 190 | /* Defined in arch/mips/sibyte/bcm1480/irq_handler.S */ |
| 191 | extern void bcm1480_irq_handler(void); |
| 192 | |
| 193 | /*****************************************************************************/ |
| 194 | |
| 195 | static unsigned int startup_bcm1480_irq(unsigned int irq) |
| 196 | { |
| 197 | bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); |
| 198 | |
| 199 | return 0; /* never anything pending */ |
| 200 | } |
| 201 | |
| 202 | |
| 203 | static void disable_bcm1480_irq(unsigned int irq) |
| 204 | { |
| 205 | bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); |
| 206 | } |
| 207 | |
| 208 | static void enable_bcm1480_irq(unsigned int irq) |
| 209 | { |
| 210 | bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); |
| 211 | } |
| 212 | |
| 213 | |
| 214 | static void ack_bcm1480_irq(unsigned int irq) |
| 215 | { |
| 216 | u64 pending; |
| 217 | unsigned int irq_dirty; |
Martin Michlmayr | 76e1dae | 2006-02-20 04:57:00 +0000 | [diff] [blame] | 218 | int k; |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 219 | |
| 220 | /* |
| 221 | * If the interrupt was an HT interrupt, now is the time to |
| 222 | * clear it. NOTE: we assume the HT bridge was set up to |
| 223 | * deliver the interrupts to all CPUs (which makes affinity |
| 224 | * changing easier for us) |
| 225 | */ |
| 226 | irq_dirty = irq; |
| 227 | if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { |
| 228 | irq_dirty -= BCM1480_NR_IRQS_HALF; |
| 229 | } |
Andrew Isaacson | f137e46 | 2005-10-19 23:56:38 -0700 | [diff] [blame] | 230 | for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ |
| 231 | pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], |
| 232 | R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); |
| 233 | pending &= ((u64)1 << (irq_dirty)); |
| 234 | if (pending) { |
| 235 | #ifdef CONFIG_SMP |
| 236 | int i; |
| 237 | for (i=0; i<NR_CPUS; i++) { |
| 238 | /* |
| 239 | * Clear for all CPUs so an affinity switch |
| 240 | * doesn't find an old status |
| 241 | */ |
| 242 | __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), |
| 243 | R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); |
| 244 | } |
| 245 | #else |
| 246 | __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); |
| 247 | #endif |
| 248 | |
| 249 | /* |
| 250 | * Generate EOI. For Pass 1 parts, EOI is a nop. For |
| 251 | * Pass 2, the LDT world may be edge-triggered, but |
| 252 | * this EOI shouldn't hurt. If they are |
| 253 | * level-sensitive, the EOI is required. |
| 254 | */ |
| 255 | #ifdef CONFIG_PCI |
| 256 | if (ht_eoi_space) |
| 257 | *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; |
| 258 | #endif |
| 259 | } |
| 260 | } |
| 261 | bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); |
| 262 | } |
| 263 | |
| 264 | |
| 265 | static void end_bcm1480_irq(unsigned int irq) |
| 266 | { |
| 267 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { |
| 268 | bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq); |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | |
| 273 | void __init init_bcm1480_irqs(void) |
| 274 | { |
| 275 | int i; |
| 276 | |
| 277 | for (i = 0; i < NR_IRQS; i++) { |
| 278 | irq_desc[i].status = IRQ_DISABLED; |
| 279 | irq_desc[i].action = 0; |
| 280 | irq_desc[i].depth = 1; |
| 281 | if (i < BCM1480_NR_IRQS) { |
| 282 | irq_desc[i].handler = &bcm1480_irq_type; |
| 283 | bcm1480_irq_owner[i] = 0; |
| 284 | } else { |
| 285 | irq_desc[i].handler = &no_irq_type; |
| 286 | } |
| 287 | } |
| 288 | } |
| 289 | |
| 290 | |
| 291 | static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id, |
| 292 | struct pt_regs *regs) |
| 293 | { |
| 294 | return IRQ_NONE; |
| 295 | } |
| 296 | |
| 297 | static struct irqaction bcm1480_dummy_action = { |
| 298 | .handler = bcm1480_dummy_handler, |
| 299 | .flags = 0, |
| 300 | .mask = CPU_MASK_NONE, |
| 301 | .name = "bcm1480-private", |
| 302 | .next = NULL, |
| 303 | .dev_id = 0 |
| 304 | }; |
| 305 | |
| 306 | int bcm1480_steal_irq(int irq) |
| 307 | { |
| 308 | irq_desc_t *desc = irq_desc + irq; |
| 309 | unsigned long flags; |
| 310 | int retval = 0; |
| 311 | |
| 312 | if (irq >= BCM1480_NR_IRQS) |
| 313 | return -EINVAL; |
| 314 | |
| 315 | spin_lock_irqsave(&desc->lock,flags); |
| 316 | /* Don't allow sharing at all for these */ |
| 317 | if (desc->action != NULL) |
| 318 | retval = -EBUSY; |
| 319 | else { |
| 320 | desc->action = &bcm1480_dummy_action; |
| 321 | desc->depth = 0; |
| 322 | } |
| 323 | spin_unlock_irqrestore(&desc->lock,flags); |
| 324 | return 0; |
| 325 | } |
| 326 | |
| 327 | /* |
| 328 | * init_IRQ is called early in the boot sequence from init/main.c. It |
| 329 | * is responsible for setting up the interrupt mapper and installing the |
| 330 | * handler that will be responsible for dispatching interrupts to the |
| 331 | * "right" place. |
| 332 | */ |
| 333 | /* |
| 334 | * For now, map all interrupts to IP[2]. We could save |
| 335 | * some cycles by parceling out system interrupts to different |
| 336 | * IP lines, but keep it simple for bringup. We'll also direct |
| 337 | * all interrupts to a single CPU; we should probably route |
| 338 | * PCI and LDT to one cpu and everything else to the other |
| 339 | * to balance the load a bit. |
| 340 | * |
| 341 | * On the second cpu, everything is set to IP5, which is |
| 342 | * ignored, EXCEPT the mailbox interrupt. That one is |
| 343 | * set to IP[2] so it is handled. This is needed so we |
| 344 | * can do cross-cpu function calls, as requred by SMP |
| 345 | */ |
| 346 | |
| 347 | #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 |
| 348 | #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 |
| 349 | #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 |
| 350 | #define IMR_IP5_VAL K_BCM1480_INT_MAP_I3 |
| 351 | #define IMR_IP6_VAL K_BCM1480_INT_MAP_I4 |
| 352 | |
| 353 | void __init arch_init_irq(void) |
| 354 | { |
| 355 | |
| 356 | unsigned int i, cpu; |
| 357 | u64 tmp; |
| 358 | unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | |
| 359 | STATUSF_IP1 | STATUSF_IP0; |
| 360 | |
| 361 | /* Default everything to IP2 */ |
| 362 | /* Start with _high registers which has no bit 0 interrupt source */ |
| 363 | for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */ |
| 364 | for (cpu = 0; cpu < 4; cpu++) { |
| 365 | __raw_writeq(IMR_IP2_VAL, |
| 366 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, |
| 367 | R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3))); |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | /* Now do _low registers */ |
| 372 | for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) { |
| 373 | for (cpu = 0; cpu < 4; cpu++) { |
| 374 | __raw_writeq(IMR_IP2_VAL, |
| 375 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, |
| 376 | R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3))); |
| 377 | } |
| 378 | } |
| 379 | |
| 380 | init_bcm1480_irqs(); |
| 381 | |
| 382 | /* |
| 383 | * Map the high 16 bits of mailbox_0 registers to IP[3], for |
| 384 | * inter-cpu messages |
| 385 | */ |
| 386 | /* Was I1 */ |
| 387 | for (cpu = 0; cpu < 4; cpu++) { |
| 388 | __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + |
| 389 | (K_BCM1480_INT_MBOX_0_0 << 3))); |
| 390 | } |
| 391 | |
| 392 | |
| 393 | /* Clear the mailboxes. The firmware may leave them dirty */ |
| 394 | for (cpu = 0; cpu < 4; cpu++) { |
| 395 | __raw_writeq(0xffffffffffffffffULL, |
| 396 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); |
| 397 | __raw_writeq(0xffffffffffffffffULL, |
| 398 | IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); |
| 399 | } |
| 400 | |
| 401 | |
| 402 | /* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */ |
| 403 | tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0)); |
| 404 | for (cpu = 0; cpu < 4; cpu++) { |
| 405 | __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); |
| 406 | } |
| 407 | tmp = ~((u64) 0); |
| 408 | for (cpu = 0; cpu < 4; cpu++) { |
| 409 | __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); |
| 410 | } |
| 411 | |
| 412 | bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0); |
| 413 | |
| 414 | /* |
| 415 | * Note that the timer interrupts are also mapped, but this is |
| 416 | * done in bcm1480_time_init(). Also, the profiling driver |
| 417 | * does its own management of IP7. |
| 418 | */ |
| 419 | |
| 420 | #ifdef CONFIG_KGDB |
| 421 | imask |= STATUSF_IP6; |
| 422 | #endif |
| 423 | /* Enable necessary IPs, disable the rest */ |
| 424 | change_c0_status(ST0_IM, imask); |
| 425 | set_except_vector(0, bcm1480_irq_handler); |
| 426 | |
| 427 | #ifdef CONFIG_KGDB |
| 428 | if (kgdb_flag) { |
| 429 | kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port; |
| 430 | |
| 431 | #ifdef CONFIG_SIBYTE_SB1250_DUART |
| 432 | sb1250_duart_present[kgdb_port] = 0; |
| 433 | #endif |
| 434 | /* Setup uart 1 settings, mapper */ |
| 435 | /* QQQ FIXME */ |
| 436 | __raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port)); |
| 437 | |
| 438 | bcm1480_steal_irq(kgdb_irq); |
| 439 | __raw_writeq(IMR_IP6_VAL, |
| 440 | IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + |
| 441 | (kgdb_irq<<3)); |
| 442 | bcm1480_unmask_irq(0, kgdb_irq); |
| 443 | |
| 444 | #ifdef CONFIG_GDB_CONSOLE |
| 445 | register_gdb_console(); |
| 446 | #endif |
| 447 | prom_printf("Waiting for GDB on UART port %d\n", kgdb_port); |
| 448 | set_debug_traps(); |
| 449 | breakpoint(); |
| 450 | } |
| 451 | #endif |
| 452 | } |
| 453 | |
| 454 | #ifdef CONFIG_KGDB |
| 455 | |
| 456 | #include <linux/delay.h> |
| 457 | |
| 458 | #define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) |
| 459 | #define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) |
| 460 | |
| 461 | void bcm1480_kgdb_interrupt(struct pt_regs *regs) |
| 462 | { |
| 463 | /* |
| 464 | * Clear break-change status (allow some time for the remote |
| 465 | * host to stop the break, since we would see another |
| 466 | * interrupt on the end-of-break too) |
| 467 | */ |
| 468 | kstat.irqs[smp_processor_id()][kgdb_irq]++; |
| 469 | mdelay(500); |
| 470 | duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | |
| 471 | M_DUART_RX_EN | M_DUART_TX_EN); |
| 472 | set_async_breakpoint(®s->cp0_epc); |
| 473 | } |
| 474 | |
| 475 | #endif /* CONFIG_KGDB */ |