Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * Ocotea board specific routines |
| 3 | * |
| 4 | * Matt Porter <mporter@kernel.crashing.org> |
| 5 | * |
| 6 | * Copyright 2003-2005 MontaVista Software Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/config.h> |
| 15 | #include <linux/stddef.h> |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/init.h> |
| 18 | #include <linux/errno.h> |
| 19 | #include <linux/reboot.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/kdev_t.h> |
| 22 | #include <linux/types.h> |
| 23 | #include <linux/major.h> |
| 24 | #include <linux/blkdev.h> |
| 25 | #include <linux/console.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/ide.h> |
| 28 | #include <linux/initrd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include <linux/seq_file.h> |
| 30 | #include <linux/root_dev.h> |
| 31 | #include <linux/tty.h> |
| 32 | #include <linux/serial.h> |
| 33 | #include <linux/serial_core.h> |
| 34 | |
| 35 | #include <asm/system.h> |
| 36 | #include <asm/pgtable.h> |
| 37 | #include <asm/page.h> |
| 38 | #include <asm/dma.h> |
| 39 | #include <asm/io.h> |
| 40 | #include <asm/machdep.h> |
| 41 | #include <asm/ocp.h> |
| 42 | #include <asm/pci-bridge.h> |
| 43 | #include <asm/time.h> |
| 44 | #include <asm/todc.h> |
| 45 | #include <asm/bootinfo.h> |
| 46 | #include <asm/ppc4xx_pic.h> |
| 47 | #include <asm/ppcboot.h> |
Eugene Surovegin | 5ce17b1 | 2005-07-29 22:59:19 -0700 | [diff] [blame] | 48 | #include <asm/tlbflush.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
| 50 | #include <syslib/gen550.h> |
| 51 | #include <syslib/ibm440gx_common.h> |
| 52 | |
Matt Porter | d5f7b06 | 2005-10-28 17:46:14 -0700 | [diff] [blame] | 53 | extern bd_t __res; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | |
| 55 | static struct ibm44x_clocks clocks __initdata; |
| 56 | |
| 57 | static void __init |
| 58 | ocotea_calibrate_decr(void) |
| 59 | { |
| 60 | unsigned int freq; |
| 61 | |
| 62 | if (mfspr(SPRN_CCR1) & CCR1_TCS) |
| 63 | freq = OCOTEA_TMR_CLK; |
| 64 | else |
| 65 | freq = clocks.cpu; |
| 66 | |
| 67 | ibm44x_calibrate_decr(freq); |
| 68 | } |
| 69 | |
| 70 | static int |
| 71 | ocotea_show_cpuinfo(struct seq_file *m) |
| 72 | { |
| 73 | seq_printf(m, "vendor\t\t: IBM\n"); |
| 74 | seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n"); |
| 75 | ibm440gx_show_cpuinfo(m); |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | static inline int |
| 80 | ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) |
| 81 | { |
| 82 | static char pci_irq_table[][4] = |
| 83 | /* |
| 84 | * PCI IDSEL/INTPIN->INTLINE |
| 85 | * A B C D |
| 86 | */ |
| 87 | { |
| 88 | { 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */ |
| 89 | { 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */ |
| 90 | { 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */ |
| 91 | { 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */ |
| 92 | }; |
| 93 | |
| 94 | const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; |
| 95 | return PCI_IRQ_TABLE_LOOKUP; |
| 96 | } |
| 97 | |
| 98 | static void __init ocotea_set_emacdata(void) |
| 99 | { |
| 100 | struct ocp_def *def; |
| 101 | struct ocp_func_emac_data *emacdata; |
| 102 | int i; |
| 103 | |
| 104 | /* |
| 105 | * Note: Current rev. board only operates in Group 4a |
| 106 | * mode, so we always set EMAC0-1 for SMII and EMAC2-3 |
| 107 | * for RGMII (though these could run in RTBI just the same). |
| 108 | * |
| 109 | * The FPGA reg 3 information isn't even suitable for |
| 110 | * determining the phy_mode, so if the board becomes |
| 111 | * usable in !4a, it will be necessary to parse an environment |
| 112 | * variable from the firmware or similar to properly configure |
| 113 | * the phy_map/phy_mode. |
| 114 | */ |
| 115 | /* Set phy_map, phy_mode, and mac_addr for each EMAC */ |
| 116 | for (i=0; i<4; i++) { |
| 117 | def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); |
| 118 | emacdata = def->additions; |
| 119 | if (i < 2) { |
| 120 | emacdata->phy_map = 0x00000001; /* Skip 0x00 */ |
| 121 | emacdata->phy_mode = PHY_MODE_SMII; |
| 122 | } |
| 123 | else { |
| 124 | emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */ |
| 125 | emacdata->phy_mode = PHY_MODE_RGMII; |
| 126 | } |
| 127 | if (i == 0) |
| 128 | memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); |
| 129 | else if (i == 1) |
| 130 | memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6); |
| 131 | else if (i == 2) |
| 132 | memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6); |
| 133 | else if (i == 3) |
| 134 | memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6); |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | #define PCIX_READW(offset) \ |
| 139 | (readw(pcix_reg_base+offset)) |
| 140 | |
| 141 | #define PCIX_WRITEW(value, offset) \ |
| 142 | (writew(value, pcix_reg_base+offset)) |
| 143 | |
| 144 | #define PCIX_WRITEL(value, offset) \ |
| 145 | (writel(value, pcix_reg_base+offset)) |
| 146 | |
| 147 | /* |
| 148 | * FIXME: This is only here to "make it work". This will move |
| 149 | * to a ibm_pcix.c which will contain a generic IBM PCIX bridge |
| 150 | * configuration library. -Matt |
| 151 | */ |
| 152 | static void __init |
| 153 | ocotea_setup_pcix(void) |
| 154 | { |
| 155 | void *pcix_reg_base; |
| 156 | |
| 157 | pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE); |
| 158 | |
| 159 | /* Enable PCIX0 I/O, Mem, and Busmaster cycles */ |
| 160 | PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND); |
| 161 | |
| 162 | /* Disable all windows */ |
| 163 | PCIX_WRITEL(0, PCIX0_POM0SA); |
| 164 | PCIX_WRITEL(0, PCIX0_POM1SA); |
| 165 | PCIX_WRITEL(0, PCIX0_POM2SA); |
| 166 | PCIX_WRITEL(0, PCIX0_PIM0SA); |
| 167 | PCIX_WRITEL(0, PCIX0_PIM0SAH); |
| 168 | PCIX_WRITEL(0, PCIX0_PIM1SA); |
| 169 | PCIX_WRITEL(0, PCIX0_PIM2SA); |
| 170 | PCIX_WRITEL(0, PCIX0_PIM2SAH); |
| 171 | |
| 172 | /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */ |
| 173 | PCIX_WRITEL(0x00000003, PCIX0_POM0LAH); |
| 174 | PCIX_WRITEL(0x80000000, PCIX0_POM0LAL); |
| 175 | PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH); |
| 176 | PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL); |
| 177 | PCIX_WRITEL(0x80000001, PCIX0_POM0SA); |
| 178 | |
| 179 | /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */ |
| 180 | PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH); |
| 181 | PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL); |
| 182 | PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA); |
| 183 | |
| 184 | eieio(); |
| 185 | } |
| 186 | |
| 187 | static void __init |
| 188 | ocotea_setup_hose(void) |
| 189 | { |
| 190 | struct pci_controller *hose; |
| 191 | |
| 192 | /* Configure windows on the PCI-X host bridge */ |
| 193 | ocotea_setup_pcix(); |
| 194 | |
| 195 | hose = pcibios_alloc_controller(); |
| 196 | |
| 197 | if (!hose) |
| 198 | return; |
| 199 | |
| 200 | hose->first_busno = 0; |
| 201 | hose->last_busno = 0xff; |
| 202 | |
| 203 | hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET; |
| 204 | |
| 205 | pci_init_resource(&hose->io_resource, |
| 206 | OCOTEA_PCI_LOWER_IO, |
| 207 | OCOTEA_PCI_UPPER_IO, |
| 208 | IORESOURCE_IO, |
| 209 | "PCI host bridge"); |
| 210 | |
| 211 | pci_init_resource(&hose->mem_resources[0], |
| 212 | OCOTEA_PCI_LOWER_MEM, |
| 213 | OCOTEA_PCI_UPPER_MEM, |
| 214 | IORESOURCE_MEM, |
| 215 | "PCI host bridge"); |
| 216 | |
| 217 | hose->io_space.start = OCOTEA_PCI_LOWER_IO; |
| 218 | hose->io_space.end = OCOTEA_PCI_UPPER_IO; |
| 219 | hose->mem_space.start = OCOTEA_PCI_LOWER_MEM; |
| 220 | hose->mem_space.end = OCOTEA_PCI_UPPER_MEM; |
Al Viro | 92a11f9 | 2005-04-25 07:55:57 -0700 | [diff] [blame] | 221 | hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE); |
| 222 | isa_io_base = (unsigned long) hose->io_base_virt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | |
| 224 | setup_indirect_pci(hose, |
| 225 | OCOTEA_PCI_CFGA_PLB32, |
| 226 | OCOTEA_PCI_CFGD_PLB32); |
| 227 | hose->set_cfg_type = 1; |
| 228 | |
| 229 | hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); |
| 230 | |
| 231 | ppc_md.pci_swizzle = common_swizzle; |
| 232 | ppc_md.pci_map_irq = ocotea_map_irq; |
| 233 | } |
| 234 | |
| 235 | |
| 236 | TODC_ALLOC(); |
| 237 | |
| 238 | static void __init |
| 239 | ocotea_early_serial_map(void) |
| 240 | { |
| 241 | struct uart_port port; |
| 242 | |
| 243 | /* Setup ioremapped serial port access */ |
| 244 | memset(&port, 0, sizeof(port)); |
| 245 | port.membase = ioremap64(PPC440GX_UART0_ADDR, 8); |
| 246 | port.irq = UART0_INT; |
| 247 | port.uartclk = clocks.uart0; |
| 248 | port.regshift = 0; |
Russell King | 9b4a161 | 2006-02-05 10:48:10 +0000 | [diff] [blame] | 249 | port.iotype = UPIO_MEM; |
Russell King | 59a675b | 2006-02-05 10:52:29 +0000 | [diff] [blame] | 250 | port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | port.line = 0; |
| 252 | |
| 253 | if (early_serial_setup(&port) != 0) { |
| 254 | printk("Early serial init of port 0 failed\n"); |
| 255 | } |
| 256 | |
| 257 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) |
| 258 | /* Configure debug serial access */ |
| 259 | gen550_init(0, &port); |
Eugene Surovegin | 5ce17b1 | 2005-07-29 22:59:19 -0700 | [diff] [blame] | 260 | |
| 261 | /* Purge TLB entry added in head_44x.S for early serial access */ |
| 262 | _tlbie(UART0_IO_BASE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | #endif |
| 264 | |
| 265 | port.membase = ioremap64(PPC440GX_UART1_ADDR, 8); |
| 266 | port.irq = UART1_INT; |
| 267 | port.uartclk = clocks.uart1; |
| 268 | port.line = 1; |
| 269 | |
| 270 | if (early_serial_setup(&port) != 0) { |
| 271 | printk("Early serial init of port 1 failed\n"); |
| 272 | } |
| 273 | |
| 274 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) |
| 275 | /* Configure debug serial access */ |
| 276 | gen550_init(1, &port); |
| 277 | #endif |
| 278 | } |
| 279 | |
| 280 | static void __init |
| 281 | ocotea_setup_arch(void) |
| 282 | { |
| 283 | ocotea_set_emacdata(); |
| 284 | |
| 285 | ibm440gx_tah_enable(); |
| 286 | |
Matt Porter | d5f7b06 | 2005-10-28 17:46:14 -0700 | [diff] [blame] | 287 | /* |
| 288 | * Determine various clocks. |
| 289 | * To be completely correct we should get SysClk |
| 290 | * from FPGA, because it can be changed by on-board switches |
| 291 | * --ebs |
| 292 | */ |
| 293 | ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); |
| 294 | ocp_sys_info.opb_bus_freq = clocks.opb; |
| 295 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | /* Setup TODC access */ |
| 297 | TODC_INIT(TODC_TYPE_DS1743, |
| 298 | 0, |
| 299 | 0, |
| 300 | ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE), |
| 301 | 8); |
| 302 | |
| 303 | /* init to some ~sane value until calibrate_delay() runs */ |
| 304 | loops_per_jiffy = 50000000/HZ; |
| 305 | |
| 306 | /* Setup PCI host bridge */ |
| 307 | ocotea_setup_hose(); |
| 308 | |
| 309 | #ifdef CONFIG_BLK_DEV_INITRD |
| 310 | if (initrd_start) |
| 311 | ROOT_DEV = Root_RAM0; |
| 312 | else |
| 313 | #endif |
| 314 | #ifdef CONFIG_ROOT_NFS |
| 315 | ROOT_DEV = Root_NFS; |
| 316 | #else |
| 317 | ROOT_DEV = Root_HDA1; |
| 318 | #endif |
| 319 | |
| 320 | ocotea_early_serial_map(); |
| 321 | |
| 322 | /* Identify the system */ |
| 323 | printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n"); |
| 324 | } |
| 325 | |
| 326 | static void __init ocotea_init(void) |
| 327 | { |
| 328 | ibm440gx_l2c_setup(&clocks); |
| 329 | } |
| 330 | |
| 331 | void __init platform_init(unsigned long r3, unsigned long r4, |
| 332 | unsigned long r5, unsigned long r6, unsigned long r7) |
| 333 | { |
Matt Porter | d5f7b06 | 2005-10-28 17:46:14 -0700 | [diff] [blame] | 334 | ibm44x_platform_init(r3, r4, r5, r6, r7); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 335 | |
| 336 | ppc_md.setup_arch = ocotea_setup_arch; |
| 337 | ppc_md.show_cpuinfo = ocotea_show_cpuinfo; |
| 338 | ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ |
| 339 | |
| 340 | ppc_md.calibrate_decr = ocotea_calibrate_decr; |
| 341 | ppc_md.time_init = todc_time_init; |
| 342 | ppc_md.set_rtc_time = todc_set_rtc_time; |
| 343 | ppc_md.get_rtc_time = todc_get_rtc_time; |
| 344 | |
| 345 | ppc_md.nvram_read_val = todc_direct_read_val; |
| 346 | ppc_md.nvram_write_val = todc_direct_write_val; |
| 347 | #ifdef CONFIG_KGDB |
| 348 | ppc_md.early_serial_map = ocotea_early_serial_map; |
| 349 | #endif |
| 350 | ppc_md.init = ocotea_init; |
| 351 | } |