Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/mmc/au1xmmc.c - AU1XX0 MMC driver |
| 3 | * |
| 4 | * Copyright (c) 2005, Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * Developed with help from the 2.4.30 MMC AU1XXX controller including |
| 7 | * the following copyright notices: |
| 8 | * Copyright (c) 2003-2004 Embedded Edge, LLC. |
| 9 | * Portions Copyright (C) 2002 Embedix, Inc |
| 10 | * Copyright 2002 Hewlett-Packard Company |
| 11 | |
| 12 | * 2.6 version of this driver inspired by: |
| 13 | * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, |
| 14 | * All Rights Reserved. |
| 15 | * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, |
| 16 | * All Rights Reserved. |
| 17 | * |
| 18 | |
| 19 | * This program is free software; you can redistribute it and/or modify |
| 20 | * it under the terms of the GNU General Public License version 2 as |
| 21 | * published by the Free Software Foundation. |
| 22 | */ |
| 23 | |
| 24 | /* Why is a timer used to detect insert events? |
| 25 | * |
| 26 | * From the AU1100 MMC application guide: |
| 27 | * If the Au1100-based design is intended to support both MultiMediaCards |
| 28 | * and 1- or 4-data bit SecureDigital cards, then the solution is to |
| 29 | * connect a weak (560KOhm) pull-up resistor to connector pin 1. |
| 30 | * In doing so, a MMC card never enters SPI-mode communications, |
| 31 | * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective |
| 32 | * (the low to high transition will not occur). |
| 33 | * |
| 34 | * So we use the timer to check the status manually. |
| 35 | */ |
| 36 | |
| 37 | #include <linux/config.h> |
| 38 | #include <linux/module.h> |
| 39 | #include <linux/init.h> |
Martin Michlmayr | b256f9d | 2006-03-04 23:01:13 +0000 | [diff] [blame] | 40 | #include <linux/platform_device.h> |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 41 | #include <linux/mm.h> |
| 42 | #include <linux/interrupt.h> |
| 43 | #include <linux/dma-mapping.h> |
| 44 | |
| 45 | #include <linux/mmc/host.h> |
| 46 | #include <linux/mmc/protocol.h> |
| 47 | #include <asm/io.h> |
| 48 | #include <asm/mach-au1x00/au1000.h> |
| 49 | #include <asm/mach-au1x00/au1xxx_dbdma.h> |
| 50 | #include <asm/mach-au1x00/au1100_mmc.h> |
| 51 | #include <asm/scatterlist.h> |
| 52 | |
| 53 | #include <au1xxx.h> |
| 54 | #include "au1xmmc.h" |
| 55 | |
| 56 | #define DRIVER_NAME "au1xxx-mmc" |
| 57 | |
| 58 | /* Set this to enable special debugging macros */ |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 59 | |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 60 | #ifdef DEBUG |
| 61 | #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args) |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 62 | #else |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 63 | #define DBG(fmt, idx, args...) |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 64 | #endif |
| 65 | |
| 66 | const struct { |
| 67 | u32 iobase; |
| 68 | u32 tx_devid, rx_devid; |
| 69 | u16 bcsrpwr; |
| 70 | u16 bcsrstatus; |
| 71 | u16 wpstatus; |
| 72 | } au1xmmc_card_table[] = { |
| 73 | { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0, |
| 74 | BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP }, |
| 75 | #ifndef CONFIG_MIPS_DB1200 |
| 76 | { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1, |
| 77 | BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP } |
| 78 | #endif |
| 79 | }; |
| 80 | |
| 81 | #define AU1XMMC_CONTROLLER_COUNT \ |
| 82 | (sizeof(au1xmmc_card_table) / sizeof(au1xmmc_card_table[0])) |
| 83 | |
| 84 | /* This array stores pointers for the hosts (used by the IRQ handler) */ |
| 85 | struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT]; |
| 86 | static int dma = 1; |
| 87 | |
| 88 | #ifdef MODULE |
Rusty Russell | 8d3b33f | 2006-03-25 03:07:05 -0800 | [diff] [blame] | 89 | module_param(dma, bool, 0); |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 90 | MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)"); |
| 91 | #endif |
| 92 | |
| 93 | static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) |
| 94 | { |
| 95 | u32 val = au_readl(HOST_CONFIG(host)); |
| 96 | val |= mask; |
| 97 | au_writel(val, HOST_CONFIG(host)); |
| 98 | au_sync(); |
| 99 | } |
| 100 | |
| 101 | static inline void FLUSH_FIFO(struct au1xmmc_host *host) |
| 102 | { |
| 103 | u32 val = au_readl(HOST_CONFIG2(host)); |
| 104 | |
| 105 | au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); |
| 106 | au_sync_delay(1); |
| 107 | |
| 108 | /* SEND_STOP will turn off clock control - this re-enables it */ |
| 109 | val &= ~SD_CONFIG2_DF; |
| 110 | |
| 111 | au_writel(val, HOST_CONFIG2(host)); |
| 112 | au_sync(); |
| 113 | } |
| 114 | |
| 115 | static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) |
| 116 | { |
| 117 | u32 val = au_readl(HOST_CONFIG(host)); |
| 118 | val &= ~mask; |
| 119 | au_writel(val, HOST_CONFIG(host)); |
| 120 | au_sync(); |
| 121 | } |
| 122 | |
| 123 | static inline void SEND_STOP(struct au1xmmc_host *host) |
| 124 | { |
| 125 | |
| 126 | /* We know the value of CONFIG2, so avoid a read we don't need */ |
| 127 | u32 mask = SD_CONFIG2_EN; |
| 128 | |
| 129 | WARN_ON(host->status != HOST_S_DATA); |
| 130 | host->status = HOST_S_STOP; |
| 131 | |
| 132 | au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host)); |
| 133 | au_sync(); |
| 134 | |
| 135 | /* Send the stop commmand */ |
| 136 | au_writel(STOP_CMD, HOST_CMD(host)); |
| 137 | } |
| 138 | |
| 139 | static void au1xmmc_set_power(struct au1xmmc_host *host, int state) |
| 140 | { |
| 141 | |
| 142 | u32 val = au1xmmc_card_table[host->id].bcsrpwr; |
| 143 | |
| 144 | bcsr->board &= ~val; |
| 145 | if (state) bcsr->board |= val; |
| 146 | |
| 147 | au_sync_delay(1); |
| 148 | } |
| 149 | |
| 150 | static inline int au1xmmc_card_inserted(struct au1xmmc_host *host) |
| 151 | { |
| 152 | return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus) |
| 153 | ? 1 : 0; |
| 154 | } |
| 155 | |
| 156 | static inline int au1xmmc_card_readonly(struct au1xmmc_host *host) |
| 157 | { |
| 158 | return (bcsr->status & au1xmmc_card_table[host->id].wpstatus) |
| 159 | ? 1 : 0; |
| 160 | } |
| 161 | |
| 162 | static void au1xmmc_finish_request(struct au1xmmc_host *host) |
| 163 | { |
| 164 | |
| 165 | struct mmc_request *mrq = host->mrq; |
| 166 | |
| 167 | host->mrq = NULL; |
| 168 | host->flags &= HOST_F_ACTIVE; |
| 169 | |
| 170 | host->dma.len = 0; |
| 171 | host->dma.dir = 0; |
| 172 | |
| 173 | host->pio.index = 0; |
| 174 | host->pio.offset = 0; |
| 175 | host->pio.len = 0; |
| 176 | |
| 177 | host->status = HOST_S_IDLE; |
| 178 | |
| 179 | bcsr->disk_leds |= (1 << 8); |
| 180 | |
| 181 | mmc_request_done(host->mmc, mrq); |
| 182 | } |
| 183 | |
| 184 | static void au1xmmc_tasklet_finish(unsigned long param) |
| 185 | { |
| 186 | struct au1xmmc_host *host = (struct au1xmmc_host *) param; |
| 187 | au1xmmc_finish_request(host); |
| 188 | } |
| 189 | |
| 190 | static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, |
| 191 | struct mmc_command *cmd) |
| 192 | { |
| 193 | |
| 194 | u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); |
| 195 | |
Martin Michlmayr | e142c24 | 2006-03-04 23:01:39 +0000 | [diff] [blame] | 196 | switch (mmc_resp_type(cmd)) { |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 197 | case MMC_RSP_R1: |
| 198 | mmccmd |= SD_CMD_RT_1; |
| 199 | break; |
| 200 | case MMC_RSP_R1B: |
| 201 | mmccmd |= SD_CMD_RT_1B; |
| 202 | break; |
| 203 | case MMC_RSP_R2: |
| 204 | mmccmd |= SD_CMD_RT_2; |
| 205 | break; |
| 206 | case MMC_RSP_R3: |
| 207 | mmccmd |= SD_CMD_RT_3; |
| 208 | break; |
| 209 | } |
| 210 | |
| 211 | switch(cmd->opcode) { |
| 212 | case MMC_READ_SINGLE_BLOCK: |
| 213 | case SD_APP_SEND_SCR: |
| 214 | mmccmd |= SD_CMD_CT_2; |
| 215 | break; |
| 216 | case MMC_READ_MULTIPLE_BLOCK: |
| 217 | mmccmd |= SD_CMD_CT_4; |
| 218 | break; |
| 219 | case MMC_WRITE_BLOCK: |
| 220 | mmccmd |= SD_CMD_CT_1; |
| 221 | break; |
| 222 | |
| 223 | case MMC_WRITE_MULTIPLE_BLOCK: |
| 224 | mmccmd |= SD_CMD_CT_3; |
| 225 | break; |
| 226 | case MMC_STOP_TRANSMISSION: |
| 227 | mmccmd |= SD_CMD_CT_7; |
| 228 | break; |
| 229 | } |
| 230 | |
| 231 | au_writel(cmd->arg, HOST_CMDARG(host)); |
| 232 | au_sync(); |
| 233 | |
| 234 | if (wait) |
| 235 | IRQ_OFF(host, SD_CONFIG_CR); |
| 236 | |
| 237 | au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); |
| 238 | au_sync(); |
| 239 | |
| 240 | /* Wait for the command to go on the line */ |
| 241 | |
| 242 | while(1) { |
| 243 | if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO)) |
| 244 | break; |
| 245 | } |
| 246 | |
| 247 | /* Wait for the command to come back */ |
| 248 | |
| 249 | if (wait) { |
| 250 | u32 status = au_readl(HOST_STATUS(host)); |
| 251 | |
| 252 | while(!(status & SD_STATUS_CR)) |
| 253 | status = au_readl(HOST_STATUS(host)); |
| 254 | |
| 255 | /* Clear the CR status */ |
| 256 | au_writel(SD_STATUS_CR, HOST_STATUS(host)); |
| 257 | |
| 258 | IRQ_ON(host, SD_CONFIG_CR); |
| 259 | } |
| 260 | |
| 261 | return MMC_ERR_NONE; |
| 262 | } |
| 263 | |
| 264 | static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) |
| 265 | { |
| 266 | |
| 267 | struct mmc_request *mrq = host->mrq; |
| 268 | struct mmc_data *data; |
| 269 | u32 crc; |
| 270 | |
| 271 | WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP); |
| 272 | |
| 273 | if (host->mrq == NULL) |
| 274 | return; |
| 275 | |
| 276 | data = mrq->cmd->data; |
| 277 | |
| 278 | if (status == 0) |
| 279 | status = au_readl(HOST_STATUS(host)); |
| 280 | |
| 281 | /* The transaction is really over when the SD_STATUS_DB bit is clear */ |
| 282 | |
| 283 | while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) |
| 284 | status = au_readl(HOST_STATUS(host)); |
| 285 | |
| 286 | data->error = MMC_ERR_NONE; |
| 287 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); |
| 288 | |
| 289 | /* Process any errors */ |
| 290 | |
| 291 | crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); |
| 292 | if (host->flags & HOST_F_XMIT) |
| 293 | crc |= ((status & 0x07) == 0x02) ? 0 : 1; |
| 294 | |
| 295 | if (crc) |
| 296 | data->error = MMC_ERR_BADCRC; |
| 297 | |
| 298 | /* Clear the CRC bits */ |
| 299 | au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); |
| 300 | |
| 301 | data->bytes_xfered = 0; |
| 302 | |
| 303 | if (data->error == MMC_ERR_NONE) { |
| 304 | if (host->flags & HOST_F_DMA) { |
| 305 | u32 chan = DMA_CHANNEL(host); |
| 306 | |
| 307 | chan_tab_t *c = *((chan_tab_t **) chan); |
| 308 | au1x_dma_chan_t *cp = c->chan_ptr; |
| 309 | data->bytes_xfered = cp->ddma_bytecnt; |
| 310 | } |
| 311 | else |
| 312 | data->bytes_xfered = |
| 313 | (data->blocks * (1 << data->blksz_bits)) - |
| 314 | host->pio.len; |
| 315 | } |
| 316 | |
| 317 | au1xmmc_finish_request(host); |
| 318 | } |
| 319 | |
| 320 | static void au1xmmc_tasklet_data(unsigned long param) |
| 321 | { |
| 322 | struct au1xmmc_host *host = (struct au1xmmc_host *) param; |
| 323 | |
| 324 | u32 status = au_readl(HOST_STATUS(host)); |
| 325 | au1xmmc_data_complete(host, status); |
| 326 | } |
| 327 | |
| 328 | #define AU1XMMC_MAX_TRANSFER 8 |
| 329 | |
| 330 | static void au1xmmc_send_pio(struct au1xmmc_host *host) |
| 331 | { |
| 332 | |
| 333 | struct mmc_data *data = 0; |
| 334 | int sg_len, max, count = 0; |
| 335 | unsigned char *sg_ptr; |
| 336 | u32 status = 0; |
| 337 | struct scatterlist *sg; |
| 338 | |
| 339 | data = host->mrq->data; |
| 340 | |
| 341 | if (!(host->flags & HOST_F_XMIT)) |
| 342 | return; |
| 343 | |
| 344 | /* This is the pointer to the data buffer */ |
| 345 | sg = &data->sg[host->pio.index]; |
| 346 | sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset; |
| 347 | |
| 348 | /* This is the space left inside the buffer */ |
| 349 | sg_len = data->sg[host->pio.index].length - host->pio.offset; |
| 350 | |
| 351 | /* Check to if we need less then the size of the sg_buffer */ |
| 352 | |
| 353 | max = (sg_len > host->pio.len) ? host->pio.len : sg_len; |
| 354 | if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER; |
| 355 | |
| 356 | for(count = 0; count < max; count++ ) { |
| 357 | unsigned char val; |
| 358 | |
| 359 | status = au_readl(HOST_STATUS(host)); |
| 360 | |
| 361 | if (!(status & SD_STATUS_TH)) |
| 362 | break; |
| 363 | |
| 364 | val = *sg_ptr++; |
| 365 | |
| 366 | au_writel((unsigned long) val, HOST_TXPORT(host)); |
| 367 | au_sync(); |
| 368 | } |
| 369 | |
| 370 | host->pio.len -= count; |
| 371 | host->pio.offset += count; |
| 372 | |
| 373 | if (count == sg_len) { |
| 374 | host->pio.index++; |
| 375 | host->pio.offset = 0; |
| 376 | } |
| 377 | |
| 378 | if (host->pio.len == 0) { |
| 379 | IRQ_OFF(host, SD_CONFIG_TH); |
| 380 | |
| 381 | if (host->flags & HOST_F_STOP) |
| 382 | SEND_STOP(host); |
| 383 | |
| 384 | tasklet_schedule(&host->data_task); |
| 385 | } |
| 386 | } |
| 387 | |
| 388 | static void au1xmmc_receive_pio(struct au1xmmc_host *host) |
| 389 | { |
| 390 | |
| 391 | struct mmc_data *data = 0; |
| 392 | int sg_len = 0, max = 0, count = 0; |
| 393 | unsigned char *sg_ptr = 0; |
| 394 | u32 status = 0; |
| 395 | struct scatterlist *sg; |
| 396 | |
| 397 | data = host->mrq->data; |
| 398 | |
| 399 | if (!(host->flags & HOST_F_RECV)) |
| 400 | return; |
| 401 | |
| 402 | max = host->pio.len; |
| 403 | |
| 404 | if (host->pio.index < host->dma.len) { |
| 405 | sg = &data->sg[host->pio.index]; |
| 406 | sg_ptr = page_address(sg->page) + sg->offset + host->pio.offset; |
| 407 | |
| 408 | /* This is the space left inside the buffer */ |
| 409 | sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; |
| 410 | |
| 411 | /* Check to if we need less then the size of the sg_buffer */ |
| 412 | if (sg_len < max) max = sg_len; |
| 413 | } |
| 414 | |
| 415 | if (max > AU1XMMC_MAX_TRANSFER) |
| 416 | max = AU1XMMC_MAX_TRANSFER; |
| 417 | |
| 418 | for(count = 0; count < max; count++ ) { |
| 419 | u32 val; |
| 420 | status = au_readl(HOST_STATUS(host)); |
| 421 | |
| 422 | if (!(status & SD_STATUS_NE)) |
| 423 | break; |
| 424 | |
| 425 | if (status & SD_STATUS_RC) { |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 426 | DBG("RX CRC Error [%d + %d].\n", host->id, |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 427 | host->pio.len, count); |
| 428 | break; |
| 429 | } |
| 430 | |
| 431 | if (status & SD_STATUS_RO) { |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 432 | DBG("RX Overrun [%d + %d]\n", host->id, |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 433 | host->pio.len, count); |
| 434 | break; |
| 435 | } |
| 436 | else if (status & SD_STATUS_RU) { |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 437 | DBG("RX Underrun [%d + %d]\n", host->id, |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 438 | host->pio.len, count); |
| 439 | break; |
| 440 | } |
| 441 | |
| 442 | val = au_readl(HOST_RXPORT(host)); |
| 443 | |
| 444 | if (sg_ptr) |
| 445 | *sg_ptr++ = (unsigned char) (val & 0xFF); |
| 446 | } |
| 447 | |
| 448 | host->pio.len -= count; |
| 449 | host->pio.offset += count; |
| 450 | |
| 451 | if (sg_len && count == sg_len) { |
| 452 | host->pio.index++; |
| 453 | host->pio.offset = 0; |
| 454 | } |
| 455 | |
| 456 | if (host->pio.len == 0) { |
| 457 | //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); |
| 458 | IRQ_OFF(host, SD_CONFIG_NE); |
| 459 | |
| 460 | if (host->flags & HOST_F_STOP) |
| 461 | SEND_STOP(host); |
| 462 | |
| 463 | tasklet_schedule(&host->data_task); |
| 464 | } |
| 465 | } |
| 466 | |
| 467 | /* static void au1xmmc_cmd_complete |
| 468 | This is called when a command has been completed - grab the response |
| 469 | and check for errors. Then start the data transfer if it is indicated. |
| 470 | */ |
| 471 | |
| 472 | static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) |
| 473 | { |
| 474 | |
| 475 | struct mmc_request *mrq = host->mrq; |
| 476 | struct mmc_command *cmd; |
| 477 | int trans; |
| 478 | |
| 479 | if (!host->mrq) |
| 480 | return; |
| 481 | |
| 482 | cmd = mrq->cmd; |
| 483 | cmd->error = MMC_ERR_NONE; |
| 484 | |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 485 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 486 | if (cmd->flags & MMC_RSP_136) { |
| 487 | u32 r[4]; |
| 488 | int i; |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 489 | |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 490 | r[0] = au_readl(host->iobase + SD_RESP3); |
| 491 | r[1] = au_readl(host->iobase + SD_RESP2); |
| 492 | r[2] = au_readl(host->iobase + SD_RESP1); |
| 493 | r[3] = au_readl(host->iobase + SD_RESP0); |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 494 | |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 495 | /* The CRC is omitted from the response, so really |
| 496 | * we only got 120 bytes, but the engine expects |
| 497 | * 128 bits, so we have to shift things up |
| 498 | */ |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 499 | |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 500 | for(i = 0; i < 4; i++) { |
| 501 | cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; |
| 502 | if (i != 3) |
| 503 | cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; |
| 504 | } |
| 505 | } else { |
| 506 | /* Techincally, we should be getting all 48 bits of |
| 507 | * the response (SD_RESP1 + SD_RESP2), but because |
| 508 | * our response omits the CRC, our data ends up |
| 509 | * being shifted 8 bits to the right. In this case, |
| 510 | * that means that the OSR data starts at bit 31, |
| 511 | * so we can just read RESP0 and return that |
| 512 | */ |
| 513 | cmd->resp[0] = au_readl(host->iobase + SD_RESP0); |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 514 | } |
| 515 | } |
| 516 | |
| 517 | /* Figure out errors */ |
| 518 | |
| 519 | if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) |
| 520 | cmd->error = MMC_ERR_BADCRC; |
| 521 | |
| 522 | trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); |
| 523 | |
| 524 | if (!trans || cmd->error != MMC_ERR_NONE) { |
| 525 | |
| 526 | IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF); |
| 527 | tasklet_schedule(&host->finish_task); |
| 528 | return; |
| 529 | } |
| 530 | |
| 531 | host->status = HOST_S_DATA; |
| 532 | |
| 533 | if (host->flags & HOST_F_DMA) { |
| 534 | u32 channel = DMA_CHANNEL(host); |
| 535 | |
| 536 | /* Start the DMA as soon as the buffer gets something in it */ |
| 537 | |
| 538 | if (host->flags & HOST_F_RECV) { |
| 539 | u32 mask = SD_STATUS_DB | SD_STATUS_NE; |
| 540 | |
| 541 | while((status & mask) != mask) |
| 542 | status = au_readl(HOST_STATUS(host)); |
| 543 | } |
| 544 | |
| 545 | au1xxx_dbdma_start(channel); |
| 546 | } |
| 547 | } |
| 548 | |
| 549 | static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) |
| 550 | { |
| 551 | |
| 552 | unsigned int pbus = get_au1x00_speed(); |
| 553 | unsigned int divisor; |
| 554 | u32 config; |
| 555 | |
| 556 | /* From databook: |
| 557 | divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1 |
| 558 | */ |
| 559 | |
| 560 | pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2); |
| 561 | pbus /= 2; |
| 562 | |
| 563 | divisor = ((pbus / rate) / 2) - 1; |
| 564 | |
| 565 | config = au_readl(HOST_CONFIG(host)); |
| 566 | |
| 567 | config &= ~(SD_CONFIG_DIV); |
| 568 | config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; |
| 569 | |
| 570 | au_writel(config, HOST_CONFIG(host)); |
| 571 | au_sync(); |
| 572 | } |
| 573 | |
| 574 | static int |
| 575 | au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data) |
| 576 | { |
| 577 | |
| 578 | int datalen = data->blocks * (1 << data->blksz_bits); |
| 579 | |
| 580 | if (dma != 0) |
| 581 | host->flags |= HOST_F_DMA; |
| 582 | |
| 583 | if (data->flags & MMC_DATA_READ) |
| 584 | host->flags |= HOST_F_RECV; |
| 585 | else |
| 586 | host->flags |= HOST_F_XMIT; |
| 587 | |
| 588 | if (host->mrq->stop) |
| 589 | host->flags |= HOST_F_STOP; |
| 590 | |
| 591 | host->dma.dir = DMA_BIDIRECTIONAL; |
| 592 | |
| 593 | host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, |
| 594 | data->sg_len, host->dma.dir); |
| 595 | |
| 596 | if (host->dma.len == 0) |
| 597 | return MMC_ERR_TIMEOUT; |
| 598 | |
| 599 | au_writel((1 << data->blksz_bits) - 1, HOST_BLKSIZE(host)); |
| 600 | |
| 601 | if (host->flags & HOST_F_DMA) { |
| 602 | int i; |
| 603 | u32 channel = DMA_CHANNEL(host); |
| 604 | |
| 605 | au1xxx_dbdma_stop(channel); |
| 606 | |
| 607 | for(i = 0; i < host->dma.len; i++) { |
| 608 | u32 ret = 0, flags = DDMA_FLAGS_NOIE; |
| 609 | struct scatterlist *sg = &data->sg[i]; |
| 610 | int sg_len = sg->length; |
| 611 | |
| 612 | int len = (datalen > sg_len) ? sg_len : datalen; |
| 613 | |
| 614 | if (i == host->dma.len - 1) |
| 615 | flags = DDMA_FLAGS_IE; |
| 616 | |
| 617 | if (host->flags & HOST_F_XMIT){ |
| 618 | ret = au1xxx_dbdma_put_source_flags(channel, |
| 619 | (void *) (page_address(sg->page) + |
| 620 | sg->offset), |
| 621 | len, flags); |
| 622 | } |
| 623 | else { |
| 624 | ret = au1xxx_dbdma_put_dest_flags(channel, |
| 625 | (void *) (page_address(sg->page) + |
| 626 | sg->offset), |
| 627 | len, flags); |
| 628 | } |
| 629 | |
| 630 | if (!ret) |
| 631 | goto dataerr; |
| 632 | |
| 633 | datalen -= len; |
| 634 | } |
| 635 | } |
| 636 | else { |
| 637 | host->pio.index = 0; |
| 638 | host->pio.offset = 0; |
| 639 | host->pio.len = datalen; |
| 640 | |
| 641 | if (host->flags & HOST_F_XMIT) |
| 642 | IRQ_ON(host, SD_CONFIG_TH); |
| 643 | else |
| 644 | IRQ_ON(host, SD_CONFIG_NE); |
| 645 | //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF); |
| 646 | } |
| 647 | |
| 648 | return MMC_ERR_NONE; |
| 649 | |
| 650 | dataerr: |
| 651 | dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir); |
| 652 | return MMC_ERR_TIMEOUT; |
| 653 | } |
| 654 | |
| 655 | /* static void au1xmmc_request |
| 656 | This actually starts a command or data transaction |
| 657 | */ |
| 658 | |
| 659 | static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) |
| 660 | { |
| 661 | |
| 662 | struct au1xmmc_host *host = mmc_priv(mmc); |
| 663 | int ret = MMC_ERR_NONE; |
| 664 | |
| 665 | WARN_ON(irqs_disabled()); |
| 666 | WARN_ON(host->status != HOST_S_IDLE); |
| 667 | |
| 668 | host->mrq = mrq; |
| 669 | host->status = HOST_S_CMD; |
| 670 | |
| 671 | bcsr->disk_leds &= ~(1 << 8); |
| 672 | |
| 673 | if (mrq->data) { |
| 674 | FLUSH_FIFO(host); |
| 675 | ret = au1xmmc_prepare_data(host, mrq->data); |
| 676 | } |
| 677 | |
| 678 | if (ret == MMC_ERR_NONE) |
| 679 | ret = au1xmmc_send_command(host, 0, mrq->cmd); |
| 680 | |
| 681 | if (ret != MMC_ERR_NONE) { |
| 682 | mrq->cmd->error = ret; |
| 683 | au1xmmc_finish_request(host); |
| 684 | } |
| 685 | } |
| 686 | |
| 687 | static void au1xmmc_reset_controller(struct au1xmmc_host *host) |
| 688 | { |
| 689 | |
| 690 | /* Apply the clock */ |
| 691 | au_writel(SD_ENABLE_CE, HOST_ENABLE(host)); |
| 692 | au_sync_delay(1); |
| 693 | |
| 694 | au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); |
| 695 | au_sync_delay(5); |
| 696 | |
| 697 | au_writel(~0, HOST_STATUS(host)); |
| 698 | au_sync(); |
| 699 | |
| 700 | au_writel(0, HOST_BLKSIZE(host)); |
| 701 | au_writel(0x001fffff, HOST_TIMEOUT(host)); |
| 702 | au_sync(); |
| 703 | |
| 704 | au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); |
| 705 | au_sync(); |
| 706 | |
| 707 | au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); |
| 708 | au_sync_delay(1); |
| 709 | |
| 710 | au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); |
| 711 | au_sync(); |
| 712 | |
| 713 | /* Configure interrupts */ |
| 714 | au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); |
| 715 | au_sync(); |
| 716 | } |
| 717 | |
| 718 | |
| 719 | static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios) |
| 720 | { |
| 721 | struct au1xmmc_host *host = mmc_priv(mmc); |
| 722 | |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 723 | DBG("set_ios (power=%u, clock=%uHz, vdd=%u, mode=%u)\n", |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 724 | host->id, ios->power_mode, ios->clock, ios->vdd, |
| 725 | ios->bus_mode); |
| 726 | |
| 727 | if (ios->power_mode == MMC_POWER_OFF) |
| 728 | au1xmmc_set_power(host, 0); |
| 729 | else if (ios->power_mode == MMC_POWER_ON) { |
| 730 | au1xmmc_set_power(host, 1); |
| 731 | } |
| 732 | |
| 733 | if (ios->clock && ios->clock != host->clock) { |
| 734 | au1xmmc_set_clock(host, ios->clock); |
| 735 | host->clock = ios->clock; |
| 736 | } |
| 737 | } |
| 738 | |
| 739 | static void au1xmmc_dma_callback(int irq, void *dev_id, struct pt_regs *regs) |
| 740 | { |
| 741 | struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id; |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 742 | |
| 743 | /* Avoid spurious interrupts */ |
| 744 | |
| 745 | if (!host->mrq) |
| 746 | return; |
| 747 | |
| 748 | if (host->flags & HOST_F_STOP) |
| 749 | SEND_STOP(host); |
| 750 | |
| 751 | tasklet_schedule(&host->data_task); |
| 752 | } |
| 753 | |
| 754 | #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) |
| 755 | #define STATUS_DATA_IN (SD_STATUS_NE) |
| 756 | #define STATUS_DATA_OUT (SD_STATUS_TH) |
| 757 | |
| 758 | static irqreturn_t au1xmmc_irq(int irq, void *dev_id, struct pt_regs *regs) |
| 759 | { |
| 760 | |
| 761 | u32 status; |
| 762 | int i, ret = 0; |
| 763 | |
| 764 | disable_irq(AU1100_SD_IRQ); |
| 765 | |
| 766 | for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { |
| 767 | struct au1xmmc_host * host = au1xmmc_hosts[i]; |
| 768 | u32 handled = 1; |
| 769 | |
| 770 | status = au_readl(HOST_STATUS(host)); |
| 771 | |
| 772 | if (host->mrq && (status & STATUS_TIMEOUT)) { |
| 773 | if (status & SD_STATUS_RAT) |
| 774 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; |
| 775 | |
| 776 | else if (status & SD_STATUS_DT) |
| 777 | host->mrq->data->error = MMC_ERR_TIMEOUT; |
| 778 | |
| 779 | /* In PIO mode, interrupts might still be enabled */ |
| 780 | IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); |
| 781 | |
| 782 | //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF); |
| 783 | tasklet_schedule(&host->finish_task); |
| 784 | } |
| 785 | #if 0 |
| 786 | else if (status & SD_STATUS_DD) { |
| 787 | |
| 788 | /* Sometimes we get a DD before a NE in PIO mode */ |
| 789 | |
| 790 | if (!(host->flags & HOST_F_DMA) && |
| 791 | (status & SD_STATUS_NE)) |
| 792 | au1xmmc_receive_pio(host); |
| 793 | else { |
| 794 | au1xmmc_data_complete(host, status); |
| 795 | //tasklet_schedule(&host->data_task); |
| 796 | } |
| 797 | } |
| 798 | #endif |
| 799 | else if (status & (SD_STATUS_CR)) { |
| 800 | if (host->status == HOST_S_CMD) |
| 801 | au1xmmc_cmd_complete(host,status); |
| 802 | } |
| 803 | else if (!(host->flags & HOST_F_DMA)) { |
| 804 | if ((host->flags & HOST_F_XMIT) && |
| 805 | (status & STATUS_DATA_OUT)) |
| 806 | au1xmmc_send_pio(host); |
| 807 | else if ((host->flags & HOST_F_RECV) && |
| 808 | (status & STATUS_DATA_IN)) |
| 809 | au1xmmc_receive_pio(host); |
| 810 | } |
| 811 | else if (status & 0x203FBC70) { |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 812 | DBG("Unhandled status %8.8x\n", host->id, status); |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 813 | handled = 0; |
| 814 | } |
| 815 | |
| 816 | au_writel(status, HOST_STATUS(host)); |
| 817 | au_sync(); |
| 818 | |
| 819 | ret |= handled; |
| 820 | } |
| 821 | |
| 822 | enable_irq(AU1100_SD_IRQ); |
| 823 | return ret; |
| 824 | } |
| 825 | |
| 826 | static void au1xmmc_poll_event(unsigned long arg) |
| 827 | { |
| 828 | struct au1xmmc_host *host = (struct au1xmmc_host *) arg; |
| 829 | |
| 830 | int card = au1xmmc_card_inserted(host); |
| 831 | int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0; |
| 832 | |
| 833 | if (card != controller) { |
| 834 | host->flags &= ~HOST_F_ACTIVE; |
| 835 | if (card) host->flags |= HOST_F_ACTIVE; |
| 836 | mmc_detect_change(host->mmc, 0); |
| 837 | } |
| 838 | |
| 839 | if (host->mrq != NULL) { |
| 840 | u32 status = au_readl(HOST_STATUS(host)); |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 841 | DBG("PENDING - %8.8x\n", host->id, status); |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 842 | } |
| 843 | |
| 844 | mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT); |
| 845 | } |
| 846 | |
| 847 | static dbdev_tab_t au1xmmc_mem_dbdev = |
| 848 | { |
| 849 | DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0 |
| 850 | }; |
| 851 | |
| 852 | static void au1xmmc_init_dma(struct au1xmmc_host *host) |
| 853 | { |
| 854 | |
| 855 | u32 rxchan, txchan; |
| 856 | |
| 857 | int txid = au1xmmc_card_table[host->id].tx_devid; |
| 858 | int rxid = au1xmmc_card_table[host->id].rx_devid; |
| 859 | |
| 860 | /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride |
| 861 | of 8 bits. And since devices are shared, we need to create |
| 862 | our own to avoid freaking out other devices |
| 863 | */ |
| 864 | |
| 865 | int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); |
| 866 | |
| 867 | txchan = au1xxx_dbdma_chan_alloc(memid, txid, |
| 868 | au1xmmc_dma_callback, (void *) host); |
| 869 | |
| 870 | rxchan = au1xxx_dbdma_chan_alloc(rxid, memid, |
| 871 | au1xmmc_dma_callback, (void *) host); |
| 872 | |
| 873 | au1xxx_dbdma_set_devwidth(txchan, 8); |
| 874 | au1xxx_dbdma_set_devwidth(rxchan, 8); |
| 875 | |
| 876 | au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT); |
| 877 | au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT); |
| 878 | |
| 879 | host->tx_chan = txchan; |
| 880 | host->rx_chan = rxchan; |
| 881 | } |
| 882 | |
| 883 | struct mmc_host_ops au1xmmc_ops = { |
| 884 | .request = au1xmmc_request, |
| 885 | .set_ios = au1xmmc_set_ios, |
| 886 | }; |
| 887 | |
Martin Michlmayr | b256f9d | 2006-03-04 23:01:13 +0000 | [diff] [blame] | 888 | static int __devinit au1xmmc_probe(struct platform_device *pdev) |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 889 | { |
| 890 | |
| 891 | int i, ret = 0; |
| 892 | |
| 893 | /* THe interrupt is shared among all controllers */ |
| 894 | ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, SA_INTERRUPT, "MMC", 0); |
| 895 | |
| 896 | if (ret) { |
| 897 | printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n", |
| 898 | AU1100_SD_IRQ, ret); |
| 899 | return -ENXIO; |
| 900 | } |
| 901 | |
| 902 | disable_irq(AU1100_SD_IRQ); |
| 903 | |
| 904 | for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { |
Martin Michlmayr | b256f9d | 2006-03-04 23:01:13 +0000 | [diff] [blame] | 905 | struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 906 | struct au1xmmc_host *host = 0; |
| 907 | |
| 908 | if (!mmc) { |
| 909 | printk(DRIVER_NAME "ERROR: no mem for host %d\n", i); |
| 910 | au1xmmc_hosts[i] = 0; |
| 911 | continue; |
| 912 | } |
| 913 | |
| 914 | mmc->ops = &au1xmmc_ops; |
| 915 | |
| 916 | mmc->f_min = 450000; |
| 917 | mmc->f_max = 24000000; |
| 918 | |
| 919 | mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE; |
| 920 | mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT; |
| 921 | |
| 922 | mmc->ocr_avail = AU1XMMC_OCR; |
| 923 | |
| 924 | host = mmc_priv(mmc); |
| 925 | host->mmc = mmc; |
| 926 | |
| 927 | host->id = i; |
| 928 | host->iobase = au1xmmc_card_table[host->id].iobase; |
| 929 | host->clock = 0; |
| 930 | host->power_mode = MMC_POWER_OFF; |
| 931 | |
| 932 | host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0; |
| 933 | host->status = HOST_S_IDLE; |
| 934 | |
| 935 | init_timer(&host->timer); |
| 936 | |
| 937 | host->timer.function = au1xmmc_poll_event; |
| 938 | host->timer.data = (unsigned long) host; |
| 939 | host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT; |
| 940 | |
| 941 | tasklet_init(&host->data_task, au1xmmc_tasklet_data, |
| 942 | (unsigned long) host); |
| 943 | |
| 944 | tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, |
| 945 | (unsigned long) host); |
| 946 | |
| 947 | spin_lock_init(&host->lock); |
| 948 | |
| 949 | if (dma != 0) |
| 950 | au1xmmc_init_dma(host); |
| 951 | |
| 952 | au1xmmc_reset_controller(host); |
| 953 | |
| 954 | mmc_add_host(mmc); |
| 955 | au1xmmc_hosts[i] = host; |
| 956 | |
| 957 | add_timer(&host->timer); |
| 958 | |
| 959 | printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n", |
| 960 | host->id, host->iobase, dma ? "dma" : "pio"); |
| 961 | } |
| 962 | |
| 963 | enable_irq(AU1100_SD_IRQ); |
| 964 | |
| 965 | return 0; |
| 966 | } |
| 967 | |
Martin Michlmayr | b256f9d | 2006-03-04 23:01:13 +0000 | [diff] [blame] | 968 | static int __devexit au1xmmc_remove(struct platform_device *pdev) |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 969 | { |
| 970 | |
| 971 | int i; |
| 972 | |
| 973 | disable_irq(AU1100_SD_IRQ); |
| 974 | |
| 975 | for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) { |
| 976 | struct au1xmmc_host *host = au1xmmc_hosts[i]; |
| 977 | if (!host) continue; |
| 978 | |
| 979 | tasklet_kill(&host->data_task); |
| 980 | tasklet_kill(&host->finish_task); |
| 981 | |
| 982 | del_timer_sync(&host->timer); |
| 983 | au1xmmc_set_power(host, 0); |
| 984 | |
| 985 | mmc_remove_host(host->mmc); |
| 986 | |
| 987 | au1xxx_dbdma_chan_free(host->tx_chan); |
| 988 | au1xxx_dbdma_chan_free(host->rx_chan); |
| 989 | |
| 990 | au_writel(0x0, HOST_ENABLE(host)); |
| 991 | au_sync(); |
| 992 | } |
| 993 | |
| 994 | free_irq(AU1100_SD_IRQ, 0); |
| 995 | return 0; |
| 996 | } |
| 997 | |
Martin Michlmayr | b256f9d | 2006-03-04 23:01:13 +0000 | [diff] [blame] | 998 | static struct platform_driver au1xmmc_driver = { |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 999 | .probe = au1xmmc_probe, |
| 1000 | .remove = au1xmmc_remove, |
| 1001 | .suspend = NULL, |
Martin Michlmayr | b256f9d | 2006-03-04 23:01:13 +0000 | [diff] [blame] | 1002 | .resume = NULL, |
| 1003 | .driver = { |
| 1004 | .name = DRIVER_NAME, |
| 1005 | }, |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 1006 | }; |
| 1007 | |
| 1008 | static int __init au1xmmc_init(void) |
| 1009 | { |
Martin Michlmayr | b256f9d | 2006-03-04 23:01:13 +0000 | [diff] [blame] | 1010 | return platform_driver_register(&au1xmmc_driver); |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 1011 | } |
| 1012 | |
| 1013 | static void __exit au1xmmc_exit(void) |
| 1014 | { |
Martin Michlmayr | b256f9d | 2006-03-04 23:01:13 +0000 | [diff] [blame] | 1015 | platform_driver_unregister(&au1xmmc_driver); |
Pete Popov | ba264b3 | 2005-09-21 06:18:27 +0000 | [diff] [blame] | 1016 | } |
| 1017 | |
| 1018 | module_init(au1xmmc_init); |
| 1019 | module_exit(au1xmmc_exit); |
| 1020 | |
| 1021 | #ifdef MODULE |
| 1022 | MODULE_AUTHOR("Advanced Micro Devices, Inc"); |
| 1023 | MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); |
| 1024 | MODULE_LICENSE("GPL"); |
| 1025 | #endif |
| 1026 | |