blob: 955d3069d7271dd0dfc65a26f9e122b7b7b502af [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * mv643xx.h - MV-643XX Internal registers definition file.
3 *
4 * Copyright 2002 Momentum Computer, Inc.
5 * Author: Matthew Dharm <mdharm@momenco.com>
6 * Copyright 2002 GALILEO TECHNOLOGY, LTD.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifndef __ASM_MV643XX_H
14#define __ASM_MV643XX_H
15
16#ifdef __MIPS__
17#include <asm/addrspace.h>
18#include <asm/marvell.h>
19#endif
20#include <asm/types.h>
21
22/****************************************/
23/* Processor Address Space */
24/****************************************/
25
26/* DDR SDRAM BAR and size registers */
27
28#define MV64340_CS_0_BASE_ADDR 0x008
29#define MV64340_CS_0_SIZE 0x010
30#define MV64340_CS_1_BASE_ADDR 0x208
31#define MV64340_CS_1_SIZE 0x210
32#define MV64340_CS_2_BASE_ADDR 0x018
33#define MV64340_CS_2_SIZE 0x020
34#define MV64340_CS_3_BASE_ADDR 0x218
35#define MV64340_CS_3_SIZE 0x220
36
37/* Devices BAR and size registers */
38
39#define MV64340_DEV_CS0_BASE_ADDR 0x028
40#define MV64340_DEV_CS0_SIZE 0x030
41#define MV64340_DEV_CS1_BASE_ADDR 0x228
42#define MV64340_DEV_CS1_SIZE 0x230
43#define MV64340_DEV_CS2_BASE_ADDR 0x248
44#define MV64340_DEV_CS2_SIZE 0x250
45#define MV64340_DEV_CS3_BASE_ADDR 0x038
46#define MV64340_DEV_CS3_SIZE 0x040
47#define MV64340_BOOTCS_BASE_ADDR 0x238
48#define MV64340_BOOTCS_SIZE 0x240
49
50/* PCI 0 BAR and size registers */
51
52#define MV64340_PCI_0_IO_BASE_ADDR 0x048
53#define MV64340_PCI_0_IO_SIZE 0x050
54#define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058
55#define MV64340_PCI_0_MEMORY0_SIZE 0x060
56#define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080
57#define MV64340_PCI_0_MEMORY1_SIZE 0x088
58#define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258
59#define MV64340_PCI_0_MEMORY2_SIZE 0x260
60#define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280
61#define MV64340_PCI_0_MEMORY3_SIZE 0x288
62
63/* PCI 1 BAR and size registers */
64#define MV64340_PCI_1_IO_BASE_ADDR 0x090
65#define MV64340_PCI_1_IO_SIZE 0x098
66#define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0
67#define MV64340_PCI_1_MEMORY0_SIZE 0x0a8
68#define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0
69#define MV64340_PCI_1_MEMORY1_SIZE 0x0b8
70#define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0
71#define MV64340_PCI_1_MEMORY2_SIZE 0x2a8
72#define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0
73#define MV64340_PCI_1_MEMORY3_SIZE 0x2b8
74
75/* SRAM base address */
76#define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268
77
78/* internal registers space base address */
79#define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068
80
81/* Enables the CS , DEV_CS , PCI 0 and PCI 1
82 windows above */
83#define MV64340_BASE_ADDR_ENABLE 0x278
84
85/****************************************/
86/* PCI remap registers */
87/****************************************/
88 /* PCI 0 */
89#define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0
90#define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
91#define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
92#define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
93#define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
94#define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
95#define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
96#define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
97#define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
98 /* PCI 1 */
99#define MV64340_PCI_1_IO_ADDR_REMAP 0x108
100#define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
101#define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
102#define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
103#define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
104#define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
105#define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
106#define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
107#define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
108
109#define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
110#define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
111#define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
112#define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
113#define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
114#define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
115#define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
116#define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
117
118/****************************************/
119/* CPU Control Registers */
120/****************************************/
121
122#define MV64340_CPU_CONFIG 0x000
123#define MV64340_CPU_MODE 0x120
124#define MV64340_CPU_MASTER_CONTROL 0x160
125#define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150
126#define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158
127#define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168
128
129/****************************************/
130/* SMP RegisterS */
131/****************************************/
132
133#define MV64340_SMP_WHO_AM_I 0x200
134#define MV64340_SMP_CPU0_DOORBELL 0x214
135#define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C
136#define MV64340_SMP_CPU1_DOORBELL 0x224
137#define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C
138#define MV64340_SMP_CPU0_DOORBELL_MASK 0x234
139#define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C
140#define MV64340_SMP_SEMAPHOR0 0x244
141#define MV64340_SMP_SEMAPHOR1 0x24c
142#define MV64340_SMP_SEMAPHOR2 0x254
143#define MV64340_SMP_SEMAPHOR3 0x25c
144#define MV64340_SMP_SEMAPHOR4 0x264
145#define MV64340_SMP_SEMAPHOR5 0x26c
146#define MV64340_SMP_SEMAPHOR6 0x274
147#define MV64340_SMP_SEMAPHOR7 0x27c
148
149/****************************************/
150/* CPU Sync Barrier Register */
151/****************************************/
152
153#define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
154#define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
155#define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
156#define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
157
158/****************************************/
159/* CPU Access Protect */
160/****************************************/
161
162#define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
163#define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188
164#define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
165#define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198
166#define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
167#define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
168#define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
169#define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
170
171
172/****************************************/
173/* CPU Error Report */
174/****************************************/
175
176#define MV64340_CPU_ERROR_ADDR_LOW 0x070
177#define MV64340_CPU_ERROR_ADDR_HIGH 0x078
178#define MV64340_CPU_ERROR_DATA_LOW 0x128
179#define MV64340_CPU_ERROR_DATA_HIGH 0x130
180#define MV64340_CPU_ERROR_PARITY 0x138
181#define MV64340_CPU_ERROR_CAUSE 0x140
182#define MV64340_CPU_ERROR_MASK 0x148
183
184/****************************************/
185/* CPU Interface Debug Registers */
186/****************************************/
187
188#define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360
189#define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368
190#define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370
191#define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378
192#define MV64340_PUNIT_MMASK 0x3e4
193
194/****************************************/
195/* Integrated SRAM Registers */
196/****************************************/
197
198#define MV64340_SRAM_CONFIG 0x380
199#define MV64340_SRAM_TEST_MODE 0X3F4
200#define MV64340_SRAM_ERROR_CAUSE 0x388
201#define MV64340_SRAM_ERROR_ADDR 0x390
202#define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8
203#define MV64340_SRAM_ERROR_DATA_LOW 0x398
204#define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0
205#define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8
206
207/****************************************/
208/* SDRAM Configuration */
209/****************************************/
210
211#define MV64340_SDRAM_CONFIG 0x1400
212#define MV64340_D_UNIT_CONTROL_LOW 0x1404
213#define MV64340_D_UNIT_CONTROL_HIGH 0x1424
214#define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408
215#define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c
216#define MV64340_SDRAM_ADDR_CONTROL 0x1410
217#define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414
218#define MV64340_SDRAM_OPERATION 0x1418
219#define MV64340_SDRAM_MODE 0x141c
220#define MV64340_EXTENDED_DRAM_MODE 0x1420
221#define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
222#define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
223#define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438
224#define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
225#define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4
226
227/****************************************/
228/* SDRAM Error Report */
229/****************************************/
230
231#define MV64340_SDRAM_ERROR_DATA_LOW 0x1444
232#define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440
233#define MV64340_SDRAM_ERROR_ADDR 0x1450
234#define MV64340_SDRAM_RECEIVED_ECC 0x1448
235#define MV64340_SDRAM_CALCULATED_ECC 0x144c
236#define MV64340_SDRAM_ECC_CONTROL 0x1454
237#define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458
238
239/******************************************/
240/* Controlled Delay Line (CDL) Registers */
241/******************************************/
242
243#define MV64340_DFCDL_CONFIG0 0x1480
244#define MV64340_DFCDL_CONFIG1 0x1484
245#define MV64340_DLL_WRITE 0x1488
246#define MV64340_DLL_READ 0x148c
247#define MV64340_SRAM_ADDR 0x1490
248#define MV64340_SRAM_DATA0 0x1494
249#define MV64340_SRAM_DATA1 0x1498
250#define MV64340_SRAM_DATA2 0x149c
251#define MV64340_DFCL_PROBE 0x14a0
252
253/******************************************/
254/* Debug Registers */
255/******************************************/
256
257#define MV64340_DUNIT_DEBUG_LOW 0x1460
258#define MV64340_DUNIT_DEBUG_HIGH 0x1464
259#define MV64340_DUNIT_MMASK 0X1b40
260
261/****************************************/
262/* Device Parameters */
263/****************************************/
264
265#define MV64340_DEVICE_BANK0_PARAMETERS 0x45c
266#define MV64340_DEVICE_BANK1_PARAMETERS 0x460
267#define MV64340_DEVICE_BANK2_PARAMETERS 0x464
268#define MV64340_DEVICE_BANK3_PARAMETERS 0x468
269#define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c
270#define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0
271#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
272#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
273#define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
274
275/****************************************/
276/* Device interrupt registers */
277/****************************************/
278
279#define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0
280#define MV64340_DEVICE_INTERRUPT_MASK 0x4d4
281#define MV64340_DEVICE_ERROR_ADDR 0x4d8
282#define MV64340_DEVICE_ERROR_DATA 0x4dc
283#define MV64340_DEVICE_ERROR_PARITY 0x4e0
284
285/****************************************/
286/* Device debug registers */
287/****************************************/
288
289#define MV64340_DEVICE_DEBUG_LOW 0x4e4
290#define MV64340_DEVICE_DEBUG_HIGH 0x4e8
291#define MV64340_RUNIT_MMASK 0x4f0
292
293/****************************************/
294/* PCI Slave Address Decoding registers */
295/****************************************/
296
297#define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08
298#define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88
299#define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08
300#define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88
301#define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c
302#define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c
303#define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c
304#define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c
305#define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10
306#define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90
307#define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10
308#define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90
309#define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18
310#define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98
311#define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14
312#define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94
313#define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
314#define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
315#define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
316#define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
317#define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
318#define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
319#define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24
320#define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4
321#define MV64340_PCI_0_CPU_BAR_SIZE 0xd28
322#define MV64340_PCI_1_CPU_BAR_SIZE 0xda8
323#define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
324#define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
325#define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
326#define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
327#define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
328#define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
329#define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
330#define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
331#define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
332#define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
333#define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
334#define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
335#define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
336#define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
337#define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
338#define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
339#define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
340#define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
341#define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
342#define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
343#define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
344#define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
345#define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
346#define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
347#define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
348#define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
349#define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
350#define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
351#define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
352#define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
353#define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
354#define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
355#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
356#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
357#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
358#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
359#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
360#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
361#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
362#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
363#define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
364#define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
365#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
366#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
367#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
368#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
369#define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
370#define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
371#define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
372#define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
373#define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c
374#define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc
375#define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
376#define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
377#define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44
378#define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4
379#define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48
380#define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
381
382/***********************************/
383/* PCI Control Register Map */
384/***********************************/
385
386#define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
387#define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
388#define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
389#define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
390#define MV64340_PCI_0_COMMAND 0xc00
391#define MV64340_PCI_1_COMMAND 0xc80
392#define MV64340_PCI_0_MODE 0xd00
393#define MV64340_PCI_1_MODE 0xd80
394#define MV64340_PCI_0_RETRY 0xc04
395#define MV64340_PCI_1_RETRY 0xc84
396#define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
397#define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
398#define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38
399#define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8
400#define MV64340_PCI_0_ARBITER_CONTROL 0x1d00
401#define MV64340_PCI_1_ARBITER_CONTROL 0x1d80
402#define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
403#define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
404#define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
405#define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
406#define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
407#define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
408#define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
409#define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
410#define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
411#define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
412#define MV64340_PCI_0_P2P_CONFIG 0x1d14
413#define MV64340_PCI_1_P2P_CONFIG 0x1d94
414
415#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
416#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
417#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
418#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
419#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
420#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
421#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
422#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
423#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
424#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
425#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
426#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
427#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
428#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
429#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
430#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
431#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
432#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
433
434#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
435#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
436#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
437#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
438#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
439#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
440#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
441#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
442#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
443#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
444#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
445#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
446#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
447#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
448#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
449#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
450#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
451#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
452
453/****************************************/
454/* PCI Configuration Access Registers */
455/****************************************/
456
457#define MV64340_PCI_0_CONFIG_ADDR 0xcf8
458#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
459#define MV64340_PCI_1_CONFIG_ADDR 0xc78
460#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
461#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
462#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
463
464/****************************************/
465/* PCI Error Report Registers */
466/****************************************/
467
468#define MV64340_PCI_0_SERR_MASK 0xc28
469#define MV64340_PCI_1_SERR_MASK 0xca8
470#define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40
471#define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0
472#define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44
473#define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4
474#define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48
475#define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8
476#define MV64340_PCI_0_ERROR_COMMAND 0x1d50
477#define MV64340_PCI_1_ERROR_COMMAND 0x1dd0
478#define MV64340_PCI_0_ERROR_CAUSE 0x1d58
479#define MV64340_PCI_1_ERROR_CAUSE 0x1dd8
480#define MV64340_PCI_0_ERROR_MASK 0x1d5c
481#define MV64340_PCI_1_ERROR_MASK 0x1ddc
482
483/****************************************/
484/* PCI Debug Registers */
485/****************************************/
486
487#define MV64340_PCI_0_MMASK 0X1D24
488#define MV64340_PCI_1_MMASK 0X1DA4
489
490/*********************************************/
491/* PCI Configuration, Function 0, Registers */
492/*********************************************/
493
494#define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000
495#define MV64340_PCI_STATUS_AND_COMMAND 0x004
496#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008
497#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
498
499#define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010
500#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014
501#define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018
502#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
503#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
504#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
505#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
506#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
507#define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034
508#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C
509 /* capability list */
510#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
511#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
512#define MV64340_PCI_VPD_ADDR 0x048
513#define MV64340_PCI_VPD_DATA 0x04c
514#define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050
515#define MV64340_PCI_MSI_MESSAGE_ADDR 0x054
516#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
517#define MV64340_PCI_MSI_MESSAGE_DATA 0x05c
518#define MV64340_PCI_X_COMMAND 0x060
519#define MV64340_PCI_X_STATUS 0x064
520#define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068
521
522/***********************************************/
523/* PCI Configuration, Function 1, Registers */
524/***********************************************/
525
526#define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110
527#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114
528#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118
529#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
530#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
531#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
532
533/***********************************************/
534/* PCI Configuration, Function 2, Registers */
535/***********************************************/
536
537#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
538#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
539#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
540#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
541#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
542#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
543
544/***********************************************/
545/* PCI Configuration, Function 3, Registers */
546/***********************************************/
547
548#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
549#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
550#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
551#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
552#define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220
553#define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224
554
555/***********************************************/
556/* PCI Configuration, Function 4, Registers */
557/***********************************************/
558
559#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
560#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
561#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
562#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
563#define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420
564#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
565
566/****************************************/
567/* Messaging Unit Registers (I20) */
568/****************************************/
569
570#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
571#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
572#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
573#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
574#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
575#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
576#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
577#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
578#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
579#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
580#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
581#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
582#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
583#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
584#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
585#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
586#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
587#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
588#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
589#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
590#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
591#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
592
593#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
594#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
595#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
596#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
597#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
598#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
599#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
600#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
601#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
602#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
603#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
604#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
605#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
606#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
607#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
608#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
609#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
610#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
611#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
612#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
613#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
614#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
615
616#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
617#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
618#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
619#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
620#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
621#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
622#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
623#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
624#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
625#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
626#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
627#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
628#define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
629#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
630#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
631#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
632#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
633#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
634#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
635#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
636#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
637#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
638#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
639#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
640#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
641#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
642#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
643#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
644#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
645#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
646#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
647#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
648#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
649#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
650#define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
651#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
652#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
653#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
654#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
655#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
656#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
657#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
658#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
659#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
660
661/****************************************/
662/* Ethernet Unit Registers */
663/****************************************/
664
665#define MV643XX_ETH_SHARED_REGS 0x2000
666#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
667
668#define MV643XX_ETH_PHY_ADDR_REG 0x2000
669#define MV643XX_ETH_SMI_REG 0x2004
670#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
671#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
672#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
673#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
674#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
675#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
676#define MV643XX_ETH_BAR_0 0x2200
677#define MV643XX_ETH_BAR_1 0x2208
678#define MV643XX_ETH_BAR_2 0x2210
679#define MV643XX_ETH_BAR_3 0x2218
680#define MV643XX_ETH_BAR_4 0x2220
681#define MV643XX_ETH_BAR_5 0x2228
682#define MV643XX_ETH_SIZE_REG_0 0x2204
683#define MV643XX_ETH_SIZE_REG_1 0x220c
684#define MV643XX_ETH_SIZE_REG_2 0x2214
685#define MV643XX_ETH_SIZE_REG_3 0x221c
686#define MV643XX_ETH_SIZE_REG_4 0x2224
687#define MV643XX_ETH_SIZE_REG_5 0x222c
688#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
689#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
690#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
691#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
692#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
693#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
694#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
695#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
696#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
697#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
698#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
699#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
700#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
701#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
702#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
703#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
704#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
705#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
706#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
707#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
708#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
709#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
710#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
711#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
712#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
713#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
714#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
715#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
716#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
717#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
718#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
719#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
720#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
721#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
722#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
723#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
724#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
725#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
726#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
727#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
728#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
729#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
730#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
731#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
732#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
733#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
734#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
735#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
736#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
737#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
738#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
739#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
740#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
741#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
742#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
743#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
744#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
745#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
746#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
747#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
748#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
749#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
750#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
751#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
752#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
753#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
754#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
755#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
756#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
757#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
758#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
759#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
760#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
761#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
762#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
763#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
764#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
765#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
766#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
767#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
768#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
769#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
770#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
771#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
772#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
773#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
774#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
775#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
776#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
777#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
778
779/*******************************************/
780/* CUNIT Registers */
781/*******************************************/
782
783 /* Address Decoding Register Map */
784
785#define MV64340_CUNIT_BASE_ADDR_REG0 0xf200
786#define MV64340_CUNIT_BASE_ADDR_REG1 0xf208
787#define MV64340_CUNIT_BASE_ADDR_REG2 0xf210
788#define MV64340_CUNIT_BASE_ADDR_REG3 0xf218
789#define MV64340_CUNIT_SIZE0 0xf204
790#define MV64340_CUNIT_SIZE1 0xf20c
791#define MV64340_CUNIT_SIZE2 0xf214
792#define MV64340_CUNIT_SIZE3 0xf21c
793#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
794#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
795#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
796#define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254
797#define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258
798#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
799
800 /* Error Report Registers */
801
802#define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310
803#define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314
804#define MV64340_CUNIT_ERROR_ADDR 0xf318
805
806 /* Cunit Control Registers */
807
808#define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300
809#define MV64340_CUNIT_CONFIG_REG 0xb40c
810#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
811
812 /* Cunit Debug Registers */
813
814#define MV64340_CUNIT_DEBUG_LOW 0xf340
815#define MV64340_CUNIT_DEBUG_HIGH 0xf344
816#define MV64340_CUNIT_MMASK 0xf380
817
818 /* MPSCs Clocks Routing Registers */
819
820#define MV64340_MPSC_ROUTING_REG 0xb400
821#define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404
822#define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408
823
824 /* MPSCs Interrupts Registers */
825
826#define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
827#define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3))
828
829#define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
830#define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
831#define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
832#define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
833#define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
834#define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
835#define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
836#define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
837#define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
838#define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
839#define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
840#define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
841#define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
842
843 /* MPSC0 Registers */
844
845
846/***************************************/
847/* SDMA Registers */
848/***************************************/
849
850#define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
851#define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
852#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
853#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
854#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
855
856#define MV64340_SDMA_CAUSE_REG 0xb800
857#define MV64340_SDMA_MASK_REG 0xb880
858
859/* BRG Interrupts */
860
861#define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
862#define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3))
863#define MV64340_BRG_CAUSE_REG 0xb834
864#define MV64340_BRG_MASK_REG 0xb8b4
865
866/****************************************/
867/* DMA Channel Control */
868/****************************************/
869
870#define MV64340_DMA_CHANNEL0_CONTROL 0x840
871#define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880
872#define MV64340_DMA_CHANNEL1_CONTROL 0x844
873#define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884
874#define MV64340_DMA_CHANNEL2_CONTROL 0x848
875#define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888
876#define MV64340_DMA_CHANNEL3_CONTROL 0x84C
877#define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C
878
879
880/****************************************/
881/* IDMA Registers */
882/****************************************/
883
884#define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800
885#define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804
886#define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808
887#define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C
888#define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810
889#define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814
890#define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818
891#define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c
892#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820
893#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824
894#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828
895#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
896#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
897#define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
898#define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
899#define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
900#define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
901#define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
902#define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
903#define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
904
905 /* IDMA Address Decoding Base Address Registers */
906
907#define MV64340_DMA_BASE_ADDR_REG0 0xa00
908#define MV64340_DMA_BASE_ADDR_REG1 0xa08
909#define MV64340_DMA_BASE_ADDR_REG2 0xa10
910#define MV64340_DMA_BASE_ADDR_REG3 0xa18
911#define MV64340_DMA_BASE_ADDR_REG4 0xa20
912#define MV64340_DMA_BASE_ADDR_REG5 0xa28
913#define MV64340_DMA_BASE_ADDR_REG6 0xa30
914#define MV64340_DMA_BASE_ADDR_REG7 0xa38
915
916 /* IDMA Address Decoding Size Address Register */
917
918#define MV64340_DMA_SIZE_REG0 0xa04
919#define MV64340_DMA_SIZE_REG1 0xa0c
920#define MV64340_DMA_SIZE_REG2 0xa14
921#define MV64340_DMA_SIZE_REG3 0xa1c
922#define MV64340_DMA_SIZE_REG4 0xa24
923#define MV64340_DMA_SIZE_REG5 0xa2c
924#define MV64340_DMA_SIZE_REG6 0xa34
925#define MV64340_DMA_SIZE_REG7 0xa3C
926
927 /* IDMA Address Decoding High Address Remap and Access
928 Protection Registers */
929
930#define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60
931#define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64
932#define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68
933#define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
934#define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80
935#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
936#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
937#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
938#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
939#define MV64340_DMA_ARBITER_CONTROL 0x860
940#define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0
941
942 /* IDMA Headers Retarget Registers */
943
944#define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84
945#define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88
946
947 /* IDMA Interrupt Register */
948
949#define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0
950#define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4
951#define MV64340_DMA_ERROR_ADDR 0x8c8
952#define MV64340_DMA_ERROR_SELECT 0x8cc
953
954 /* IDMA Debug Register ( for internal use ) */
955
956#define MV64340_DMA_DEBUG_LOW 0x8e0
957#define MV64340_DMA_DEBUG_HIGH 0x8e4
958#define MV64340_DMA_SPARE 0xA8C
959
960/****************************************/
961/* Timer_Counter */
962/****************************************/
963
964#define MV64340_TIMER_COUNTER0 0x850
965#define MV64340_TIMER_COUNTER1 0x854
966#define MV64340_TIMER_COUNTER2 0x858
967#define MV64340_TIMER_COUNTER3 0x85C
968#define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864
969#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
970#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
971
972/****************************************/
973/* Watchdog registers */
974/****************************************/
975
976#define MV64340_WATCHDOG_CONFIG_REG 0xb410
977#define MV64340_WATCHDOG_VALUE_REG 0xb414
978
979/****************************************/
980/* I2C Registers */
981/****************************************/
982
Mark A. Greerd01c08c2005-09-03 15:55:56 -0700983#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984#define MV64XXX_I2C_OFFSET 0xc000
985#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020
986
987/****************************************/
988/* GPP Interface Registers */
989/****************************************/
990
991#define MV64340_GPP_IO_CONTROL 0xf100
992#define MV64340_GPP_LEVEL_CONTROL 0xf110
993#define MV64340_GPP_VALUE 0xf104
994#define MV64340_GPP_INTERRUPT_CAUSE 0xf108
995#define MV64340_GPP_INTERRUPT_MASK0 0xf10c
996#define MV64340_GPP_INTERRUPT_MASK1 0xf114
997#define MV64340_GPP_VALUE_SET 0xf118
998#define MV64340_GPP_VALUE_CLEAR 0xf11c
999
1000/****************************************/
1001/* Interrupt Controller Registers */
1002/****************************************/
1003
1004/****************************************/
1005/* Interrupts */
1006/****************************************/
1007
1008#define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004
1009#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
1010#define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014
1011#define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c
1012#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024
1013#define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034
1014#define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c
1015#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044
1016#define MV64340_INTERRUPT0_MASK_0_LOW 0x054
1017#define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c
1018#define MV64340_INTERRUPT0_SELECT_CAUSE 0x064
1019#define MV64340_INTERRUPT1_MASK_0_LOW 0x074
1020#define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c
1021#define MV64340_INTERRUPT1_SELECT_CAUSE 0x084
1022
1023/****************************************/
1024/* MPP Interface Registers */
1025/****************************************/
1026
1027#define MV64340_MPP_CONTROL0 0xf000
1028#define MV64340_MPP_CONTROL1 0xf004
1029#define MV64340_MPP_CONTROL2 0xf008
1030#define MV64340_MPP_CONTROL3 0xf00c
1031
1032/****************************************/
1033/* Serial Initialization registers */
1034/****************************************/
1035
1036#define MV64340_SERIAL_INIT_LAST_DATA 0xf324
1037#define MV64340_SERIAL_INIT_CONTROL 0xf328
1038#define MV64340_SERIAL_INIT_STATUS 0xf32c
1039
1040extern void mv64340_irq_init(unsigned int base);
1041
1042/* MPSC Platform Device, Driver Data (Shared register regions) */
1043#define MPSC_SHARED_NAME "mpsc_shared"
1044
1045#define MPSC_ROUTING_BASE_ORDER 0
1046#define MPSC_SDMA_INTR_BASE_ORDER 1
1047
1048#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c
1049#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084
1050
1051struct mpsc_shared_pdata {
1052 u32 mrr_val;
1053 u32 rcrr_val;
1054 u32 tcrr_val;
1055 u32 intr_cause_val;
1056 u32 intr_mask_val;
1057};
1058
1059/* MPSC Platform Device, Driver Data */
1060#define MPSC_CTLR_NAME "mpsc"
1061
1062#define MPSC_BASE_ORDER 0
1063#define MPSC_SDMA_BASE_ORDER 1
1064#define MPSC_BRG_BASE_ORDER 2
1065
1066#define MPSC_REG_BLOCK_SIZE 0x0038
1067#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18
1068#define MPSC_BRG_REG_BLOCK_SIZE 0x0008
1069
1070struct mpsc_pdata {
1071 u8 mirror_regs;
1072 u8 cache_mgmt;
1073 u8 max_idle;
1074 int default_baud;
1075 int default_bits;
1076 int default_parity;
1077 int default_flow;
1078 u32 chr_1_val;
1079 u32 chr_2_val;
1080 u32 chr_10_val;
1081 u32 mpcr_val;
1082 u32 bcr_val;
1083 u8 brg_can_tune;
1084 u8 brg_clk_src;
1085 u32 brg_clk_freq;
1086};
1087
1088/* i2c Platform Device, Driver Data */
1089struct mv64xxx_i2c_pdata {
1090 u32 freq_m;
1091 u32 freq_n;
1092 u32 timeout; /* In milliseconds */
1093 u32 retries;
1094};
1095
1096/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
1097#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
1098#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
1099#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
1100#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
1101#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
1102#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
1103#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
1104#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
1105#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
1106#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
1107#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
1108#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
1109#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
1110#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
1111#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
1112#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
1113#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
1114#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
1115#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
1116#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
1117#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
1118#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
1119#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
1120#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
1121#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
1122#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
1123#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
1124#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
1125#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
1126#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
1127#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
1128#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
1129#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
1130#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
1131#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
1132#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
1133#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
1134#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
1135#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
1136#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
1137#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
1138#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 ((1<<21)
1139#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
1140#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
1141#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
1142#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
1143#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
1144#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
1145#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
1146#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
1147#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
1148#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
1149#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
1150
1151#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
1152 MV643XX_ETH_UNICAST_NORMAL_MODE | \
1153 MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
1154 MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
1155 MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
1156 MV643XX_ETH_RECEIVE_BC_IF_IP | \
1157 MV643XX_ETH_RECEIVE_BC_IF_ARP | \
1158 MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
1159 MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
1160 MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
1161 MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
1162 MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
1163
1164/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
1165#define MV643XX_ETH_CLASSIFY_EN (1<<0)
1166#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
1167#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
1168#define MV643XX_ETH_PARTITION_DISABLE 0
1169#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
1170
1171#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
1172 MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
1173 MV643XX_ETH_PARTITION_DISABLE
1174
1175/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
1176#define MV643XX_ETH_RIFB (1<<0)
1177#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
1178#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
1179#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
1180#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
1181#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
1182#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
1183#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
1184#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
1185#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
1186#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
1187#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
1188#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
1189#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
1190#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
1191#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
1192#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
1193
1194#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
1195
1196#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
1197 MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
1198 MV643XX_ETH_IPG_INT_RX(0) | \
1199 MV643XX_ETH_TX_BURST_SIZE_4_64BIT
1200
1201/* These macros describe Ethernet Port serial control reg (PSCR) bits */
1202#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
1203#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
1204#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
1205#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
1206#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
1207#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
1208#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
1209#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
1210#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
1211#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
1212#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
1213#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
1214#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
1215#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
1216#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
James Chapmand0412d92006-01-27 01:15:30 -07001217#define MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED (1<<9)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218#define MV643XX_ETH_FORCE_LINK_FAIL 0
1219#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
1220#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
1221#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
1222#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
1223#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
1224#define MV643XX_ETH_DTE_ADV_0 0
1225#define MV643XX_ETH_DTE_ADV_1 (1<<14)
1226#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
1227#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
1228#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
1229#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
1230#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
1231#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
1232#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
1233#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
1234#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
1235#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
1236#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
1237#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
1238#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
1239#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
1240#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
1241#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
1242#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
1243#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
1244#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
1245#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
1246
James Chapmand0412d92006-01-27 01:15:30 -07001247#define MV643XX_ETH_MAX_RX_PACKET_MASK (0x7<<17)
1248
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
1250 MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
1251 MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
1252 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
1253 MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
1254 MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
1255 MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
1256 (1<<9) /* reserved */ | \
1257 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
1258 MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
1259 MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
1260 MV643XX_ETH_DTE_ADV_0 | \
1261 MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
1262 MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
1263 MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
1264 MV643XX_ETH_CLR_EXT_LOOPBACK | \
1265 MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
1266 MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
1267
1268/* These macros describe Ethernet Serial Status reg (PSR) bits */
1269#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
1270#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
1271#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
1272#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
1273#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
1274#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
1275/* PSR bit 6 is undocumented */
1276#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
1277#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
1278#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
1279#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
1280/* PSR bits 11-31 are reserved */
1281
1282#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
1283#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
1284
1285#define MV643XX_ETH_DESC_SIZE 64
1286
1287#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
1288#define MV643XX_ETH_NAME "mv643xx_eth"
1289
1290struct mv643xx_eth_platform_data {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001291 char *mac_addr; /* pointer to mac address */
Dale Farnsworth01999872006-01-27 01:18:01 -07001292 u16 force_phy_addr; /* force override if phy_addr == 0 */
1293 u16 phy_addr;
1294
1295 /* If speed is 0, then speed and duplex are autonegotiated. */
1296 int speed; /* 0, SPEED_10, SPEED_100, SPEED_1000 */
1297 int duplex; /* DUPLEX_HALF or DUPLEX_FULL */
1298
1299 /* non-zero values of the following fields override defaults */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 u32 tx_queue_size;
1301 u32 rx_queue_size;
1302 u32 tx_sram_addr;
1303 u32 tx_sram_size;
1304 u32 rx_sram_addr;
1305 u32 rx_sram_size;
1306};
1307
1308#endif /* __ASM_MV643XX_H */