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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2003-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * Copyright 2003 Benjamin Herrenschmidt
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 *
Jeff Garzik953d1132005-08-26 19:46:24 -040030 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
46#include <linux/libata.h>
47
48#define DRV_NAME "sata_sil"
Jeff Garzikcb48cab2007-02-26 06:04:24 -050049#define DRV_VERSION "2.1"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090052 SIL_MMIO_BAR = 5,
53
Tejun Heoe653a1e2006-03-05 16:03:52 +090054 /*
55 * host flags
56 */
Tejun Heo201ce852006-06-26 21:23:52 +090057 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
Tejun Heoe4e10e32006-02-25 13:52:30 +090058 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
Tejun Heoe4deec62005-08-23 07:27:25 +090059 SIL_FLAG_MOD15WRITE = (1 << 30),
Tejun Heo20888d82006-05-31 18:27:53 +090060
Jeff Garzikcca39742006-08-24 03:19:22 -040061 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heoe5738902006-05-31 18:28:16 +090062 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
Tejun Heoe4deec62005-08-23 07:27:25 +090063
Tejun Heoe653a1e2006-03-05 16:03:52 +090064 /*
65 * Controller IDs
66 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 sil_3112 = 0,
Tejun Heo201ce852006-06-26 21:23:52 +090068 sil_3112_no_sata_irq = 1,
69 sil_3512 = 2,
70 sil_3114 = 3,
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Tejun Heoe653a1e2006-03-05 16:03:52 +090072 /*
73 * Register offsets
74 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 SIL_SYSCFG = 0x48,
Tejun Heoe653a1e2006-03-05 16:03:52 +090076
77 /*
78 * Register bits
79 */
80 /* SYSCFG */
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 SIL_MASK_IDE0_INT = (1 << 22),
82 SIL_MASK_IDE1_INT = (1 << 23),
83 SIL_MASK_IDE2_INT = (1 << 24),
84 SIL_MASK_IDE3_INT = (1 << 25),
85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 SIL_MASK_4PORT = SIL_MASK_2PORT |
87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88
Tejun Heoe653a1e2006-03-05 16:03:52 +090089 /* BMDMA/BMDMA2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 SIL_INTR_STEERING = (1 << 1),
Tejun Heoe653a1e2006-03-05 16:03:52 +090091
Tejun Heo20888d82006-05-31 18:27:53 +090092 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
102
103 /* SIEN */
104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
105
Tejun Heoe653a1e2006-03-05 16:03:52 +0900106 /*
107 * Others
108 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 SIL_QUIRK_MOD15WRITE = (1 << 0),
110 SIL_QUIRK_UDMA5MAX = (1 << 1),
111};
112
113static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700114#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900115static int sil_pci_device_resume(struct pci_dev *pdev);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700116#endif
Alancd0d3bb2007-03-02 00:56:15 +0000117static void sil_dev_config(struct ata_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
119static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120static void sil_post_set_mode (struct ata_port *ap);
David Howells7d12e782006-10-05 14:55:46 +0100121static irqreturn_t sil_interrupt(int irq, void *dev_instance);
Tejun Heof6aae272006-05-15 20:58:27 +0900122static void sil_freeze(struct ata_port *ap);
123static void sil_thaw(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124
Jeff Garzik374b1872005-08-30 05:42:52 -0400125
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500126static const struct pci_device_id sil_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400127 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
129 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
130 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
131 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
132 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
133 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
134
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 { } /* terminate list */
136};
137
138
139/* TODO firmware versions should be added - eric */
140static const struct sil_drivelist {
141 const char * product;
142 unsigned int quirk;
143} sil_blacklist [] = {
144 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
145 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
146 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
147 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
149 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
154 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
155 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
156 { }
157};
158
159static struct pci_driver sil_pci_driver = {
160 .name = DRV_NAME,
161 .id_table = sil_pci_tbl,
162 .probe = sil_init_one,
163 .remove = ata_pci_remove_one,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700164#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900165 .suspend = ata_pci_device_suspend,
166 .resume = sil_pci_device_resume,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700167#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168};
169
Jeff Garzik193515d2005-11-07 00:59:37 -0500170static struct scsi_host_template sil_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 .module = THIS_MODULE,
172 .name = DRV_NAME,
173 .ioctl = ata_scsi_ioctl,
174 .queuecommand = ata_scsi_queuecmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 .can_queue = ATA_DEF_QUEUE,
176 .this_id = ATA_SHT_THIS_ID,
177 .sg_tablesize = LIBATA_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
179 .emulated = ATA_SHT_EMULATED,
180 .use_clustering = ATA_SHT_USE_CLUSTERING,
181 .proc_name = DRV_NAME,
182 .dma_boundary = ATA_DMA_BOUNDARY,
183 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900184 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 .bios_param = ata_std_bios_param,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900186#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900187 .suspend = ata_scsi_device_suspend,
188 .resume = ata_scsi_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900189#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190};
191
Jeff Garzik057ace52005-10-22 14:27:05 -0400192static const struct ata_port_operations sil_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 .port_disable = ata_port_disable,
194 .dev_config = sil_dev_config,
195 .tf_load = ata_tf_load,
196 .tf_read = ata_tf_read,
197 .check_status = ata_check_status,
198 .exec_command = ata_exec_command,
199 .dev_select = ata_std_dev_select,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 .post_set_mode = sil_post_set_mode,
201 .bmdma_setup = ata_bmdma_setup,
202 .bmdma_start = ata_bmdma_start,
203 .bmdma_stop = ata_bmdma_stop,
204 .bmdma_status = ata_bmdma_status,
205 .qc_prep = ata_qc_prep,
206 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900207 .data_xfer = ata_data_xfer,
Tejun Heof6aae272006-05-15 20:58:27 +0900208 .freeze = sil_freeze,
209 .thaw = sil_thaw,
210 .error_handler = ata_bmdma_error_handler,
211 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heocbe88fb2006-05-31 18:27:55 +0900212 .irq_handler = sil_interrupt,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900214 .irq_on = ata_irq_on,
215 .irq_ack = ata_irq_ack,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 .scr_read = sil_scr_read,
217 .scr_write = sil_scr_write,
218 .port_start = ata_port_start,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219};
220
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100221static const struct ata_port_info sil_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 /* sil_3112 */
223 {
224 .sht = &sil_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400225 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
Tejun Heoe4deec62005-08-23 07:27:25 +0900226 .pio_mask = 0x1f, /* pio0-4 */
227 .mwdma_mask = 0x07, /* mwdma0-2 */
228 .udma_mask = 0x3f, /* udma0-5 */
229 .port_ops = &sil_ops,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900230 },
Tejun Heo201ce852006-06-26 21:23:52 +0900231 /* sil_3112_no_sata_irq */
232 {
233 .sht = &sil_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400234 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
Tejun Heo201ce852006-06-26 21:23:52 +0900235 SIL_FLAG_NO_SATA_IRQ,
236 .pio_mask = 0x1f, /* pio0-4 */
237 .mwdma_mask = 0x07, /* mwdma0-2 */
238 .udma_mask = 0x3f, /* udma0-5 */
239 .port_ops = &sil_ops,
240 },
Tejun Heo0ee304d2006-02-25 13:52:30 +0900241 /* sil_3512 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 {
243 .sht = &sil_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400244 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Tejun Heo0ee304d2006-02-25 13:52:30 +0900245 .pio_mask = 0x1f, /* pio0-4 */
246 .mwdma_mask = 0x07, /* mwdma0-2 */
247 .udma_mask = 0x3f, /* udma0-5 */
248 .port_ops = &sil_ops,
249 },
250 /* sil_3114 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 {
252 .sht = &sil_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400253 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 .pio_mask = 0x1f, /* pio0-4 */
255 .mwdma_mask = 0x07, /* mwdma0-2 */
256 .udma_mask = 0x3f, /* udma0-5 */
257 .port_ops = &sil_ops,
258 },
259};
260
261/* per-port register offsets */
262/* TODO: we can probably calculate rather than use a table */
263static const struct {
264 unsigned long tf; /* ATA taskfile register block */
265 unsigned long ctl; /* ATA control/altstatus register block */
266 unsigned long bmdma; /* DMA register block */
Tejun Heo20888d82006-05-31 18:27:53 +0900267 unsigned long bmdma2; /* DMA register block #2 */
Tejun Heo48d4ef22006-03-05 16:03:52 +0900268 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 unsigned long scr; /* SATA control register block */
270 unsigned long sien; /* SATA Interrupt Enable register */
271 unsigned long xfer_mode;/* data transfer mode register */
Tejun Heoe4e10e32006-02-25 13:52:30 +0900272 unsigned long sfis_cfg; /* SATA FIS reception config register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273} sil_port[] = {
274 /* port 0 ... */
Tejun Heo20888d82006-05-31 18:27:53 +0900275 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
276 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
277 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
278 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279 /* ... port 3 */
280};
281
282MODULE_AUTHOR("Jeff Garzik");
283MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
284MODULE_LICENSE("GPL");
285MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
286MODULE_VERSION(DRV_VERSION);
287
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500288static int slow_down = 0;
289module_param(slow_down, int, 0444);
290MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
291
Jeff Garzik374b1872005-08-30 05:42:52 -0400292
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
294{
295 u8 cache_line = 0;
296 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
297 return cache_line;
298}
299
300static void sil_post_set_mode (struct ata_port *ap)
301{
Jeff Garzikcca39742006-08-24 03:19:22 -0400302 struct ata_host *host = ap->host;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 struct ata_device *dev;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900304 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
305 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 u32 tmp, dev_mode[2];
307 unsigned int i;
308
309 for (i = 0; i < 2; i++) {
310 dev = &ap->device[i];
Tejun Heoe1211e32006-04-01 01:38:18 +0900311 if (!ata_dev_enabled(dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 dev_mode[i] = 0; /* PIO0/1/2 */
313 else if (dev->flags & ATA_DFLAG_PIO)
314 dev_mode[i] = 1; /* PIO3/4 */
315 else
316 dev_mode[i] = 3; /* UDMA */
317 /* value 2 indicates MDMA */
318 }
319
320 tmp = readl(addr);
321 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
322 tmp |= dev_mode[0];
323 tmp |= (dev_mode[1] << 4);
324 writel(tmp, addr);
325 readl(addr); /* flush */
326}
327
Tejun Heo0d5ff562007-02-01 15:06:36 +0900328static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900330 void __iomem *offset = ap->ioaddr.scr_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331
332 switch (sc_reg) {
333 case SCR_STATUS:
334 return offset + 4;
335 case SCR_ERROR:
336 return offset + 8;
337 case SCR_CONTROL:
338 return offset;
339 default:
340 /* do nothing */
341 break;
342 }
343
Randy Dunlap8d9db2d2007-02-16 01:40:06 -0800344 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345}
346
347static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
348{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900349 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350 if (mmio)
351 return readl(mmio);
352 return 0xffffffffU;
353}
354
355static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
356{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900357 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 if (mmio)
359 writel(val, mmio);
360}
361
Tejun Heocbe88fb2006-05-31 18:27:55 +0900362static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
363{
Tejun Heoea547632006-11-17 12:06:21 +0900364 struct ata_eh_info *ehi = &ap->eh_info;
Tejun Heocbe88fb2006-05-31 18:27:55 +0900365 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
366 u8 status;
367
Tejun Heoe5738902006-05-31 18:28:16 +0900368 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
Tejun Heod4c85322006-06-12 18:45:55 +0900369 u32 serror;
370
371 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
372 * controllers continue to assert IRQ as long as
373 * SError bits are pending. Clear SError immediately.
374 */
375 serror = sil_scr_read(ap, SCR_ERROR);
376 sil_scr_write(ap, SCR_ERROR, serror);
377
378 /* Trigger hotplug and accumulate SError only if the
379 * port isn't already frozen. Otherwise, PHY events
380 * during hardreset makes controllers with broken SIEN
381 * repeat probing needlessly.
382 */
Tejun Heob51e9e52006-06-29 01:29:30 +0900383 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heod4c85322006-06-12 18:45:55 +0900384 ata_ehi_hotplugged(&ap->eh_info);
385 ap->eh_info.serror |= serror;
386 }
387
Tejun Heoe5738902006-05-31 18:28:16 +0900388 goto freeze;
389 }
390
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900391 if (unlikely(!qc))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900392 goto freeze;
393
Tejun Heoe2f8fb72007-02-24 22:30:36 +0900394 if (unlikely(qc->tf.flags & ATA_TFLAG_POLLING)) {
395 /* this sometimes happens, just clear IRQ */
396 ata_chk_status(ap);
397 return;
398 }
399
Tejun Heocbe88fb2006-05-31 18:27:55 +0900400 /* Check whether we are expecting interrupt in this state */
401 switch (ap->hsm_task_state) {
402 case HSM_ST_FIRST:
403 /* Some pre-ATAPI-4 devices assert INTRQ
404 * at this state when ready to receive CDB.
405 */
406
407 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
408 * The flag was turned on only for atapi devices.
409 * No need to check is_atapi_taskfile(&qc->tf) again.
410 */
411 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
412 goto err_hsm;
413 break;
414 case HSM_ST_LAST:
415 if (qc->tf.protocol == ATA_PROT_DMA ||
416 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
417 /* clear DMA-Start bit */
418 ap->ops->bmdma_stop(qc);
419
420 if (bmdma2 & SIL_DMA_ERROR) {
421 qc->err_mask |= AC_ERR_HOST_BUS;
422 ap->hsm_task_state = HSM_ST_ERR;
423 }
424 }
425 break;
426 case HSM_ST:
427 break;
428 default:
429 goto err_hsm;
430 }
431
432 /* check main status, clearing INTRQ */
433 status = ata_chk_status(ap);
434 if (unlikely(status & ATA_BUSY))
435 goto err_hsm;
436
437 /* ack bmdma irq events */
438 ata_bmdma_irq_clear(ap);
439
440 /* kick HSM in the ass */
441 ata_hsm_move(ap, qc, status, 0);
442
Tejun Heoea547632006-11-17 12:06:21 +0900443 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
444 qc->tf.protocol == ATA_PROT_ATAPI_DMA))
445 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
446
Tejun Heocbe88fb2006-05-31 18:27:55 +0900447 return;
448
449 err_hsm:
450 qc->err_mask |= AC_ERR_HSM;
451 freeze:
452 ata_port_freeze(ap);
453}
454
David Howells7d12e782006-10-05 14:55:46 +0100455static irqreturn_t sil_interrupt(int irq, void *dev_instance)
Tejun Heocbe88fb2006-05-31 18:27:55 +0900456{
Jeff Garzikcca39742006-08-24 03:19:22 -0400457 struct ata_host *host = dev_instance;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900458 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900459 int handled = 0;
460 int i;
461
Jeff Garzikcca39742006-08-24 03:19:22 -0400462 spin_lock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900463
Jeff Garzikcca39742006-08-24 03:19:22 -0400464 for (i = 0; i < host->n_ports; i++) {
465 struct ata_port *ap = host->ports[i];
Tejun Heocbe88fb2006-05-31 18:27:55 +0900466 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
467
468 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
469 continue;
470
Tejun Heo201ce852006-06-26 21:23:52 +0900471 /* turn off SATA_IRQ if not supported */
472 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
473 bmdma2 &= ~SIL_DMA_SATA_IRQ;
474
Tejun Heo23fa9612006-06-12 14:18:51 +0900475 if (bmdma2 == 0xffffffff ||
476 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
Tejun Heocbe88fb2006-05-31 18:27:55 +0900477 continue;
478
479 sil_host_intr(ap, bmdma2);
480 handled = 1;
481 }
482
Jeff Garzikcca39742006-08-24 03:19:22 -0400483 spin_unlock(&host->lock);
Tejun Heocbe88fb2006-05-31 18:27:55 +0900484
485 return IRQ_RETVAL(handled);
486}
487
Tejun Heof6aae272006-05-15 20:58:27 +0900488static void sil_freeze(struct ata_port *ap)
489{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900490 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900491 u32 tmp;
492
Tejun Heoe5738902006-05-31 18:28:16 +0900493 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
494 writel(0, mmio_base + sil_port[ap->port_no].sien);
495
Tejun Heof6aae272006-05-15 20:58:27 +0900496 /* plug IRQ */
497 tmp = readl(mmio_base + SIL_SYSCFG);
498 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
499 writel(tmp, mmio_base + SIL_SYSCFG);
500 readl(mmio_base + SIL_SYSCFG); /* flush */
501}
502
503static void sil_thaw(struct ata_port *ap)
504{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900505 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
Tejun Heof6aae272006-05-15 20:58:27 +0900506 u32 tmp;
507
508 /* clear IRQ */
509 ata_chk_status(ap);
510 ata_bmdma_irq_clear(ap);
511
Tejun Heo201ce852006-06-26 21:23:52 +0900512 /* turn on SATA IRQ if supported */
513 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
514 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
Tejun Heoe5738902006-05-31 18:28:16 +0900515
Tejun Heof6aae272006-05-15 20:58:27 +0900516 /* turn on IRQ */
517 tmp = readl(mmio_base + SIL_SYSCFG);
518 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
519 writel(tmp, mmio_base + SIL_SYSCFG);
520}
521
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522/**
523 * sil_dev_config - Apply device/host-specific errata fixups
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 * @dev: Device to be examined
525 *
526 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
527 * device is known to be present, this function is called.
528 * We apply two errata fixups which are specific to Silicon Image,
529 * a Seagate and a Maxtor fixup.
530 *
531 * For certain Seagate devices, we must limit the maximum sectors
532 * to under 8K.
533 *
534 * For certain Maxtor devices, we must not program the drive
535 * beyond udma5.
536 *
537 * Both fixups are unfairly pessimistic. As soon as I get more
538 * information on these errata, I will create a more exhaustive
539 * list, and apply the fixups to only the specific
540 * devices/hosts/firmwares that need it.
541 *
542 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
543 * The Maxtor quirk is in the blacklist, but I'm keeping the original
544 * pessimistic fix for the following reasons...
545 * - There seems to be less info on it, only one device gleaned off the
546 * Windows driver, maybe only one is affected. More info would be greatly
547 * appreciated.
548 * - But then again UDMA5 is hardly anything to complain about
549 */
Alancd0d3bb2007-03-02 00:56:15 +0000550static void sil_dev_config(struct ata_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551{
Alancd0d3bb2007-03-02 00:56:15 +0000552 struct ata_port *ap = dev->ap;
Tejun Heoefdaedc2006-11-01 18:38:52 +0900553 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554 unsigned int n, quirks = 0;
Tejun Heoa0cf7332007-01-02 20:18:49 +0900555 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556
Tejun Heoa0cf7332007-01-02 20:18:49 +0900557 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558
Jeff Garzik8a60a072005-07-31 13:13:24 -0400559 for (n = 0; sil_blacklist[n].product; n++)
Tejun Heo2e026712006-02-12 22:47:04 +0900560 if (!strcmp(sil_blacklist[n].product, model_num)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561 quirks = sil_blacklist[n].quirk;
562 break;
563 }
Jeff Garzik8a60a072005-07-31 13:13:24 -0400564
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 /* limit requests to 15 sectors */
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500566 if (slow_down ||
567 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
568 (quirks & SIL_QUIRK_MOD15WRITE))) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900569 if (print_info)
570 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
571 "errata fix (mod15write workaround)\n");
Tejun Heob00eec12006-02-12 23:32:59 +0900572 dev->max_sectors = 15;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573 return;
574 }
575
576 /* limit to udma5 */
577 if (quirks & SIL_QUIRK_UDMA5MAX) {
Tejun Heoefdaedc2006-11-01 18:38:52 +0900578 if (print_info)
579 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
580 "errata fix %s\n", model_num);
Tejun Heo5a529132006-03-24 14:07:50 +0900581 dev->udma_mask &= ATA_UDMA5;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582 return;
583 }
584}
585
Tejun Heo3d8ec912006-07-03 16:07:27 +0900586static void sil_init_controller(struct pci_dev *pdev,
Jeff Garzikcca39742006-08-24 03:19:22 -0400587 int n_ports, unsigned long port_flags,
Tejun Heo3d8ec912006-07-03 16:07:27 +0900588 void __iomem *mmio_base)
589{
590 u8 cls;
591 u32 tmp;
592 int i;
593
594 /* Initialize FIFO PCI bus arbitration */
595 cls = sil_get_device_cache_line(pdev);
596 if (cls) {
597 cls >>= 3;
598 cls++; /* cls = (line_size/8)+1 */
599 for (i = 0; i < n_ports; i++)
600 writew(cls << 8 | cls,
601 mmio_base + sil_port[i].fifo_cfg);
602 } else
603 dev_printk(KERN_WARNING, &pdev->dev,
604 "cache line size not set. Driver may not function\n");
605
606 /* Apply R_ERR on DMA activate FIS errata workaround */
Jeff Garzikcca39742006-08-24 03:19:22 -0400607 if (port_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
Tejun Heo3d8ec912006-07-03 16:07:27 +0900608 int cnt;
609
610 for (i = 0, cnt = 0; i < n_ports; i++) {
611 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
612 if ((tmp & 0x3) != 0x01)
613 continue;
614 if (!cnt)
615 dev_printk(KERN_INFO, &pdev->dev,
616 "Applying R_ERR on DMA activate "
617 "FIS errata fix\n");
618 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
619 cnt++;
620 }
621 }
622
623 if (n_ports == 4) {
624 /* flip the magic "make 4 ports work" bit */
625 tmp = readl(mmio_base + sil_port[2].bmdma);
626 if ((tmp & SIL_INTR_STEERING) == 0)
627 writel(tmp | SIL_INTR_STEERING,
628 mmio_base + sil_port[2].bmdma);
629 }
630}
631
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
633{
634 static int printed_version;
Tejun Heo24dc5f32007-01-20 16:00:28 +0900635 struct device *dev = &pdev->dev;
636 struct ata_probe_ent *probe_ent;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400637 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 int rc;
639 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640
641 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500642 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643
Tejun Heo24dc5f32007-01-20 16:00:28 +0900644 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 if (rc)
646 return rc;
647
Tejun Heo0d5ff562007-02-01 15:06:36 +0900648 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
649 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900650 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900651 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900652 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653
654 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
655 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900656 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
658 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900659 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660
Tejun Heo24dc5f32007-01-20 16:00:28 +0900661 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
662 if (probe_ent == NULL)
663 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 INIT_LIST_HEAD(&probe_ent->node);
666 probe_ent->dev = pci_dev_to_dev(pdev);
667 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
668 probe_ent->sht = sil_port_info[ent->driver_data].sht;
669 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
670 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
671 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
672 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
673 probe_ent->irq = pdev->irq;
Thomas Gleixner1d6f3592006-07-01 19:29:42 -0700674 probe_ent->irq_flags = IRQF_SHARED;
Jeff Garzikcca39742006-08-24 03:19:22 -0400675 probe_ent->port_flags = sil_port_info[ent->driver_data].flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676
Tejun Heo0d5ff562007-02-01 15:06:36 +0900677 probe_ent->iomap = pcim_iomap_table(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678
Tejun Heo0d5ff562007-02-01 15:06:36 +0900679 mmio_base = probe_ent->iomap[SIL_MMIO_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680
681 for (i = 0; i < probe_ent->n_ports; i++) {
Tejun Heo0d5ff562007-02-01 15:06:36 +0900682 probe_ent->port[i].cmd_addr = mmio_base + sil_port[i].tf;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 probe_ent->port[i].altstatus_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +0900684 probe_ent->port[i].ctl_addr = mmio_base + sil_port[i].ctl;
685 probe_ent->port[i].bmdma_addr = mmio_base + sil_port[i].bmdma;
686 probe_ent->port[i].scr_addr = mmio_base + sil_port[i].scr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 ata_std_ports(&probe_ent->port[i]);
688 }
689
Jeff Garzikcca39742006-08-24 03:19:22 -0400690 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
Tejun Heo3d8ec912006-07-03 16:07:27 +0900691 mmio_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 pci_set_master(pdev);
694
Tejun Heo24dc5f32007-01-20 16:00:28 +0900695 if (!ata_device_add(probe_ent))
696 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697
Tejun Heo24dc5f32007-01-20 16:00:28 +0900698 devm_kfree(dev, probe_ent);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700}
701
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700702#ifdef CONFIG_PM
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900703static int sil_pci_device_resume(struct pci_dev *pdev)
704{
Jeff Garzikcca39742006-08-24 03:19:22 -0400705 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo553c4aa2006-12-26 19:39:50 +0900706 int rc;
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900707
Tejun Heo553c4aa2006-12-26 19:39:50 +0900708 rc = ata_pci_device_do_resume(pdev);
709 if (rc)
710 return rc;
711
Jeff Garzikcca39742006-08-24 03:19:22 -0400712 sil_init_controller(pdev, host->n_ports, host->ports[0]->flags,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900713 host->iomap[SIL_MMIO_BAR]);
Jeff Garzikcca39742006-08-24 03:19:22 -0400714 ata_host_resume(host);
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900715
716 return 0;
717}
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700718#endif
Tejun Heoafb5a7c2006-07-03 16:07:27 +0900719
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720static int __init sil_init(void)
721{
Pavel Roskinb7887192006-08-10 18:13:18 +0900722 return pci_register_driver(&sil_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723}
724
725static void __exit sil_exit(void)
726{
727 pci_unregister_driver(&sil_pci_driver);
728}
729
730
731module_init(sil_init);
732module_exit(sil_exit);