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Tejun Heoedb33662005-07-28 10:36:22 +09001/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
Tejun Heoedb33662005-07-28 10:36:22 +09008 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050027#include <linux/device.h>
Tejun Heoedb33662005-07-28 10:36:22 +090028#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050029#include <scsi/scsi_cmnd.h>
Tejun Heoedb33662005-07-28 10:36:22 +090030#include <linux/libata.h>
Tejun Heoedb33662005-07-28 10:36:22 +090031
32#define DRV_NAME "sata_sil24"
Jeff Garzikcb48cab2007-02-26 06:04:24 -050033#define DRV_VERSION "0.8"
Tejun Heoedb33662005-07-28 10:36:22 +090034
Tejun Heoedb33662005-07-28 10:36:22 +090035/*
36 * Port request block (PRB) 32 bytes
37 */
38struct sil24_prb {
Alexey Dobriyanb4772572006-06-06 07:31:14 +040039 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
Tejun Heoedb33662005-07-28 10:36:22 +090042 u8 fis[6 * 4];
43};
44
45/*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48struct sil24_sge {
Alexey Dobriyanb4772572006-06-06 07:31:14 +040049 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
Tejun Heoedb33662005-07-28 10:36:22 +090052};
53
54/*
55 * Port multiplier
56 */
57struct sil24_port_multiplier {
Alexey Dobriyanb4772572006-06-06 07:31:14 +040058 __le32 diag;
59 __le32 sactive;
Tejun Heoedb33662005-07-28 10:36:22 +090060};
61
62enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090063 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
Tejun Heoedb33662005-07-28 10:36:22 +090066 /*
67 * Global controller registers (128 bytes @ BAR0)
68 */
69 /* 32 bit regs */
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
71 HOST_CTRL = 0x40,
72 HOST_IRQ_STAT = 0x44,
73 HOST_PHY_CFG = 0x48,
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
79 /* 8 bit regs */
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
84 HOST_I2C_DATA = 0x7c,
85 HOST_I2C_XFER_CNT = 0x7e,
86 HOST_I2C_CTRL = 0x7f,
87
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
90
Tejun Heo7dafc3f2006-04-11 22:32:18 +090091 /* HOST_CTRL bits */
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
Tejun Heod2298dc2006-07-03 16:07:27 +090097 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
Tejun Heo7dafc3f2006-04-11 22:32:18 +090098
Tejun Heoedb33662005-07-28 10:36:22 +090099 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
Tejun Heo135da342006-05-31 18:27:57 +0900104
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
Tejun Heo135da342006-05-31 18:27:57 +0900106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
Tejun Heoedb33662005-07-28 10:36:22 +0900107
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
Tejun Heoc0c55902006-10-16 08:47:18 +0900109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112
Tejun Heoedb33662005-07-28 10:36:22 +0900113 /* 32 bit regs */
Tejun Heo83bbecc2005-08-17 13:09:18 +0900114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
Tejun Heoedb33662005-07-28 10:36:22 +0900119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
Tejun Heo83bbecc2005-08-17 13:09:18 +0900120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
Tejun Heoedb33662005-07-28 10:36:22 +0900122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
124 /* 16 bit regs */
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
131 /* 32 bit regs */
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
Tejun Heoc0c55902006-10-16 08:47:18 +0900135 PORT_CONTEXT = 0x1e04,
Tejun Heoedb33662005-07-28 10:36:22 +0900136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
142
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
Tejun Heod10cb352005-11-16 16:56:49 +0900148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
Tejun Heoe382eb12005-08-17 13:09:13 +0900150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
Tejun Heoe382eb12005-08-17 13:09:13 +0900152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
Tejun Heoedb33662005-07-28 10:36:22 +0900153
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
Tejun Heo7dafc3f2006-04-11 22:32:18 +0900162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
Tejun Heo3b9f1d02006-04-11 22:32:18 +0900167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
Tejun Heoedb33662005-07-28 10:36:22 +0900168
Tejun Heo88ce7552006-05-15 20:58:32 +0900169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
Tejun Heo05429252006-05-31 18:28:20 +0900170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 PORT_IRQ_UNK_FIS,
Tejun Heo88ce7552006-05-15 20:58:32 +0900172
Tejun Heoedb33662005-07-28 10:36:22 +0900173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
177
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
181
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
Tejun Heo64008802006-04-11 22:32:18 +0900202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
Tejun Heoedb33662005-07-28 10:36:22 +0900203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
Tejun Heo83bbecc2005-08-17 13:09:18 +0900204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
Tejun Heoedb33662005-07-28 10:36:22 +0900205
Tejun Heod10cb352005-11-16 16:56:49 +0900206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
212
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
220
Tejun Heoedb33662005-07-28 10:36:22 +0900221 /*
222 * Other constants
223 */
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
Tejun Heod10cb352005-11-16 16:56:49 +0900225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
Tejun Heoedb33662005-07-28 10:36:22 +0900229
Tejun Heoaee10a02006-05-15 21:03:56 +0900230 SIL24_MAX_CMDS = 31,
231
Tejun Heoedb33662005-07-28 10:36:22 +0900232 /* board id */
233 BID_SIL3124 = 0,
234 BID_SIL3132 = 1,
Tejun Heo042c21f2005-10-09 09:35:46 -0400235 BID_SIL3131 = 2,
Tejun Heoedb33662005-07-28 10:36:22 +0900236
Tejun Heo9466d852006-04-11 22:32:18 +0900237 /* host flags */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heoaee10a02006-05-15 21:03:56 +0900239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Tejun Heo05429252006-05-31 18:28:20 +0900240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY,
Tejun Heo37024e82006-04-11 22:32:19 +0900241 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
Tejun Heo9466d852006-04-11 22:32:18 +0900242
Tejun Heoedb33662005-07-28 10:36:22 +0900243 IRQ_STAT_4PORTS = 0xf,
244};
245
Tejun Heo69ad1852005-11-18 14:16:45 +0900246struct sil24_ata_block {
Tejun Heoedb33662005-07-28 10:36:22 +0900247 struct sil24_prb prb;
248 struct sil24_sge sge[LIBATA_MAX_PRD];
249};
250
Tejun Heo69ad1852005-11-18 14:16:45 +0900251struct sil24_atapi_block {
252 struct sil24_prb prb;
253 u8 cdb[16];
254 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
255};
256
257union sil24_cmd_block {
258 struct sil24_ata_block ata;
259 struct sil24_atapi_block atapi;
260};
261
Tejun Heo88ce7552006-05-15 20:58:32 +0900262static struct sil24_cerr_info {
263 unsigned int err_mask, action;
264 const char *desc;
265} sil24_cerr_db[] = {
266 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
267 "device error" },
268 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
269 "device error via D2H FIS" },
270 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
271 "device error via SDB FIS" },
272 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
273 "error in data FIS" },
274 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
275 "failed to transmit command FIS" },
276 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
277 "protocol mismatch" },
278 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "data directon mismatch" },
280 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "ran out of SGEs while writing" },
282 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "ran out of SGEs while reading" },
284 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
285 "invalid data directon for ATAPI CDB" },
286 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
287 "SGT no on qword boundary" },
288 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
289 "PCI target abort while fetching SGT" },
290 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI master abort while fetching SGT" },
292 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI parity error while fetching SGT" },
294 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
295 "PRB not on qword boundary" },
296 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
297 "PCI target abort while fetching PRB" },
298 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI master abort while fetching PRB" },
300 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI parity error while fetching PRB" },
302 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "undefined error while transferring data" },
304 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "PCI target abort while transferring data" },
306 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI master abort while transferring data" },
308 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
309 "PCI parity error while transferring data" },
310 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
311 "FIS received while sending service FIS" },
312};
313
Tejun Heoedb33662005-07-28 10:36:22 +0900314/*
315 * ap->private_data
316 *
317 * The preview driver always returned 0 for status. We emulate it
318 * here from the previous interrupt.
319 */
320struct sil24_port_priv {
Tejun Heo69ad1852005-11-18 14:16:45 +0900321 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
Tejun Heoedb33662005-07-28 10:36:22 +0900322 dma_addr_t cmd_block_dma; /* DMA base addr for them */
Tejun Heo6a575fa2005-10-06 11:43:39 +0900323 struct ata_taskfile tf; /* Cached taskfile registers */
Tejun Heoedb33662005-07-28 10:36:22 +0900324};
325
Alancd0d3bb2007-03-02 00:56:15 +0000326static void sil24_dev_config(struct ata_device *dev);
Tejun Heoedb33662005-07-28 10:36:22 +0900327static u8 sil24_check_status(struct ata_port *ap);
Tejun Heoedb33662005-07-28 10:36:22 +0900328static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
329static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
Tejun Heo7f726d12005-10-07 01:43:19 +0900330static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
Tejun Heoedb33662005-07-28 10:36:22 +0900331static void sil24_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900332static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
Tejun Heoedb33662005-07-28 10:36:22 +0900333static void sil24_irq_clear(struct ata_port *ap);
David Howells7d12e782006-10-05 14:55:46 +0100334static irqreturn_t sil24_interrupt(int irq, void *dev_instance);
Tejun Heo88ce7552006-05-15 20:58:32 +0900335static void sil24_freeze(struct ata_port *ap);
336static void sil24_thaw(struct ata_port *ap);
337static void sil24_error_handler(struct ata_port *ap);
338static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
Tejun Heoedb33662005-07-28 10:36:22 +0900339static int sil24_port_start(struct ata_port *ap);
Tejun Heoedb33662005-07-28 10:36:22 +0900340static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700341#ifdef CONFIG_PM
Tejun Heod2298dc2006-07-03 16:07:27 +0900342static int sil24_pci_device_resume(struct pci_dev *pdev);
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700343#endif
Tejun Heoedb33662005-07-28 10:36:22 +0900344
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500345static const struct pci_device_id sil24_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400346 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
347 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
348 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
Jamie Clark722d67b2007-03-13 12:48:00 +0800349 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400350 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
351 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
352
Tejun Heo1fcce8392005-10-09 09:31:33 -0400353 { } /* terminate list */
Tejun Heoedb33662005-07-28 10:36:22 +0900354};
355
356static struct pci_driver sil24_pci_driver = {
357 .name = DRV_NAME,
358 .id_table = sil24_pci_tbl,
359 .probe = sil24_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900360 .remove = ata_pci_remove_one,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700361#ifdef CONFIG_PM
Tejun Heod2298dc2006-07-03 16:07:27 +0900362 .suspend = ata_pci_device_suspend,
363 .resume = sil24_pci_device_resume,
Alexey Dobriyan281d4262006-08-14 22:49:30 -0700364#endif
Tejun Heoedb33662005-07-28 10:36:22 +0900365};
366
Jeff Garzik193515d2005-11-07 00:59:37 -0500367static struct scsi_host_template sil24_sht = {
Tejun Heoedb33662005-07-28 10:36:22 +0900368 .module = THIS_MODULE,
369 .name = DRV_NAME,
370 .ioctl = ata_scsi_ioctl,
371 .queuecommand = ata_scsi_queuecmd,
Tejun Heoaee10a02006-05-15 21:03:56 +0900372 .change_queue_depth = ata_scsi_change_queue_depth,
373 .can_queue = SIL24_MAX_CMDS,
Tejun Heoedb33662005-07-28 10:36:22 +0900374 .this_id = ATA_SHT_THIS_ID,
375 .sg_tablesize = LIBATA_MAX_PRD,
Tejun Heoedb33662005-07-28 10:36:22 +0900376 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
377 .emulated = ATA_SHT_EMULATED,
378 .use_clustering = ATA_SHT_USE_CLUSTERING,
379 .proc_name = DRV_NAME,
380 .dma_boundary = ATA_DMA_BOUNDARY,
381 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900382 .slave_destroy = ata_scsi_slave_destroy,
Tejun Heoedb33662005-07-28 10:36:22 +0900383 .bios_param = ata_std_bios_param,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900384#ifdef CONFIG_PM
Tejun Heod2298dc2006-07-03 16:07:27 +0900385 .suspend = ata_scsi_device_suspend,
386 .resume = ata_scsi_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900387#endif
Tejun Heoedb33662005-07-28 10:36:22 +0900388};
389
Jeff Garzik057ace52005-10-22 14:27:05 -0400390static const struct ata_port_operations sil24_ops = {
Tejun Heoedb33662005-07-28 10:36:22 +0900391 .port_disable = ata_port_disable,
392
Tejun Heo69ad1852005-11-18 14:16:45 +0900393 .dev_config = sil24_dev_config,
394
Tejun Heoedb33662005-07-28 10:36:22 +0900395 .check_status = sil24_check_status,
396 .check_altstatus = sil24_check_status,
Tejun Heoedb33662005-07-28 10:36:22 +0900397 .dev_select = ata_noop_dev_select,
398
Tejun Heo7f726d12005-10-07 01:43:19 +0900399 .tf_read = sil24_tf_read,
400
Tejun Heoedb33662005-07-28 10:36:22 +0900401 .qc_prep = sil24_qc_prep,
402 .qc_issue = sil24_qc_issue,
403
Tejun Heoedb33662005-07-28 10:36:22 +0900404 .irq_handler = sil24_interrupt,
405 .irq_clear = sil24_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900406 .irq_on = ata_dummy_irq_on,
407 .irq_ack = ata_dummy_irq_ack,
Tejun Heoedb33662005-07-28 10:36:22 +0900408
409 .scr_read = sil24_scr_read,
410 .scr_write = sil24_scr_write,
411
Tejun Heo88ce7552006-05-15 20:58:32 +0900412 .freeze = sil24_freeze,
413 .thaw = sil24_thaw,
414 .error_handler = sil24_error_handler,
415 .post_internal_cmd = sil24_post_internal_cmd,
416
Tejun Heoedb33662005-07-28 10:36:22 +0900417 .port_start = sil24_port_start,
Tejun Heoedb33662005-07-28 10:36:22 +0900418};
419
Tejun Heo042c21f2005-10-09 09:35:46 -0400420/*
Jeff Garzikcca39742006-08-24 03:19:22 -0400421 * Use bits 30-31 of port_flags to encode available port numbers.
Tejun Heo042c21f2005-10-09 09:35:46 -0400422 * Current maxium is 4.
423 */
424#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
425#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
426
Tejun Heoedb33662005-07-28 10:36:22 +0900427static struct ata_port_info sil24_port_info[] = {
428 /* sil_3124 */
429 {
430 .sht = &sil24_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400431 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
Tejun Heo37024e82006-04-11 22:32:19 +0900432 SIL24_FLAG_PCIX_IRQ_WOC,
Tejun Heoedb33662005-07-28 10:36:22 +0900433 .pio_mask = 0x1f, /* pio0-4 */
434 .mwdma_mask = 0x07, /* mwdma0-2 */
435 .udma_mask = 0x3f, /* udma0-5 */
436 .port_ops = &sil24_ops,
437 },
Jeff Garzik2e9edbf2006-03-24 09:56:57 -0500438 /* sil_3132 */
Tejun Heoedb33662005-07-28 10:36:22 +0900439 {
440 .sht = &sil24_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400441 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
Tejun Heo042c21f2005-10-09 09:35:46 -0400442 .pio_mask = 0x1f, /* pio0-4 */
443 .mwdma_mask = 0x07, /* mwdma0-2 */
444 .udma_mask = 0x3f, /* udma0-5 */
445 .port_ops = &sil24_ops,
446 },
447 /* sil_3131/sil_3531 */
448 {
449 .sht = &sil24_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400450 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
Tejun Heoedb33662005-07-28 10:36:22 +0900451 .pio_mask = 0x1f, /* pio0-4 */
452 .mwdma_mask = 0x07, /* mwdma0-2 */
453 .udma_mask = 0x3f, /* udma0-5 */
454 .port_ops = &sil24_ops,
455 },
456};
457
Tejun Heoaee10a02006-05-15 21:03:56 +0900458static int sil24_tag(int tag)
459{
460 if (unlikely(ata_tag_internal(tag)))
461 return 0;
462 return tag;
463}
464
Alancd0d3bb2007-03-02 00:56:15 +0000465static void sil24_dev_config(struct ata_device *dev)
Tejun Heo69ad1852005-11-18 14:16:45 +0900466{
Alancd0d3bb2007-03-02 00:56:15 +0000467 void __iomem *port = dev->ap->ioaddr.cmd_addr;
Tejun Heo69ad1852005-11-18 14:16:45 +0900468
Tejun Heo6e7846e2006-02-12 23:32:58 +0900469 if (dev->cdb_len == 16)
Tejun Heo69ad1852005-11-18 14:16:45 +0900470 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
471 else
472 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
473}
474
Tejun Heo6a575fa2005-10-06 11:43:39 +0900475static inline void sil24_update_tf(struct ata_port *ap)
476{
477 struct sil24_port_priv *pp = ap->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900478 void __iomem *port = ap->ioaddr.cmd_addr;
Al Viro4b4a5ea2005-10-29 06:38:44 +0100479 struct sil24_prb __iomem *prb = port;
480 u8 fis[6 * 4];
Tejun Heo6a575fa2005-10-06 11:43:39 +0900481
Al Viro4b4a5ea2005-10-29 06:38:44 +0100482 memcpy_fromio(fis, prb->fis, 6 * 4);
483 ata_tf_from_fis(fis, &pp->tf);
Tejun Heo6a575fa2005-10-06 11:43:39 +0900484}
485
Tejun Heoedb33662005-07-28 10:36:22 +0900486static u8 sil24_check_status(struct ata_port *ap)
487{
Tejun Heo6a575fa2005-10-06 11:43:39 +0900488 struct sil24_port_priv *pp = ap->private_data;
489 return pp->tf.command;
Tejun Heoedb33662005-07-28 10:36:22 +0900490}
491
Tejun Heoedb33662005-07-28 10:36:22 +0900492static int sil24_scr_map[] = {
493 [SCR_CONTROL] = 0,
494 [SCR_STATUS] = 1,
495 [SCR_ERROR] = 2,
496 [SCR_ACTIVE] = 3,
497};
498
499static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
500{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900501 void __iomem *scr_addr = ap->ioaddr.scr_addr;
Tejun Heoedb33662005-07-28 10:36:22 +0900502 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
Al Viro4b4a5ea2005-10-29 06:38:44 +0100503 void __iomem *addr;
Tejun Heoedb33662005-07-28 10:36:22 +0900504 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
505 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
506 }
507 return 0xffffffffU;
508}
509
510static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
511{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900512 void __iomem *scr_addr = ap->ioaddr.scr_addr;
Tejun Heoedb33662005-07-28 10:36:22 +0900513 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
Al Viro4b4a5ea2005-10-29 06:38:44 +0100514 void __iomem *addr;
Tejun Heoedb33662005-07-28 10:36:22 +0900515 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
516 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
517 }
518}
519
Tejun Heo7f726d12005-10-07 01:43:19 +0900520static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
521{
522 struct sil24_port_priv *pp = ap->private_data;
523 *tf = pp->tf;
524}
525
Tejun Heob5bc4212006-04-11 22:32:19 +0900526static int sil24_init_port(struct ata_port *ap)
527{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900528 void __iomem *port = ap->ioaddr.cmd_addr;
Tejun Heob5bc4212006-04-11 22:32:19 +0900529 u32 tmp;
530
531 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
532 ata_wait_register(port + PORT_CTRL_STAT,
533 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
534 tmp = ata_wait_register(port + PORT_CTRL_STAT,
535 PORT_CS_RDY, 0, 10, 100);
536
537 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
538 return -EIO;
539 return 0;
540}
541
Tejun Heo2bf2cb22006-04-11 22:16:45 +0900542static int sil24_softreset(struct ata_port *ap, unsigned int *class)
Tejun Heoca451602005-11-18 14:14:01 +0900543{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900544 void __iomem *port = ap->ioaddr.cmd_addr;
Tejun Heoca451602005-11-18 14:14:01 +0900545 struct sil24_port_priv *pp = ap->private_data;
Tejun Heo69ad1852005-11-18 14:16:45 +0900546 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
Tejun Heoca451602005-11-18 14:14:01 +0900547 dma_addr_t paddr = pp->cmd_block_dma;
Tejun Heo88ce7552006-05-15 20:58:32 +0900548 u32 mask, irq_stat;
Tejun Heo643be972006-04-11 22:22:29 +0900549 const char *reason;
Tejun Heoca451602005-11-18 14:14:01 +0900550
Tejun Heo07b73472006-02-10 23:58:48 +0900551 DPRINTK("ENTER\n");
552
Tejun Heo81952c52006-05-15 20:57:47 +0900553 if (ata_port_offline(ap)) {
Tejun Heo10d996a2006-03-11 11:42:34 +0900554 DPRINTK("PHY reports no device\n");
555 *class = ATA_DEV_NONE;
556 goto out;
557 }
558
Tejun Heo2555d6c2006-04-11 22:32:19 +0900559 /* put the port into known state */
560 if (sil24_init_port(ap)) {
561 reason ="port not ready";
562 goto err;
563 }
564
Tejun Heo0eaa6052006-04-11 22:32:19 +0900565 /* do SRST */
Tejun Heobad28a32006-04-11 22:32:19 +0900566 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
Tejun Heo28c8f3b2006-10-16 08:47:18 +0900567 prb->fis[1] = 0; /* no PMP yet */
Tejun Heoca451602005-11-18 14:14:01 +0900568
569 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
Tejun Heo26ec6342006-04-11 22:32:19 +0900570 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
Tejun Heoca451602005-11-18 14:14:01 +0900571
Tejun Heo7dd29dd2006-04-11 22:22:30 +0900572 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
573 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
574 100, ATA_TMOUT_BOOT / HZ * 1000);
Tejun Heoca451602005-11-18 14:14:01 +0900575
Tejun Heo7dd29dd2006-04-11 22:22:30 +0900576 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
577 irq_stat >>= PORT_IRQ_RAW_SHIFT;
Tejun Heoca451602005-11-18 14:14:01 +0900578
Tejun Heo10d996a2006-03-11 11:42:34 +0900579 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
Tejun Heo643be972006-04-11 22:22:29 +0900580 if (irq_stat & PORT_IRQ_ERROR)
581 reason = "SRST command error";
582 else
583 reason = "timeout";
584 goto err;
Tejun Heo07b73472006-02-10 23:58:48 +0900585 }
Tejun Heo10d996a2006-03-11 11:42:34 +0900586
587 sil24_update_tf(ap);
588 *class = ata_dev_classify(&pp->tf);
589
Tejun Heo07b73472006-02-10 23:58:48 +0900590 if (*class == ATA_DEV_UNKNOWN)
591 *class = ATA_DEV_NONE;
592
Tejun Heo10d996a2006-03-11 11:42:34 +0900593 out:
Tejun Heo07b73472006-02-10 23:58:48 +0900594 DPRINTK("EXIT, class=%u\n", *class);
Tejun Heoca451602005-11-18 14:14:01 +0900595 return 0;
Tejun Heo643be972006-04-11 22:22:29 +0900596
597 err:
Tejun Heof15a1da2006-05-15 20:57:56 +0900598 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo643be972006-04-11 22:22:29 +0900599 return -EIO;
Tejun Heoca451602005-11-18 14:14:01 +0900600}
601
Tejun Heo2bf2cb22006-04-11 22:16:45 +0900602static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
Tejun Heo489ff4c2006-02-10 23:58:48 +0900603{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900604 void __iomem *port = ap->ioaddr.cmd_addr;
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900605 const char *reason;
Tejun Heoe8e008e2006-05-31 18:27:59 +0900606 int tout_msec, rc;
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900607 u32 tmp;
Tejun Heo489ff4c2006-02-10 23:58:48 +0900608
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900609 /* sil24 does the right thing(tm) without any protection */
Tejun Heo3c567b72006-05-15 20:57:23 +0900610 sata_set_spd(ap);
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900611
612 tout_msec = 100;
Tejun Heo81952c52006-05-15 20:57:47 +0900613 if (ata_port_online(ap))
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900614 tout_msec = 5000;
615
616 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
617 tmp = ata_wait_register(port + PORT_CTRL_STAT,
618 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
619
Tejun Heoe8e008e2006-05-31 18:27:59 +0900620 /* SStatus oscillates between zero and valid status after
621 * DEV_RST, debounce it.
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900622 */
Tejun Heoe9c83912006-07-03 16:07:26 +0900623 rc = sata_phy_debounce(ap, sata_deb_timing_long);
Tejun Heoe8e008e2006-05-31 18:27:59 +0900624 if (rc) {
625 reason = "PHY debouncing failed";
626 goto err;
627 }
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900628
629 if (tmp & PORT_CS_DEV_RST) {
Tejun Heo81952c52006-05-15 20:57:47 +0900630 if (ata_port_offline(ap))
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900631 return 0;
632 reason = "link not ready";
633 goto err;
634 }
635
Tejun Heoe8e008e2006-05-31 18:27:59 +0900636 /* Sil24 doesn't store signature FIS after hardreset, so we
637 * can't wait for BSY to clear. Some devices take a long time
638 * to get ready and those devices will choke if we don't wait
639 * for BSY clearance here. Tell libata to perform follow-up
640 * softreset.
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900641 */
Tejun Heoe8e008e2006-05-31 18:27:59 +0900642 return -EAGAIN;
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900643
644 err:
Tejun Heof15a1da2006-05-15 20:57:56 +0900645 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
Tejun Heoecc2e2b2006-04-11 22:32:19 +0900646 return -EIO;
Tejun Heo489ff4c2006-02-10 23:58:48 +0900647}
648
Tejun Heoedb33662005-07-28 10:36:22 +0900649static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
Tejun Heo69ad1852005-11-18 14:16:45 +0900650 struct sil24_sge *sge)
Tejun Heoedb33662005-07-28 10:36:22 +0900651{
Jeff Garzik972c26b2005-10-18 22:14:54 -0400652 struct scatterlist *sg;
Tejun Heoedb33662005-07-28 10:36:22 +0900653
Jeff Garzik972c26b2005-10-18 22:14:54 -0400654 ata_for_each_sg(sg, qc) {
Tejun Heoedb33662005-07-28 10:36:22 +0900655 sge->addr = cpu_to_le64(sg_dma_address(sg));
656 sge->cnt = cpu_to_le32(sg_dma_len(sg));
Jeff Garzik972c26b2005-10-18 22:14:54 -0400657 if (ata_sg_is_last(sg, qc))
658 sge->flags = cpu_to_le32(SGE_TRM);
659 else
660 sge->flags = 0;
Jeff Garzik972c26b2005-10-18 22:14:54 -0400661 sge++;
Tejun Heoedb33662005-07-28 10:36:22 +0900662 }
663}
664
665static void sil24_qc_prep(struct ata_queued_cmd *qc)
666{
667 struct ata_port *ap = qc->ap;
668 struct sil24_port_priv *pp = ap->private_data;
Tejun Heoaee10a02006-05-15 21:03:56 +0900669 union sil24_cmd_block *cb;
Tejun Heo69ad1852005-11-18 14:16:45 +0900670 struct sil24_prb *prb;
671 struct sil24_sge *sge;
Tejun Heobad28a32006-04-11 22:32:19 +0900672 u16 ctrl = 0;
Tejun Heoedb33662005-07-28 10:36:22 +0900673
Tejun Heoaee10a02006-05-15 21:03:56 +0900674 cb = &pp->cmd_block[sil24_tag(qc->tag)];
675
Tejun Heoedb33662005-07-28 10:36:22 +0900676 switch (qc->tf.protocol) {
677 case ATA_PROT_PIO:
678 case ATA_PROT_DMA:
Tejun Heoaee10a02006-05-15 21:03:56 +0900679 case ATA_PROT_NCQ:
Tejun Heoedb33662005-07-28 10:36:22 +0900680 case ATA_PROT_NODATA:
Tejun Heo69ad1852005-11-18 14:16:45 +0900681 prb = &cb->ata.prb;
682 sge = cb->ata.sge;
Tejun Heoedb33662005-07-28 10:36:22 +0900683 break;
Tejun Heo69ad1852005-11-18 14:16:45 +0900684
685 case ATA_PROT_ATAPI:
686 case ATA_PROT_ATAPI_DMA:
687 case ATA_PROT_ATAPI_NODATA:
688 prb = &cb->atapi.prb;
689 sge = cb->atapi.sge;
690 memset(cb->atapi.cdb, 0, 32);
Tejun Heo6e7846e2006-02-12 23:32:58 +0900691 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
Tejun Heo69ad1852005-11-18 14:16:45 +0900692
693 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
694 if (qc->tf.flags & ATA_TFLAG_WRITE)
Tejun Heobad28a32006-04-11 22:32:19 +0900695 ctrl = PRB_CTRL_PACKET_WRITE;
Tejun Heo69ad1852005-11-18 14:16:45 +0900696 else
Tejun Heobad28a32006-04-11 22:32:19 +0900697 ctrl = PRB_CTRL_PACKET_READ;
698 }
Tejun Heo69ad1852005-11-18 14:16:45 +0900699 break;
700
Tejun Heoedb33662005-07-28 10:36:22 +0900701 default:
Tejun Heo69ad1852005-11-18 14:16:45 +0900702 prb = NULL; /* shut up, gcc */
703 sge = NULL;
Tejun Heoedb33662005-07-28 10:36:22 +0900704 BUG();
705 }
706
Tejun Heobad28a32006-04-11 22:32:19 +0900707 prb->ctrl = cpu_to_le16(ctrl);
Tejun Heoedb33662005-07-28 10:36:22 +0900708 ata_tf_to_fis(&qc->tf, prb->fis, 0);
709
710 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo69ad1852005-11-18 14:16:45 +0900711 sil24_fill_sg(qc, sge);
Tejun Heoedb33662005-07-28 10:36:22 +0900712}
713
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900714static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
Tejun Heoedb33662005-07-28 10:36:22 +0900715{
716 struct ata_port *ap = qc->ap;
717 struct sil24_port_priv *pp = ap->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900718 void __iomem *port = ap->ioaddr.cmd_addr;
Tejun Heoaee10a02006-05-15 21:03:56 +0900719 unsigned int tag = sil24_tag(qc->tag);
720 dma_addr_t paddr;
721 void __iomem *activate;
Tejun Heoedb33662005-07-28 10:36:22 +0900722
Tejun Heoaee10a02006-05-15 21:03:56 +0900723 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
724 activate = port + PORT_CMD_ACTIVATE + tag * 8;
725
726 writel((u32)paddr, activate);
727 writel((u64)paddr >> 32, activate + 4);
Tejun Heo26ec6342006-04-11 22:32:19 +0900728
Tejun Heoedb33662005-07-28 10:36:22 +0900729 return 0;
730}
731
732static void sil24_irq_clear(struct ata_port *ap)
733{
734 /* unused */
735}
736
Tejun Heo88ce7552006-05-15 20:58:32 +0900737static void sil24_freeze(struct ata_port *ap)
Tejun Heo7d1ce682005-11-18 14:09:05 +0900738{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900739 void __iomem *port = ap->ioaddr.cmd_addr;
Tejun Heo87466182005-08-17 13:08:57 +0900740
Tejun Heo88ce7552006-05-15 20:58:32 +0900741 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
742 * PORT_IRQ_ENABLE instead.
Tejun Heoc0ab4242005-11-18 14:22:03 +0900743 */
Tejun Heo88ce7552006-05-15 20:58:32 +0900744 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
745}
Tejun Heo87466182005-08-17 13:08:57 +0900746
Tejun Heo88ce7552006-05-15 20:58:32 +0900747static void sil24_thaw(struct ata_port *ap)
748{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900749 void __iomem *port = ap->ioaddr.cmd_addr;
Tejun Heo88ce7552006-05-15 20:58:32 +0900750 u32 tmp;
751
752 /* clear IRQ */
753 tmp = readl(port + PORT_IRQ_STAT);
754 writel(tmp, port + PORT_IRQ_STAT);
755
756 /* turn IRQ back on */
757 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
758}
759
760static void sil24_error_intr(struct ata_port *ap)
761{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900762 void __iomem *port = ap->ioaddr.cmd_addr;
Tejun Heo88ce7552006-05-15 20:58:32 +0900763 struct ata_eh_info *ehi = &ap->eh_info;
764 int freeze = 0;
765 u32 irq_stat;
766
767 /* on error, we need to clear IRQ explicitly */
768 irq_stat = readl(port + PORT_IRQ_STAT);
769 writel(irq_stat, port + PORT_IRQ_STAT);
770
771 /* first, analyze and record host port events */
772 ata_ehi_clear_desc(ehi);
773
774 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
775
Tejun Heo05429252006-05-31 18:28:20 +0900776 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
777 ata_ehi_hotplugged(ehi);
778 ata_ehi_push_desc(ehi, ", %s",
779 irq_stat & PORT_IRQ_PHYRDY_CHG ?
780 "PHY RDY changed" : "device exchanged");
Tejun Heo88ce7552006-05-15 20:58:32 +0900781 freeze = 1;
Tejun Heo6a575fa2005-10-06 11:43:39 +0900782 }
783
Tejun Heo88ce7552006-05-15 20:58:32 +0900784 if (irq_stat & PORT_IRQ_UNK_FIS) {
785 ehi->err_mask |= AC_ERR_HSM;
786 ehi->action |= ATA_EH_SOFTRESET;
787 ata_ehi_push_desc(ehi , ", unknown FIS");
788 freeze = 1;
Albert Leea22e2eb2005-12-05 15:38:02 +0800789 }
Tejun Heo88ce7552006-05-15 20:58:32 +0900790
791 /* deal with command error */
792 if (irq_stat & PORT_IRQ_ERROR) {
793 struct sil24_cerr_info *ci = NULL;
794 unsigned int err_mask = 0, action = 0;
795 struct ata_queued_cmd *qc;
796 u32 cerr;
797
798 /* analyze CMD_ERR */
799 cerr = readl(port + PORT_CMD_ERR);
800 if (cerr < ARRAY_SIZE(sil24_cerr_db))
801 ci = &sil24_cerr_db[cerr];
802
803 if (ci && ci->desc) {
804 err_mask |= ci->err_mask;
805 action |= ci->action;
806 ata_ehi_push_desc(ehi, ", %s", ci->desc);
807 } else {
808 err_mask |= AC_ERR_OTHER;
809 action |= ATA_EH_SOFTRESET;
810 ata_ehi_push_desc(ehi, ", unknown command error %d",
811 cerr);
812 }
813
814 /* record error info */
815 qc = ata_qc_from_tag(ap, ap->active_tag);
816 if (qc) {
Tejun Heo88ce7552006-05-15 20:58:32 +0900817 sil24_update_tf(ap);
818 qc->err_mask |= err_mask;
819 } else
820 ehi->err_mask |= err_mask;
821
822 ehi->action |= action;
823 }
824
825 /* freeze or abort */
826 if (freeze)
827 ata_port_freeze(ap);
828 else
829 ata_port_abort(ap);
Tejun Heo87466182005-08-17 13:08:57 +0900830}
831
Tejun Heoaee10a02006-05-15 21:03:56 +0900832static void sil24_finish_qc(struct ata_queued_cmd *qc)
833{
834 if (qc->flags & ATA_QCFLAG_RESULT_TF)
835 sil24_update_tf(qc->ap);
836}
837
Tejun Heoedb33662005-07-28 10:36:22 +0900838static inline void sil24_host_intr(struct ata_port *ap)
839{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900840 void __iomem *port = ap->ioaddr.cmd_addr;
Tejun Heoaee10a02006-05-15 21:03:56 +0900841 u32 slot_stat, qc_active;
842 int rc;
Tejun Heoedb33662005-07-28 10:36:22 +0900843
844 slot_stat = readl(port + PORT_SLOT_STAT);
Tejun Heo37024e82006-04-11 22:32:19 +0900845
Tejun Heo88ce7552006-05-15 20:58:32 +0900846 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
847 sil24_error_intr(ap);
848 return;
849 }
Tejun Heo37024e82006-04-11 22:32:19 +0900850
Tejun Heo88ce7552006-05-15 20:58:32 +0900851 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
852 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
853
Tejun Heoaee10a02006-05-15 21:03:56 +0900854 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
855 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
856 if (rc > 0)
857 return;
858 if (rc < 0) {
859 struct ata_eh_info *ehi = &ap->eh_info;
860 ehi->err_mask |= AC_ERR_HSM;
861 ehi->action |= ATA_EH_SOFTRESET;
862 ata_port_freeze(ap);
Tejun Heo88ce7552006-05-15 20:58:32 +0900863 return;
864 }
865
866 if (ata_ratelimit())
867 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
Tejun Heoaee10a02006-05-15 21:03:56 +0900868 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
869 slot_stat, ap->active_tag, ap->sactive);
Tejun Heoedb33662005-07-28 10:36:22 +0900870}
871
David Howells7d12e782006-10-05 14:55:46 +0100872static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
Tejun Heoedb33662005-07-28 10:36:22 +0900873{
Jeff Garzikcca39742006-08-24 03:19:22 -0400874 struct ata_host *host = dev_instance;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900875 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
Tejun Heoedb33662005-07-28 10:36:22 +0900876 unsigned handled = 0;
877 u32 status;
878 int i;
879
Tejun Heo0d5ff562007-02-01 15:06:36 +0900880 status = readl(host_base + HOST_IRQ_STAT);
Tejun Heoedb33662005-07-28 10:36:22 +0900881
Tejun Heo06460ae2005-08-17 13:08:52 +0900882 if (status == 0xffffffff) {
883 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
884 "PCI fault or device removal?\n");
885 goto out;
886 }
887
Tejun Heoedb33662005-07-28 10:36:22 +0900888 if (!(status & IRQ_STAT_4PORTS))
889 goto out;
890
Jeff Garzikcca39742006-08-24 03:19:22 -0400891 spin_lock(&host->lock);
Tejun Heoedb33662005-07-28 10:36:22 +0900892
Jeff Garzikcca39742006-08-24 03:19:22 -0400893 for (i = 0; i < host->n_ports; i++)
Tejun Heoedb33662005-07-28 10:36:22 +0900894 if (status & (1 << i)) {
Jeff Garzikcca39742006-08-24 03:19:22 -0400895 struct ata_port *ap = host->ports[i];
Tejun Heo198e0fe2006-04-02 18:51:52 +0900896 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
Jeff Garzikcca39742006-08-24 03:19:22 -0400897 sil24_host_intr(host->ports[i]);
Tejun Heo3cc45712005-08-17 13:08:47 +0900898 handled++;
899 } else
900 printk(KERN_ERR DRV_NAME
901 ": interrupt from disabled port %d\n", i);
Tejun Heoedb33662005-07-28 10:36:22 +0900902 }
903
Jeff Garzikcca39742006-08-24 03:19:22 -0400904 spin_unlock(&host->lock);
Tejun Heoedb33662005-07-28 10:36:22 +0900905 out:
906 return IRQ_RETVAL(handled);
907}
908
Tejun Heo88ce7552006-05-15 20:58:32 +0900909static void sil24_error_handler(struct ata_port *ap)
910{
911 struct ata_eh_context *ehc = &ap->eh_context;
912
913 if (sil24_init_port(ap)) {
914 ata_eh_freeze_port(ap);
915 ehc->i.action |= ATA_EH_HARDRESET;
916 }
917
918 /* perform recovery */
Tejun Heof5914a42006-05-31 18:27:48 +0900919 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
920 ata_std_postreset);
Tejun Heo88ce7552006-05-15 20:58:32 +0900921}
922
923static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
924{
925 struct ata_port *ap = qc->ap;
926
927 if (qc->flags & ATA_QCFLAG_FAILED)
928 qc->err_mask |= AC_ERR_OTHER;
929
930 /* make DMA engine forget about the failed command */
931 if (qc->err_mask)
932 sil24_init_port(ap);
933}
934
Tejun Heoedb33662005-07-28 10:36:22 +0900935static int sil24_port_start(struct ata_port *ap)
936{
Jeff Garzikcca39742006-08-24 03:19:22 -0400937 struct device *dev = ap->host->dev;
Tejun Heoedb33662005-07-28 10:36:22 +0900938 struct sil24_port_priv *pp;
Tejun Heo69ad1852005-11-18 14:16:45 +0900939 union sil24_cmd_block *cb;
Tejun Heoaee10a02006-05-15 21:03:56 +0900940 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
Tejun Heoedb33662005-07-28 10:36:22 +0900941 dma_addr_t cb_dma;
Tejun Heo24dc5f32007-01-20 16:00:28 +0900942 int rc;
Tejun Heoedb33662005-07-28 10:36:22 +0900943
Tejun Heo24dc5f32007-01-20 16:00:28 +0900944 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heoedb33662005-07-28 10:36:22 +0900945 if (!pp)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900946 return -ENOMEM;
Tejun Heoedb33662005-07-28 10:36:22 +0900947
Tejun Heo6a575fa2005-10-06 11:43:39 +0900948 pp->tf.command = ATA_DRDY;
949
Tejun Heo24dc5f32007-01-20 16:00:28 +0900950 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500951 if (!cb)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900952 return -ENOMEM;
Tejun Heoedb33662005-07-28 10:36:22 +0900953 memset(cb, 0, cb_size);
954
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500955 rc = ata_pad_alloc(ap, dev);
956 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +0900957 return rc;
Jeff Garzik6037d6b2005-11-04 22:08:00 -0500958
Tejun Heoedb33662005-07-28 10:36:22 +0900959 pp->cmd_block = cb;
960 pp->cmd_block_dma = cb_dma;
961
962 ap->private_data = pp;
963
964 return 0;
Tejun Heoedb33662005-07-28 10:36:22 +0900965}
966
Tejun Heo2a41a612006-07-03 16:07:27 +0900967static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
Jeff Garzikcca39742006-08-24 03:19:22 -0400968 unsigned long port_flags,
Tejun Heo2a41a612006-07-03 16:07:27 +0900969 void __iomem *host_base,
970 void __iomem *port_base)
971{
972 u32 tmp;
973 int i;
974
975 /* GPIO off */
976 writel(0, host_base + HOST_FLASH_CMD);
977
978 /* clear global reset & mask interrupts during initialization */
979 writel(0, host_base + HOST_CTRL);
980
981 /* init ports */
982 for (i = 0; i < n_ports; i++) {
983 void __iomem *port = port_base + i * PORT_REGS_SIZE;
984
985 /* Initial PHY setting */
986 writel(0x20c, port + PORT_PHY_CFG);
987
988 /* Clear port RST */
989 tmp = readl(port + PORT_CTRL_STAT);
990 if (tmp & PORT_CS_PORT_RST) {
991 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
992 tmp = ata_wait_register(port + PORT_CTRL_STAT,
993 PORT_CS_PORT_RST,
994 PORT_CS_PORT_RST, 10, 100);
995 if (tmp & PORT_CS_PORT_RST)
996 dev_printk(KERN_ERR, &pdev->dev,
997 "failed to clear port RST\n");
998 }
999
1000 /* Configure IRQ WoC */
Jeff Garzikcca39742006-08-24 03:19:22 -04001001 if (port_flags & SIL24_FLAG_PCIX_IRQ_WOC)
Tejun Heo2a41a612006-07-03 16:07:27 +09001002 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1003 else
1004 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1005
1006 /* Zero error counters. */
1007 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1008 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1009 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1010 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1011 writel(0x0000, port + PORT_CRC_ERR_CNT);
1012 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1013
1014 /* Always use 64bit activation */
1015 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1016
1017 /* Clear port multiplier enable and resume bits */
Tejun Heo28c8f3b2006-10-16 08:47:18 +09001018 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1019 port + PORT_CTRL_CLR);
Tejun Heo2a41a612006-07-03 16:07:27 +09001020 }
1021
1022 /* Turn on interrupts */
1023 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1024}
1025
Tejun Heoedb33662005-07-28 10:36:22 +09001026static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1027{
1028 static int printed_version = 0;
Tejun Heo24dc5f32007-01-20 16:00:28 +09001029 struct device *dev = &pdev->dev;
Tejun Heoedb33662005-07-28 10:36:22 +09001030 unsigned int board_id = (unsigned int)ent->driver_data;
Tejun Heo042c21f2005-10-09 09:35:46 -04001031 struct ata_port_info *pinfo = &sil24_port_info[board_id];
Tejun Heo24dc5f32007-01-20 16:00:28 +09001032 struct ata_probe_ent *probe_ent;
Tejun Heo24dc5f32007-01-20 16:00:28 +09001033 void __iomem *host_base;
1034 void __iomem *port_base;
Tejun Heoedb33662005-07-28 10:36:22 +09001035 int i, rc;
Tejun Heo37024e82006-04-11 22:32:19 +09001036 u32 tmp;
Tejun Heoedb33662005-07-28 10:36:22 +09001037
1038 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001039 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Tejun Heoedb33662005-07-28 10:36:22 +09001040
Tejun Heo24dc5f32007-01-20 16:00:28 +09001041 rc = pcim_enable_device(pdev);
Tejun Heoedb33662005-07-28 10:36:22 +09001042 if (rc)
1043 return rc;
1044
Tejun Heo0d5ff562007-02-01 15:06:36 +09001045 rc = pcim_iomap_regions(pdev,
1046 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1047 DRV_NAME);
Tejun Heoedb33662005-07-28 10:36:22 +09001048 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001049 return rc;
Tejun Heoedb33662005-07-28 10:36:22 +09001050
Tejun Heo0d5ff562007-02-01 15:06:36 +09001051 /* allocate & init probe_ent */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001052 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001053 if (!probe_ent)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001054 return -ENOMEM;
Tejun Heoedb33662005-07-28 10:36:22 +09001055
Tejun Heoedb33662005-07-28 10:36:22 +09001056 probe_ent->dev = pci_dev_to_dev(pdev);
1057 INIT_LIST_HEAD(&probe_ent->node);
1058
Tejun Heo042c21f2005-10-09 09:35:46 -04001059 probe_ent->sht = pinfo->sht;
Jeff Garzikcca39742006-08-24 03:19:22 -04001060 probe_ent->port_flags = pinfo->flags;
Tejun Heo042c21f2005-10-09 09:35:46 -04001061 probe_ent->pio_mask = pinfo->pio_mask;
Tejun Heofbfda6e2006-03-05 23:03:42 +09001062 probe_ent->mwdma_mask = pinfo->mwdma_mask;
Tejun Heo042c21f2005-10-09 09:35:46 -04001063 probe_ent->udma_mask = pinfo->udma_mask;
1064 probe_ent->port_ops = pinfo->port_ops;
Jeff Garzikcca39742006-08-24 03:19:22 -04001065 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->flags);
Tejun Heoedb33662005-07-28 10:36:22 +09001066
1067 probe_ent->irq = pdev->irq;
Thomas Gleixner1d6f3592006-07-01 19:29:42 -07001068 probe_ent->irq_flags = IRQF_SHARED;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001069 probe_ent->iomap = pcim_iomap_table(pdev);
Tejun Heoedb33662005-07-28 10:36:22 +09001070
Tejun Heo0d5ff562007-02-01 15:06:36 +09001071 host_base = probe_ent->iomap[SIL24_HOST_BAR];
1072 port_base = probe_ent->iomap[SIL24_PORT_BAR];
Tejun Heoedb33662005-07-28 10:36:22 +09001073
1074 /*
1075 * Configure the device
1076 */
Tejun Heo26ec6342006-04-11 22:32:19 +09001077 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1078 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1079 if (rc) {
1080 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1081 if (rc) {
1082 dev_printk(KERN_ERR, &pdev->dev,
1083 "64-bit DMA enable failed\n");
Tejun Heo24dc5f32007-01-20 16:00:28 +09001084 return rc;
Tejun Heo26ec6342006-04-11 22:32:19 +09001085 }
1086 }
1087 } else {
1088 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1089 if (rc) {
1090 dev_printk(KERN_ERR, &pdev->dev,
1091 "32-bit DMA enable failed\n");
Tejun Heo24dc5f32007-01-20 16:00:28 +09001092 return rc;
Tejun Heo26ec6342006-04-11 22:32:19 +09001093 }
1094 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1095 if (rc) {
1096 dev_printk(KERN_ERR, &pdev->dev,
1097 "32-bit consistent DMA enable failed\n");
Tejun Heo24dc5f32007-01-20 16:00:28 +09001098 return rc;
Tejun Heo26ec6342006-04-11 22:32:19 +09001099 }
Tejun Heoedb33662005-07-28 10:36:22 +09001100 }
1101
Tejun Heo37024e82006-04-11 22:32:19 +09001102 /* Apply workaround for completion IRQ loss on PCI-X errata */
Jeff Garzikcca39742006-08-24 03:19:22 -04001103 if (probe_ent->port_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
Tejun Heo37024e82006-04-11 22:32:19 +09001104 tmp = readl(host_base + HOST_CTRL);
1105 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1106 dev_printk(KERN_INFO, &pdev->dev,
1107 "Applying completion IRQ loss on PCI-X "
1108 "errata fix\n");
1109 else
Jeff Garzikcca39742006-08-24 03:19:22 -04001110 probe_ent->port_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
Tejun Heo37024e82006-04-11 22:32:19 +09001111 }
1112
Tejun Heoedb33662005-07-28 10:36:22 +09001113 for (i = 0; i < probe_ent->n_ports; i++) {
Tejun Heo0d5ff562007-02-01 15:06:36 +09001114 void __iomem *port = port_base + i * PORT_REGS_SIZE;
Tejun Heoedb33662005-07-28 10:36:22 +09001115
Tejun Heo0d5ff562007-02-01 15:06:36 +09001116 probe_ent->port[i].cmd_addr = port;
1117 probe_ent->port[i].scr_addr = port + PORT_SCONTROL;
Tejun Heoedb33662005-07-28 10:36:22 +09001118
1119 ata_std_ports(&probe_ent->port[i]);
Tejun Heoedb33662005-07-28 10:36:22 +09001120 }
1121
Jeff Garzikcca39742006-08-24 03:19:22 -04001122 sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
Tejun Heo2a41a612006-07-03 16:07:27 +09001123 host_base, port_base);
Tejun Heoedb33662005-07-28 10:36:22 +09001124
1125 pci_set_master(pdev);
1126
Tejun Heo24dc5f32007-01-20 16:00:28 +09001127 if (!ata_device_add(probe_ent))
1128 return -ENODEV;
Tejun Heoedb33662005-07-28 10:36:22 +09001129
Tejun Heo24dc5f32007-01-20 16:00:28 +09001130 devm_kfree(dev, probe_ent);
Tejun Heoedb33662005-07-28 10:36:22 +09001131 return 0;
Tejun Heoedb33662005-07-28 10:36:22 +09001132}
1133
Alexey Dobriyan281d4262006-08-14 22:49:30 -07001134#ifdef CONFIG_PM
Tejun Heod2298dc2006-07-03 16:07:27 +09001135static int sil24_pci_device_resume(struct pci_dev *pdev)
1136{
Jeff Garzikcca39742006-08-24 03:19:22 -04001137 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001138 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1139 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
Tejun Heo553c4aa2006-12-26 19:39:50 +09001140 int rc;
Tejun Heod2298dc2006-07-03 16:07:27 +09001141
Tejun Heo553c4aa2006-12-26 19:39:50 +09001142 rc = ata_pci_device_do_resume(pdev);
1143 if (rc)
1144 return rc;
Tejun Heod2298dc2006-07-03 16:07:27 +09001145
1146 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
Tejun Heo0d5ff562007-02-01 15:06:36 +09001147 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
Tejun Heod2298dc2006-07-03 16:07:27 +09001148
Jeff Garzikcca39742006-08-24 03:19:22 -04001149 sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags,
Tejun Heo0d5ff562007-02-01 15:06:36 +09001150 host_base, port_base);
Tejun Heod2298dc2006-07-03 16:07:27 +09001151
Jeff Garzikcca39742006-08-24 03:19:22 -04001152 ata_host_resume(host);
Tejun Heod2298dc2006-07-03 16:07:27 +09001153
1154 return 0;
1155}
Alexey Dobriyan281d4262006-08-14 22:49:30 -07001156#endif
Tejun Heod2298dc2006-07-03 16:07:27 +09001157
Tejun Heoedb33662005-07-28 10:36:22 +09001158static int __init sil24_init(void)
1159{
Pavel Roskinb7887192006-08-10 18:13:18 +09001160 return pci_register_driver(&sil24_pci_driver);
Tejun Heoedb33662005-07-28 10:36:22 +09001161}
1162
1163static void __exit sil24_exit(void)
1164{
1165 pci_unregister_driver(&sil24_pci_driver);
1166}
1167
1168MODULE_AUTHOR("Tejun Heo");
1169MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1170MODULE_LICENSE("GPL");
1171MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1172
1173module_init(sil24_init);
1174module_exit(sil24_exit);